LC2MOS Complete,

12-Bit, 100 kHz, Sampling ADCs

AD7870/AD7875/AD7876
FEATURES

FUNCTIONAL BLOCK DIAGRAM

AGND

VIN

REF OUT

VDD

INPUT
SCALING

AD7870/AD7875/
AD7876

TRACK-AND-HOLD

COMP
3V
REFERENCE

12-BIT
DAC

CLOCK

CLK

SAR +
COUNTER
12/8/CLK
CONTROL LOGIC
CONVST

CS

RD BUSY/INT

PARALLEL
AND SERIAL
INTERFACE

DB11

DB0

DGND

VSS

07730-001

Complete monolithic 12-bit ADCs with

2 s track-and-hold amplifier
8 s ADC
On-chip reference
Laser-trimmed clock
Parallel, byte, and serial digital interface
72 dB SNR at 10 kHz input frequency
(AD7870, AD7875)
57 ns data access time
Low power: 60 mW typical
Variety of input ranges
3 V for AD7870
0 V to +5 V for AD7875
10 V for AD7876

Figure 1.

GENERAL DESCRIPTION
The AD7870/AD7875/AD7876 are fast, complete, 12-bit
analog-to-digital converters (ADCs). These converters consist
of a track-and-hold amplifier, an 8 s successive approximation
ADC, a 3 V buried Zener reference, and versatile interface logic.
The ADCs feature a self-contained internal clock which is laser
trimmed to guarantee accurate control of conversion time. No
external clock timing components are required; the on-chip
clock may be overridden by an external clock if required.
The parts offer a choice of three data output formats: a single,
parallel, 12-bit word; two 8-bit bytes or serial data. Fast bus
access times and standard control inputs ensure easy interfacing
to modern microprocessors and digital signal processors.
All parts operate from 5 V power supplies. The AD7870 and
AD7876 accept input signal ranges of 3 V and 10 V, respectively, while the AD7875 accepts a unipolar 0 V to +5 V input
range. The parts can convert full power signals up to 50 kHz.
The AD7870/AD7875/AD7876 feature dc accuracy specifications, such as linearity, full-scale and offset error. In addition,
the AD7870 and AD7875 are fully specified for dynamic
performance parameters including distortion and signal-tonoise ratio.

The parts are available in a 24-pin, 0.3 inch-wide, plastic or

hermetic dual-in-line package (DIP). The AD7870 and AD7875
are available in a 28-pin plastic leaded chip carrier (PLCC),
while the AD7876 is available and in a 24-pin small outline
(SOIC) package.

PRODUCT HIGHLIGHTS
1.

Complete 12-bit ADC on a chip.

The AD7870/AD7875/AD7876 provide all the functions
necessary for analog-to-digital conversion and combine a
12-bit ADC with internal clock, track-and-hold amplifier
and reference on a single chip.

2.

Dynamic specifications for DSP users.

The AD7870 and AD7875 are fully specified and tested for
ac parameters, including signal-to-noise ratio, harmonic
distortion and intermodulation distortion.

3.

Fast microprocessor interface.

Data access times of 57 ns make the parts compatible with
modern 8-bit and 16-bit microprocessors and digital signal
processors. Key digital timing parameters are tested and
guaranteed over the full operating temperature range.

Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 19972009 Analog Devices, Inc. All rights reserved.

AD7870/AD7875/AD7876
TABLE OF CONTENTS
Features .............................................................................................. 1

Offset And Full-Scale AdjustmentAD7876 ........................ 13

Functional Block Diagram .............................................................. 1

Offset And Full-Scale AdjustmentAD7875 ........................ 13

General Description ......................................................................... 1

Timing and Control ....................................................................... 14

Product Highlights ........................................................................... 1

Data Output Formats ................................................................. 14

Revision History ............................................................................... 2

Mode 1 Interface......................................................................... 14

Specifications..................................................................................... 3

Mode 2 Interface......................................................................... 15

AD7870 Specifications ................................................................. 3

Dynamic Specifications ............................................................. 16

AD7875/AD7876 Specifications................................................. 4

Microprocessor Interface............................................................... 19

Timing Characteristics ................................................................ 6

Parallel Read Interfacing ........................................................... 19

Absolute Maximum Ratings............................................................ 7

Two-Byte Read Interfacing ....................................................... 19

ESD Caution .................................................................................. 7

Serial Interfacing ........................................................................ 20

Pin Configurations and Function Descriptions ........................... 8

Standalone Operation ................................................................ 21

Load Circuits ................................................................................... 10

Applications Information .............................................................. 22

Converter Details ............................................................................ 11

Layout Hints ................................................................................ 22

Internal Reference ...................................................................... 11

Noise ............................................................................................ 22

Track-and-Hold Amplifier ........................................................ 11

Outline Dimensions ....................................................................... 23

Analog Input ............................................................................... 11

Ordering Guide .......................................................................... 25

Offset And Full-Scale AdjustmentAD7870 ........................ 12

REVISION HISTORY
2/09Rev. B to Rev. C
Updated Format .................................................................. Universal
Reorganized Layout ............................................................ Universal
Deleted S Version ................................................................ Universal
Changes to Internal Clock Parameter, Table 1 and
Added Endnote to Table 1 ............................................................... 4
Changes to Internal Clock Parameter, Table 2.............................. 5
Changes to Mode 1 Interface Section .......................................... 14
Deleted Data Acquisition Board and Interface Connections
Sections and Figure 26 ................................................................... 15
Deleted Figure 27 and Power Supply Connections, Shorting
Plug Options and Components List Sections ............................. 16
Deleted Figure 28 and Figure 29 ................................................... 17
Deleted Figure 30 and Figure 31 ................................................... 18
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 25

Rev. C | Page 2 of 28

AD7870/AD7875/AD7876
SPECIFICATIONS
VDD = +5 V 5%, VSS = 5 V 5%, AGND = DGND = 0 V, fCLK = 2.5 MHz external, unless otherwise stated. All Specifications Tmin to
Tmax, unless otherwise noted.

AD7870 SPECIFICATIONS
Table 1.
Parameter
DYNAMIC PERFORMANCE 2
Signal-to-Noise Ratio 3 (SNR)
@ +25C
TMIN to TMAX
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Second Order Terms
Third Order Terms
Track-and-Hold Acquisition Time
DC ACCURACY
Resolution
Minimum Resolution for which No Missing Codes
are Guaranteed
Integral Nonlinearity
Integral Nonlinearity
Differential Nonlinearity
Bipolar Zero Error
Positive Full-Scale Error 4
Negative Full-Scale Error4
ANALOG INPUT
Input Voltage Range
Input Current
REFERENCE OUTPUT
REF OUT @ +25C
REF OUT Tempco
Reference Load Sensitivity
(REF OUT/I)
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Current (12/8/CLK Input Only)
Input Capacitance, CIN 5
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
DB11 to DB0
Floating-State Leakage Current
Floating-State Output Capacitance5

J, A

ADN7870 1
K, B
L, C

Units

Test Conditions/Comments

70
70
80

70
70
80

72
71
80

69
69
78

dB min
dB min
dB max

80

80

80

78

dB max

VIN = 10 kHz sine wave, fSAMPLE = 100 kHz

Typically 71.5 dB for 0 < VIN < 50 kHz
VIN = 10 kHz sine wave, fSAMPLE = 100 kHz
Typically 86 dB for 0 < VIN < 50 kHz
VIN = 10 kHz, fSAMPLE = 100 kHz
Typically 86 dB for 0 < VIN < 50 kHz

80
80
2

80
80
2

80
80
2

78
78
2

dB max
dB max
s max

12
12

12
12

12
12

12
12

Bits
Bits

1/2

5
5
5

1/2
1
1
5
5
5

1/4
1/2
1
5
5
5

1/2
1
1
5
5
5

LSB typ
LSB max
LSB max
LSB max
LSB max
LSB max

3
500

3
500

3
500

3
500

V
A max

2.99
3.01
60

2.99
3.01
60

2.99
3.01
35

2.99
3.01
35

V min
V max
ppm/C
max
mV max

2.4
0.8
10
10
10

2.4
0.8
10
10
10

2.4
0.8
10
10
10

2.4
0.8
10
10
10

V min
V max
A max
A max
pF max

VDD = 5 V 5%
VDD = 5 V 5%
VIN = 0 V to VDD
VIN = VSS to VDD

4.0
0.4

4.0
0.4

4.0
0.4

4.0
0.4

V min
V max

ISOURCE = 40 A
ISINK = 1.6 mA

10
15

10
15

10
15

10
15

A max
pF max

Rev. C | Page 3 of 28

fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz

fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz

Reference load current change (0 A to

500 A). Reference load should not be
changed during conversion.

AD7870/AD7875/AD7876
Parameter
CONVERSION TIME
External Clock (fCLK = 2.5 MHz)
Internal Clock 6
POWER REQUIREMENTS
VDD
VSS
IDD
ISS
Power Dissipation

J, A

ADN7870 1
K, B
L, C

Units

8
6.5/9

8
6.5/9

8
6.5/9

8
6.5/9

s max
s min/
s max

+5
5
13
6
95

+5
5
13
6
95

+5
5
13
6
95

+5
5
13
6
95

V nom
V nom
mA max
mA max
mW max

Test Conditions/Comments

5% for specified performance

5% for specified performance
Typically 8 mA
Typically 4 mA
Typically 60 mW

The temperature range for the J, K, and L versions is from 0C to +70C; for the A, B, and C versions is40C to +85C; and for the T version is 55C to +125C.
VIN (p-p) = 3 V.
SNR calculation includes distortion and noise components.
4
Measured with respect to internal reference and includes bipolar offset error.
5
Sample tested @ +25C to ensure compliance.
6
Conversion time specification for the AD7870A device with internal clock used is 8 s/10 s minimum/maximum.
2
3

AD7875/AD7876 SPECIFICATIONS
Table 2.
AD7875/AD7876 1
K, B
L, C
T

Units

12
12

12
12

12
12

Bits
Bits

1
1
1
1
5
6
8
60
2

1/2
1
1/2
1
5
2
8
35
2

1
1
1
1.5/1.0
5
6
8
60
2

LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
ppm/C max
s max

70
70
80

72
71
80

69
69
78

dB min
dB min
dB max

Peak Harmonic or Spurious Noise

80

80

78

dB max

Intermodulation Distortion (IMD)

Second Order Terms
Third Order Terms

80
80

80
80

78
78

dB max
dB max

Parameter
DC ACCURACY
Resolution
Min Resolution for which No Missing
Codes Are Guaranteed
Integral Nonlinearity @ +25C
TMIN to TMAX (AD7875 Only)
TMIN to TMAX (AD7876 Only)
Differential Nonlinearity
Unipolar Offset Error (AD7875 Only)
Bipolar Zero Error (AD7876 Only)
Full-Scale Error at +25C 2
Full-Scale TC2
Track-and-Hold Acquisition Time
DYNAMIC PERFORMANCE 3 (AD7875
ONLY)
Signal-to-Noise Ratio 4 (SNR)
@ +25C
TMIN to TMAX
Total Harmonic Distortion (THD)

Rev. C | Page 4 of 28

Test Conditions/Comments

Typical full-scale error is 1 LSB

Typical TC is 20 ppm/C

VIN = 10 kHz sine wave, fSAMPLE = 100 kHz

Typically 71.5 dB for 0 < VIN < 50 kHz
VIN = 10 kHz sine wave, fSAMPLE = 100 kHz
Typically 86 dB for 0 < VIN < 50 kHz
VIN = 10 kHz, fSAMPLE = 100 kHz
Typically 86 dB for 0 < VIN < 50 kHz
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz

AD7870/AD7875/AD7876
Parameter
ANALOG INPUT
AD7875 Input Voltage Range
AD7875 Input Current
AD7876 Input Voltage Range
AD7876 Input Current
REFERENCE OUTPUT
REF OUT @ +25C
REF OUT Tempco
Reference Load Sensitivity
(REF OUT/I)
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Current (12/8/CLK Input Only)
Input Capacitance, CIN 5
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
DB11DB0
Floating-State Leakage Current
Floating-State Output
Capacitance5
CONVERSION TIME
External Clock (fCLK = 2.5 MHz)
Internal Clock
POWER REQUIREMENTS

AD7875/AD7876 1
K, B
L, C
T

Units

0 to +5
500
10
600

0 to +5
500
10
600

0 to +5
500
10
600

V
A max
V
A max

2.99
3.01
60
1

2.99
3.01
35
1

2.99
3.01
60
1

V min
V max
ppm/C max
mV max

2.4
0.8
10
10
10

2.4
0.8
10
10
10

2.4
0.8
10
10
10

V min
V max
A max
A max
pF max

VDD = 5 V 5%
VDD = 5 V 5%
VIN = 0 V to VDD
VIN = VSS to VDD

4.0
0.4

4.0
0.4

4.0
0.4

V min
V max

ISOURCE = 40 mA
ISINK = 1.6 mA

10
15

10
15

10
15

A max
pF max

8
6.5/9

8
6.5/9

8
6.5/9

s max
s min/s
max

As per AD7870

Test Conditions/Comments

Typical tempco Is 20 ppm/C

Reference load current change (0 A to 500 A).
Reference load should not be changed during
conversion.

Refer to the power requirements in Table 1.

For the AD7875, the temperature range for the K and L versions is from 0C to +70C; for the B and C versions is40C to +85C; and for the T version is 55C to
+125C. For the AD7876, the temperature range for the B and C versions is from 40C to +85C and for the T version is55C to +125C.
2
Includes internal reference error and is calculated after unipolar offset error (AD7875) or bipolar zero error (AD7876) has been adjusted out. Full-scale error refers to
both positive and negative full-scale error for the AD7876.
3
Dynamic performance parameters are not tested on the AD7876, but these are typically the same as for the AD7875.
4
SNR calculation includes distortion and noise components.
5
Sample tested @ +25C to ensure compliance.

Rev. C | Page 5 of 28

AD7870/AD7875/AD7876
TIMING CHARACTERISTICS
VDD = +5 V 5%, VSS = 5 V 5%, AGND = DGND = 0 V. See Figure 14, Figure 15, Figure 16, and Figure 17. Timing specifications are
sample tested at 25C to ensure compliance, unless otherwise noted. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V)
and timed from a voltage level of 1.6 V.
Table 3.
Parameter 1
t1
t2
t3 2
t4
t5
t62, 3
t72, 4
t8
t9
t10
t11 5
t12 6
t13
t14
t15
t16
t17
t18
t19
t20

Limit at TMIN, TMAX

(J, K, L, A, B, C Versions)
50
0
60
0
70

Limit at TMIN, TMAX

(T Version)
50
0
75
0
70

57
5
50
0
0
100
370
135
20
100
10
100
60
120
200
0
0
0

70
5
50
0
0
100
370
150
20
100
10
100
60
120
200
0
0
0

Units
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min

Conditions/Comments
CONVST pulse width
CS to RD setup time (Mode 1)
RD pulse width
CS to RD hold time (Mode 1)
RD to INT delay
Data access time after RD
Bus relinquish time after RD
HBEN to RD setup time
HBEN to RD hold time
SSTRB to SCLK falling edge setup time
SCLK cycle time
SCLK to valid data delay. CL = 35 pF
SCLK rising edge to SSTRB
Bus relinquish time after SCLK
CS to RD setup time (Mode 2)
CS to BUSY propagation delay
Data setup time prior to BUSY
CS to RD hold time (Mode 2)
HBEN to CS setup time
HBEN to CS hold time

Serial timing is measured with a 4.7 k pull-up resistor on SDATA and SSTRB and a 2 k pull-up on SCLK. The capacitance on all three outputs is 35 pF.
Timing specifications for t3, t6, and for the maximum limit at t7 are 100% production tested.
3
t6 is measured with the load circuits of Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
t7 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 5.
5
SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.
6
SDATA will drive higher capacitive loads but this will add to t12 since it increases the external RC time constant (4.7 k||CL) and thus the time to reach 2.4 V.
1
2

Rev. C | Page 6 of 28

AD7870/AD7875/AD7876
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
VDD to AGND
VSS to AGND
AGND to DGND
VIN to AGND
REF OUT to AGND
Digital Inputs to DGND
Digital Outputs to DGND
Operating Temperature Range
Commercial (J, K, L VersionsAD7870)
Commercial (K, L VersionsAD7875)
Industrial (A, B, C VersionsAD7870)
Industrial (B, C VersionsAD7875/
AD7876)
Extended (T Version)
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Power Dissipation (Any Package) to +75C
Derates above +75C by

Rating
0.3 V to +7 V
+0.3 V to 7 V
0.3 V to VDD +0.3 V
15 V to +15 V
0 V to VDD
0.3 V to VDD +0.3 V
0.3 V to VDD +0.3 V

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

0C to +70C
0C to +70C
25C to +85C
40C to +85C
55C to +125C
65C to +150C
+300C
450 mW
10 mW/C

Rev. C | Page 7 of 28

AD7870/AD7875/AD7876

5
6

DB9/SCLK

7
8

16

DB0/DB8

DB5/LOW 10

15

DB1/DB9

DB8/SDATA

DB4/LOW 11

14

DB2/DB10

DB7/LOW

10

DGND 12

13

DB3/DB11

DB6/LOW

11

07730-004

DB6/LOW 9

NC

CS

CONVST

12/8/CLK

28

27

26

PIN 1
INDENTFIER

25

VSS

24

VIN

AD7870/AD7875/
AD7876

23

REF OUT

22

NC

TOP VIEW
(Not to Scale)

21

AGND

20

VDD

19

DB0/DB8

DB5/LOW

12

13

14

15

16

17

18

NC = NO CONNECT

07730-005

DB11/HBEN
DB10/SSTRB

DB1/DB9

19 REF OUT
TOP VIEW
DB8/SDATA 7 (Not to Scale) 18 AGND
17 VDD
DB7/LOW 8

DB2/DB10

DB9/SCLK 6

NC

VIN

DB3/DB11

VSS

20

DB10/SSTRB 5

RD

12/8/CLK

21

DB11/HBEN 4

NC

CONVST

22

AD7870/
AD7875/
AD7876

CLK 3

BUSY/INT

CS

23

DGND

24

DB4/LOW

RD 1
BUSY/INT 2

CLK

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. PLCC Pin Configuration

Figure 2. DIP and SOIC Pin Configuration

Table 5. Pin Function Descriptions

DIP and SOIC
Pin No.
N/A
1
2

PLCC
Pin No.
1, 8, 15,
22
2
3

CLK

DB11/HBEN

DB10/SSTRB

DB9/SCLK

DB8/SDATA

8 to11

10 to 13

DB7/LOW
DB4/LOW

12
13 to 16

14
16 to 19

DGND
DB3/DB11
DB0/DB8

17

20

VDD

Mnemonic
NC

Function
No Connect.

RD
BUSY/INT

Read. Active low logic input. This input is used in conjunction with CS low to enable the data outputs.
Busy/Interrupt. Active low logic output indicating converter status. See Figure 14, Figure 15, Figure 16,
and Figure 17.
Clock Input. An external TTL-compatible clock may be applied to this input pin. Alternatively, tying this
pin to VSS enables the internal laser-trimmed clock oscillator.
Data Bit 11 (MSB)/High Byte Enable. The function of this pin is dependent on the state of the 12/8/CLK
input. When 12-bit parallel data is selected, this pin provides the DB11 output. When byte data is
selected, this pin becomes the HBEN logic input. HBEN is used for 8-bit bus interfacing. When HBEN is
low, DB7/LOW to DB0/DB8 become DB7 to DB0. With HBEN high, DB7/LOW to DB0/DB8 are used for
the upper byte of data (see Table 6).
Data Bit 10/Serial Strobe. When 12-bit parallel data is selected, this pin provides the DB10 output.
SSTRB is an active low open-drain output that provides a strobe or framing pulse for serial data. An
external 4.7 k pull-up resistor is required on SSTRB.
Data Bit 9/Serial Clock. When 12-bit parallel data is selected, this pin provides the DB9 output. SCLK is
the gated serial clock output derived from the internal or external ADC clock. If the 12/8/CLK input is at
5 V, then SCLK runs continuously. If 12/8/CLK is at 0 V, then SCLK is gated off after serial transmission is
complete. SCLK is an open-drain output and requires an external 2 k pull-up resistor.
Data Bit 8/Serial Data. When 12-bit parallel data is selected, this pin provides the DB8 output. SDATA is
an open-drain serial data output which is used with SCLK and SSTRB for serial data transfer. Serial data
is valid on the falling edge of SCLK while SSTRB is low. An external 4.7 k pull-up resistor is required on
SDATA.
Three-state data outputs controlled by CS and RD. Their function depends on the 12/8/CLK and HBEN
inputs. With 12/8/CLK high, they are always DB7DB4. With 12/8/CLK low or 5 V, their function is
controlled by HBEN (see Table 6).
Digital Ground. Ground reference for digital circuitry.
Three-state data outputs which are controlled by CS and RD. Their function depends on the 12/8/CLK
and HBEN inputs. With 12/8/CLK high, they are always DB3DB0. With 12/8/CLK low or 5 V, their
function is controlled by HBEN (see Table 6).
Positive Supply, +5 V 5%.

Rev. C | Page 8 of 28

AD7870/AD7875/AD7876
DIP and SOIC
Pin No.
18
19

PLCC
Pin No.
21
23

Mnemonic
AGND
REF OUT

20

24

VIN

21
22

25
26

VSS
12/8/CLK

23

27

CONVST

24

28

CS

Function
Analog Ground. Ground reference for track-and-hold, reference and DAC.
Voltage Reference Output. The internal 3 V reference is provided at this pin. The external load capability is
500 A.
Analog Input. The analog input range is 3 V for the AD7870, 10 V for the AD7876, and 0 V to +5 V for the
AD7875.
Negative Supply, 5 V 5%.
Three Function Input. Defines the data format and serial clock format. With this pin at +5 V, the output
data for-mat is 12-bit parallel only. With this pin at 0 V, either byte or serial data is available and SCLK is
not continuous. With this pin at 5 V, either byte or serial data is again available but SCLK is now
continuous.
Convert Start. A low to high transition on this input puts the track-and-hold into its hold mode and
starts conversion. This input is asynchronous to the CLK input.
Chip Select. Active low logic input. The device is selected when this input is active. With CONVST tied
low, a new conversion is initiated when CS goes low.

Table 6. Output Data for Byte Interfacing

HBEN
High
Low

DB7/Low
Low
DB7

DB6/Low
Low
DB6

DB5/Low
Low
DB5

DB4/Low
Low
DB4

Rev. C | Page 9 of 28

DB3/DB11
DB11(MSB)
DB3

DB2/DB10
DB10
DB2

DB1/DB9
DB9
DB1

DB0/DB8
DB8
DB0 (LSB)

AD7870/AD7875/AD7876
LOAD CIRCUITS
5V

5V

3k

56k
DBN
50pF

DGND
HIGH-Z TO VOH

3k

50pF
DGND
HIGH-Z TO VOL

07730-002

56k

DBN
10pF

10pF

DGND

DGND

VOH TO HIGH-Z

VOL TO HIGH-Z

Figure 5. Load Circuits for Output Float Delay

Figure 4. Load Circuits for Access Time

Rev. C | Page 10 of 28

07730-003

DBN

DBN

AD7870/AD7875/AD7876
CONVERTER DETAILS
The AD7870/AD7875/AD7876 is a complete 12-bit ADC,
requiring no external components apart from power supply
decoupling capacitors. It is comprised of a 12-bit successive
approximation ADC based on a fast settling voltage output
DAC, a high speed comparator and SAR, a track-and-hold
amplifier, a 3 V buried Zener reference, a clock oscillator,
and control logic.

TRACK-AND-HOLD AMPLIFIER
The track-and-hold amplifier on the analog input of the
AD7870/AD7875/AD7876 allows the ADC to accurately
convert input frequencies to 12-bit accuracy. The input
bandwidth of the track-and-hold amplifier is much greater
than the Nyquist rate of the ADC even when the ADC is
operated at its maximum throughput rate. The 0.1 dB cutoff
frequency occurs typically at 500 kHz. The track-and-hold
amplifier acquires an input signal to 12-bit accuracy in less than
2 s. The overall throughput rate is equal to the conversion time
plus the track-and-hold amplifier acquisition time. For a 2.5 MHz
input clock the throughput rate is 10 s max.

INTERNAL REFERENCE
The AD7870/AD7875/AD7876 have on-chip temperature
compensated buried Zener reference that is factory trimmed
to 3 V 10 mV. Internally it provides both the DAC reference
and the dc bias required for bipolar operation (AD7870 and
AD7876). The reference output is available (REF OUT) and
capable of providing up to 500 A to an external load.

The operation of the track-and-hold is essentially transparent

to the user. The track-and-hold amplifier goes from its tracking
mode to its hold mode at the start of conversion.

The maximum recommended capacitance on REF OUT for

normal operation is 50 pF. If the reference is required for use
external to the ADC, it should be decoupled with a 200
resistor in series with a parallel combination of a 10 F
tantalum capacitor and a 0.1 F ceramic capacitor. These
decoupling components are required to remove voltage
spikes caused by the ADCs internal operation.
VDD

If the CONVST input is used to start conversion then the track

to hold transition occurs on the rising edge of CONVST. If CS
starts conversion, this transition occurs on the falling edge of CS.

ANALOG INPUT
The three parts differ from each other in the analog input
voltage range that they can handle. The AD7870 accepts 3 V
input signals, the AD7876 accepts a 10 V input range, while
the input range for the AD7875 is 0 V to +5 V.

AD7870/AD7875/AD7876

TEMPERATURE
COMPENSATION

REF OUT

07730-006

VSS

Figure 8 shows the AD7870 analog input. The analog input

range is 3 V into an input resistance of typically 15 k. The
designed code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . .
FS3/2 LSBs). The output code is twos complement binary with
1 LSB = FS/4096 = 6 V/4096 = 1.46 mV. The ideal input/output
transfer function is shown in Figure 11.

Figure 6. Reference Circuit

The reference output voltage is 3 V. For applications using the

AD7875 or AD7876, a 5 V or 10 V reference may be required.
Figure 7 shows how to scale the 3 V REF OUT voltage to
provide either a 5 V or 10 V external reference.

AD7870
TRACK-AND-HOLD
AMPLIFIER

TO INTERNAL
COMPARATOR

AD7870/AD7875/AD7876

INTERNAL 3V
REFERENCE

TO INTERNAL
3V REFERENCE

REF OUT
VOUT = 5V (10V)

07730-008

Figure 8. AD7970 Analog Input

15k
(3.9k)

Figure 7. Generating a 5 V or 10 V Reference

07730-007

10k
(9.1k)

The AD7876 analog input structure is shown in Figure 9. The

analog input range is 10 V into an input resistance of typically
33 k. As before, the designed code transitions occur midway
between successive integer LSB values. The output code is twos
complement with 1 LSB = FS/4096 = 20 V/4096 = 4.88 mV. The
ideal input/output transfer function is shown in Figure 11.

Rev. C | Page 11 of 28

AD7870/AD7875/AD7876
OUTPUT
CODE

AD7876

7R

VIN

111111

TRACK-AND-HOLD
AMPLIFIER
TO INTERNAL
COMPARATOR

2.1R

111110
111101

3R

111100
TO INTERNAL
REFERENCE

07730-009

TO INTERNAL AGND

AGND

FS = 5V

000011

FS
1LSB = 4096

000010

Figure 9. AD7876 Analog Input

07730-012

REF OUT

000001

Figure 10 shows the analog input for the AD7875. The input
range is 0 V to +5 V into an input resistance of typically 25 k.
Once again, the designed code transitions occur midway
between successive integer LSB values. The output code is
straight binary with 1 LSB = FS/4096 = 5 V/4096 = 1.22 mV.
The ideal input/output transfer function is shown in Figure 12.
AD7875
TRACK-AND-HOLD
AMPLIFIER
2R

VIN

TO INTERNAL
COMPARATOR
3R
TO INTERNAL AGND
07730-010

AGND

Figure 10. AD7875 Analog Input

OUTPUT
CODE

AD7870 (AD7876)

011110

000010

000000

FS
2
+FS 1LSB
2

111111
111110

FS = 6V (20V)

+FS 1LSB

OFFSET AND FULL-SCALE ADJUSTMENT

AD7870
In most digital signal processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain
by ac coupling. Full-scale error effect is linear and does not
cause problems as long as the input signal is within the full
dynamic range of the ADC. Some applications will require
that the input signal span the full analog input dynamic range.
In such applications, offset and full-scale error have to be
adjusted to zero.

FS
1LSB = 4096

100000

VIN INPUT VOLTAGE

Figure 12. AD7875 Transfer Function

07730-011

100001

0V

Where adjustment is required, offset error must be adjusted

before full-scale error. This is achieved by trimming the offset
of the op amp driving the analog input of the AD7870 while the
input voltage is 1/2 LSB below ground. The trim procedure is as
follows: apply a voltage of 0.73 mV(1/2 LSB) at V1 in Figure 13
and adjust the op amp offset voltage until the ADC output code
flickers between 1111 1111 1111 and 0000 0000 0000. Gain
error can be adjusted at either the first code transition (ADC
negative full-scale) or the last code transition (ADC positive full
scale). The trim procedures for both cases are as follows (see
Figure 13).

011111

000001

000000

0V
VIN INPUT VOLTAGE

Figure 11. AD7870/AD7876 Transfer Function

Rev. C | Page 12 of 28

AD7870/AD7875/AD7876
V1

R1
10k

Positive Full-Scale Adjust

R2
500

Apply a voltage of 9.9927 V (FS/2 3/2 LSBs) at V1. Adjust R2

until the ADC output code flickers between 0111 1111 1110 and
0111 1111 1111.

VIN
R4
10k

R3
10k

R5
10k

AD7870/
AD7875/
AD78761

Negative Full-Scale Adjust

Apply a voltage of 9.9976 V (FS/2 + 1/2 LSB) at V1 and adjust
R2 until the ADC output code flickers between 1000 0000 0000
and 1000 0000 0001.

1ADDITIONAL PINS OMITTED FOR CLARITY.

07730-013

AGND

OFFSET AND FULL-SCALE ADJUSTMENT

AD7875

Figure 13. Offset and Full-Scale Adjust Circuit

Positive Full-Scale Adjust

Apply a voltage of 2.9978 V (FS/2 3/2 LSBs) at V1. Adjust R2
until the ADC output code flickers between 0111 1111 1110 and
0111 1111 1111.

Negative Full-Scale Adjust

Apply a voltage of 2.9993 V (FS/2 + 1/2 LSB) at V1 and adjust
R2 until the ADC output code flickers between 1000 0000 0000
and 1000 0000 0001.

OFFSET AND FULL-SCALE ADJUSTMENT

AD7876

Similar to the AD7870, most of the DSP applications in which

the AD7875 is used do not require offset and full-scale
adjustment. For applications that do require adjustment, offset
error must be adjusted before full-scale (gain) error. This is
achieved by applying an input voltage of 0.61 mV (1/2 LSB) to
V1 in Figure 13 and adjusting the op amp offset voltage until
the ADC output code flickers between 0000 0000 0000 and
0000 0000 0001. For full-scale adjustment, apply an input
voltage of 4.9982 V (FS 3/2 LSBs) to V1 and adjust R2 until
the ADC output code flickers between 1111 1111 1110 and
1111 1111 1111.

The offset and full-scale adjustment for the AD7876 is similar

to that just outlined for the AD7870. The trim procedure, for
those applications that do require adjustment, is as follows:
apply a voltage of 2.44 mV (1/2 LSB) at V1 and adjust the op
amp offset voltage until the ADC output code flickers between
1111 1111 1111 and 0000 0000 0000. Full-scale error can be
adjusted at either the first code transition (ADC negative full
scale) or the last code transition (ADC positive full scale). The
trim procedure for both case is as described in the following
sections (see Figure 13).

Rev. C | Page 13 of 28

AD7870/AD7875/AD7876
TIMING AND CONTROL
The AD7870/AD7875/AD7876 is capable of two basic operating modes. In the first mode (Mode 1), the CONVST line is
used to start conversion and drive the track-and-hold into its
hold mode. At the end of conversion, the track-and-hold returns
to its tracking mode. It is intended principally for digital signal
processing and other applications where precise sampling in
time is required. In these applications, it is important that the
signal sampling occur at exactly equal intervals to minimize
errors due to sampling uncertainty or jitter. For these cases, the
CONVST line is driven by a timer or some precise clock source.
The second mode is achieved by hardwiring the CONVST line
low. This mode (Mode 2) is intended for use in systems where
the microprocessor has total control of the ADC, both initiating
the conversion and reading the data. CS starts conversion and
the microprocessor is normally driven into a WAIT state for the
duration of conversion by BUSY/INT.

DATA OUTPUT FORMATS

In addition to the two operating modes, the AD7870/AD7875/
AD7876 also offers a choice of three data output formats, one
serial and two parallel. The parallel data formats are a single,
12-bit parallel word for 16-bit data buses and a two-byte format
for 8-bit data buses. The data format is controlled by the 12/8/
CLK input. A logic high on this pin selects the 12-bit parallel
output format only. A logic low or 5 V applied to this pin
allows the user access to either serial or byte formatted data.
Three of the pins previously assigned to the four MSBs in
parallel form are now used for serial communications while
the fourth pin becomes a control input for the byte-formatted
data. The three possible data output formats can be selected
in either of the modes of operation.

Parallel Output Format

The two parallel formats available on the part are a 12-bit wide
data word and a two-byte data word. In the first format, all
12 bits of data are available at the same time on DB11 (MSB)
through DB0 (LSB). In the second, two reads are required to
access the data. When this data format is selected, the DB11/
HBEN pin assumes the HBEN function. HBEN selects which
byte of data is to be read from the ADC. When HBEN is low,
the lower eight bits of data are placed on the data bus during a
read operation; with HBEN high, the upper four bits of the 12bit word are placed on the data bus. These four bits are right
justified and thereby occupy the lower nibble of data while the
upper nibble contains four zeros.

Serial Output Format

Serial data is available on the AD7870/AD7875/AD7876 when
the 12/8/CLK input is at 0 V or 5 V and in this case the DB10/
SSTRB, DB9/SCLK and DB8/SDATA pins assume their serial
functions. Serial data is available during conversion with a
word length of 16 bits; four leading zeros, followed by the 12-bit
conversion result starting with the MSB. The data is synchro-

nized to the serial clock output (SCLK) and framed by the serial
strobe (SSTRB). Data is clocked out on a low to high transition
of the serial clock and is valid on the falling edge of this clock
while the SSTRB output is low. SSTRB goes low within three
clock cycles after CONVST, and the first serial data bit (the first
leading zero) is valid on the first falling edge of SCLK. All three
serial lines are open-drain outputs and require external pull-up
resistors.
The serial clock out is derived from the ADC clock source,
which may be internal or external. Normally, SCLK is required
during the serial transmission only. In these cases, it can be shut
down at the end of conversion to allow multiple ADCs to share
a common serial bus. However, some serial systems (such as the
TMS32020) require a serial clock that runs continuously. Both
options are available on the AD7870/AD7875/AD7876 using
the 12/8/CLK input. With this input at 5 V, the serial clock
(SCLK) runs continuously; when 12/8/CLK is at 0 V, SCLK is
turned off at the end of transmission.

MODE 1 INTERFACE
Conversion is initiated by a low going pulse on the CONVST
input. The rising edge of this CONVST pulse starts conversion
and drives the track-and-hold amplifier into its hold mode
(AD7870/AD7875/AD7876). The falling edge of the CONVST
pulse starts conversion and drives the track-and-hold amplifier
into its hold mode (AD7870A). Conversion is not initiated if
the CS is low. The BUSY/INT status output assumes its INT
function in this mode. INT is normally high and goes low at the
end of conversion. This INT line can be used to interrupt the
microprocessor. A read operation to the ADC accesses the data
and the INT line is reset high on the falling edge of CS and RD.
The CONVST input must be high when CS and RD are brought
low for the ADC to operate correctly in this mode. The CS or
RD input should not be hardwired low in this mode. Data
cannot be read from the part during conversion because the onchip latches are disabled when conversion is in progress. In
applications where precise sampling is not critical, the
CONVST pulse can be generated from a microprocessor WR
line OR-gated with a decoded address. In some applications,
depending on power supply turn-on time, the
AD7870/AD7875/AD7876 may perform a conversion on
power-up. In this case, the INT line powers-up low and a
dummy read to the AD7870/AD7875/AD7876 is required to
reset the INT line before starting conversion.
Figure 18 shows the Mode 1 timing diagram for a 12-bit parallel
data output format (12/8/CLK = +5 V). A read to the ADC at
the end of conversion accesses all 12 bits of data at the same
time. Serial data is not available for this data output format.

Rev. C | Page 14 of 28

AD7870/AD7875/AD7876
t1
TRACK-AND-HOLD
GOES INTO HOLD

CONVST

CS

t4

t2
t3
TRACK-AND-HOLD RETURNS
TO TRACK AND
ACQUISITION TIME BEGINS

INT

t5
t7

tCONVERT

t4

THREE-STATE

DATA

VALID
DATA
DB11 TO DB0

07730-014

RD

Figure 14. Mode 1 Timing Diagram, 12-Bit Parallel Read

t1
TRACK-AND-HOLD GOES INTO HOLD

CONVST

HBEN1

t9

t8
CS

t2
RD

t4
t3

TRACK-AND-HOLD RETURNS TO TRACK

AND ACQUISITION TIME BEGINS

t5

INT

tCONVERT

t6

THREE-STATE

DATA

t7
VALID
DATA
DB7 TO DB0

VALID
DATA
DB11 TO DB8

SSTRB2

t10

t11

t13

SCLK3

t12
SDATA2

LEADING
ZEROS

t14
DB11

DB10

DB0

SERIAL DATA

t2, t3, t4, t8, AND t9 ARE THE SAME

2EXTERNAL 4.7k PULL-UP RESISTOR.

1TIMES

FOR A HIGH BYTE READ AS FOR A LOW BYTE READ.

3EXTERNAL

07730-015

2k PULL-UP RESISTOR;
CONTINUOUS SCLK (DASHED LINE) WHEN 12/8/CLK = 5V;
NONCONTINUOUS WHEN 12/8/CLK = 0V.

Figure 15. Mode 1 Timing Diagram, Byte or Serial Read

The Mode 1 timing diagram for byte and serial data is shown
in Figure 15. INT goes low at the end of conversion and is reset
high by the first falling edge of CS and RD. This first read at the
end of conversion can either access the low byte or high byte of
data depending on the status of HBEN (Figure 15 shows low
byte only for example). The diagram shows both a noncontinuously and a continuously running clock (dashed line).

MODE 2 INTERFACE
The second interface mode is achieved by hard wiring
CONVST low and conversion is initiated by taking CS low
while HBEN is low. The track-and-hold amplifier goes into the
hold mode on the falling edge of CS. In this mode, the BUSY
/INT pin assumes its BUSY function. BUSY goes low at the start

of conversion, stays low during the conversion and returns high

when the conversion is complete. It is normally used in parallel
interfaces to drive the microprocessor into a WAIT state for the
duration of conversion. Mode 2 is not relevant for the AD7870A
device.
Figure 16 shows the Mode 2 timing diagram for the 12-bit
parallel data output format (12/8/CLK = +5 V). In this case, the
ADC behaves like slow memory. The major advantage of this
interface is that it allows the microprocessor to start conversion,
WAIT and then read data with a single READ instruction. The
user does not have to worry about servicing interrupts or
ensuring that software delays are long enough to avoid reading
during conversion.

Rev. C | Page 15 of 28

AD7870/AD7875/AD7876
TRACK-AND-HOLD
GOES INTO HOLD

CS

t18

t15
RD

tCONVERT
t16

TRACK-AND-HOLD RETURNS TO TRACK

AND ACQUISITION TIME BEGINS

BUSY

t7
t17
THREE-STATE

VALID
DATA

07730-016

DATA

DB11 TO DB0

Figure 16. Mode 2 Timing Diagram, 12-Bit Parallel Read

HBEN1

t8

t19

t20

TRACK-AND-HOLD
GOES INTO HOLD

CS

t2

t15

t6

t18

RD

tCONVERT

t16

TRACK-AND-HOLD RETURNS TO TRACK

AND ACQUISITION TIME BEGINS

BUSY

t17

THREE-STATE

t7

VALID
DATA
DB7 TO DB0

DATA

t7

t6

VALID
DATA
DB11 TO DB8

SSTRB2

t10

t11

t13

SCLK3

t12
SDATA2

LEADING
ZEROS

t14
DB11 DB10

DB0

SERIAL DATA

t15, t16, AND t20 ARE THE SAME FOR A HIGH BYTE READ AS FOR A LOW BYTE READ.
2EXTERNAL 4.7k PULL-UP RESISTOR.

1TIMES

3EXTERNAL 2k PULL-UP RESISTOR;

07730-017

CONTINUOUS SCLK (DASHED LINE) WHEN 12/8/CLK = 5V;

NONCONTINUOUS WHEN 12/8/CLK = 0V.

Figure 17. Mode 2 Timing Diagram, Byte or Serial Read

The Mode 2 timing diagram for byte and serial data is shown in
Figure 17. For a two-byte data read, the lower byte (DB0 DB7)
has to be accessed first since HBEN must be low to start conversion. The ADC behaves like slow memory for this first read,
but the second read to access the upper byte of data is a normal
read. Operation of the serial functions is identical between
Mode 1 and Mode 2. The timing diagram of Figure 17 shows
both a noncontinuously and a continuously running SCLK
(dashed line).

DYNAMIC SPECIFICATIONS
The AD7870 and AD7875 are specified and 100% tested for
dynamic performance specifications as well as traditional dc
specifications such as integral and differential nonlinearity.
Although the AD7876 is not production tested for ac
parameters, its dynamic performance is similar to the AD7870
and AD7875. The ac specifications are required for signal
processing applications such as speech recognition, spectrum
analysis and high speed modems. These applications require
information on the ADCs effect on the spectral content of the

input signal. Thus, the parameters for which the AD7870 and
AD7875 are specified include SNR, harmonic distortion,
intermodulation distortion and peak harmonics. These terms
are discussed in more detail in the following sections.

Signal-to-Noise Ratio (SNR)

SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up
to half the sampling frequency (FS/2) excluding dc. SNR is
dependent upon the number of quantization levels used in
the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal-to-noise ratio for
a sine wave input is given by
SNR = (6.02N + 1.76) dB

(1)

where N is the number of bits. Thus for an ideal 12-bit

converter, SNR = 74 dB.
Note that a sine wave signal is of very low distortion to the VIN
input which is sampled at a 100 kHz sampling rate. A fast

Rev. C | Page 16 of 28

AD7870/AD7875/AD7876
Fourier transform (FFT) plot is generated from which the SNR
data can be obtained. Figure 18 shows a typical 2048 point FFT
plot of the AD7870KN/AD7875KN with an input signal of 25 kHz
and a sampling frequency of 100 kHz. The SNR obtained from
this graph is 72.6 dB. It should be noted that the harmonics are
taken into account when calculating the SNR.
0

INPUT FREQUENCY = 25kHz

SAMPLE FREQUENCY = 100kHz
SNR = 72.6dB
TA = 25C

SIGNAL AMPLITUDE (dB)

30

THD is the ratio of the rms sum of harmonics to the rms

value of the fundamental. For the AD7870/AD7875, THD is
defined as

THD = 20 log

V2 2 + V3 2 + V 4 2 + V5 2 + V 6 2
V1

where V1 is the rms amplitude of the fundamental and V2, V3,

V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic. The THD is also derived from the FFT plot of
the ADC output spectrum.

60

Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation terms are those
for which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa fb), while the
third order terms include (2fa + fb), (2fa fb), (fa + 2fb) and
(fa 2fb).

90

140

07730-018

120

25
FREQUENCY (kHz)

50

Figure 18. FFT Plot

Effective Number of Bits

The formula given in Equation 1 relates SNR to the number of
bits. Rewriting the formula, as in Equation 2, it is possible to get
a measure of performance expressed in effective number of
bits (N).

N=

SNR 1.76

(2)

6.02

The effective number of bits for a device can be calculated

directly from its measured SNR.
Figure 19 shows a typical plot of effective number of bits vs.
frequency for an AD7870KN/AD7875KN with a sampling
frequency of 100 kHz. The effective number of bits typically
falls between 11.7 and 11.85 corresponding to SNR figures of
72.2 and 73.1 dB.
12.0

11.5

11.0

Using the CCIF standard, where two input frequencies near the
top end of the input bandwidth are used, the second and third
order terms are of different significance. The second order
terms are usually distanced in frequency from the original sine
waves while the third order terms are usually at a frequency
close to the input frequencies. As a result, the second and third
order terms are specified separately. The calculation of the
intermodulation distortion is as per the THD specification
where it is the ratio of the rms sum of the individual distortion
products to the rms amplitude of the fundamental expressed in
dBs. In this case, the input consists of two, equal amplitude, low
distortion sine waves. Figure 20 shows a typical IMD plot for
the AD7870/AD7875.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to FS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor the peak is a
noise peak.

10.5
SAMPLE FREQUENCY = 100kHz
TA = 25C
10.0

6.25

12.5

18.75

25.0

07730-019

EFFECTIVE NUMBER OF BITS

Total Harmonic Distortion (THD)

31.25

37.5

43.75

50.0

INPUT FREQUENCY (kHz)

Figure 19. Effective Number of Bits vs. Frequency

Rev. C | Page 17 of 28

AD7870/AD7875/AD7876

SIGNAL AMPLITUDE (dB)

30

INPUT FREQUENCIES
F1 = 9.05kHz
F2 = 9.55kHz
SAMPLING FREQUENCY = 100kHz
TA = 25C

60

IMD
ALL TERMS = 90.06dB
SECOND ORDER TERMS = 92.73dB
THIRD ORDER TERSM = 93.45dB

V(i), the estimated code transition point, is derived as follows:

V (i ) = A Cos

[ cum (i )]
N

where:
A is the peak signal amplitude.
N is the number of histogram samples.
cum(i) =

90

i
n=0

V (n ) occurrences.

FREQUENCY (kHz)

Figure 20. IMD Plot

AC Linearity Plot
When a sine wave of specified frequency is applied to the VIN
input of the AD7870/AD7875 and several million samples are
taken, a histogram showing the frequency of occurrence of each
of the 4096 ADC codes can be generated. From this histogram
data it is possible to generate an ac integral linearity plot as
shown in Figure 21. This shows very good integral linearity
performance from the AD7870/AD7875 at an input frequency
of 25 kHz. The absence of large spikes in the plot shows good
differential linearity. Simplified versions of the formulae used
are outlined below.

V (i ) V (o )

INL (i ) =
4096 i
V ( fs ) V (o )

where:
INL(i) is the integral linearity at code i.
V(fs) and V(o) are the estimated full-scale and offset transitions.
V(i) is the estimated transition for the ith code.

Rev. C | Page 18 of 28

INPUT FREQUENCY = 25kHz

SAMPLE FREQUENCY = 100kHz
TA = 25C
0.25

0.25
07730-021

07730-020

50

AC RELATIVE ACCURACY (LSB)

0.5
120

0.50
0

511

1023

1535

2047
CODE

2559

Figure 21. AC INL Plot

3071

3583

4095

AD7870/AD7875/AD7876
MICROPROCESSOR INTERFACE
TIMER

The AD7870/AD7875/AD7876 have a wide variety of

interfacing options. They offer two operating modes and
three data-output formats. Fast data access times allow
direct interfacing to most microprocessors including the
DSP processors.

PA2
PA0

AD7870/
AD7875/
AD78761

TMS32010

CONVST

PARALLEL READ INTERFACING

MEN

12/8/CLK
BUSY/INT
RD
DB11
DB0

D15

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 23. TMS32010 Parallel Interface

TIMER
A15
A0

ADDRESS BUS

AD7870/
AD7875/
AD78761

TMS32020

CONVST

IS

CS
5V

EN

12/8/CLK
BUSY/INT

INTn
STRB

RD

R/W

DB11
DB0

D15

AD7870/
AD7875/
AD78761

D0

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 24. TMS32020 Parallel Interface

CONVST
ADDR
DECODE

CS

TWO-BYTE READ INTERFACING

5V

EN

IRQn
DMRD

DATA BUS

07730-024

ADDR
DECODE

ADDRESS BUS

ADSP-2100

07730-023

DATA BUS

D0

TIMER

12/8/CLK

68008 Interface

BUSY/INT

Figure 25 shows an 8-bit bus interface for the MC68008 microprocessor. For this interface, the 12/8/CLK input is tied to 0 V
and the DB11/HBEN pin is driven from the microprocessor
least significant address bit. Conversion start control is provided
by the microprocessor. In this interface example, a Move instruction from the ADC address both starts a conversion and reads
the conversion result.

RD

DATA BUS

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 22. ADSP-2100 Parallel Interface

07730-022

DB11
DB0
DMD0

EN

DEN

Some applications may require that conversions be initiated by

the microprocessor rather than an external timer. One option
is to decode the CONVST signal from the address bus so that a
write operation to the ADC starts a conversion. Data is read at
the end of conversion as described earlier. Note: a read
operation must not be attempted during conversion.

DMD15

5V

INT

ADSP-2100: MR0 = DM(ADC)

TMS32010: IN D,ADC
TMS32020: IN D,ADC
MR0 = ADSP-2100 MR0 Register
D = Data Memory Address
ADC = AD7870/AD7875/AD7876 Address

DMS

CS

ADDR
DECODE

Figure 22, Figure 23, and Figure 24 show interfaces to the

ADSP-2100, TMS32010 and the TMS32020 DSP processors.
The ADC is operating in Mode 1, parallel read for all three
interfaces. An external timer controls conversion start asynchronously to the microprocessor. At the end of each conversion
the ADC BUSY/INT interrupts the microprocessor. The
conversion result is read from the ADC with the following
instruction:

DMA13
DMA0

ADDRESS BUS

MOVEW ADC,DO
ADC = AD7870/AD7875/AD7876 address
D0 = 68008 D0 register

Rev. C | Page 19 of 28

AD7870/AD7875/AD7876
This is a two-byte read instruction. During the first read
operation BUSY, in conjunction with CS, forces the microprocessor to WAIT for the ADC conversion. At the end of
conversion the ADC low byte (DB7 DB0) is loaded into
D15 D8 of the D0 register and the ADC high byte (DB15
DB7) is loaded into Bits D7 D0 of the D0 register.

conversion. During conversion, data is valid on the SDATA

output of the ADC and is clocked into the receive data shift
register of the DSP56000. When this register has received
16 bits of data, it generates an internal interrupt on the
DSP56000 to read the data from the register.
AD7870/
AD7875/
AD78761

The following rotate instruction to the D0 register swaps the

high and low bytes to the correct format.

TIMER

5V

R0L = 8, D0.

CONVST
12/8/CLK

2k

SCK

SCLK

SRD

SDATA

ADDRESS BUS
1ADDITIONAL

A0
HBEN

MC68008

Figure 26. DSP56000 Serial Interface

AD7870/
AD7875/
AD78761

12/8/CLK
CONVST

NEC7720/77230 Serial Interface

DB7
DB0

A serial interface between the AD7870/AD7875/AD7876 and

the NEC7720 is shown in Figure 27. In the interface shown, the
ADC is configured for continuous clock operation. This can be
changed to a noncontinuous clock by simply tying the 12/8/CLK
input of the ADC to 0 V with all other connections remaining
the same. The NEC7720 expects valid data on the rising edge of
its SCK input and therefore an inverter is required on the SCLK
output of the ADC. The NEC7720 is configured for a 16-bit
data word. Once the 16 bits of data have been received by the SI
register of the NEC7720, an internal interrupt is generated to
read the contents of the SI register.

EN
DTACK

BUSY/INT
R2
RD

STRB

R/W

D15

1ADDITIONAL PINS OMITTED FOR CLARITY.

2RESISTOR AND CAPACITOR REQUIRED TO GUARANTEE t .
15

07730-025

DATA BUS

D0

PINS OMITTED FOR CLARITY.

The DSP56000 and AD7870/AD7875/AD7876 can also be

configured for continuous clock operation (12/8/CLK = 5 V).
In this case, a strobe pulse is required by the DSP56000 to
indicate when data is valid. The SSTRB output of the ADC
is inverted and applied to the SC1 input of the DSP56000 to
provide this strobe pulse. All other conditions and connections
are the same as for gated clock operation.

CS

ADDR
DECODE

AS

4.7k

Figure 25. MC68008 Byte Interface

SERIAL INTERFACING
Figure 26, Figure 27, Figure 28, and Figure 29 show the
AD7870/AD7875/AD7876 configured for serial interfacing. In
all four interfaces, the ADC is configured for Mode 1 operation.
The interfaces show a timer driving the CONVST input, but
this could be generated from a decoded address if required. The
SCLK, SDAT and SSTRB are open-drain outputs. If these are
required to drive capacitive loads in excess 35 pF, buffering is
recommended.

The NEC77230 interface is similar to that just outlined for the

NEC7720. However, the clock input of the NEC77230 is SICLK.
Additionally, no inverter is required between the ADC SCLK
output and this SICLK input since the NEC77230 assumes data
is valid on the falling edge of SICLK.

DSP56000 Serial Interface

Figure 26 shows a serial interface between the AD7870/AD7875/
AD7876, and the DSP56000. The interface arrangement is
two-wire with the ADC configured for noncontinuous clock
operation (12/8/CLK = 0 V). The DSP56000 is configured
for normal mode asynchronous operation with gated clock.
It is also set up for a 16-bit word with SCK and SC1 as inputs
and the FSL control bit set to a 0. In this configuration, the
DSP56000 assumes valid data on the first falling edge of SCK.
Since the ADC provides valid data on this first edge, there is
no need for a strobe or framing pulse for the data. SCLK and
SDATA are gated off when the ADC is not performing a

AD7870/
AD7875/
AD78761
+5V

TIMER

CONVST
12/8/CLK

PD7720
4.7k

4.7k

2k 5V

SIEN

SSTRB

SCLK

SCLK

SI

SDATA

1ADDITIONAL PINS OMITTED FOR CLARITY.

Rev. C | Page 20 of 28

Figure 27. NEC7720 Serial Interface

07730-027

A15
A0

DSP56000

07730-026

Note that while executing the two-byte read instruction above,

WAIT states are inserted during the first read operation only
and not for the second.

AD7870/AD7875/AD7876
TMS32020 Serial Interface

4.7k

2k

SSTRB

FSR

SDATA

07730-028

SCLK

DR

12/8/CLK
4.7k

2k

4.7k 5V

FSR

SSTRB

CLKR

SCLK

DR

SDATA

1ADDITIONAL PINS OMITTED FOR CLARITY.

The AD7870/AD7875/AD7876 can be used in its Mode 2,

parallel interface mode for standalone operation. In this case,
conversion is initiated with a pulse to the ADC CS input. This
pulse must be longer than the conversion time of the ADC. The
BUSY output is used to drive the RD input. Data is latched from
the ADC DB0DB11 outputs to an external latch on the rising
edge of BUSY.

CONVST

4.7k 5V

CLKR

CONVST

STANDALONE OPERATION

12/8/CLK

TMS32020

ADSP-2101/
ADSP-2102

TIMER

1ADDITIONAL PINS OMITTED FOR CLARITY.

AD7870/
AD7875/
AD78762

Figure 28. TMS32020 Serial Interface

tCS1

ADSP-2101/ADSP-2102 Serial Interface

Figure 29 shows a serial interface between the AD7870/
AD7875/AD7876 and the ADSP-2101/ADSP-2102. The ADC
is configured for continuous clock operation. Data is clocked
into the serial port register of the ADSP-2101/ADSP-2102
during conversion. As with the previous interfaces, when a 16bit data word is received by the ADSP-2101/ADSP-2102 an
internal microprocessor interrupt is generated and the data is
read from the serial port register.

CS
EN
LATCH

BUSY
RD

DB11
DB0
1t
CS > t16 + tCONVERT .
2ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 30. Stand-Alone Operation

Rev. C | Page 21 of 28

07730-030

TIMER

+5V

Figure 29. ADSP-2101/ADSP-2102 Serial Interface

AD7870/
AD7875/
AD78761
5V

AD7870/
AD7875/
AD78761

07730-029

Figure 28 shows a serial interface between the AD7870/

AD7875/AD7876 and the TMS32020. The AD7870/AD7875/
AD7876 is configured for continuous clock operation. Note
that the ADC will not interface correctly to the TMS32020 if the
ADC is configured for a noncontinuous clock. Data is clocked
into the data receive register (DRR) of the TMS32020 during
conversion. As with the previous interfaces, when a 16-bit word
is received by the TMS32020 it generates an internal interrupt
to read the data from the DRR.

AD7870/AD7875/AD7876
APPLICATIONS INFORMATION
Good printed circuit board (PCB) layout is as important as
the overall circuit design itself in achieving high speed analogto-digital performance. The designer has to be conscious of
noise both in the ADC itself and in the preceding analog
circuitry. Switching mode power supplies are not recommended
because the switching spikes feed through to the comparator
causing noisy code transitions. Other causes of concern are
ground loops and digital feedthrough from microprocessors.
These are factors which influence any ADC, and a proper
PCB layout which minimizes these effects is essential for best
performance.

AD7870/AD7875/AD7876 DGND to this single analog

ground point. Do not connect any other digital grounds to
this analog ground point.

LAYOUT HINTS

NOISE

Ensure that the layout for the printed circuit board has the
digital and analog signal lines separated as much as possible.
Take care not to run any digital track alongside an analog signal
track. Guard (screen) the analog input with AGND.

Keep the input signal leads to VIN and signal return leads from
AGND as short as possible to minimize input noise coupling.
In applications where this is not possible, use a shielded cable
between the source and the ADC. Reduce the ground circuit
impedance as much as possible since any potential difference
in grounds between the signal source and the ADC appears as
an error voltage in series with the input signal.

Establish a single point analog ground (star ground) separate

from the logic system ground at the AGND pin or as close
as possible to the ADC. Connect all other grounds and the

Low impedance analog and digital power supply common

returns are essential to low noise operation of the ADC, so
make the foil width for these tracks as wide as possible. The
use of ground planes minimizes impedance paths and also
guards the analog circuitry from digital noise. The circuit
layout has both analog and digital ground planes which are
kept separated and only joined together at the AD7870/
AD7875/AD7876 AGND pin.

Rev. C | Page 22 of 28

AD7870/AD7875/AD7876
OUTLINE DIMENSIONS
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)
24

13

12

0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)

0.100 (2.54)
BSC

0.060 (1.52)
MAX

0.210 (5.33)
MAX

0.195 (4.95)
0.130 (3.30)
0.115 (2.92)

0.015
(0.38)
MIN

0.150 (3.81)
0.130 (3.30)
0.115 (2.92)

0.015 (0.38)
GAUGE
PLANE
SEATING
PLANE

0.022 (0.56)
0.018 (0.46)
0.014 (0.36)

0.005 (0.13)
MIN

0.430 (10.92)
MAX

0.014 (0.36)
0.010 (0.25)
0.008 (0.20)

0.070 (1.78)
0.060 (1.52)
0.045 (1.14)

071006-A

COMPLIANT TO JEDEC STANDARDS MS-001

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 31. 24-Lead Plastic Dual In-Line Package [PDIP]

Narrow Body
(N-24-1)
Dimensions shown in inches and (millimeters)

0.098 (2.49)
MAX
24

13

12

PIN 1
0.200 (5.08)
MAX

0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)

0.310 (7.87)
0.220 (5.59)

1.280 (32.51) MAX

0.060 (1.52)
0.015 (0.38)

0.320 (8.13)
0.290 (7.37)

0.150 (3.81)
MIN

0.100
(2.54)
BSC

0.070 (1.78) SEATING

0.030 (0.76) PLANE

15
0

0.015 (0.38)
0.008 (0.20)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 32. 24-Lead Ceramic Dual In-Line Package [CERDIP]

Narrow Body
(Q-24-1)
Dimensions shown in inches and (millimeters)

Rev. C | Page 23 of 28

100808-A

0.005 (0.13)
MIN

AD7870/AD7875/AD7876
0.180 (4.57)
0.165 (4.19)

0.048 (1.22)
0.042 (1.07)

0.048 (1.22)
0.042 (1.07)

0.056 (1.42)
0.042 (1.07)

4
5

PIN 1
IDENTIFIER

26
25

0.021 (0.53)
0.013 (0.33)

0.050
(1.27)
BSC

TOP VIEW
(PINS DOWN)
11
12

0.020 (0.51)
MIN

0.032 (0.81)
0.026 (0.66)

19
18

0.456 (11.582)
SQ
0.450 (11.430)
0.495 (12.57)
SQ
0.485 (12.32)

0.120 (3.04)
0.090 (2.29)

BOTTOM
VIEW
(PINS UP)

0.430 (10.92)
0.390 (9.91)

0.045 (1.14)
R
0.025 (0.64)

042508-A

COMPLIANT TO JEDEC STANDARDS MO-047-AB

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 33. 28-Lead Plastic Leaded Chip Carrier [PLCC]

(P-28)
Dimensions shown in inches and (millimeters)

15.60 (0.6142)
15.20 (0.5984)

13

24

7.60 (0.2992)
7.40 (0.2913)
12

2.65 (0.1043)
2.35 (0.0925)

0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10

10.65 (0.4193)
10.00 (0.3937)

1.27 (0.0500)
BSC

0.51 (0.0201)
0.31 (0.0122)

SEATING
PLANE

0.75 (0.0295)
0.25 (0.0098)
8
0

0.33 (0.0130)
0.20 (0.0079)

COMPLIANT TO JEDEC STANDARDS MS-013-AD

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 34. 24-Lead Standard Small Outline Package [SOIC_W]

Wide Body
(RW-24)
Dimensions shown in millimeters and (inches)

Rev. C | Page 24 of 28

45

1.27 (0.0500)
0.40 (0.0157)

060706-A

AD7870/AD7875/AD7876
ORDERING GUIDE
Table 7.
Model
AD7870JN

Temperature Range
0C to +70C

VIN Voltage Range

(V)
3

SNR
(dBs)
70 min

Integral
Nonlinearity (LSB)
1/2 typ

Package Description
24-Lead PDIP

Package
Option
N-24-1

AD7870JNZ 1

0C to +70C

70 min

1/2 typ

24-Lead PDIP

N-24-1

AD7870KN
AD7870KNZ1
AD7870LN
AD7870LNZ1
AD7870JP
AD7870JP-REEL
AD7870JPZ1
AD7870JPZ-REEL1
AD7870KP
AD7870KP-REEL
AD7870KPZ1
AD7870KPZ-REEL1
AD7870LP
AD7870LP-REEL
AD7870LPZ1
AD7870AQ
AD7870BQ
AD7870CQ
AD7870TQ
AD7875KN
AD7875KNZ1
AD7875LN
AD7875LNZ1
AD7875KP
AD7875KPZ1
AD7875KPZ-REEL1
AD7875LP-REEL
AD7875LPZ1
AD7875LPZ-REEL1
AD7875BQ
AD7875CQ
AD7875TQ
AD7876BN
AD7876BNZ1
AD7876CN
AD7876CNZ1
AD7876BR
AD7876BR-REEL
AD7876BR-REEL7
AD7876BRZ1
AD7876BRZ-REEL1
AD7876BRZ-REEL71
AD7876CR
AD7876CR-REEL
AD7876CRZ1
AD7876BQ
AD7876TQ

0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
25C to +85C
25C to +85C
25C to +85C
55C to +125C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
40C to +85C
40C to +85C
55C to +125C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
55C to +125C

3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
0 to +5
0 to +5
0 to +5
0 to +5
0 to +5
0 to +5
0 to +5
0 to +5
0 to +5
0 to +5
0 to +5
0 to +5
0 to +5
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10

70 min
70 min
72 min
72 min
70 min
70 min
70 min
70 min
70 min
70 min
70 min
70 min
72 min
72 min
72 min
70 min
70 min
72 min
70 min
70 min
70 min
72 min
72 min
70 min
70 min
70 min
72 min
72 min
72 min
70 min
72 min
70 min

1 max
1 max
1/2 max
1/2 max
1/2 typ
1/2 typ
1/2 typ
1/2 typ
1 max
1 max
1 max
1 max
1/2 max
1/2 max
1/2 max
1/2 typ
1 max
1/2 max
1 max
1 max
1 max
1/2 max
1/2 max
1 max
1 max
1 max
1/2 max
1/2 max
1/2 max
1 max
1/2 max
1 max
1 max
1 max
1/2 max
1/2 max
1 max
1 max
1 max
1 max
1 max
1 max
1/2 max
1/2 max
1/2 max
1 max
1 max

24-Lead PDIP
24-Lead PDIP
24-Lead PDIP
24-Lead PDIP
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
24-Lead CERDIP
24-Lead CERDIP
24-Lead CERDIP
24-Lead CERDIP
24-Lead PDIP
24-Lead PDIP
24-Lead PDIP
24-Lead PDIP
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
24-Lead CERDIP
24-Lead CERDIP
24-Lead CERDIP
24-Lead PDIP
24-Lead PDIP
24-Lead PDIP
24-Lead PDIP
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead CERDIP
24-Lead CERDIP

N-24-1
N-24-1
N-24-1
N-24-1
P-28
P-28
P-28
P-28
P-28
P-28
P-28
P-28
P-28
P-28
P-28
Q-24-1
Q-24-1
Q-24-1
Q-24-1
N-24-1
N-24-1
N-24-1
N-24-1
P-28
P-28
P-28
P-28
P-28
P-28
Q-24-1
Q-24-1
Q-24-1
N-24-1
N-24-1
N-24-1
N-24-1
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
Q-24-1
Q-24-1

Z = RoHS Compliant Part.

Rev. C | Page 25 of 28

AD7870/AD7875/AD7876
NOTES

Rev. C | Page 26 of 28

AD7870/AD7875/AD7876
NOTES

Rev. C | Page 27 of 28

AD7870/AD7875/AD7876
NOTES

19972009 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D07730-0-2/09(C)

Rev. C | Page 28 of 28