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SN65HVD10, SN65HVD10Q, SN75HVD10, SN65HVD11


SN65HVD12, SN75HVD12, SN65HVD11Q, SN75HVD11
SLLS505N FEBRUARY 2002 REVISED JULY 2015

SNx5HVD1x 3.3-V RS-485 Transceivers


1 Features

3 Description

The SN65HVD10, SN75HVD10, SN65HVD11,


SN75HVD11, SN65HVD12, and SN75HVD12 bus
transceivers combine a 3-state differential line driver
and differential input line receiver that operate with a
single 3.3-V power supply. They are designed for
balanced transmission lines and meet or exceed
ANSI standard TIA/EIA-485-A and ISO 8482:1993.
These differential bus transceivers are monolithic
integrated circuits designed for bidirectional data
communication on multipoint bus-transmission lines.
The drivers and receivers have active-high and
active-low enables, respectively, that can be
externally connected together to function as direction
control. Very low device standby supply current can
be achieved by disabling the driver and the receiver.

Operates With a 3.3-V Supply


Bus-Pin ESD Protection Exceeds 16-kV HBM
1/8 Unit-Load Option Available (Up to 256 Nodes
on the Bus)
Optional Driver Output Transition Times for
Signaling Rates (1) of 1 Mbps, 10 Mbps, and
32 Mbps
Meets or Exceeds the Requirements of ANSI
TIA/EIA-485-A
Bus-Pin Short-Circuit Protection From 7 V to
12 V
Low-Current Standby Mode: 1 A, Typical
Open-Circuit, Idle-Bus, and Shorted-Bus Failsafe
Receiver
Thermal Shutdown Protection
Glitch-Free Power-Up and Power-Down Protection
for Hot-Plugging Applications
SN75176 Footprint

The driver differential outputs and receiver differential


inputs connect internally to form a differential input/
output (I/O) bus port that is designed to offer
minimum loading to the bus whenever the driver is
disabled or VCC = 0. These parts feature wide positive
and negative common-mode voltage ranges making
them suitable for party-line applications.

2 Applications

(1)

Device Information(1)

Digital Motor Control


Utility Meters
Chassis-to-Chassis Interconnects
Electronic Security Stations
Industrial Process Control
Building Automation
Point-of-Sale (POS) Terminals and Networks

PART NUMBER

PACKAGE

SN65HVD12
SN75HVD12
SN65HVD11
SN75HVD12
SN65HVD10
SN75HVD10

BODY SIZE (NOM)

SOIC (8)

4.90 mm 3.91 mm

PDIP (8)

9.81 mm 6.35 mm

(1) For all available packages, see the orderable addendum at


the end of the data sheet.

The signaling rate of a line is the number of voltage


transitions that are made per second expressed in the units
bps (bits per second).

Typical Application Diagram


R

RE

DE
D

R
A

A
RT

RT

R RE DE D

RE

DE
D

R RE DE D

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN65HVD10, SN65HVD10Q, SN75HVD10, SN65HVD11


SN65HVD12, SN75HVD12, SN65HVD11Q, SN75HVD11
SLLS505N FEBRUARY 2002 REVISED JULY 2015

www.ti.com

Table of Contents
1
2
3
4
5
6
7

Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11

8
9

1
1
1
2
3
3
4

Absolute Maximum Ratings ...................................... 4


ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Driver Electrical Characteristics ................................ 6
Receiver Electrical Characteristics ........................... 7
Power Dissipation Characteristics ............................ 7
Driver Switching Characteristics ............................... 8
Receiver Switching Characteristics........................... 9
Dissipation Ratings ................................................. 9
Typical Characteristics .......................................... 10

Parameter Measurement Information ................ 12


Detailed Description ............................................ 18

9.1
9.2
9.3
9.4

Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................

18
18
18
18

10 Application and Implementation........................ 20


10.1 Application Information.......................................... 20
10.2 Typical Application ................................................ 21

11 Power Supply Recommendations ..................... 24


12 Layout................................................................... 24
12.1 Layout Guidelines ................................................. 24
12.2 Layout Example .................................................... 25
12.3 Thermal Considerations ........................................ 25

13 Device and Documentation Support ................. 27


13.1
13.2
13.3
13.4
13.5
13.6

Device Support......................................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................

27
27
27
27
27
27

14 Mechanical, Packaging, and Orderable


Information ........................................................... 28

4 Revision History
Changes from Revision M (July 2013) to Revision N

Page

Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Revision L (July 2013) to Revision M

Page

Changed the VIT+ TYP value From: 0.65 V To: 0.065 V ................................................................................................... 7

Changes from Revision K (September 2011) to Revision L

Page

Added TYP = 0.65 V to VIT+ ................................................................................................................................................ 7

Added TYP = 0.1 V to VIT ................................................................................................................................................... 7

Changes from Revision J (February 2009) to Revision K

Page

Added new section 'LOW-POWER STANDBY MODE', in the Application Information section........................................... 19

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Copyright 20022015, Texas Instruments Incorporated

Product Folder Links: SN65HVD10 SN65HVD10Q SN75HVD10 SN65HVD11 SN65HVD12 SN75HVD12


SN65HVD11Q SN75HVD11

SN65HVD10, SN65HVD10Q, SN75HVD10, SN65HVD11


SN65HVD12, SN75HVD12, SN65HVD11Q, SN75HVD11
www.ti.com

SLLS505N FEBRUARY 2002 REVISED JULY 2015

5 Device Comparison Table


PART NUMBER

SIGNALING RATE

UNIT LOADS

SN65HVD10P

32 Mbps

1/2

SN65HVD11D

SN65HVD11P

10 Mbps

1/8

SN65HVD12D

SN65HVD12P

1 Mbps

1/8

VP12

SN75HVD10D

SN75HVD10P

32 Mbps

1/2

VN10

SN75HVD11D

SN75HVD11P

10 Mbps

1/8

SOIC (1)

PDIP

SN65HVD10D

TA

SOIC MARKING
VP10

40C to 85C

0C to 70C

VP11

VN11

SN75HVD12D

SN75HVD12P

1 Mbps

1/8

VN12

SN65HVD10QD

SN65HVD10QP

32 Mbps

1/2

VP10Q

SN65HVD11QD

SN65HVD11QP

10 Mbps

1/8

(1)

40C to 125C

VP11Q

The D package is available as a tape and reel. Add an R suffix to the part number (that is, SN75HVD11DR) for this option.

6 Pin Configuration and Functions


D or P Package
8-Pin SOIC or PDIP
Top View

R
RE
DE
D

VCC
B
A
GND

Pin Functions
PIN
NAME

NO.

TYPE

DESCRIPTION

Bus input/output

Driver output or receiver input (complementary to B)

Bus input/output

Driver output or receiver input (complementary to A)

Digital input

Driver data input

DE

Digital input

Active-high driver enable

GND

Reference potential

Local device ground

Digital output

Receive data output

RE

Digital input

VCC

Supply

Copyright 20022015, Texas Instruments Incorporated

Active-low receiver enable


3-V to 3.6-V supply

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SN65HVD11Q SN75HVD11

SN65HVD10, SN65HVD10Q, SN75HVD10, SN65HVD11


SN65HVD12, SN75HVD12, SN65HVD11Q, SN75HVD11
SLLS505N FEBRUARY 2002 REVISED JULY 2015

www.ti.com

7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted
VCC

(1) (2)

Supply voltage
Voltage at A or B

IO

MIN

MAX

UNIT

0.3

14

Input voltage at D, DE, R, or RE

0.5

VCC + 0.5

Voltage input, transient pulse, A and B, through 100 , see Figure 22

50

50

11

11

mA

Receiver output current


Continuous total power dissipation

See Dissipation Ratings

TJ

Junction temperature

170

Tstg

Storage temperature

145

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

(2)

7.2 ESD Ratings


VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
Electrostatic
discharge

V(ESD)

(1)
(2)
(3)

Pins 5, 6, and 7

16000

All pins

4000

Charged device model (CDM), per JEDEC specification


JESD22-C101 (2)

All pins

1000

Electrical fast transient/burst (3)

Pins 5, 6, and 7

UNIT

4000

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Tested in accordance with IEC 61000-4-4.

7.3 Recommended Operating Conditions


over operating free-air temperature range unless otherwise noted
MIN
VCC

Supply voltage

VI or VIC

Voltage at any bus terminal (separately or common mode)

VIH

High-level input voltage

VIL
VID

12

VCC

Low-level input voltage

D, DE, RE

0.8

Differential input voltage

See Figure 18

12

12

Driver

60

IOL

Low-level output current

RL

Differential load resistance

CL

Differential load capacitance


Signaling rate

(1)
(2)

Junction temperature

Receiver

mA

Driver

60

Receiver

8
54

UNIT

3.6

D, DE, RE

High-level output current

(2)

MAX

7 (1)

IOH

TJ

NOM

mA

60
50

pF

HVD10

32

HVD11

10

HVD12

1
145

Mbps
C

The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
See thermal characteristics table for information regarding this specification.

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Copyright 20022015, Texas Instruments Incorporated

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SN65HVD11Q SN75HVD11

SN65HVD10, SN65HVD10Q, SN75HVD10, SN65HVD11


SN65HVD12, SN75HVD12, SN65HVD11Q, SN75HVD11
www.ti.com

SLLS505N FEBRUARY 2002 REVISED JULY 2015

7.4 Thermal Information


SNx5HVD1xx
THERMAL METRIC

D (SOIC) P (PDIP)
8 Pins

RJA

Junction-to-ambient thermal resistance (1)

RJB

Junction-to-board thermal resistance

RJC

Junction-to-case thermal resistance

(1)
(2)
(3)

HighK board (2), No airflow


No airflow
See

121

(3)

HighK board

UNIT

8 Pins
93

67

(3)

57
41

55

C/W
C/W
C/W

The intent of RJA specification is solely for a thermal performance comparison of one package to another in a standardized
environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment.
JSD517, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
JESD5110, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements.

Copyright 20022015, Texas Instruments Incorporated

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SN65HVD11Q SN75HVD11

SN65HVD10, SN65HVD10Q, SN75HVD10, SN65HVD11


SN65HVD12, SN75HVD12, SN65HVD11Q, SN75HVD11
SLLS505N FEBRUARY 2002 REVISED JULY 2015

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7.5 Driver Electrical Characteristics


over recommended operating conditions unless otherwise noted
PARAMETER
VIK

TEST CONDITIONS

Input clamp voltage

II = 18 mA

Differential output voltage (2)

RL = 54 , See Figure 11

1.5

Vtest = 7 V to 12 V, See Figure 12

1.5

Change in magnitude of differential output


voltage

VOC(PP)

Peak-to-peak common-mode output voltage

VOC(SS)

Steady-state common-mode output voltage

VOC(SS)

Change in steady-state common-mode


output voltage

IOZ

High-impedance output current

II

Input current

IOS

Short-circuit output current

7 V VO 12 V

C(OD)

Differential output capacitance

VOD = 0.4 sin(4E6t) + 0.5 V, DE at 0 V

(1)
(2)

See Figure 11 and Figure 12

VCC
V

0.2

0.2
400

See Figure 13

UNIT
V

|VOD|

ICC

MAX

1.5

IO = 0
|VOD|

MIN TYP (1)

V
mV

1.4

2.5

0.05

0.05

See receiver input currents


D
DE

Supply current

100

100

250

250
16

A
mA
pF

RE at VCC,
D and DE at VCC,
No load

Receiver disabled and


driver enabled

15.5

mA

RE at VCC,
D at VCC,
DE at 0 V,
No load

Receiver disabled and


driver disabled
(standby)

RE at 0 V,
D and DE at VCC,
No load

Receiver enabled and


driver enabled

15.5

mA

All typical values are at 25C and with a 3.3-V supply.


For TA > 85C, VCC is 5%.

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SN65HVD11Q SN75HVD11

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SN65HVD12, SN75HVD12, SN65HVD11Q, SN75HVD11
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SLLS505N FEBRUARY 2002 REVISED JULY 2015

7.6 Receiver Electrical Characteristics


over recommended operating conditions unless otherwise noted
PARAMETER

TEST CONDITIONS

VIT+

Positive-going input threshold voltage

IO = 8 mA

VIT

Negative-going input threshold


voltage

IO = 8 mA

Vhys

Hysteresis voltage (VIT+ VIT)

VIK

Enable-input clamp voltage

II = 18 mA

VOH

High-level output voltage

VID = 200 mV, IOH = 8 mA, see Figure 18

VOL

Low-level output voltage

VID = 200 mV, IOL = 8 mA, see Figure 18

IOZ

High-impedance-state output current

VO = 0 or VCC, RE at VCC

MIN

TYP (1)

MAX

0.065

0.01

0.2

35

VA or VB = 7 V

2.4

HVD11, HVD12,
Other inputs at 0 V

HVD10,
Other inputs at 0 V

0.06

0.13

0.05

0.04
0.2

0.5

0.25

0.5

0.4

0.2
0.15

VA or VB = 7 V, VCC = 0 V

0.4

High-level input current, RE

VIH = 2 V

30

IIL

Low-level input current, RE

VIL = 0.8 V

30

CID

Differential input capacitance

VID = 0.4 sin(4E6t) + 0.5 V, DE at 0 V

(1)

1
0.11

0.05

IIH

Supply current

0.05
0.1

VA or VB = 12 V
VA or VB = 7 V

0.4
1

VA or VB = 7 V, VCC = 0 V
VA or VB = 12 V, VCC = 0 V

ICC

mV

1.5

VA or VB = 12 V, VCC = 0 V

Bus input current

0.1

VA or VB = 12 V

II

UNIT

mA

mA

15

pF

RE at 0 V
D and DE at 0 V
No load

Receiver enabled and driver


disabled

mA

RE at VCC
D at VCC
DE at 0 V
No load

Receiver disabled and driver


disabled (standby)

RE at 0 V
D and DE at VCC
No load

Receiver enabled and driver


enabled

15.5

mA

All typical values are at 25C and with a 3.3-V supply.

7.7 Power Dissipation Characteristics


PARAMETER

PD

Device power dissipation

TEST CONDITIONS
RL= 60 , CL = 50 pF,
DE at VCC, RE at 0 V,
Input to D is a 50% duty-cycle
square wave at indicated signaling
rate

MIN

MAX

198

250

HVD11
(10Mbps)

141

176

HVD12
(500 kbps)

133

161

High-K board, no airflow

D pkg

40

116

No airflow (2)

P pkg

40

123

TA

Ambient air temperature (1)

TJSD

Thermal shutdown junction temperature (1)

(1)
(2)

TYP

HVD10
(32Mbps)

UNIT

165

mW

C
C

See Thermal Characteristics of IC Packages section for an explanation of these parameters.


JESD5110, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements.

Copyright 20022015, Texas Instruments Incorporated

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SN65HVD11Q SN75HVD11

SN65HVD10, SN65HVD10Q, SN75HVD10, SN65HVD11


SN65HVD12, SN75HVD12, SN65HVD11Q, SN75HVD11
SLLS505N FEBRUARY 2002 REVISED JULY 2015

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7.8 Driver Switching Characteristics


over recommended operating conditions unless otherwise noted
MIN

TYP (1)

MAX

HVD10

8.5

16

HVD11

18

25

40

HVD12

135

200

300

HVD10

8.5

16

PARAMETER
Propagation delay time,
low-to-high-level output

tPLH

Propagation delay time,


high-to-low-level output

tPHL

TEST CONDITIONS

HVD11

18

25

40

HVD12

135

200

300

4.5

10

HVD10
Differential output signal
rise time

tr

Differential output signal


fall time

tf

tsk(p)

tsk(pp)

tPZH

tPHZ

tPZL

tPLZ

Pulse skew (|tPHL tPLH|)

(2)

Part-to-part skew

Propagation delay time,


high-impedance-to-highlevel output
Propagation delay time,
high-level-to-highimpedance output
Propagation delay time,
high-impedance-to-lowlevel output
Propagation delay time,
low-level-to-highimpedance output

HVD11

RL = 54 , CL = 50 pF
See Figure 14

10

20

30

HVD12

100

170

300

HVD10

4.5

10

HVD11

10

20

30

HVD12

100

170

300

HVD10

1.5

HVD11

2.5

HVD12

HVD10

HVD11

11

HVD12

100

HVD10

31

HVD11

55

HVD12
HVD10

RL = 110 , RE at 0 V
See Figure 15

ns

ns

ns

ns

ns

ns

25
55

HVD12

300

HVD10

26

HVD11

55

HVD12

300

RL = 110 , RE at 0 V
See Figure 16

ns

300

HVD11

HVD10

UNIT

ns

ns

26

HVD11

75

HVD12

400

ns

tPZH

Propagation delay time, standby-to-high- RL = 110 , RE at 3 V


level output
See Figure 15

tPZL

Propagation delay time, standby-to-lowlevel output

RL = 110 , RE at 3 V
See Figure 16

(1)
(2)

All typical values are at 25C and with a 3.3-V supply.


tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

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SN65HVD11Q SN75HVD11

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SN65HVD12, SN75HVD12, SN65HVD11Q, SN75HVD11
www.ti.com

SLLS505N FEBRUARY 2002 REVISED JULY 2015

7.9 Receiver Switching Characteristics


over recommended operating conditions unless otherwise noted
PARAMETER

TEST CONDITIONS

MIN

TYP (1)

MAX

UNIT

tPLH

Propagation delay time,


low-to-high-level output

HVD10

12.5

20

25

tPHL

Propagation delay time,


high-to-low-level output

HVD10

12.5

20

25

tPLH

Propagation delay time,


low-to-high-level output

HVD11
HVD12

30

55

70

ns

tPHL

Propagation delay time,


high-to-low-level output

HVD11
HVD12

30

55

70

ns

tsk(p)

Pulse skew (|tPHL tPLH|)

tsk(pp)

(2)

Part-to-part skew

tr

Output signal rise time

tf

Output signal fall time

ns

HVD10

1.5

HVD11

HVD12

HVD10

HVD11

15

HVD12

15
CL = 15 pF
See Figure 19

tPZH

(1)

Output enable time to high level

tPZL

(1)

Output enable time to low level


Output disable time from high level

tPLZ

Output disable time from low level


(2)

tPZL

(2)

(1)
(2)

ns

ns

ns

15

tPHZ

tPZH

VID = 1.5 V to 1.5 V


CL = 15 pF
See Figure 19

15

CL = 15 pF, DE at 3 V
See Figure 20

20

ns

15

Propagation delay time, standby-to-highlevel output


CL = 15 pF, DE at 0
Propagation delay time, standby-to-low- See Figure 21
level output

6
s
6

All typical values are at 25C and with a 3.3-V supply


tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

7.10 Dissipation Ratings


PACKAGE

TA 25C
POWER RATING

DERATING FACTOR (1)


ABOVE TA = 25C

TA = 70C
POWER RATING

TA = 85C
POWER RATING

TA = 125C
POWER RATING

D (2)

597 mW

4.97 mW/C

373 mW

298 mW

100 mW

D (3)

990 mW

8.26 mW/C

620 mW

496 mW

165 mW

1290 mW

10.75 mW/C

806 mW

645 mW

215 mW

(1)
(2)
(3)

This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7.

Copyright 20022015, Texas Instruments Incorporated

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SLLS505N FEBRUARY 2002 REVISED JULY 2015

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7.11 Typical Characteristics


70
TA = 25C
RE at VCC
DE at VCC

RL = 54 W
CL = 50 pF
VCC = 3.6 V

60

50
VCC = 3 V

VCC = 3.3 V

40

30

10

15

20

25

30

35

TA = 25C
RE at VCC
DE at VCC

I CC RMS Supply Current mA

I CC RMS Supply Current mA

70

50
VCC = 3 V
VCC = 3.3 V

40

30
0

2.5

Signaling Rate Mbps

TA = 25C
RE at VCC
DE at VCC

5
7.5
Signaling Rate Mbps

10

Figure 2. HVD11 RMS Supply Current vs Signaling Rate


300

RL = 54 W
CL = 50 pF

250

VCC = 3.6 V

I I Bus Input Current mA

I CC RMS Supply Current mA

70

VCC = 3.6 V

60

40

Figure 1. HVD10 RMS Supply Current vs Signaling Rate

RL = 54 W
CL = 50 pF

60
VCC = 3.3 V
50

VCC = 3 V

40

TA = 25C
DE at 0 V

200
VCC = 0 V

150
100
50

VCC = 3.3 V

0
50
100
150

30
100

400
700
Signaling Rate kbps

200
7 65 43 21 0 1 2 3 4 5 6 7 8 9 10 11 12
VI Bus Input Voltage V

1000

Figure 3. HVD12 RMS Supply Current vs Signaling Rate

Figure 4. HVD10 Bus Input Current vs Bus Input Voltage

90

I I Bus Input Current mA

70

150
TA = 25C
DE at 0 V

60
50
40

VCC = 0 V

30
20
10
0

VCC = 3.3 V

10
20
30
40

IOH High-Level Output Current mA

80

TA = 25C
DE at VCC
D at VCC
VCC = 3.3 V

100
50
0
50
100
150

50
60
76 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12
VI Bus Input Voltage V

Figure 5. HVD11 or HVD12 Bus Input Current vs Bus Input


Voltage

10

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200

2
0
2
4
VOH Driver High-Level Output Voltage V

Figure 6. High-Level Output Current vs Driver High-Level


Output Voltage

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Typical Characteristics (continued)


200

2.5
TA = 25C
DE at VCC
D at 0 V
VCC = 3.3 V

160
140

2.4
VOD Driver Differential Output V

I OL Low-Level Output Current mA

180

120
100
80
60
40
20

2.2
2.1
2.0
1.9
1.8
1.7
1.6

0
20
4

2
0
2
4
6
VOL Driver Low-Level Output Voltage V

1.5
40

Figure 7. Low-Level Output Current vs Driver Low-Level


Output Voltage

15
10
35
60
TA Free-Air Temperature C

85

Figure 8. Driver Differential Output vs Free-Air Temperature


600

40
TA = 25C
DE at VCC
D at VCC
RL = 54

35
30

500
HVD12

Enable Time ns

I O Driver Output Current mA

2.3

VCC = 3.3 V
DE at VCC
D at VCC

25
20
15

400
HVD11
300
HVD10
200

10

100

5
0

0
0

0.50

1.50

2.50

3.50

VCC Supply Voltage V

Figure 9. Driver Output Current vs Supply Voltage

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-7

-2

13

V(TEST) Common-Mode Voltage V

Figure 10. Enable Time vs Common-Mode Voltage

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8 Parameter Measurement Information


VCC
II

DE

IOA

VOD

0 or 3 V
B

54 1%

IOB

VI
VOB

VOA

Figure 11. Driver VOD Test Circuit and Voltage and Current Definitions
375 1%

VCC
DE
0 or 3 V

A
VOD

60 1%

+
_ 7 V < V(test) < 12 V

375 1%

Figure 12. Driver VOD With Common-Mode Loading Test Circuit

VCC
DE
Input

27 1%
A

VA

VB
VOC(PP)

27 1%
B

CL = 50 pF 20%

VOC

VOC(SS)

VOC

CL Includes Fixture and


Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle,tr<6ns, tf<6ns, ZO = 50

Figure 13. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
3V

VCC
DE
D
Input
Generator

VI

50

CL = 50 pF 20%

A
B

VOD
RL = 54
1%

CL Includes Fixture
and Instrumentation
Capacitance

1.5 V

VI
tPLH

1.5 V
tPHL

90%
VOD

90%

tr

2V
0V
10%
2 V

0V
10%
tf

Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50

Figure 14. Driver Switching Test Circuit and Voltage Waveforms

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Parameter Measurement Information (continued)


A
3V

3V
S1

VO

VI

1.5 V

1.5 V

B
DE
Input
Generator

VI

50

CL Includes Fixture
and Instrumentation
Capacitance

0V

0.5 V

RL = 110
1%

CL = 50 pF 20%

tPZH
VOH
VO

2.3 V
0V

tPHZ
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50

Figure 15. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
3V

A
3V

VI

3V
1.5 V

VI

S1

1.5 V

VO
DE

Input
Generator

RL = 110
1%

50

0V

tPZL

tPLZ
3V

CL = 50 pF 20%

0.5 V

CL Includes Fixture
and Instrumentation
Capacitance

VO

2.3 V
VOL

Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50

Figure 16. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
375 W 1%
Y
D
0 or 3 V

-7 V < V(TEST) < 12 V


VOD

60 W
1%

Z
DE
375 W 1%
Input
Generator

50 W

50%
tpZH(diff)

VOD (high)
1.5 V

0V
tpZL(diff)

-1.5 V
VOD (low)

The time tPZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.

Figure 17. Driver Enable Time from DE to VOD

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Parameter Measurement Information (continued)


IA

VA + VB
2

VID

VB

VIC

A
R

VA

IO

B
VO

IB

Figure 18. Receiver Voltage and Current Definitions


A
Input
Generator

R
VI

50

1.5 V
0V

VO
CL = 15 pF 20%

RE

CL Includes Fixture
and Instrumentation
Capacitance

Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50
3V
1.5 V

VI

1.5 V
0V

tPLH
VO

tPHL
90% 90%

1.5 V
10%
tr

VOH
1.5 V
10% V
OL

tf

Figure 19. Receiver Switching Test Circuit and Voltage Waveforms

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Parameter Measurement Information (continued)


3V

3V
A

DE
0 V or 3 V

VO

B
RE
Input
Generator

VI

1 k 1%

S1

CL = 15 pF 20%

CL Includes Fixture
and Instrumentation
Capacitance

50

Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50
3V
VI

1.5 V

1.5 V
0V

tPZH(1)

tPHZ
VOH 0.5 V

VOH

D at 3 V
S1 to B

1.5 V

VO

0V
tPZL(1)

tPLZ
3V

VO

1.5 V

VOL +0.5 V

D at 0 V
S1 to A

VOL

Figure 20. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled

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Parameter Measurement Information (continued)


3V
A

0 V or 1.5 V

1.5 V or 0 V

RE

Input
Generator

VI

1 k 1%

VO

S1
CL = 15 pF 20%

CL Includes Fixture
and Instrumentation
Capacitance

50

Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50
3V
1.5 V

VI

0V
tPZH(2)
VOH

A at 1.5 V
B at 0 V
S1 to B

1.5 V

VO

GND
tPZL(2)
3V
1.5 V

VO

A at 0 V
B at 1.5 V
S1 to A

VOL

Figure 21. Receiver Enable Time From Standby (Driver Disabled)


0 V or 3 V
RE

Pulse Generator,
15 s Duration,
1% Duty Cycle
tr, tf 100 ns

100
1%

+
_
DE
3 V or 0 V

NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified.

Figure 22. Test Circuit, Transient Over Voltage Test

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Parameter Measurement Information (continued)


D and RE Inputs

DE Input
VCC

VCC

100 kW
1 kW

1 kW

Input

Input
100 kW

9V
9V

A Input

B Input
VCC

VCC
16 V

16 V
R3

R1

R1

R3

Input

Input
16 V

R2

16 V

A and B Outputs

R2

R Output

VCC

VCC
16 V
5W
Output

Output
9V

16 V

R1/R2

R3

SN65HVD10

9 kW

45 kW

SN65HVD11

36 kW

180 kW

SN65HVD12

36 kW

180 kW

Figure 23. Equivalent Input and Output Schematic Diagrams

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9 Detailed Description
9.1 Overview
The SN65HVD10, SN65HVD11, and SN65HVD12 are 3.3 V, half-duplex, RS-485 transceivers available in 3
speed grades suitable for data transmission up to 32 Mbps, 10 Mbps, and 1 Mbps, respectively.
These devices have active-high driver enables and active-low receiver enables. A standby current of less than
5 A can be achieved by disabling both driver and receiver.

9.2 Functional Block Diagram

9.3 Feature Description


Internal ESD protection circuits protect the transceiver bus terminals against 16-kV Human Body Model (HBM)
electrostatic discharges and 4-kV electrical fast transients (EFT) according to IEC61000-4-4.
The SN65HVD1x half-duplex family provides internal biasing of the receiver input thresholds for open-circuit,
bus-idle, or short-circuit failsafe conditions, and a typical receiver hysteresis of 35 mV.

9.4 Device Functional Modes


When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as
VOD = VA VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pulldown resistor to ground; thus, when left open, the driver is disabled (high-impedance) by
default. The D pin has an internal pullup resistor to VCC; thus, when left open while the driver is enabled, output A
turns high and B turns low.
Table 1. Driver Functions (1)

(1)

18

INPUT

ENABLE

DE

OUTPUTS

Actively drive bus High

Actively drive bus Low

Driver disabled

OPEN

Driver disabled by default

OPEN

Actively drive bus High by default

FUNCTION

H = high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate

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When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA VB is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and lower than the negative input threshold, VIT, the receiver output, R, turns
low. If VID is between VIT+ and VIT, the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven
(idle bus).
Table 2. Receiver Functions (1)

(1)

DIFFERENTIAL INPUT
VID = VA VB

ENABLE
RE

OUTPUT
R

VID > VIT+

Receive valid bus High

VIT < VID < VIT+

Indeterminate bus state

FUNCTION

VID < VIT

Receive valid bus Low

Receiver disabled

OPEN

Receiver disabled by default

Open-circuit bus

Fail-safe high output

Short-circuit bus

Fail-safe high output

H = high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate

9.4.1 Low-Power Standby Mode


When both the driver and receiver are disabled (DE low and RE high) the device is in standby mode. If the
enable inputs are in this state for less than 60 ns, the device does not enter standby mode. This guards against
inadvertently entering standby mode during driver or receiver enabling. Only when the enable inputs are held in
this state for 300 ns or more, the device is assured to be in standby mode. In this low-power standby mode, most
internal circuitry is powered down, and the supply current is typically less than 1 A. When either the driver or the
receiver is re-enabled, the internal circuitry becomes active.

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10 Application and Implementation


NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information


The SN65HVD10, 'HVD11, and 'HVD12 are half-duplex RS-485 transceivers commonly used for asynchronous
data transmissions. The driver and receiver enable pins allow for the configuration of different operating modes.
R

RE

RE

RE

DE

DE

DE

a) Independent driver and


receiver enable signals

b) Combined enable signals for


use as directional control pin

c) Receiver always on

Figure 24. Half-Duplex Transceiver Configurations


a. Using independent enable lines provides the most flexible control as it allows for the driver and the receiver
to be turned on and off individually. While this configuration requires two control lines, it allows for selective
listening into the bus traffic, whether the driver is transmitting data or not.
b. Combining the enable signals simplifies the interface to the controller by forming a single direction-control
signal. In this configuration, the transceiver operates as a driver when the direction-control line is high, and
as a receiver when the direction-control line is low.
c. Only one line is required when connecting the receiver-enable input to ground and controlling only the driverenable input. In this configuration, a node not only receives the data from the bus, but also the data it sends
and can verify that the correct data have been transmitted.

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10.2 Typical Application


An RS-485 bus consists of multiple transceivers connected in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over a
longer cable length.
R

RE

DE
D

R
A

A
RT

RT

R RE DE D

RE

DE
D

R RE DE D

Figure 25. Typical RS-485 Network With Half-Duplex Transceivers


10.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
10.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and bus length, meaning the higher the data rate, the shorter
the cable length; and conversely, the lower the data rate, the longer the cable may be without introducing data
errors. While most RS-485 systems use data rates between 10 kbps and 100 kbps, some applications require
data rates up to 250 kbps at distances of 4000 feet and longer. Longer distances are possible by allowing for
small signal jitter of up to 5 or 10%.
10000
Cable Length (ft)

5%, 10%, and 20% Jitter


1000
Conservative
Characteristics
100

10
100

1k

10k

100k

1M

10M

100M

Data Rate (bps)

Figure 26. Cable Length vs Data Rate Characteristic

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Typical Application (continued)


10.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a nonterminated piece of bus line which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as
shown in Equation 1.
L(STUB) 0.1 tr v c

where

tr is the 10/90 rise time of the driver


v is the signal velocity of the cable or trace as a factor of c
c is the speed of light (3 108 m/s)

(1)

Per Equation 1, Table 3 lists the maximum cable-stub lengths for the minimum-driver output rise-times of the
SN65HVD1x full-duplex family of transceivers for a signal velocity of 78%.
Table 3. Maximum Stub Length
MAXIMUM STUB LENGTH

DEVICE

MINIMUM DRIVER OUTPUT


RISE TIME (ns)

(m)

(ft)

SN65HVD10

0.07

0.23

SN65HVD11

10

0.23

0.75

SN65HVD12

100

2.34

7.67

10.2.1.3 Bus Loading


The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit
load represents a load impedance of approximately 12 k. Because the SN65HVD11 and HVD12 are each 1/8
UL transceivers, it is possible to connect up to 256 receivers to the bus. The SN65HVD10 is a 1/4 UL
transceiver, and up to 64 receivers may be connected to the bus.
10.2.1.4 Receiver Failsafe
The differential receivers of the SN65HVD1x family are failsafe to invalid bus states caused by:
Open bus conditions, such as a disconnected connector
Shorted bus conditions, such as cable damage shorting the twisted-pair together
Idle bus conditions that occur when no driver on the bus is actively driving.
In any of these cases, the differential receiver will output a failsafe logic High state so that the output of the
receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range
does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output
must output a High when the differential input VID is more positive than +200 mV, and must output a Low when
VID is more negative than 200 mV. The receiver parameters which determine the failsafe performance are VIT(+)
and VIT(). As shown in Receiver Electrical Characteristics, differential signals more negative than 200 mV will
always cause a Low receiver output, and differential signals more positive than +200 mV will always cause a
High receiver output.
When the differential input signal is close to zero, it is still above the maximum VIT(+) threshold of 10 mV, and
the receiver output will be High.

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10.2.2 Detailed Design Procedure


To protect bus nodes against high-energy transients, the implementation of external transient protection devices
is therefore necessary. Figure 27 shows a protection circuit against 10-kV ESD (IEC 61000-4-2), 4-kV EFT (IEC
61000-4-4), and 1-kV surge (IEC 61000-4-5) transients.
Vcc
Vcc

10k
1

RE

DIR

DE

TxD

RxD
MCU

Vcc

GND

XCVR

0.1F

R1
TVS

R2
10k

Figure 27. Transient Protection Against ESD, EFT, and Surge Transients
Table 4. Bill of Materials
DEVICE

FUNCTION

ORDER NUMBER
SN65HVD1xD

MANUFACTURER

XCVR

3.3-V, full-duplex RS-485


transceiver

R1, R2

10-, pulse-proof, thick-film CRCW0603010RJNEAHP


resistor

Vishay

TVS

Bidirectional 400-W
transient suppressor

Bourns

CDSOT23-SM712

TI

10.2.3 Application Curve


Figure 28 demonstrates operation of the SN65HVD12 at a signaling rate of 250 kbps. Two SN65HVD12
transceivers are used to transmit data through a 2,000 foot (600 m) segment of Commscope 5524 category 5e+
twisted pair cable. The bus is terminated at each end by a 100- resistor, matching the cable characteristic
impedance.

Driver Input

Driver Output

Receiver Input

Receiver Output

Figure 28. SN65HVD12 Input and Output Through 2000 Feet of Cable

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11 Power Supply Recommendations


To assure reliable operation at all data rates and supply voltages, each supply must be buffered with a 100-nF
ceramic capacitor located as close to the supply pins as possible. The TPS76333 linear voltage regulator is
suitable for the 3.3-V supply.

12 Layout
12.1 Layout Guidelines
On-chip IEC-ESD protection is sufficient for laboratory and portable equipment but never sufficient for EFT and
surge transients occurring in industrial environments. Therefore, robust and reliable bus node design requires the
use of external transient protection devices.
Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, highfrequency layout techniques must be applied during PCB design.
1. Place the protection circuitry close to the bus connector to prevent noise transients from entering the board.
2. Use VCC and ground planes to provide low-inductance. Note that high-frequency currents follow the path of
least inductance and not the path of least impedance.
3. Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
4. Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC pins of transceiver, UART, and
controller ICs on the board.
5. Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via-inductance.
6. Use 1-k to 10-k pull-up or pull-down resistors for enable lines to limit noise currents in these lines during
transient events.
7. Insert pulse-proof series resistors into the A and B bus lines if the TVS clamping voltage is higher than the
specified maximum voltage of the transceiver bus terminals. These resistors limit the residual clamping
current into the transceiver and prevent it from latching up.
8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.

24

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Copyright 20022015, Texas Instruments Incorporated

Product Folder Links: SN65HVD10 SN65HVD10Q SN75HVD10 SN65HVD11 SN65HVD12 SN75HVD12


SN65HVD11Q SN75HVD11

SN65HVD10, SN65HVD10Q, SN75HVD10, SN65HVD11


SN65HVD12, SN75HVD12, SN65HVD11Q, SN75HVD11
www.ti.com

SLLS505N FEBRUARY 2002 REVISED JULY 2015

12.2 Layout Example

Via to ground
Via to VCC

6 R

MCU

6 R
XCVR

JMP

TVS

Figure 29. SN65HVD1x Layout Example

12.3 Thermal Considerations


12.3.1 Thermal Characteristics of IC Packages
RJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient
temperature divided by the operating power.
RJA is not a constant and is a strong function of:
the PCB design (50% variation)
altitude (20% variation)
device power (5% variation)
RJA can be used to compare the thermal performance of packages if the specific test conditions are defined and
used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations,
and the thermal characteristics of holding fixtures. RJA is often misused when it is used to calculate junction
temperatures for other installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition
thermal performance, and it consists of a single copper trace layer 25 mm long and 2-oz thick. The high-k board
gives best case in-use condition, and it consists of two 1-oz buried power planes with a single copper trace layer
25 mm long and 2-oz thick. A 4% to 50% difference in RJA can be measured between these two test cards.
RJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided
by the operating power. It is measured by putting the mounted package up against a copper block cold plate to
force heat to flow from die, through the mold compound into the copper block.
RJC is a useful thermal characteristic when a heatsink is applied to package. It is not a useful characteristic to
predict junction temperature because it provides pessimistic numbers if the case temperature is measured in a
nonstandard system and junction temperatures are backed out. It can be used with RJB in 1-dimensional thermal
simulation of a package system.
RJB (Junction-to-Board Thermal Resistance) is defined as the difference in the junction temperature and the
PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate
structure. RJB is only defined for the high-k test card.
RJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal
resistance (especially for BGAs with thermal balls) and can be used for simple 1-dimensional network analysis of
package system, see Figure 30.
Copyright 20022015, Texas Instruments Incorporated

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Product Folder Links: SN65HVD10 SN65HVD10Q SN75HVD10 SN65HVD11 SN65HVD12 SN75HVD12


SN65HVD11Q SN75HVD11

25

SN65HVD10, SN65HVD10Q, SN75HVD10, SN65HVD11


SN65HVD12, SN75HVD12, SN65HVD11Q, SN75HVD11
SLLS505N FEBRUARY 2002 REVISED JULY 2015

www.ti.com

Thermal Considerations (continued)

Figure 30. PCB Thermal Resistances

26

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Copyright 20022015, Texas Instruments Incorporated

Product Folder Links: SN65HVD10 SN65HVD10Q SN75HVD10 SN65HVD11 SN65HVD12 SN75HVD12


SN65HVD11Q SN75HVD11

SN65HVD10, SN65HVD10Q, SN75HVD10, SN65HVD11


SN65HVD12, SN75HVD12, SN65HVD11Q, SN75HVD11
www.ti.com

SLLS505N FEBRUARY 2002 REVISED JULY 2015

13 Device and Documentation Support


13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

13.2 Related Links


The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS

PRODUCT FOLDER

SAMPLE & BUY

TECHNICAL
DOCUMENTS

TOOLS &
SOFTWARE

SUPPORT &
COMMUNITY

SN65HVD12

Click here

Click here

Click here

Click here

Click here

SN75HVD12

Click here

Click here

Click here

Click here

Click here

SN65HVD11

Click here

Click here

Click here

Click here

Click here

SN65HVD11Q

Click here

Click here

Click here

Click here

Click here

SN75HVD11

Click here

Click here

Click here

Click here

Click here

SN65HVD10

Click here

Click here

Click here

Click here

Click here

SN65HVD10Q

Click here

Click here

Click here

Click here

Click here

SN75HVD10

Click here

Click here

Click here

Click here

Click here

13.3 Community Resources


The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

13.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

13.5 Electrostatic Discharge Caution


These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

Copyright 20022015, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Links: SN65HVD10 SN65HVD10Q SN75HVD10 SN65HVD11 SN65HVD12 SN75HVD12


SN65HVD11Q SN75HVD11

27

SN65HVD10, SN65HVD10Q, SN75HVD10, SN65HVD11


SN65HVD12, SN75HVD12, SN65HVD11Q, SN75HVD11
SLLS505N FEBRUARY 2002 REVISED JULY 2015

www.ti.com

14 Mechanical, Packaging, and Orderable Information


The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

28

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Copyright 20022015, Texas Instruments Incorporated

Product Folder Links: SN65HVD10 SN65HVD10Q SN75HVD10 SN65HVD11 SN65HVD12 SN75HVD12


SN65HVD11Q SN75HVD11

PACKAGE OPTION ADDENDUM

www.ti.com

24-Apr-2015

PACKAGING INFORMATION
Orderable Device

Status
(1)

Package Type Package Pins Package


Drawing
Qty

Eco Plan

Lead/Ball Finish

MSL Peak Temp

(2)

(6)

(3)

Op Temp (C)

Device Marking
(4/5)

SN65HVD10D

ACTIVE

SOIC

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 85

VP10

SN65HVD10DG4

ACTIVE

SOIC

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 85

VP10

SN65HVD10DR

ACTIVE

SOIC

2500

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 85

VP10

SN65HVD10DRG4

ACTIVE

SOIC

2500

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 85

VP10

SN65HVD10P

ACTIVE

PDIP

50

Pb-Free
(RoHS)

CU NIPDAU

N / A for Pkg Type

-40 to 85

65HVD10

SN65HVD10QD

ACTIVE

SOIC

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125

VP10Q

SN65HVD10QDG4

ACTIVE

SOIC

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125

VP10Q

SN65HVD10QDR

ACTIVE

SOIC

2500

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125

VP10Q

SN65HVD10QDRG4

ACTIVE

SOIC

2500

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125

VP10Q

SN65HVD11D

ACTIVE

SOIC

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 85

VP11

SN65HVD11DG4

ACTIVE

SOIC

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 85

VP11

SN65HVD11DR

ACTIVE

SOIC

2500

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 85

VP11

SN65HVD11DRG4

ACTIVE

SOIC

2500

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 85

VP11

SN65HVD11P

ACTIVE

PDIP

50

Pb-Free
(RoHS)

CU NIPDAU

N / A for Pkg Type

-40 to 85

65HVD11

SN65HVD11PE4

ACTIVE

PDIP

50

Pb-Free
(RoHS)

CU NIPDAU

N / A for Pkg Type

-40 to 85

65HVD11

SN65HVD11QD

ACTIVE

SOIC

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125

VP11Q

SN65HVD11QDG4

ACTIVE

SOIC

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125

VP11Q

Addendum-Page 1

Samples

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device

24-Apr-2015

Status
(1)

Package Type Package Pins Package


Drawing
Qty
2500

Eco Plan

Lead/Ball Finish

MSL Peak Temp

(2)

(6)

(3)

Op Temp (C)

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125

TBD

Call TI

Call TI

-40 to 125

Device Marking
(4/5)

SN65HVD11QDR

ACTIVE

SOIC

SN65HVD11QDRG4

ACTIVE

SOIC

SN65HVD12D

ACTIVE

SOIC

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 85

VP12

SN65HVD12DG4

ACTIVE

SOIC

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 85

VP12

SN65HVD12DR

ACTIVE

SOIC

2500

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 85

VP12

SN65HVD12DRG4

ACTIVE

SOIC

2500

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 85

VP12

SN65HVD12P

ACTIVE

PDIP

50

Pb-Free
(RoHS)

CU NIPDAU

N / A for Pkg Type

-40 to 85

65HVD12

SN65HVD12PE4

ACTIVE

PDIP

50

Pb-Free
(RoHS)

CU NIPDAU

N / A for Pkg Type

-40 to 85

65HVD12

SN75HVD10D

ACTIVE

SOIC

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

0 to 70

VN10

SN75HVD10DG4

ACTIVE

SOIC

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

0 to 70

VN10

SN75HVD10DR

ACTIVE

SOIC

2500

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

0 to 70

VN10

SN75HVD10DRG4

ACTIVE

SOIC

2500

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

0 to 70

VN10

SN75HVD10P

ACTIVE

PDIP

50

Pb-Free
(RoHS)

CU NIPDAU

N / A for Pkg Type

0 to 70

75HVD10

SN75HVD11D

ACTIVE

SOIC

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

0 to 70

VN11

SN75HVD11DG4

ACTIVE

SOIC

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

0 to 70

VN11

SN75HVD11DR

ACTIVE

SOIC

2500

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

0 to 70

VN11

SN75HVD11DRG4

ACTIVE

SOIC

2500

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

0 to 70

VN11

SN75HVD12D

ACTIVE

SOIC

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

0 to 70

VN12

Addendum-Page 2

VP11Q

Samples

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device

24-Apr-2015

Status
(1)

Package Type Package Pins Package


Drawing
Qty

Eco Plan

Lead/Ball Finish

MSL Peak Temp

(2)

(6)

(3)

Op Temp (C)

Device Marking
(4/5)

SN75HVD12DG4

ACTIVE

SOIC

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

0 to 70

VN12

SN75HVD12DR

ACTIVE

SOIC

2500

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

0 to 70

VN12

SN75HVD12DRG4

ACTIVE

SOIC

2500

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

0 to 70

VN12

SN75HVD12P

ACTIVE

PDIP

50

Pb-Free
(RoHS)

CU NIPDAU

N / A for Pkg Type

0 to 70

75HVD12

SN75HVD12PE4

ACTIVE

PDIP

50

Pb-Free
(RoHS)

CU NIPDAU

N / A for Pkg Type

0 to 70

75HVD12

(1)

The marketing status values are defined as follows:


ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Addendum-Page 3

Samples

PACKAGE OPTION ADDENDUM

www.ti.com

24-Apr-2015

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD10, SN65HVD11, SN65HVD12 :

Enhanced Product: SN65HVD10-EP, SN65HVD12-EP


NOTE: Qualified Version Definitions:

Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 4

PACKAGE MATERIALS INFORMATION


www.ti.com

1-Oct-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins


Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

SN65HVD10DR

SOIC

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

SN65HVD10QDR

SOIC

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

SN65HVD11DR

SOIC

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

SN65HVD11QDR

SOIC

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

SN65HVD12DR

SOIC

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

SN75HVD10DR

SOIC

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

SN75HVD11DR

SOIC

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

SN75HVD12DR

SOIC

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION


www.ti.com

1-Oct-2014

*All dimensions are nominal

Device

Package Type

Package Drawing

Pins

SPQ

Length (mm)

Width (mm)

Height (mm)

SN65HVD10DR

SOIC

2500

340.5

338.1

20.6

SN65HVD10QDR

SOIC

2500

340.5

338.1

20.6

SN65HVD11DR

SOIC

2500

340.5

338.1

20.6

SN65HVD11QDR

SOIC

2500

340.5

338.1

20.6

SN65HVD12DR

SOIC

2500

340.5

338.1

20.6

SN75HVD10DR

SOIC

2500

340.5

338.1

20.6

SN75HVD11DR

SOIC

2500

340.5

338.1

20.6

SN75HVD12DR

SOIC

2500

340.5

338.1

20.6

Pack Materials-Page 2

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Products

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