TVE-MFE; 19001

Examensarbete 30 hp
Maj 2019

Design and construction of a

voltage source converter for a
laboratory setup

Henrik Lindblom

Masterprogram i förnybar elgenerering

Master Programme in Renewable Electricity Production
 Abstract
Design and construction of a voltage source converter
for a laboratory setup
Henrik Lindblom

Teknisk- naturvetenskaplig fakultet

UTH-enheten The grid stability and reliability is facing new challenges as the
emerging number of intermittent renewable sources connected to the
Besöksadress: grid is increasing. With the introduction of the insulated-gate
Ångströmlaboratoriet
Lägerhyddsvägen 1 bipolar transistor, the three-phase VSC has grown more popular and is
Hus 4, Plan 0 used in many applications.
Postadress: In this thesis a two-Level Voltage Source Converter was designed and
Box 536
751 21 Uppsala constructed with rated IGBT modules at 1200V and 150A. It focuses on
the design, construction and control of said converter. The control
Telefon: is done through the LabVIEW FPGA module. Tests showed that the
018 – 471 30 03 converter is working according to wanted specifications and can be
Telefax: used in a laboratory setup.
018 – 471 30 00

Hemsida:
http://www.teknat.uu.se/student

Handledare: Markus Gabrysch

Ämnesgranskare: Mikael Bergkvist
Examinator: Irina Temiz
TVE-MFE; 19001
Contents

1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Report structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Theory 3
2.1 Voltage source converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Space vectors and reference frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.1 Clarke transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.2 Park transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Phase-locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 dq-current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.1 DC voltage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Bipolar SPWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Design of bidirectional converter 11

3.1 IGBT module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Gate driver - 2SC0108T driver core . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1 Primary side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.2 Half bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.3 Secondary side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.4 Active clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 DC capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4 LabView implementation 19
4.1 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Bipolar SPWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4 abc to dq transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5 Current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5.1 id and iq current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5.2 DC voltage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.6 dq to abc transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.7 Converter safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.8 Real Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5 Results 29
5.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2 id and iq current control test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3 DC voltage control test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6 Conclusions and future work 35

Bibliography 35

Appendix A Low voltage side schematic 38

Appendix B High voltage side schematic 39

Chapter 1

Introduction

1.1 Background
The grid stability and reliability is facing new challenges as the emerging number of grid-connected
intermittent renewable sources to the grid increases. Renewable resources often have an intermit-
tent nature that can affect voltage and frequency fluctuation that varies with weather condition.
Thus, the electric grid cannot rely only on renewable resources unless there is a huge capacity
of electric storage or fast-response dispatchable sources such as hydro power with a dam or gas
turbine.

Power electronics such as the Insulated gate bipolar junction transistor IGBT is considered to be
one of the key technologies when introducing renewable energy sources. Converters built on this is
what allows for efficient integration of renewable energy sources into the grid. They are the core for
voltage-source-converter-high-voltage direct current (VSC-HVDC) transmission technology and it
overcomes the limitations of long distance AC transmission [1].

The VSC is inherently bi-directional in its power flow, meaning that the transmission permits active
and reactive power flow in either direction. It can be controlled to generate or absorb reactive
power independently of the active power flow. There are several applications where the VSC-
HVDC transmission technology can be utilized such as, supply of power to isolated areas without
generating resources, interconnection of two or more asynchronous AC networks and linking remote
offshore wind-power plants to the mainland networks [2].

1.2 Objectives
A three-phase bi-directional AC-DC converter will be designed and constructed with rated IGBT
modules at 1200V and 150A. The constructed converter will be tested and its control will be
implemented in LabVIEW’s FPGA enviroment using a compactRIO. The aim is to build a student
laboratory test setup with said converter, this includes

• Literature survey. The literature survey includes a general description of HVDC technology.
• Construction and testing of the converter. Once built, the converter will be tested both in
rectification mode and in inverter mode.
• Control of the converter. The converter is controlled by a CompactRIO which is setup in the
LabVIEW FPGA environment.

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Uppsala University 2018 CHAPTER 1

1.3 Limitations
This master thesis focuses on the design, construction and control of a three-phase bi-directional
AC-DC converter. The technical aspect of connecting this to the grid is discussed and the theory
revolves around it. However in this thesis the converter will not be connected to the grid but only
tested with a resistive load both for rectifying mode and inverting mode.
The converter control will be used in student laboratories and in the future it will be connected
with another converter to form a HVDC-link. This thesis lays the ground for this implementation
with the control programming being able to control two converters at the same time.

1.4 Report structure

The report begins with an introduction to the HVDC converter and the objectives that guided this
masters thesis, followed by a more in depth description of the theory behind the voltage source
converter and its control.
The following chapters will describe the construction and design of the converter and the control
which is set up in the LabVIEW FPGA environment. Finally the results, finding and reflections
will be presented.

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Chapter 2

Theory

This chapter gives an introduction to the voltage source converter and covers the mathematical
model of the converter, reference frame transformation and control in the dq-reference frame.

2.1 Voltage source converter

Today there exist a wide variety of voltage source converters (VSC). With the introduction of
the insulated-gate bipolar transistor (IGBT) the three-phase VSC has grown more popular and is
today used in many applications.
Diode clamped (NPC), flying capacitors (FCs) and cascaded H-bridge (CHB) are types of three-
phase VSC converters to name a few. All these are multi-level converters and are derived from the
2-level converter which is shown in figure 2.1 and is the one used in this thesis [3].

VDC /2

VDC

2
ia vta

vtb
0
ib vtc
ia
VDC

−VDC /2

Figure 2.1: Schematic of an ideal two-level VSC.

It is called 2-level since the AC sides of the converter can assume two voltage levels, VDC
and −VDC . The converter can supply a bidirectional power flow between the DC-side and the
three-phase AC system [4].
The converter is controlled with pulse width modulation (PWM) as switching strategy. From
this and [4] p. 120 it can be derived that the AC-side terminal voltages of the ideal converter is.

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Uppsala University 2018 CHAPTER 2

VDC
Vta = ma (t)
2
VDC
Vtb = mb (t) (2.1)
2
VDC
Vtc = mc (t)
2
where m(t) is a three-phase balanced modulation signal. With this it is possible to control
active and reactive power flow of the converter. This will be further explained in chapter 2.4.
Figure 2.2 shows the VSC converter connected to the grid and a DC source. It also shows
the current controlled real/reactive power controller. The control is preformed in the dq-frame.
With this configuration the converter can regulate the power flow with simple PI controllers as
compensators.
Seven measurements are needed for the control, phase voltages, phase currents and the DC
voltage. It is also good to monitor the DC current. These are then transformed into the dq-frame
and fed into the compensators which either regulates the currents id and iq or VDC to a reference
value. The compensator then returns the modulation signals in dq-frame. The chosen PWM
strategy takes the signals and output the switching pulses for the IGBTs.

va R L vta
ia iDC

vb
ib
R L vtb VDC
CDC

vc R L vtc
ic

PW M

abc abc
θ θ
PLL
dq dq

vd vq id iq md mq

VDC,ref VDC
Compensators in dq − f rame
id,ref iq,ref

Figure 2.2: Schematic diagram of a current-controlled real-/reactive-power controller in dq-frame.

If the AC system is assumed to be ideal with a balanced sinusoidal three-phase source which
has a constant frequency, the dynamics from of figure 2.2 can be described by

dia
L = vta − va − Ria
dt
dib
L = vtb − vb − Rib (2.2)
dt
dic
L = vtc − vc − Ric
dt
depending on the control strategy, the VSC can be used as either a real-/reactive power con-
troller or a DC voltage controller [4].

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Uppsala University 2018 CHAPTER 2

2.2 Space vectors and reference frame

When controlling a three-phase VSC system some sort of closed loop compensator needs to be
implemented in order to obtain a wanted power flow. If it is desired to control a current i(t) at
i(t)ref that is connected to a three-phase system, it means that it is a sinusoidal signal that needs
to be tracked. In that case the steady-state value varies with time.
The compensator structure for sinusoidal command tracker is far more complex than a DC
command tracker which has a time-invariant steady state value [4]. Therefore, the sinusoidal
signals of a balanced three phase system is converted to a DC-valued signal the control design can
be simplified. A balanced three-phase sinusoidal system can be expressed as

va (t) = V̂ cos(ωt + θ0 )
2π
vb (t) = V̂ cos(ωt + θ0 − ) (2.3)
3
4π
vc (t) = V̂ cos(ωt + θ0 − )
3

If the quantities are voltages then va,b,c are phase voltages and V̂ are the peak values. θ0 is the
initial phase angle. The phases time-response can be seen in figure 2.3 A. This system can in turn
be described by a space vector which is a complex function of time. In polar form it is given by
2 2π 4π
(va (t) + ej 3 vb (t) + ej 3 vc (t))
~v (t) = (2.4)
3
This vector is presented in figure 2.4. The zero-sequence component can normally be disregarded
and therefore it is possible to reduce the three-phase system to a equivalent two-phase system that
has a 90◦ phase-shift [1]. This transformation is called the Clarke transformation [5]. It is also
known as the αβ-frame. If the αβ-frame is then rotated around an angle θ a DC-valued signal is
obtained as seen in figure 2.3 C. This transformation is called the park transformation [6] and it
simplifies the analysis and control of the system.

A B C
1 1
1
0.8 0.8

0.6 0.6
0.8
0.4 0.4

0.2 0.2 0.6

0 0

-0.2 -0.2 0.4

-0.4 -0.4
0.2
-0.6 -0.6

-0.8 -0.8
0
-1 -1

0 0.01 0.02 0.03 0.04 0 0.01 0.02 0.03 0.04 0 0.01 0.02 0.03 0.04
Time [S] Time [S] Time [S]

Figure 2.3: Time response for A) abc reference frame. B) αβ reference frame. C) dq reference frame.

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Uppsala University 2018 CHAPTER 2

Figure 2.4: Space vector in the abc-, αβ- and dq-frame.

2.2.1 Clarke transform

The space vector from equation 2.4 can be rewritten and be given by its real and complex values

~v (t) = vα + jvβ (2.5)

Where vα and vβ are components of the α and β axis as seen in figure 2.4. This transformation
can be written in matrix form as

1 − 13 − 31  
 
 
vα √ √  va
 vβ  = 2  0

3 3  v  (2.6)
2 − 2  b
3
v0 1 1 1 vc
2 2 2
In a balanced system where va + cb + vc = 0 and thus v0 = 0. This transformation preserves the
amplitudes of the variables. If a scaling constant K is introducedq
it is possible to get rms-value
scaling and power-invariant scaling by selecting K = √12 and K = 23 , respectively [1].
The abc-frame can also be represented in terms of αβ. The inverse transform is given by

1 0 1  
 
 
va √  vα
3
 1
 vb  = − 1
 vβ (2.7)
 
 2 2
vc √ v0
− 21 − 23 1

2.2.2 Park transform

The signals are reduced from two to three when applying the Clarke transform but they are still
in general a sinusoidal function of time. If the Park transform is applied then the signals assume
a DC-value whilst in a steady state. It is achieved by rotating the αβ- reference frame around an
angle. This is known as the dq-transform and it is given by

vd + jvq = (vα + vβ )e−jθ(t) (2.8)

Where θ is the phase angle of the grid voltages and is defined as θ(t) = θ0 + ωt. By doing this
vd and vq are not time-varying and from figure 2.4 the following matrix relations can be obtained

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Uppsala University 2018 CHAPTER 2

 
  cos(θ(t)) sin(θ(t)) 0  
vd   vα
vq  = −sin(θ(t)) cos(θ(t)) 1 vβ (2.9)
  

v0 v0
0 0 1
The inverse transform is obtained when rotation of the dq-frame is canceled out. This is done by
multiplying both sides with ejθ(t) and thus changing to rotation direction to clockwise
vα + jvβ = (vd + vq )ejθ(t) (2.10)
The matrix relations can then be written as
 
  cos(θ(t)) −sin(θ(t)) 0  
vα   vd
vβ  = sin(θ(t)) cos(θ(t)) 0
 vq (2.11)
 

v0 v0
0 0 1
In time domain a balanced three phase systems total instantaneous power can be described by
P (t) = va (t)ia (t) + vb (t)ib (t) + vc (t)ic (t) and in [4] the instantaneous complex power is derived to
be
3
S(t) = P (t) + jQ(t) = ~v (t)~i∗ (t) (2.12)
2
Where * denotes the complex conjugate. From 2.10 we get that ~v = (vd + vq )ej θ(t) and ~i∗ =
(id + iq )e− jθ(t) The instantaneous complex is then represented in the dq-frame and is formulated
as
3
P = [vd id + vq iq ]
2 (2.13)
3
Q = [−vd iq + vq id ]
2
It can be observed that if vq = 0 the real and reactive power are proportional to id and iq ,
respectively. This allows for full control of the power flow and is very usable in a three phase VSC
system.

2.3 Phase-locked loop

The phase-locked loop, PLL transforms vabc to vdq and dynamically adjusts the rotational speed
of the dq-frame to keep vq = 0 [4]. The space vector from 2.4 can be written as

~v (t) = V̂ ej(ω+tθ0 ) (2.14)

from 2.14 and 2.8 we get

vd = V̂ cos(ωt + θ0 − θ(t))
(2.15)
vq = V̂ sin(ωt + θ0 − θ(t))
By choosing θ(t) = ωt + θ0 the desired result of keeping vq = 0 is obtained. There are several
different PLL methods available, but synchronous reference frame phase-locked loop, SRF-PLL is
the standard configuration in three phase PLL applications [7]. This was also the one used in this
project. Figure 2.5 shows the block diagram of the SRF-PLL.

vα vd
va a α α d ω

vb b
Δωg ωg
vβ vq
vc c β β q
PI ∫
θ

Figure 2.5: Block diagram for SRF-PLL.

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Uppsala University 2018 CHAPTER 2

The input signal vq is fed into the PI controller which outputs the angular frequency deviation
∆ω. ω = 2πf is then added to this which is finally integrated into θ. As it can be observed in
figure 2.5 and in [1] page 194. θ can be formulated by.
Z Z
θ = ωg dt = ωt + ∆ωg dt (2.16)

2.4 dq-current control

The dq-frame control is based on 2.2. With the help from the selection of θ(t) = ωt + θ0 and the
space vector along with [4] p. 208 the equations can be deduced to

did
L = Lωiq − Rid + vtd − vd
dt (2.17)
diq
L = −Lωid − Riq + vtq − vq
dt
Where vtd and vtq are equation 2.1 in dq-reference frame. Due to the presence of Lω the
dynamics of id and iq are coupled [4] p 219. To decouple the dynamics we can write

2
md = (ud − Lωiq + vd )
VDC
(2.18)
2
mq = (uq + Lωid + vq )
VDC
Two new terms are introduced, ud and uq these are two new control inputs. Figure 2.6 shows
the block diagram implementation of equation 2.18. From 2.17, 2.1 in dq-frame and 2.18 the
following can be deduced

did
L = −Rid + ud
dt (2.19)
did
L = −Riq + uq
dt
These equation describes two first-order, linear systems. Based on them id and iq can be
controlled by ud and uq which can be outputs from a simple PI compensator. In short, they can
be dimensioned by [4] p.221

kp = L/τi
(2.20)
ki = R/τi
Where the time constant τi is a design choice.

vd

ud
id,ref
PI md

id ωL

VDC

2
iq ωL

iq,ref
PI mq

uq

vq

Figure 2.6: Block diagram for dq control. Based on equation 2.18.

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Uppsala University 2018 CHAPTER 2

2.4.1 DC voltage control

Alternatively to controlling id and iq it is also possible to regulate the DC voltage via the currents.
2
Due to the nonlinear characteristics of the model it is chosen to regulate VDC instead of VDC .
Practically this means that the energy is controlled instead voltage. When no control is active on
the converter it acts as an passive rectifier. By applying control it is possible to boost the DC
voltage. Following [8] p. 90 and [9] the following system model can be described as
2
1 dVDC 3
C = vd id − Pload (2.21)
2 dt 2
2
And it turns out from [9] that the transfer function from id to W = VDC is
W 3vd
G(s) = = (2.22)
id sC
From this it is found that a PI controller with only a proportional part can be used to regulate
id,ref with VDC . The values of the compensator can be chosen by
αC
kp = (2.23)
3vd
Where α is given in rad/s and is the bandwidth of the voltage controller [9]. It is also important
to have a small integrator part as well for zero remaining error after a load power step [8]. Figure
2.7 shows the block diagram for the DC voltage controller.

V
2
DCref
PI id,ref

2
V
DC

Figure 2.7: Block diagram for the DC voltage controller.

2.5 Bipolar SPWM

There are many different modulation techniques. Bipolar sinusoidal pulse width modulation,
SPWM is a widely used PWM method. It also achieves reduction in output harmonics. It consist
of a reference signal, which is the wanted output waveform and a triangular carrier signal of con-
stant amplitude and relatively higher frequency. The ratio between them is called the frequency
modulation ratio and is often chosen to be an integer.
The maximum allowed switching voltage is ± VDC 2 and if the reference voltage stays withing
this we have a linear response with the wanted output [3].

Figure 2.8 shows how the pulses are generated for one leg of the converter. The carrier and
reference signal are compared and the switching for the transistor are determined by

VRef erence > VCarrier : T op : ON Bottom : OF F

(2.24)
VRef erence < VCarrier : T op : OF F Bottom : ON

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Uppsala University 2018 CHAPTER 2

1
Refrence
0.5 Carrier

-0.5

-1
0 2 4 6 8 10 12 14 16 18 20
Time [mS]

0.5

0
0 2 4 6 8 10 12 14 16 18 20
Time [mS]

Figure 2.8: Carrier, reference and output signals for SPWM.

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Chapter 3

Design of bidirectional converter

In this thesis a bidirectional converter was built. It is a copy of an already existing converter made
in a previous project. These two are eventually to be connected together to form a HVDC-link.
They are designed with a rated DC voltage of 900V. Some of the parts of it needed to be custom
made. These are the metal sheets that connects all the terminals in the converter and the sheet
that the capacitors are standing on as seen in figure 3.1. The dimensions was measured from the
already existing converter and then and drawn in CAD.
The converter consists of the following main parts: 3x IGBT modules, heat sink, 3x gate drivers,
2x DC capacitors, 2x bleeding resistors and 3x snubber capacitors. The following chapter describes
the function and design choices of the parts.

Figure 3.1: The fully assembled converter.

3.1 IGBT module

The IGBT module consists of two IGBTs connected in series with a reverse diode each. The
IGBT module 2MBI100U4A-120 is manufactured by Fuji Electric Device Technology Co [10]. The
equivalent circuit is shown in figure 3.2. Some of its electrical characteristics and absolute maximum
rating are displayed in the table below.

Table 3.1: Electrical characteristics and ratings for the module

Items Characteristics and Ratings Comment

Collector-Emitter Voltage 1200V max.
Gate-Emitter Voltage ±20V max.
Collector Current 150A max. at 25◦ C
Turn-on time 0.32µs typ.
Turn-off time 0.41µs typ.

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Uppsala University 2018 CHAPTER 3

C1 E2

C2E1

G1 E1 G2 E2

Figure 3.2: Equivalent circuit of the IGBT module.

3.2 Gate driver - 2SC0108T driver core

The 2SC0108T is a dual-driver core that can drive all usual IGBT modules up to 600A/1200V
or 450A/1700V [11]. It was manufactured by CT-Concept until they were acquired by Power
Integrations, Inc in 2012.
The driver core comes with an isolated DC/DC converter, short-circuit protection and supply
voltage monitoring. The circuit board consists of a primary and secondary side that are isolated
from each other. Both of them need some additional circuitry in order to work according to
wanted specifications. The driver was chosen because of its small footprint along with it being
highly flexible and reliable. It allows for a easier converter design that cover the wanted power
ratings.

Figure 3.3: 3D rendering of the 2SC0108T driver core.

The primary side has 8 pins and the secondary side has two 5 pin connectors as seen in figure
3.3. The secondary side connects to one IGBT each in the IGBT module. In total three driver
cores was used in the converter, one for each leg. The following chapters describes the circuitry
design and component sizing.

3.2.1 Primary side

The primary side is the part or the driver core that is connected to the controller, in this case it
is the CompactRIO Controller. It has the following 8 pin interface

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Uppsala University 2018 CHAPTER 3

• GND - Ground

• INA and INB - Drive inputs, PWM

• TB - Blocking time
• VCC - Power-supply terminal
• SO1 and SO2 - Status output

• MOD - Mode selection

Where INA and INB are the gate signals to the IGBTs. They work on a wide range of voltages,
in fact the whole logic-level range between 3.3V and 15V and are triggered on at any edge of a
signal.
Since the 2SC0108T drive core has very fast signal propagation delays of typically < 90ns [12]
it is recommended to add additional RC filters to avoid false gate switching. It is however not
recommended to directly add the filter to the inputs as the jitter of the propagation delay may
increase considerably. A Schmitt trigger can be added to solve this problem. The recommended
circuit diagram without the RC-filter can be seen in figure 3.4.

Figure 3.4: Recommended circuit for primary side [11].

In our design the CD40106B CMOS Hex Schmitt trigger inverter [13] was used. It consists of
six Schmitt trigger inputs with an inverter on each output. Its typical hysteresis voltage VH , is
3.5 V when the supply voltage is VDD = 15 V. The upper and lower voltage threshold VT H,high
and VT H,low is then approximately 9 V and 5.5 V, respectively. The minimum voltage suppression
time at turn-on and turn-off can then be estimated by

VDD
Tmin,on = RC · ln( )
VDD − VT H,high
(3.1)
VDD
Tmin,of f = RC · ln( )
VT H,low

In our case the total resistor and capacitor value for the filter is R = 3 kΩ and C = 100 pF
which results in a minimum voltage suppression for turn-on at Tmin,on = 280 ns and a turn-off at
Tmin,of f = 300ns. Figure 3.5 shows the input part of the primary side schematic.
It has a protective circuit consisting of a current limiting resistor and shottky clipping diodes.
This protects the core from over voltages and short circuits. Since the Schmitt trigger inverts the
input signal it goes through it twice to get the correct value. The full schematic of the low voltage
side schematic can be seen in appendix A.

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Uppsala University 2018 CHAPTER 3

Figure 3.5: Schematic for input signal. With Protection and short pulse rejection. Designed by P.
Nordström and S. Apelfröjd at Uppsala Universitet.

The status outputs, SO1 and S02 are normally high. When a under voltage is detected on
the primary side, both status outputs are pulled to low and are reset when the under voltage
disappears. A supply under voltage or short-circuit of IGBT module on the secondary side is
transmitted to the corresponding status output and reset after the blocking time Tb has elapsed
[11]. In the circuit used in this application both status outputs are connected to a common fault
signal. The blocking time Tb is selected by a resistor connected to the Tb pin on the primary side.
The time value in milliseconds is given by

Tb = Rb − 51 (3.2)
where Rb is given in kilo ohms and in this design it was set to Rb = 82kΩ which result in a blocking
time of Tb = 31µs.

3.2.2 Half bridge mode

The driver core can run in two modes, direct mode and half bridge mode. In direct mode there is
no interdependence between the two channels. The input signal on InA and InB directly control
the gate signals. If not careful this could lead to shorting the DC-link of the converter if the input
signals overlaps each other. A dead time must be implemented in he control circuitry to avoid this
shot-through effect.
The half bridge mode is selected by connecting a resistor 71k < Rm < 181k to the MOD pin.
In our design we chose a resistor of Rm = 140kΩ in parallel with a capacitor Cm = 22nF to reduce
the deviation between the dead times and the rising and falling edges of InA.
In half bridge mode, InA is the drive signal and InB can be seen as a enable input. If InB is low
then both channels are blocked. If it goes high both channels are enabled and follows the signal
on InA. When InA switches from high to low the gate signal, G1 is immediately pulled low and
G2 is goes to high after a dead time Td . The opposite happens when InA goes from low to high.
The signal switching is shown in figure 3.6.

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Uppsala University 2018 CHAPTER 3

15V
InA
0V

15V
InB
0V

15V
G1
-8V

15V
G2
-8V

Figure 3.6: Signals in half-bridge mode.

The dead time is also set by the resistor Td and the time delay is given by,
Rm − 56.4
Td = (3.3)
33
Where Td is given in microseconds and Rm in kilo ohms. A resistor with the value Rm = 140kΩ
results in a blocking time of Td = 2.53µs.

3.2.3 Secondary side

The secondary side is the part that is connected to the IGBT module. It consists of a 5-pin
interface for each driver channel. X stands for the number of the driver channel, 1 or 2.

• VEx - Emiter terminal

• REFx - Reference terminal for over current and short-circuit

• VCEx - Collector sense terminal

• GHx - Gate turn-on terminal
• GLx - Gate turn-off terminal

VEx must be directly connected to the IGBT emitter terminal as seen in figure 3.7. The ref-
erence terminal, REFx sets the threshold for short-circuit and overcurrent protection by placing
a resistor Rth between REFx and VEx. The reference terminal, REFx has a constant current of
150µA and thus a reference voltage can then easily be dimensioned with a resistor. The recom-
mended resistor value of Rth = 68kΩ was chosen. This will protect against short-circuit but not
necessarily overcurrent. It is recommended to realize that protection in the controller design [11].
Inside the driver core there is a comparator circuit that triggers status outputs SOx on the
primary side if the the collector-Emitter saturation voltage, Vce,sat is higher than the voltage on
REFx. The blocking time, Tb immediately starts when a fault is detected.

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Uppsala University 2018 CHAPTER 3

Figure 3.7: Recommended circuit for the secondary side [11].

Since VCEx is connected to the DC rail the current must be limited and not exceed 1mA. The
maximum DC voltage for this converter is set to 900V and a series of three resistor with the total
value RCEx = 780Ω was selected.
When the IGBT is in an off-state the capacitor Cax is precharged/discharged, via internal
transistors, to the negative supply voltage which is -8V referred to VEx. During this time a
current flows through the RCEx resistor network and the diode D11 to the GHx terminal.
During the turn-on of the IGBT the capacitor, Cax is charged to the IGBT saturation voltage
which approximately is Vce,sat = 2.0V. During this charging time the monitor circuit is inactive.
The charging time depends on the DC rail voltage, value of Rax and the capacitor value. From
the application manual [11] the following values was selected, R120kΩ and Cax = 22pF which gives
an typical response time of 6.5µs if VDC > 550V.

Figure 3.8 shows the implementation of the monitoring circuitry and is located on the same
board as in figure 3.5 as they need to be close to the driver core. The 22k resistor is used to provide
a low-impedance path from the IGBT gate to the emitter even if the driver is not supplied with
power [11].

Figure 3.8: Secondary side monitoring circuit. Designed by P. Nordström and S. Apelfröjd at Uppsala
Universitet.

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3.2.4 Active clamping

The 2SC0108T supports basic active clamping. It is a technique that keeps a transient overvoltage
below a predefined threshold voltage when the IGBT turns off. When the collector-emitter voltage
rises above the transient voltage suppressor, TVS diode breakdown voltage the IGBT is partially
turned on and kept in linear operation and thus reducing the overvoltage [14]. The full schematic
of the high voltage side can be seen in appendix B.

Figure 3.9: Secondary side monitoring circuit. Designed by S. Apelfröjd at Uppsala Universitet.

For 1200V IGBTs with DC-link voltages up to 800V it is recommended to have six 150V TVS
diodes where at least one is bidirectional [11]. Five SMBJ154A-TR and one SMP100MC-160 TVS
diode was chosen and should give good clamping results. It is possible to improve the clamping
performance by reducing Rg,of f .

The gate resistors for turn-on and turn-off are separated to set them independently. The
smallest resistor value allowed is 2Ω [15]. Three 21.5Ω in parallel was chosen which gives a total
of Rg,on,of f = 7.17Ω for both turn-on and turn-off resistor.

D5x is a transient voltage suppressor device that protects against high gate-emitter voltages in
the IGBT short-circuit condition.

3.3 DC capacitor
The DC capacitors used are two electrolytic capacitors. The rated voltage is 450V with a capaci-
tance of 3300µF. Connected in series they have a rated voltage of 900V. The bleeding resistors are
there to discharge the electric energy stored in the capacitors when the converter is turned off, for
safety reasons. The resistors have a value of 18kΩ and a power rating of 10W.

Figure 3.10 shows how the capacitors are connected in the converter and is viewed from same
angle as the left figure in fig 3.1. The converter has three layers of metal sheets with a insulating
material between them. The top layer is the positive terminal on the DC side of the converter
and is connected to the top collectors of the IGBT modules and the positive terminal on one of
the capacitors. The bottom layer is the negative terminal on the DC side and is connected to
the bottom emittors of the IGBT modules and the negative side on one the other capacitor. The
middle layer connects the other two layers via the remaining terminals of the capacitors.

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Uppsala University 2018 CHAPTER 3

Figure 3.10: Illustration of how the DC capacitors are connected and a equivalent circuit.

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Chapter 4

LabView implementation

The control of the converter is done through LabVIEW which is a visual programming language
from National Instruments and their compact real-time embedded industrial controller (cRIO).
This consists of a real time (RT) microprocessor controller and I/O FPGA modules [16][17]. The
setup consited of cRIO-9066 as controller, NI-9401 module for digital I/O and NI-9206 as voltage
analog input.
Figure 4.1 shows the user interface the user sees. The graphs to the left shows the measurements
when in DC voltage control mode and the right shows it when in active-/reactive-mode. In the
middle there is a visual representation of a HVDC-link and a block diagram of the control strategy
along with RMS-values of the grid voltages and currents. Finally at the bottom the reference
values are set along with the abillity to tune the PI controllers.

Figure 4.1: User interface for converter control.

4.1 Measurements
The measurement system used in this project comes a from previous student thesis. It measures
voltages through differential measurements and for the current it uses a current transducer. There
is a switch where you can choose between the wire running through the current transducer one or
six times. There are two boxes in total labeled ”box A” and ”box B” [18].

In this project it is important that the rectifier measurements are connected to box A and the
inverter measurements are connected to box B. The voltage and current measurements of phase
a,b and c must also be connected to the U1-U3 and I1-I3 terminals, respectively as seen in figure
4.3. The DC bus measurements must always be connected to the U0 and I0 terminals of box A.

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Uppsala University 2018 CHAPTER 4

Figure 4.2: Measurement box.

Figure 4.3: Data acquisition and calibration.

Table 4.1: Caption

Box A - Rectifier Box B - Inverter

Measurement Pin Measurement Pin
Ua AI3 Ua AI19
Ia AI2 Ia AI18
Ub AI5 Ub AI21
Ib AI4 Ib AI20
Uc AI7 Uc AI23
Ic AI6 Ic AI22
U dc AI1 U dc -
I dc AI0 I dc -

In the FPGA there is a ”Data acquisition and calibration” loop that runs at 4 kHz. It retrieves
the measurements from the cRIO NI 9205 pins according to table 4.1. These are represented by
the pink boxes as seen in figure 4.3. The measurements has a voltage range of ±10V so the values
needs to be scaled to the correct value. A sub VI implements a linear function, y = kx + m which
allows for scaling and offsetting for all the channels. It can also invert the values. they are then
put into two arrays, one for voltages and the other for currents.

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4.2 Bipolar SPWM

Bipolar Sinusoidal pulse width modulation is a technique that compares the three sinusoidal ref-
erence signals to a triangular carrier signal in order to create the switching signals as described
in section 2.5. The carrier signal is generated in its own loop. This is a singe-cycle timed loop
(SCTL) which can be recognized by its clocks on the side of the loop as seen in figure 4.4. The
SCTL executes all the functions in it during one clock cycle [19]. In this case it is set to the on
board clock that is 40MHz. This makes it possible to generate a signal with a accurate frequency
since the execution time for the function is known.

Figure 4.4: Carrier signal generation.

The function of the triangle wave generation subVI is relatively simple. An increment value is
fed into the subVI. In every loop cycle it is added to the previous value and checked if it is in the
range of ±1. If this is true it just continuous like the previous loop. If it is false the function checks
if the accumulated value is < 0 if that is true nothing happens to the input increment value. If it
is false it means that signal is at its top peak and thus the increment value is negated. In short,
first it checks if it is in range. If not it checks if it is on its top peak or bottom peak. This means
that the increment value sets the frequency and its function is given by

increment = fCarrier · 4 · dT (4.1)

Where fCarrier is the wanted frequency and dT is the clock frequency, in this case 40MHz. For
a 4kHz carrier signal a increment value of 0.0004 is selected.

The carrier signal is then compared to either the rectifier reference signals or inverter reference
signals depending on which mode is selected. There will only be an output if the converter is
enabled.
The purple boxes in figure 4.5 are connected to the NI 9401 which is a digital module. The top
three are INA for each gate driver and the bottom three is INB as described in chapter 3.2.2

Figure 4.5: PWM signal generation.

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Uppsala University 2018 CHAPTER 4

4.3 PLL
There is a express VI in the LabVIEW FPGA environment that implements the SRF-PLL discussed
in chapter 2.3. The outputs for the phase are given in pi radians which is a value in radians divided
by pi. This uses fewer resources than radians [20]. The express VI seen in figure 4.6 uses the
following inputs and outputs.

Table 4.2: The inputs and Outputs used in the 3-phase PLL express VI

Inputs Description Outputs Description

reset Resets the PLL frequency in Hz
Input Phase voltages Phase pi radians
PI gains Proportional- and integral gain
Anti-windup sets Anti-windup gain
dt sample time

For a three phase signal with an amplitude of A the tuning is done as follows: Kp , Ki , KA =
12 200 200
A, A , A .

The while loop in figure 4.6 is for box A i.e the rectifier. It takes the phase voltage measurements
and puts them into the PLL which output the phase, θ in pi radians. It also has a feed forward
control, this was however set to zero for the tests. The sinus and cosinus is the directly calculated
for the phase, θ. This saves resources on the FPGA. This loop also runs at 4KHz.

Figure 4.6: Phase locked loop for box A.

4.4 abc to dq transform

The measurements and the PLL phase is retrieved from its respective loop which are fed into the
loop in figure 4.7 where both the voltage and currents first transformed into the αβ-frame and
then into dq-frame. An averaging function is applied to Vd to improve the current control. This
loop also runs at 4KHz.

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Uppsala University 2018 CHAPTER 4

Figure 4.7: abc to dq transform.

The subVI in figure 4.8 implements the Clarke transform given in equation 2.6. It does it in a
resourceful way by minimizing the use of multiplications which are resource demanding.

Figure 4.8: Clarke transform subVI.

The subVI in figure 4.9 implements the Park transform given in equation 2.9. It also does
it in a resourceful way by taking the already calculated values for Sin(θ) and Cos(θ) instead of
calculating it again every time.

Figure 4.9: Park transform subVI.

4.5 Current control

The methods from chapter 2.4 was implemented into LabVIEW. In the program, one can choose
to either control the active-/reactive power using the id and iq current control or the DC voltage.
They were programmed on the FPGA and RT, respectively due resource limitations on the FPGA
and ease of testing.

4.5.1 id and iq current control

With the dq- currents and voltages the controller can be implemented. Since the compensators in
figure 2.6 are identical the same proportional and integral values are used for both of them. L and
id,ref &iq,ref is chosen in the RT front panel. The Figure 4.10 implements the equations given in
2.18.

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Uppsala University 2018 CHAPTER 4

Figure 4.10: Data from FPGA and current control for the inverter.

The PI compensator used is designed to use as few resources on the FPGA as possible. It
does not however have a anti-windup mechanism so the controller runs the risk of running out of
control. The subVI for the PI compensator is shown in figure 4.11. The control is placed in a for
loop that runs once for each compensator.

Figure 4.11: PI compensator SubVI for real-/reactive-power control.

4.5.2 DC voltage control

As mentioned the DC voltage control runs on the RT. That means that we need to exchange data
with the FPGA. That is done through the read/write block to the left in figure 4.12. The needed
input parameters described in 2.4 are then given to the DC controller subVI where the control
takes place.

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Uppsala University 2018 CHAPTER 4

Figure 4.12: Data from FPGA and current control.

Figure 4.13 is the same as the id and iq current control with the addition of the DC voltage
compensator described in chapter 2.4.1. It utilizes a saturation block limiting the maximum id,ref
along with a anti-windup. The other two compensator also has a saturation block that limits the
modulation signals to stay within ± VDC
2 [8].

Figure 4.13: DC voltage control subVI.

The modulation signals are then fed back into the FPGA. Putting the controller on the RT
instead of the FPGA is not the optimal solution as the FPGA runs at a faster clock speed and is
better at timing/syncing [16].

4.6 dq to abc transform

From the current control the reference voltages are obtained in dq reference frame and are divided
by 12 VDC as mentioned in 2.18. They are then transformed into the abc reference frame with a
range of ±1. This is displayed in figure 4.14.

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Uppsala University 2018 CHAPTER 4

Figure 4.14: dq to abc transform

The subVI in figure 4.15 implements the inverse Park transform given in equation 2.11.

Figure 4.15: Inverse Park transform subVI.

The subVI in figure 4.16 implements the inverse Clarke transform given in equation 2.7. It does
it in a resourceful way by minimizing the use of multiplications which are resource demanding.

Figure 4.16: Inverse Clarke transform subVI.

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4.7 Converter safety

It is important to always have some sort of protection to avoid damaging equipment or harming
persons. Since the converters will be used in a laboratory by users that might not have a full
understanding of the equipment’s limitations and function a safety system is in put in place. This
system monitors the peak grid current and the DC bus voltage. figure 4.17 shows the system in
place. It is put in a loop that is set to run as fast as possible in order to detect a fault as fast
as possible. The measurements are compared to a chosen maximum value. If any of these are
triggered a s-r latch is set and disables the converter. In order to start the converter again the
latch must be reset. The ”Enable converter” which is the main ON/OFF switch must also be True
in order for the converter to turn on. ”Converter Active” is the output from this loop and fed into
the SPWM generation loop.

Figure 4.17: Converter safety.

This is a relatively simple safety feature and should not be fully relied on. The capacitors can
hold a lot of charge and there are a lot of exposed areas where a person can be struck and in worst
case be killed by an electric shock. There are bleeding resistors in place which dissipates the charge
in the capacitor so they don’t pose as a threat when it is turned off.
Like with any electrical equipment, the converters should always be approached with caution.

4.8 Real Time

All the measurements and calculations done on the FPGA is transferred to the real time through
the FIFO. Figure 4.18 can be called the producer loop. It requests a defined set of data and when
the FIFO meets this condition the data is released and sorted. It does this for all 30 measurements
and calculations. These are then transferred to the consumer loop in figure 4.19.
The amount of data the user demands defines how many periods will be shown on the graphs.
The FIFO operates at 4KHz this means that it reads 4000 data points every second. If two periods
of a 50Hz signal is to be displayed 160 data points is wanted. This is then multiplied by the amount
of data channels, which is 30. So, to show two periods the amount of data requested from the
FIFO should be 160 · 30 = 4800.

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Uppsala University 2018 CHAPTER 4

Figure 4.18: Data from FIFO.

The consumer loop in figure 4.19 takes this data and does RMS calculations for the grid
measurements. It also displays the data on graphs on the front panel as seen in figure 4.1.

Figure 4.19: Data from FIFO.

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Chapter 5

Results

This section presents the testing of the bidirectional converter in DC voltage control and id and
iq current control over a resistive load. The tests were conducted in a lab environment where they
also will be used in course laboratory work.

5.1 Setup
The setup used for testing is shown in figure 5.1. The voltage supply in the bottom left of the
picture and can supply both a variable DC voltage and three phase AC voltage along with fixed
voltages. It is connected to the grid via a transformer that brings down the line-to-line voltage
from 400V to 230V. The voltage supply is also equipped with breakers up to 10A.
Depending on the selection of controller type, DC voltage control or active-/reactive power
control it is connected to three phase AC supply or DC supply, respectively. The measurement
boxes are then connected to the voltage supply for measurements. Again, box A or box B is used
depending on the type of controller used as mentioned in chapter 4.1. From the box it is connected
to the line inductor, L. This is labeled as a ”load inductor” and has a variety of configurations.
Attempts to estimate the inductance were made and are shown in table 5.1. The line inductor is
connected to the AC side of the converter.
Since the tests in this project never connected to the grid, a resistive load was used for testing
purposes. It is located in the center of figure 5.1, the load is a variable three phase resistive load. To
the far right is the computer on which the user interface is displayed. The computer is connected
to the compactRIO via ethernet.

Table 5.1: Rating of the equipment used for testing.

item rating
VDC 0-220V
Vl−l 0-230V
L 0.072-0.8H
Rload 0-300Ω

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Uppsala University 2018 CHAPTER 5

Figure 5.1: Laboratory test setup.

5.2 id and iq current control test

Two tests were conducted for id and iq current control. One with id = 2 and iq = 0 and another
with a step response of id = 1 − 2 and iq = 0.

A DC voltage was connected to the converter which in turn was connected to a load. Since the
converter is not connected to the grid a simulated three-phase grid was implemented into the
FPGA that the PLL could track. This may effect the results since there is no real grid for the
converter to relate to.
Table 5.1 shows the parameters for the testing results in figure 5.3. Where VDC and IDC is the
supply voltage and vrms and vrms is the load voltage and load current, respectively. From this we
get that the input power is 93.6W and the output power is 88.2W which results in a 94% efficiency
for this test. Figure 5.2 shows the converter voltage at one of its AC output terminal.

Table 5.2: Values for id and iq current control.

item rating item rating

VDC 117V Rload 15Ω
IDC 0.5A Idref 2
vrms 21V Iqref 0
irms 1.4A kp 240
L 0.28H ki 3

50

40

30

20

10
[V]

-10

-20

-30

-40

-50
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time [S]

Figure 5.2: Voltage at the on of the converter AC outputs.

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Figure 5.3 shows the plots from the test with id = 2 and iq = 0 in steady state and they are; a)
is the load voltage and as it can be seen there is a lot disturbances which will manifest themselves
through out the control. b) shows the load current, the peak is at 2A which is the reference id
current since the amplitude variant of the reference frame transform is used. c) Shows the load
voltages in dq-frame and the disturbances from a) are visible, there are high fluctuations of about
±6V for both Vd and Vq . d) shows the load currents in dq-frame and it has the desired outputs
from the reference values. e) Is the PLL and it tracks the simulated three-phase system. It can
be observed that phase a (blue) in a) is at its peak when θ is zero. f) Shows the three modulation
signals and they are not over modulated. They do however jump to zero at times. It is unclear
where this is introduced into the system. It can be due to the programming of the simulated grid.
40 2.5

2
30

1.5
20
1
Load voltage[V]

Load current[V]
10
0.5

0 0

-0.5
-10
-1
-20
-1.5
-30
-2

-40 -2.5
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Time [S] Time [S]

(a) (b)
40 2.5

35
2
30

25
1.5
20
Vd & Vq

Id & Iq

15 1

10
0.5
5

0
0
-5

-10 -0.5
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Time [S] Time [S]

(c) (d)
1
1
0.8
0.8
0.6
0.6
0.4 0.4
ma. mb and mc

0.2 0.2
Theta

0 0

-0.2 -0.2

-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1
-1
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Time [S] Time [S]

(e) (f)

Figure 5.3: a) load voltage b) load current c) Vd Vq d) Id Iq e) Theta from PLL f) modulation
signals ma mb mc .

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Figure 5.4 shows when a step response test was conducted with id going from 1A to 2A and
iq = 0. As it can be seen when the step is initialized at 3s the power drops to about 20W and is
then in steady state right after 4s. Although the controller is responsive there is large disturbances
in the power.
120

100

80
P [W]

60

40

20

0
0 0.5 1 1.5 2 2.5 3 3.5 4
Time [S]

Figure 5.4: Power Step response for id = 1 − 2 and iq = 0.

5.3 DC voltage control test

Table 5.3 shows the parameters for the DC voltage controller test. VDC and IDC is the DC values
when the converter is turned off and act as an passive rectifier. vrms and irms is the grid voltage
and current. L is the estimated line inductance and VDCref is the value the converter regulates
the DC voltage at. The pi controller values are for the inner and outer control, respectively.

Table 5.3: Values for DC voltage control.

item rating
VDC 50V
IDC 0.15A
vrms 23V
irms 0.15A
L 0.28H
Rload 300Ω
VDCef 90
kp 240 and 0.004
ki 3 and 0.003

Figure 5.5 shows the DC voltage at 90V and in steady state with the parameters from table 5.3.
With this setup it was possible to comfortably boost the DC voltage up to 240V. After that it had
problems keeping the voltage steady and current draw started to get to high for the equipment.
Figure 5.6 shows the plots from the test and they are; a) is the grid voltage and as it can be seen
there is some disturbances introduced when the converter is turned on. b) shows the grid current,
it is in phase with the grid voltage which means that only real power is absorbed from the grid.
c) shows the grid voltages in dq-frame. The average is taken on Vd so the value presented is very
consistent while Vq has more disturbances but is at zero which means that the PLL is working
correctly. d) Is the grid current in dq-frame and it shows iq at zero which grants unity power
factor. e) Is the PLL which tracks the grid. It can be observed that phase a (blue) in a) is at its
peak when θ is zero. f) Shows the modulation signals and they are not over modulated.

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95

94

93

92

91

Vdc
90

89

88

87

86

85
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Time [S]

Figure 5.5: DC voltage at steady state.

40 0.8

30 0.6

20 0.4
Grid voltage [V]

Grid current [A]

10 0.2

0 0

-10 -0.2

-20 -0.4

-30 -0.6

-40 -0.8
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Time [S] Time [S]

(a) (b)
35 0.7

30 0.6

25 0.5

20 0.4
Vd & Vq

Id & Iq

15 0.3

10 0.2

5 0.1

0 0

-5 -0.1
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Time [S] Time [S]

(c) (d)
1 0.8

0.8
0.6
0.6
0.4
0.4
ma, mb and mc

0.2
0.2
Theta

0 0

-0.2
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8

-1 -0.8
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Time [S] Time [S]

(e) (f)

Figure 5.6: a) grid voltage b) grid current c) Vd and Id d) id and iq e) PLL f) modulation signals
ma , mb and mc .

33
Uppsala University 2018 CHAPTER 5

Figure 5.7 shows when the converter starts up. In the beginning it acts as a passive rectifier
and is stable at 50V. When it starts the voltage quickly drops to zero and then rises and overshoots
with about 50V to 140V until it settles at the desired 90V. The whole start up sequence takes
about 13 seconds.
150

100
Vdc

50

0
0 2 4 6 8 10 12
Time [S]

Figure 5.7: Start up for DC voltage control.

34
Chapter 6

Conclusions and future work

In this thesis, a two level bidirectional VSC for a laboratory test setup was designed and built. A
control system was also developed to enable the control of active-/reactive power flow along with
a DC voltage control.
The converter was tested both in inverter and rectifier mode connected to a resistive load.
Start-up sequences and power flow step changes was also analyzed with promesing results.

Some conclusions that can be drawn from the design and construction, programming of the control
system and the testing, are the following

• The converter constructed was a copy of an already existing and functioning converter. The
behaviour of the two was found to be similar. Tests showed that the converter was working
according to the wanted specifications and thus, it can be used for laboratory use.

• Using the compactRIO and LabVIEW offers a reliable and convenient method when mea-
suring and processing data. The responsiveness of the control might be affected depending
on if it placed on the FPGA or the real time microprocessor.
• The converter is able to work as an inverter and regulate the current flow to resistive load
using a simulated grid. A lot of harmonics is introduced to the AC load voltage and there
are large fluctuations in the load power.
• The converter is also able to function as an rectifier and regulate the DC voltage over an
resistive load. It has the ability to boost the voltage DC voltage several magnitudes but is
limited when trying to deliver a larger effect. The start up of the converter delivers a large
voltage spike.

There is a wide range of other uses for a VSC converter and for the existing system there is
room for great improvements. Some suggested future works are the following.

• Improve the control and connect the converter to the grid to fully test the ability of controlling
the active-/reactive power flow.

• Connect two converters back-to-back and thus forming a HVDC-link and connect them to
the grid.
• Develop a laboratory test for students where they can observer the behaviour of the converter
when changing parameters such as, PI controller constants, carrier frequency, DC voltages,
etc.

35
Bibliography

[1] K. Sharifabadi et al. Design, Control, and Application of Modular Multilevel Converters for
HVDC Transmission Systems. Wiley - IEEE. Wiley, 2016. isbn: 9781118851562.
[2] J. Arrillaga, Y.H. Liu, and N.R. Watson. Flexible Power Transmission: The HVDC Options.
Wiley, 2007. isbn: 9780470511855. url: https : / / books . google . se / books ? id = 3LZ -
284jCf4C.
[3] Markus Gabrysch. Lecture slides. Inverter Design with Applications. The Faculty Board of
Science and Technology Uppsala University. 2017.
[4] Amirnaser Yazdani and Reza Iravani. Voltage-sourced converters in power systems: modeling,
control, and applications. John Wiley & Sons, 2010.
[5] W. C. Duesterhoeft, M. W. Schulz, and E. Clarke. “Determination of Instantaneous Currents
and Voltages by Means of Alpha, Beta, and Zero Components”. In: Transactions of the
American Institute of Electrical Engineers 70.2 (July 1951), pp. 1248–1255. issn: 0096-3860.
doi: 10.1109/T-AIEE.1951.5060554.
[6] R. H. Park. “Two-reaction theory of synchronous machines generalized method of analysis-
part I”. In: Transactions of the American Institute of Electrical Engineers 48.3 (July 1929),
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[7] S. Golestan, J. M. Guerrero, and J. C. Vasquez. “Three-Phase PLLs: A Review of Recent
Advances”. In: IEEE Transactions on Power Electronics 32.3 (Mar. 2017), pp. 1894–1907.
issn: 0885-8993. doi: 10.1109/TPEL.2016.2565642.
[8] OTTERSTEN ROLF. On Control of Back-to-Back converters and Sensorless Induction Ma-
chine Drives. PhD Thesis, Department of Electric Power Engineering, Chalmers University
of Technology, Göteborg, Sweden. 2003.
[9] Sylvain LECHAT SANJUAN. Voltage Oriented Control of Three-Phase Boost PWM Con-
verters. Department of Electric Power Engineering, Chalmers University of Technology,
Göteborg, Sweden. 2010.
[10] Fuji Electric Device Technology Co. 93193.pdf. http://www.farnell.com/datasheets/
93193.pdf. 2005.
[11] Power Integrations Switzerland GmBH. 2SC0108T Preliminary Description and Application
Manual. Jan. 2018.
[12] Power Integrations Switzerland GmBH. Application with SCALETM -2 and SCALETM -2+
Gate Driver Cores. Apr. 2016.
[13] CD40106B CMOS Hex Schmitt-Triggers Inverters datasheet (Rev. F). http://www.ti.com/
lit/ds/symlink/cd40106b.pdf. Mar. 2017.
[14] Inc Littelfuse. littelfuse tvs diode protection for vfds igbt inverters.pdf. https://www.littelfuse.
com/ ~ /media/electronics/application_notes/littelfuse_tvs_diode_protection_
for_vfds_igbt_inverters.pdf. 2016.
[15] Power Integrations Switzerland GmBH. 2SC0108T2F1(C)-17 Data Sheet. https://gate-
driver.power.com/sites/default/files/product_document/data_sheet/2SC0108T2F1-
17.pdf. 2018.
[16] National instruments. NI LabVIEW Real-Time and FPGA - National Instruments. ftp :
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36
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[17] CompactRIO Systems - National Instruments. http://www.ni.com/sv-se/shop/compactrio.

html.
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SE. July 2018.
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http://zone.ni.com/reference/en-XX/help/371599M-01/lvfpga/fpga_3phase_pll/.
June 2016.

37
 MMXIII Version 4 Rev.2013-10
PinHead IN PinHead HighSide and LowSide Driver Settings
Id Pin Type Info
Direct Mode - Connect Mode-1 and Mode-2
VCC 3, 4, 5 Supply 15V 1W
Appendix A

GND 1,5,6,9 Supply Ground Complimentary Mode - Connect Mode-3 and Mode-4 (Recommended)
INA 2 Controller Driver signal, 15V 5mA
INB 10 Controller Driver signal, 15V 5mA
DF 8 Indicator Error out, 15V (Default Low)

Supply Input with surge protection and small buffer Driver De-coupling
+15V +15V

14
D1

VDD
C2 C7 C3 C4

R7
IC1P
CD

VSS
7
LED1
GND GND

CM
+15V

GND
CORE HIGHSIDE
VCE2
RA1 10 9
RM LV HV VCE2 VCE Rvce

R9
Error out - NOT(SO1 OR SO2) (Normal Low) MOD 8 7
MOD

38
1 2 6 5
3 4 REF2
RTH1 4 3
REF

GND
40106D REF2

+15V
5 6 2 1

+15V
GND
7 8 12 13 T1 SO1
SO1

D11

+15V
9 10 BC847 GL2 GL Goff
GL2
IC1F High Side Driver HV
IN ERROR_OUT_SO1_OR_SO2

TOP SIDE
SO2 VE2 VE

22K_1
R8 SO2 VE2
CA1
VE
GH2 GH Gon
RB GH2
GND TB
TB
Inputs with protection and short pulse rejection

GND
IC1D IC1E
R4 R5 9 8 11 10 INB LOWSIDE
Top Side INB RA2
VCE1 VCE Rvce 10 9
VCE1
C5 40106D 40106D 8 7
D7 6 5

R6
VCC REF1
RTH2 4 3
VCC REF1 REF

GND
+15V
+15V
2 1

D12
GND GND
IC1A IC1B GL1 GL Goff
R1 R2 GL1
Bottom Side 1 2 3 4 INA
INA
C1 40106D 40106D VE1 VE

22K_2
VE1

BOTTOM SIDE
D6 CA2

R3
Low Side Driver HV

GND VE
GND

GND
+15V
GH1 GH Gon

GND
GH1
GND GND
2SC0108T
Low voltage side schematic

MMXIII
2013-10-23
IGBT Driver
UU - Elektricitetslära
P. Norström
S.Apelfröjd

Figure A.1: Designed by P. Nordström and S. Apelfröjd at Uppsala Universitet.

 1 2 3 4 5 6

RVCE2-1 RVCE2-2 RVCE2-3

RG_OFF2-1
A C_HS A
HIGHSIDE RG_OFF2-2
Appendix B
10 9 C2/E1 D32-1 D32-2 D32-3 D42-1 D42-2 D42-3
8 7
RG_OFF2-3
H1 6 5 E2
4
RG_ON2-1
MOUNT-PAD-ROUND4.3 3 G_OFF2
G_HS
2 1 G_ON2
RG_ON2-2

X1-G SHIELD RG_ON2-3

D52
E_HS1
E_HS
X1-9 SV3
S2 10 9
X1-7

GND
ERROR 8 7
X1-6 X1-3

GND GND
B 6 5 B
X1-5 RVCE1-1 RVCE1-2 RVCE1-3

GND
4 3
X1-4 2 1
S1

VCCVCC
X1-2 RG_OFF1-3

GND
X1-1 RG_OFF1-2 D31-1 D31-2 D31-3 D41-1 D41-2 D41-3

VCC
LOWSIDE
10 9 C1
RG_OFF1-1 C_LS
8 7
6

39
5 E_IGBT1
4 3 G_OFF1
2 1 G_ON1
RG_ON1-1

RG_ON1-3

RG_ON1-2 G_LS

C C

D51
VCC VCC VCC E_LS

R1
5
IC1
3
NTC 1
X1-8
C1 1 C2 4
2 OPA642N

2
D D
GND MMXIII
GND GND 2013-10-23
Driver_Mount

Figure B.1: Designed by S. Apelfröjd at Uppsala Universitet.

UU - Elektricitetslära
High voltage side schematic

S.Apelfröjd

1 2 3 4 5 6