A 25GHz 100ns Lock Time Digital LC

PLL with an 8-phase Output Clock

Reza Navid, Mohammad Hekmat, Farshid

Aryanfar, Jason Wei, Vijay Gadde

Rambus Inc., Sunnyvale, CA

2013 VLSI Circuit Symposium June 14, 2013

Outline

• Introduction and motivation

• PLL architecture
• Key components
• Fast-lock features
• Multiphase digitally controlled oscillator

• Measured results
• Conclusions
2013 VLSI Circuits Symposium Navid : C15P3
Slide 2
 Beyond Active Power: Turn-on/off
Slow
Power-up Data Tx Rx
Data
PLL PLL
ref ref
Power-up
Control

• PLLs: Closed-loop, low-bandwidth systems

• Slow power-up and long lock time (-)

• Alternative: Injection locked oscillators

• Fast lock (+)
• Potential spurs due to frequency mismatch (-)
• Poor control of jitter transfer functions (-)
2013 VLSI Circuits Symposium Navid : C15P3
Slide 3

Fast Power-on Digital PLLs

• Digital PLLs (DPLL):
• Easy to adjust loop parameters during power-up
• Easy to store and restore digital numbers
• At wakeup, frequency is “right;” phase is arbitrary
• Adjust phase of feedback clock for faster lock (this work)
• ➔ Shorter lock time (+)

Analog PLL: DPLL: Digital Number

(easy to store)
Ref out
Ref Digital
out TDC DCO
Filter
PFD CP+LF VCO

Digital Control
/N of Loop Parameters
Phase
Adjust Phase Rotator /N
2013 VLSI Circuits Symposium Navid : C15P3
Slide 4
 Multi-phase LC Oscillators
Data Tx Rx
Data
PLL PLL
ref I/Q ref
Phase
Needs a Interpolator
Multiphase Clock

• Conventional multiphase LC oscillators:

• Off-resonance ➔ Phase noise penalty

• This work:
• An area efficient on-resonance design using
magnetic coupling
2013 VLSI Circuits Symposium Navid : C15P3
Slide 5

Overview of This Work

• Two independent components are integrated:
• A fast-lock DPLL
• A multiphase digitally controlled LC oscillator
Differential LC
Oscillator
Ref Multiphase 8 out
Digital
!!PFD
Filter DCO
Fast-Lock
Features m -m
Digital Control
of Loop Parameters

Phase
Calibration /N
State Machine

m m
Magnetic
Coupling

2013 VLSI Circuits Symposium Navid : C15P3

Slide 6
 PLL Architecture: Block Diagram
Synthesized Logic Coarse Step = 0.4%
PLL Control Effective Fine Step = 0.002%

Frequency 5 Coarse
Ref.
Calibration
390MHz
Out
Binary 8 MSB Binary to 255 25GHz
up/dn Digital
Phase Thermometer DCO
Loop Filter Decoder
Detector

Fine
2 LSB By-4 CML
 Prescaler
1.6GHz

Phase Calibration State Machine I/Q By-4 CMOS

and By-4 CMOS Divider Divider

2013 VLSI Circuits Symposium Navid : C15P3

Slide 7

PLL State Diagram

Transitional States
Power Down Reset
Stable States

Frequency
Fast-Lock Calibration
Features
sleep=0
Phase Calibration
Startup
Sequence
Wakeup Sleep
Sequence Bandwidth Control
(~10% power)

Normal sleep=1
Operation

2013 VLSI Circuits Symposium Navid : C15P3

Slide 8
 Phase Calibration Circuitry
Ref Digital Multiphase
!!PFD
Filter DCO

FB ki,kp

Phase
Calibration /N
State Machine

1.6GHz (DSM Clk)

up/dn Phase
Calibration
FB
390MHz I/Q By-4 Phase I/Q 1.6GHz I/Q
Divider Interpolator

Glitch-Free Quadrant Rotators

2013 VLSI Circuits Symposium Navid : C15P3

Slide 9

Phase Calibration Algorithm

Disable Feedback Clock

(fb) Until up=1

Advance Phase of fb in
90o Steps Until up=0

Delay Phase of fb in 22.5o

In 1.6GHz
Steps Until up=1
Domain (90/4=22.5)

Fine-adjust Phase of fb
In 1.6GHz Domain to
Using Phase Interpolator
Preserve Phase
Relationship Between
DSM Clock and FB To Bandwidth
Control
2013 VLSI Circuits Symposium Navid : C15P3
Slide 10
 Multiphase DCO Design
-R IB
OSC3

1X, 2X, 4X, 8X and 16X

OSC0 OSC2
MOM MOM
-M M
-R -R
Cap M1 Cap

M M
5 bits Coarse M2 M2
(binary)
OSC1
-R 255 bits fine 256 256
(thermometer)
+ 1 
Coarse Step = 0.4%
→ Total Coarse = 13%
Effective Fine Step = 0.002%
→ Total Fine = 2%

2013 VLSI Circuits Symposium Navid : C15P3

Slide 11

8-phase DCO Using Magnetic Coupling

-R
OSC2
OSC3
OSC3 OSC1
OSC0 OSC2
-M M
-R -R 45o
Coupling: OSC1 to OSC0
M M

OSC0
OSC1 -M Total Coupling on OSC0
-R

45o Coupling: OSC3 to OSC0

OSC[0-3]
• In-phase coupling results in
on-resonance oscillation and
better phase noise
2013 VLSI Circuits Symposium Navid : C15P3
Slide 12
 8-Port Unified Transformer
Inductor with
half loop inverted
OSC2 OSC3

Inverted half

OSC1
OSC0
Three
identical inductors

• An area-efficient, 4-inductor design occupies

the area of only two inductors
2013 VLSI Circuits Symposium Navid : C15P3
Slide 13

Die Photo

• In a 40nm LP CMOS
process:
• PLL area: 0.1mm2
• DCO area: 0.06 mm2
• Synthesized logic
area: 0.008mm2

2013 VLSI Circuits Symposium Navid : C15P3

Slide 14
 Measured DCO Frequency Curves

25.1GHz

Coarse Code

Fine Linearity:
DNL < 1.5 LSB
21.4GHz
INL < 4 LSB

• DCO achieves a 16% tuning range

2013 VLSI Circuits Symposium Navid : C15P3
Slide 15

Measured DCO Phase Noise

• In-phase coupling ➔ 6-dB improvement

2013 VLSI Circuits Symposium Navid : C15P3
Slide 16
 Measured PLL Phase Noise

Integrated Jitter
= 394fs
(100kHz-100MHz)

2013 VLSI Circuits Symposium Navid : C15P3

Slide 17

Jitter Component Breakdown

2013 VLSI Circuits Symposium Navid : C15P3

Slide 18
 Measured Multiphase Clock

2013 VLSI Circuits Symposium Navid : C15P3

Slide 19

Lock Behavior at Wakeup

• Jitter flat after 100ns

➔ Steady-state (locked)

2013 VLSI Circuits Symposium Navid : C15P3

Slide 20
 Summary and Comparison
[3] [4] [1] [5]
This work
ISSCC 2011 JSSC 2011 JSSC 2010 ISSCC 2009
Circuit Osc. only Osc. only Analog PLL Digital PLL Digital PLL
Technology 65nm CMOS 0.13mm CMOS 40nm LP CMOS 65nm CMOS 40nm LP CMOS
Frequency 56.0-60.5GHz 48.6-52.0GHz 2.7-4.3 GHz 16.4-22.4GHz 21.4-25.1GHz
No. of phases 4 (Quad.) 8 (45 Degrees) 2 (Diff.) 2 (Diff.) 8 (45 Degrees)
PLL area - - - 0.1 mm2 0.1 mm2
PLL power - - - 64mW 64mW
250ns 100ns
PLL lock time - - -
130 ref cycles 40 ref cycles
PLL phase -100dBc/Hz -102dBc/Hz
- - -
noise @ 1MHz @ 1MHz
Integrated PLL 962 fs 394 fs
- - -
jitter .001 to 10GHz 0.1 to 100MHz
Osc. area 0.075mm2 0.09mm2 - - 0.063mm2
Osc. power 22mW 35mW - - 23mW
Osc. phase -117/-115dBC/Hz -128dBc/Hz -119/-117dBc/Hz
- -
noise @10MHz @10MHz @10MHz

2013 VLSI Circuits Symposium Navid : C15P3

Slide 21

Conclusions
• Dynamic power cycling helps to improve
power efficiency

• DPLLs facilitate design for fast power-on:

• A 25GHz DPLL in a 40nm CMOS technology
achieves a 100ns (40 ref. cycles) lock time
• More than 90% power reduction in sleep mode will
help to improve system power efficiency

• An 8-phase area-efficient on-resonance LC

oscillator achieves a 16% tuning range and
phase noise improvement at 25GHz
2013 VLSI Circuits Symposium Navid : C15P3
Slide 22
 Thank You

2013 VLSI Circuit Symposium June 14, 2013

Backup Slides

2013 VLSI Circuit Symposium June 14, 2013

 Beyond Active Power: Turn-on/off

Server CPU
Utilization
Idle Time Rarely
(Idle Power) at 100%

Source:
Luiz Barroso & Urs
Hölzle, IEEE Computer,
December 2007

• For better system power efficiency:

• Dynamic power cycling with fast-turn-on circuits
2013 VLSI Circuits Symposium Navid : C15P3
Slide 25

PLL Architecture: Details

Synthesized Logic
PLL Control
Frequency 5 Coarse
Ref. Calibration
390MHz
KI + Out
BB- up/dn 8 255 25GHz
PFD + Decoder
Fine
DCO

KP 2
Digital 
Clock Div. by 4
Phase 1.6GHz
Prescaler
Calibration

I/Q By-4 Phase I/Q I/Q By-4

Divider Interpolator Divider

Glitch-Free Quadrant Rotators

2013 VLSI Circuits Symposium Navid : C15P3
Slide 26
 Fast-Lock Features
Phase Calibration: Align phase of FB and Ref
Ref Digital Multiphase
!!PFD
Filter DCO

FB ki,kp
Phase
Calibration /N

Bandwidth Control: Adjust loop filter parameters

kp

ki

Time After
Wakeup
2013 VLSI Circuits Symposium Navid : C15P3
Slide 27

Glitch-free Quadrant Rotators

2013 VLSI Circuits Symposium Navid : C15P3

Slide 28
 Electromagnetic Model
P3

P2 P3

m -m

P0
P2
P1 P0 m m

P1

Lumped Model
Fitted Into 3-D EM
Simulation for All Ports

2013 VLSI Circuits Symposium Navid : C15P3

Slide 29

Measured DCO Linearity

• Differential non-linearity better than 1.5 LSB

• Integral non-linearity better than 4 LSB
2013 VLSI Circuits Symposium Navid : C15P3
Slide 30
 Measured Clock Spectrum at 25GHz

2013 VLSI Circuits Symposium Navid : C15P3

Slide 31

Eye Mask

2013 VLSI Circuits Symposium Navid : C15P3

Slide 32
 Lock Behavior at Wakeup

• Reference and feedback clocks are delay-

matched from !!PD input to instrument
2013 VLSI Circuits Symposium Navid : C15P3
Slide 33