ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2010
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2010
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2010
Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Announcements
• Project Preliminary Report #2 due now
• Feedback meetings on Friday 10:30-12
• Exam 2 is April 30
2
Agenda
• Analog & digital CDRs
• Analog dual-loop CDRs
• Digital dual-loop CDRs
• Phase Interpolators
• Delay-Locked Loops
3
Embedded Clock I/O Circuits
• TX PLL
• TX Clock Distribution
• CDR
• Per-channel PLL-based
• Dual-loop w/ Global PLL &
• Local DLL/PI
• Local Phase-Rotator PLLs
• Global PLL requires RX
clock distribution to
individual channels
4
Embedded Clocking (CDR)
PLL-based CDR Dual-Loop CDR
VCTRL Frequency 800MHZ
CP PFD Ref Clk
Synthesis
VCO PLL Vctrl
4
ΦPLL[0]
Din RX CP
integral
gain
Interpolator
Pairs 15
PD early/ Ψ[4:0]
late early/
RX late sel
FSM
Loop Filter (16Gb/s) PD
Phase-Recovery Loop
• Clock frequency and optimum phase position are extracted from incoming data
• Phase detection continuously running
• Jitter tracking limited by CDR bandwidth
• With technology scaling we can make CDRs with higher bandwidths and the jitter tracking
advantages of source synchronous systems is diminished
• Possible CDR implementations
• Stand-alone PLL
• “Dual-loop” architecture with a PLL or DLL and phase interpolators (PI)
• Phase-rotator PLL
5
Analog PLL-based CDR
“Linearized” KPD
[Lee]
6
Analog PLL-based CDR
[Lee]
Open-Loop Gain:
Σ
proportional
ΦRX[n:0] gain
Din RX CP
integral
gain
PD early/
late
Loop Filter
[Razavi]
• Capture range
~<15%
frequency offset
15
Phase Interpolator (PI) Based CDR
• Frequency synthesis loop
can be a global PLL
• Can be difficult to
distribute multiple phases
long distance
• Need to preserve phase
spacing
• Clock distribution power
increases with phase number
• If CDR needs more than 4
phases consider local phase
generation
16
DLL Local Phase Generation
• Only differential clock is
distributed from global PLL
• Delay-Locked Loop (DLL)
locally generates the
multiple clock phases for
the phase interpolators
• DLL can be per-channel or
shared by a small number (4)
• Same architecture can be
used in a forwarded-clock
system
• Replace frequency synthesis
PLL with forwarded-clock
signals
17
Phase Rotator PLL
• Phase interpolators can be
expensive in terms of power
and area
• Phase rotator PLL places
one interpolator in PLL
feedback to adjust all VCO
output phases
simultaneously
• Now frequency synthesis
and phase recovery loops
are coupled
• Need PLL bandwidth greater
than phase loop
• Useful in filtering VCO noise
18
Phase Interpolators
• Phase interpolators realize
digital-to-phase conversion (DPC)
• Produce an output clock that is a
weighted sum of two input clock
phases
• Common circuit structures
• Tail current summation interpolation
• Voltage-mode interpolation
[Bulzacchelli]
• Interpolator code mapping
techniques
• Sinusoidal
• Linear
19
Phase Interpolator Examples
Tail-Current Summation Voltage-Mode Summation
20
Delay-Locked Loop (DLL)
22
Next Time
• CDR Wrap-Up
• PI
• DLL
• Jitter Properties
23