PROJECT REPORT

ON

Double Sequence Detector

GUIDED BY: SUBMITTED BY:

Dr. Dipankar Nagchoudhuri Vivek Kr. Choudhary (200611029)

Sudhir Kr. Sa (200711040)

K. Ram Prasad Rao (200711039)

Dhirubhai Ambani Institute of

Information and Communication Technology Gandhinagar India

November 2007
Contents:

 Symbols used

 Project Description

 Application of Double Sequence Detector

 State Diagram

 State Table

 Karnaugh Map

 Design Issues

 Design Strategy

 Design Goals

 Design Approach

 Logic Effort Calculation

 Area Estimation

 Transistor sizing and Logical area calculation

 Floor Plan

 Specifications

 Simulations results and waveforms

 References
Symbols Used: -
Symbol Description

VDD Supply Voltage

GND Ground

CLK Clock signal

X Input sequence

Y Output

ID Drain current .

tr Rise time

tf Fall time

L Channel Length
µ Ratio of mobility of PMOS and NMOS transistor
Project Description

 Aim is to design a Double Sequence Detector with one input and two
outputs.

 The output of the circuit will be a 1 and 0 corresponding on input

depending on sequence and goes to the inverter relay circuits.

Overall circuit as a black box:

Battery Voltage Controller

I/p or
Periodically charger O/P’s

Figure 1: Inverter Circuit controlled Logic

Application of double sequence detector:

step Down X-mer

step up X-mer

T
555
Amp. U
Timer
B
E

D.C. Battery

Voltage controller or
Periodically charger

Figure 2: Inverter Circuit with controlled Logic

The above schematic arrangement summarizes the application we are aiming at through this
project. In brief the circuit operation can be summed up as under:
The voltage of the D.C battery is sampled and quantized continuously. The
so obtained value of voltage is fed into the charger , which in turn monitors the voltage by
detecting the sequence being fed into it. In case the sequence detector encounters a sequence 011
it switches the relay circuit on there by initiating the process of charging the battery. The
charging continues until a sequence 101 is encountered which indicates the completion of
charging process there by switching the relay circuitry off and hence terminating the process.
Thus the voltage of the battery is monitored continuously and maintained between the required
levels.

State Diagram of Double Sequence Detector:

 Figure 3: State diagram for double sequence detector

State Table:

Present State Next State Output

A B C X DA=A(t+1) DB=B(t+1) DC=C(t+1) Y
0 0 0 0 0 0 1 0

0 0 0 1 0 1 0 0

0 0 1 0 0 0 1 0

0 0 1 1 0 1 1 0

0 1 0 0 1 0 0 0

0 1 0 1 0 1 0 0

0 1 1 0 1 0 0 0

0 1 1 1 1 0 1 1

1 0 0 0 0 0 1 0

1 0 0 1 1 1 0 1

1 0 1 0 1 0 0 0

1 0 1 1 0 1 0 0

1 1 0 0 1 0 0 0

1 1 0 1 1 0 1 0

1 1 1 0 x x x x

1 1 1 1 x x x x

Figure 4: State Table for double sequence detector

Karnaugh map:

CX CX
00 01 11 10 00 01 11 10
AB AB

00 00 1 1

01 1 1 1 01 1

11 1 1 x x 11 x x

10 1 1 10 1 1

Da = CB + ACX' + BX' + AC'X DB = XB' + A'C'X

s

CX CX
00 01 11 10 00 01 11 10
AB AB

00 1 1 1 00

01 1 01 1

11 1 x x 11 x x

1 10 1
10

Dc = X'B' C' + A'B'C + A'CX + ABX O/P Y = AB' C'X + BCX

Figure 5: Maps for double sequence detector

Design Issues
 If the logic expressions are derived directly from the K -map shown before, then
expressions of length 16 terms with each term containing 4 variables on an average were
obtained.
 Hence NAND /NOT based design are adopted.
 We opted D-flip flop because it has a single input hence the resulting circuit is less
complex.
 The use of D-flip flop avoids occurrance of race around condition because it’s an edge
triggered flip flop.

Design Strategy
 Standard Cell based design
 Inverter based design for standard cells with equivalent Inverter ratio of 2:1 (minimum
average delay)
 NAND based Combinational logic blocks (Minimum Logical effort)
 We opted for Static Logic because NAND implementation is easier in case of this logic
style; besides this our application required low power consumption, low noise sensitivity
and negligible power dissipation.
 We preferred Static Logic because it detects both low and high logic strongly.
 Static Logic also supports large fan in which is a major requirement while using multiple
input NAND gates.

Design Goals
 Compact and simple layout
 Power considerations

Design approach
We used the following standard cells:

 Inverter
 NAND-2
 NAND-3
  NAND-4

B
X
C

B
X'

X'

A
D Q
C

A CLK Q
C'
X

A' y
C' D Q
X

+
B' 1000fF
X CLK Q

B' D Q
C' 1fF

CLK Q
A'
B'
C

A'
C CLK
X

A
B
X

Figure 6: Double Sequence Detector

Table: Summary of terms and equations for concepts in the
method of logical Effort
To find the best number of stages, the best size of each gate, and
the minimum delay of a circuit with the following procedure:
Logical Effort Calculation:

A'
C'
X
1fF x
Y = XB' + A'C'X

+
B' y 1000fF
X

P=3+2=5
G = 5/3 x 4/3 = 20/9
B=1
h = 1000
F = G x B x H = 20000/9
f = (20000/9) ^ (1/2) = 47.15
d = N x f + P = 2 x 47.14 + 5
= 99.2809
x-ter Sizing y = 1000 x (4/3)/47.14
= 28.28
x = 28.28 x (5/3)/47.14 = 1

Figure 7: Logical effort for double sequence detector

Logical Effort Calculation:

A
B'
C'
X
1fF x Y = XBC + A'B'C'X

+
B y
C 1000fF
X

P=4+2=6
G = 6/3 x 4/3 = 8/3
B=1
h = 1000
F = G x B x H = 8000/3
f = (8000/3) ^ (1/2) = 51.63978
d = N x f + P = 2 x 51.6398 + 6
= 109.27956
x-ter Sizing y = 1000 x (4/3)/51.63
= 25.81989
x = 25.81989 x (5/3)/51.63 = 1

Figure 8: Logical effort for double sequence detector

Logical Effort Calculation:
X'

B'
x
C'

Y = X'B'C' + A'B'C + A'CX + ABX

1fF y

A'

+
B'
C
1000fF
z
A'
C
X

A
B
X

P=1+3+4=8
G = 1 x 5/3 x 2 = 10/3
B=1
H = 1000
F = G x B x H = 10000/3
f = (10000/3) ^ (1/3) = 14.93802
d = N x f + P = 3 x 14.93802 + 8
= 52.81405
x-ter Sizing z = 1000 x (6/3)/14.93802
= 133.88655
y = 133.88655 x (5/3)/14.93802 = 14.93809
x = 14.93809 x 1/14.93802 = 1

Figure 9: Logical effort for double sequence detector

Logical Effort Calculation:

B
C
1fF
x
B Y = CB + ACX' +BX' + AC'X
X'y

+
X' z 1000fF
y
A
C x
w A
C'
X

P=2+1+2+3=8
G = 4/3 x 1x 4/3 x 5/3 = 80/27
B=1
h = 1000
F = G x B x H = 80000/27
f = (80000/27) ^ (1/4) = 7.377
d = N x f + P = 4 x 7.377 + 8
= 37.511
x-ter Sizing z = 1000 x (5/3)/7.377
= 225.927
y = 225.927 x (4/3)/7.377 = 40.83456
x = 40.83456 x 1/7.377 = 5.53539
w = 5.53539 x (4/3)/7.377 = 1

Figure 10: Logical effort for double sequence detector

 VDD
VDD 20.42 20.42
X' B
VDD 20.42 20.42

A
3.69
X'
20.42
A 20.42
1.84
B 20.42

20.42
X'
75.31
75.31 VDD
VDD 75.31
VDD 75.31

0.5 0.5
C 3.69
To DA
A
150.61 1000fF

1.84
A 0.5
150.61

150.61
C 0.5
X
150.61

VDD
VDD
A'
20.42 20.42
16.34 16.34 16.34
B C A
C' X

B A
20.42 24.50

20.42 C' 24.50

C

X 24.50

Figure 11: X-ter sizing and Logical area calculation

 VDD
0.5 0.5
X
B' VDD

14.14
0.5
X 14.14
To DB
0.5
B' 1000fF
14.14

VDD 14.14
0.4 0.4 0.4
X A' C'

0.6
X

A' 0.6

C' 0.6

Figure 12: X-ter sizing and Logical area calculation.

 VDD
VDD 5.98 5.98 5.98
X B' C'
VDD 5.98
5.98 5.98
A B

X' 8.96

A 8.96

B' 8.96

B 8.96

C' 8.96
X'
8.96 44.63
44.63 VDD
44.63
44.6
VDD 3

5.98 5.98 5.98

To Dc
A' C X
89.25 1000fF

A' 8.96 89.25

89.25
C 8.96

89.25

X 8.96

VDD
5.98 5.98 5.98
A'
C
B'

A' 8.96

B' 8.96

C 8.96

Figure 13: X-ter sizing and Logical area calculation.

 VDD

0.3 0.3 0.3 0.3

X A B' C'

12.91 VDD
A 0.6
12.91
To O/P Y
B' 0.6
1000fF
12.91
C' 0.6

X 0.6 12.91

VDD
0.4 0.4 0.4
X B C

X
0.6

B 0.6

C 0.6

Figure 14: X-ter sizing and Logical area calculation.

Logical Area Estimation

N-Channel Transistor Sizes:

2 x14.14 + 0.5 x 2 + 0.6 x 3 + ( 25.81 / 2 ) + ( 3 / 5 )x 3 + ( 4 / 6 ) x 4 + ( 4 / 6 ) x
133.88 x 4 + ( 3 / 6 ) x 14.93 x 3 x 4 + ( 1 / 3 ) x 1 + ( 4 / 6 ) x 225.92 x 4 + ( 2 / 4 )
x 40.83 x 2 x 3 + 40.83 x ( 3 / 5 ) x 3 + 5.53 x ( 1 / 3 ) x 2 + ( 2 / 4 ) x 1 x 2

= 1298.50233 λ2

P-Channel transistor Sizes:

2 x 14.14 + 0.5 x 2 + 0.4 x 3 + ( 25.81 / 2 ) + ( 2 / 5 ) x 3 + ( 2 / 6 ) x 4 + ( 2/ 6 ) x
133.88 x 4 + ( 2 / 6 ) x 14.93 x 3 x 4 + ( 2 / 3 ) x 1 + ( 2 / 6 ) x 225.92 x 4 + ( 2 / 4 )
x 40.83 x 2 x 3 + 40.83 x ( 2 / 5 ) x 3 + 5.53 x ( 2 / 3 ) x 2 + ( 2 / 4 ) x 1 x 2

= 765.89767 λ2

Total Area:
P-Channel area + N-Channel area = 765.89767 λ2+ 1298.50233 λ2

=2064.4 λ2

= 722.54 µm2

where λ = 0.35µm
D-Flip flop:
Single edge Triggered (SET flip flop)

Master Slave configuration

CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch

Latch

QM
D Q
CLK CLK

Figure 15: Single Edge triggered D-flip Flop

Floor Plan:
I/P from battery

555 Voltage controller Relay

Timer or and supply
Periodically Charger Circuit

Step Up
Rectifier and
Power Amplifier
Circuit Step Down
Circuit
Transformer

Figure 16: Overall floor Plan of Design.

Specifications
 No of transistor in combinational circuit = 100
 No of transistor in D-flipflop= 48
 Total Transistor count = 148
 Total Estimated logical area = 2064.4 λ2 (722.54 µm2)
 Operating Voltage Vdd = 3-5Volts

Operating frequency range = 10MHz-100MHz

Spice simulation results:

Supply

(Vdd) 3 3.5 4 4.5 5

O/P Delay 0.58 .69 0.82 0.95 1.10

Y (psec)

Input Delay 0.20 0.24 0.28 0.32 0.38

DA (psec)
Input Delay 0.53 0.63 0.75 0.86 1.0

DB (psec)
Input Delay 0.28 0.33 0.40 0.46 0.53

DC (psec)
Rise time 1 1.5 2 2.5 3

Tr (nsec)

Fall time 1 1.5 2 2.5 3

Tf (nsec)

Power 3.78*10^(-5) 5.11*10^(-5) 6.88*10^(-5) 8.42*10^(-5) 1.03*10^(-4)

Dissipation(uW)
(Id*Vdd)
References
 Sabih H.Gerez “Algorithms for VLSI Design Automation ”,Wiley Publications ,June
2000 Edition

 Etienne Sicard , Sonia Delmas Bendhia “Basics of CMOS Cell Design”,Tata McGraw-
Hill Publications,2005 Edition

 John P.Uyemura “Introduction to VLSI circuits and system”,Wiley

Publications,2006 Edition

 Jan M.Rabaey , A. Chandrakasan , B.Nikolic “Digital Integrated Circuits”,Prentice –

Hall India, Second Edition 2006

 Sung-Mo Kang ,Yusuf Leblebici “CMOS Digital Integrated Circuits”, Tata McGraw-
Hill Publications, Third Edition 2003.