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    Sample Final 2017 Solutions

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    akayerdem00

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    Sample Final 2017 Solutions

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    akayerdem00
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    sample_final_2017_solutions (1)

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    9 views7 pages

    Sample Final 2017 Solutions

    Uploaded by

    akayerdem00

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    © All Rights Reserved
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    Download as pdf or txt
    of 7

    CS303 – Logic & Digital System Design

    Sample Final

    1) Answer the following questions for the circuit given below.

     A
    x  D Q y1

    Q’

    B
    D Q y2

    Q’

    clk

    a. Obtain the next state and output equations, and the state table.

    Present State Input Next State Output


    A B x A(t+1) B(t+1) y1 y2
    0 0 0 0 1 0 0
    0 0 1 1 1 0 0
    0 1 0 1 0 0 1
    0 1 1 0 0 0 1
    1 0 0 1 1 1 0
    1 0 1 0 1 1 0
    1 1 0 0 0 1 1
    1 1 1 1 0 1 1
    CS303 – Logic & Digital System Design

    b. Draw the state diagram.

    c. What does this circuit do?

    Counts up when input is 0 and counts down when input is 1.

    2) A finite state machine (FSM) has one input and one output. If {101} pattern is
    detected on the input, its output is 1 for one clock cycle, otherwise it is 0. Note that
    {…10101…} pattern contains two {101} patterns. Draw a state diagram for this FSM.
    CS303 – Logic & Digital System Design

    3) Consider the following two sequential circuits:

    1 T y0 count T z0
    clock
    k

    y1
    T T z1

    clock
    k

    The propagation delay of T flip-flop is tP,FF = 10 ps. The propagation delay of AND gate
    is tP,AND = 10 ps. Two circuits are using the same clock. Fill the following timing diagram.
    CS303 – Logic & Digital System Design

    4) Analyze the 3-bit binary ripple counter shown below.

    a. Fill the following table.

    Present State Next State


    A2 A1 A0 A2 A1 A0
    0 0 0 0 0 1
    0 0 1 0 1 0
    0 1 0 0 1 1
    0 1 1 1 0 0
    1 0 0 1 0 1
    1 0 1 0 0 0
    1 1 0 0 0 0
    1 1 1 0 0 0

    b. Show the counting sequence starting from 000 state.

    000 -> 001 -> 010 -> 011 -> 100 -> 101 -> 000 -> 001 -> 010 -> …
    CS303 – Logic & Digital System Design

    5) Design a counter with T flip-flops that goes through the following repeated
    sequence: 0, 1, 3, 7, 6, 4, 0, 1, 3, ... Treat unused states 010 and 101 as don’t care
    conditions, i.e. we don’t care what their next states are.

    Present State Next State Flip-Flop Inputs


    A B C A(t+1) B(t+1) C(t+1) TA TB TC
    0 0 0 0 0 1 0 0 1
    0 0 1 0 1 1 0 1 0
    0 1 0 X X X X X X
    0 1 1 1 1 1 1 0 0
    1 0 0 0 0 0 1 0 0
    1 0 1 X X X X X X
    1 1 0 1 0 0 0 1 0
    1 1 1 1 1 0 0 0 1

    A(t+1) = TA  A = (A’B + AB’)  A

    B(t+1) = TB  B = (C ’B + CB’)  B

    C(t+1) = TC  C = (C ’A’ + CA)  C


    CS303 – Logic & Digital System Design

    6) Draw logic diagram of the circuit that would result from synthesizing the following
    Verilog module.

    module final_exam_question (A, B, clk, result);


    input [2:0] A, B;
    input clk;
    output [2:0] result;
    reg [2:0] result;

    always @ (posedge clk)


    if (A == B) result <= A;
    else result <= B;
    endmodule

    (A==B) can be represented as ((A[0] ⊕ B[0]) + (A[1] ⊕ B[1]) + (A[2] ⊕ B[2]))’


    CS303 – Logic & Digital System Design

    7) Implement the following three Boolean functions using a PLA with 3 inputs, 4 product
    terms, 3 outputs. Fill in the PLA programming table. Show your work.

    F1 (x2, x1, x0) =  (0, 2, 5, 7)


    F2 (x2, x1, x0) =  (1, 3, 4, 6, 7)
    F3 (x2, x1, x0) =  (1, 2, 5)

    Outputs
    Inputs
    Product Term C T C

    x2 x1 x0 F1 F2 F3

    1 x2’x0 0 - 1 1 1 -
    2 x2x0’ 1 - 0 1 1 1
    3 x1x0 - 1 1 - 1 1
    4 x1’x0’ - 0 0 - - 1

    A1A0 A1A0 A1A0


    A2 00 01 11 10 A2 00 01 11 10 A2 00 01 11 10
    0 1 0 0 1 0 0 1 1 0 0 0 1 0 1
    1 0 1 1 0 1 1 0 1 1 1 0 1 0 0

    F1 = x2’x0’ + x2x0 F2 = x2’x0 + x2x0’ + x1x0 F3 = x1’x0 + x2’x1x0’


    F1 = (x2’x0 + x2x0’)’ F3 = (x1’x0’ + x1x0 + x2x0’)’

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