Unit II

COMBINATIONAL CIRCUITS

By
Kanchan S
Assistant Professor
Department of Computer Applications
ASC Degree College, Bangalore
Combinational Logic Circuits

Combinational circuits are the circuits whose output is a pure function

of the present input only ( ie output depends only on present input)
ALU (Arithmetic Logic Unit) which does mathematical operations are
constructed using combinational logic .
Eg :Half adders ,Full adders, Half Subtractor ,Full Subtractor, Encoder
,Decoder ,Multiplexer ,Demultiplexer
Combinational Logic Circuits
• Combinational Logic Circuits are made up from basic logic
NAND, NOR or NOT gates that are “combined” or connected
together to produce more complicated switching circuits. These
logic gates are the building blocks of combinational logic circuits.
• Combinational logic circuits can be very simple or very
complicated and any combinational circuit can be implemented
with only NAND and NOR gates as these are classed as “universal”
gates.
The three main ways of specifying the function of a combinational
logic circuit are:
1. Boolean Algebra – This forms the algebraic expression showing the
operation of the logic circuit for each input variable either True or
False that results in a logic “1” output.
2. Truth Table – A truth table defines the function of a logic gate by
providing a concise list that shows all the output states in tabular form
for each possible combination of input variable that the gate could
encounter.
3. Logic Diagram – This is a graphical representation of a logic circuit
that shows the wiring and connections of each individual logic gate,
represented by a specific graphical symbol, that implements the logic
circuit.
Classification of Combinational Logic
Half Adder
• A half adder is a logical circuit that performs an addition operation on two
binary digits. The half adder produces a sum and a carry value which are
both binary digits.
BLOCK DIAGRAM • From the truth table of the half adder we
can see that the SUM (S) output is the result
of the Exclusive-OR gate and the Carry-out
(Cout) is the result of the AND gate. Then the
Boolean expression for a half adder is as
follows.
LOGIC CIRCUIT TRUTH TABLE BOOLEAN EXPRESSION
A B
• For the SUM bit:
SUM = A(~B)+(~A)B=A XOR B = A ⊕ B
• For the CARRY bit:
CARRY = A AND B = A.B
 Full Adder
• Full adder is a logical circuit that performs an addition operation on three binary
digits and produces Sum and Carry .Like the half adder, it also generates a carry
out to the next addition column. Then a Carry-in is a possible carry from a less
significant digit, while a Carry-out represents a carry to a more significant digit.
Full adder implementation using 2 Half adder
BLOCK DIAGRAM
A B CIN

LOGIC CIRCUIT BOOLEAN EXPRESSION

Then the Boolean expression for a full adder is as
follows.
• For the SUM (S) bit:
SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕ Cin
• For the CARRY-OUT (Cout) bit:
CARRY-
OUT = A AND B OR Cin(A XOR B) = A.B + Cin(A ⊕ B)
Multiplexer
• Multiplexer is a combinational circuit that has maximum
of 2n data inputs, ‘n’ selection lines and single output line.
One of these data inputs will be connected to the output
based on the values of selection lines.
• Since there are ‘n’ selection lines, there will be 2n possible
combinations of zeros and ones. So, each combination will
select only one data input. Multiplexer is also called
as Mux or Data Selector.
 4x1 Multiplexer
• 4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output Y. One of
these 4 inputs will be connected to the output based on the combination of inputs present at these
two selection lines.
• The block diagram of 4x1 Multiplexer is shown in the following figure.
Truth Table
Block Diagram
Selection Lines Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

From Truth table, we can directly write the Boolean function for
output, Y as
Y = S1 S0 I0 + S1 S0 I1 + S1 S0 I2 + S1 S0 I3
• From Truth table, we can directly write the Boolean function for output,
Y as
Y = S1 S0 I0 + S1 S0 I1 + S1 S0 I2 + S1 S0 I3
We can implement this Boolean function using Inverters, AND gates & OR gate. The circuit diagram of 4x1
multiplexer is shown in the following figure.
Encoders
The combinational circuits that change the binary information into N output lines are known as Encoders.
The binary information is passed in the form of 2N input lines. The output lines define the N-bit code for the
binary information. In simple words, the Encoder performs the reverse operation of the Decoder. At a time,
only one input line is activated for simplicity. The produced N-bit output code is equivalent to the binary
information.
8 to 3 Encoder:

he 8 to 3 line Encoder is also known as Octal to Binary Encoder. In 8 to 3 line encoder, there is a total of eight
inputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e., A0, A1, and A2. In 8-input lines, one
input-line is set to true at a time to get the respective binary code in the output side. Below are the block
diagram and the truth table of the 8 to 3 line encoder

Block Diagram:
Decoders

The combinational circuit that change the binary information into 2N output lines is known as Decoders. The
binary information is passed in the form of N input lines. The output lines define the 2N-bit code for the binary
information. In simple words, the Decoder performs the reverse operation of the Encoder. At a time, only one
input line is activated for simplicity. The produced 2N-bit output code is equivalent to the binary information.
3 to 8 Line Decoder
S0 S1 S2 E D0 D1 D2 D3 D4 D5 D6 D7

x x x 0 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 0 0 0 1

0 0 1 1 0 0 0 0 0 0 1 0

0 1 0 1 0 0 0 0 0 1 0 0

0 1 1 1 0 0 0 0 1 0 0 0

1 0 0 1 0 0 0 1 0 0 0 0

1 0 1 1 0 0 1 0 0 0 0 0

1 1 0 1 0 1 0 0 0 0 0 0

1 1 1 1 1 0 0 0 0 0 0 0

• This decoder circuit gives 8 logic outputs for 3 inputs and has a
enable pin. The circuit is designed with AND and NAND logic gates.
It takes 3 binary inputs and activates one of the eight outputs. 3 to
8 line decoder circuit is also called as binary to an octal decoder.
• Application of Decoder
• The Decoders were used in analog to digital conversion in analog decoders.
• Used in electronic circuits to convert instructions into CPU control signals.
• They mainly used in logical circuits, data transfer.
Shift Register
Applications of shift registers

1. Temporary memory: Shift registers are used as temporary storage for data, usually by the
CPU while processing data.
2. Data conversion: Shift registers can convert data from one form to another, such as from
serial to parallel or vice versa.
3. Data transfer: Shift registers can transfer data between different parts of a system.
4. Data manipulation: Shift registers can perform bitwise operations on data, such as shifting
or rotating.
5. Delay: Shift registers can be used to create time delays in digital circuits.
2. Serial In Parallel Out (SIPO) Shift Register

In the "Serial IN Parallel OUT" shift register, the data is passed serially to the flip flop, and
outputs are fetched in a parallel way. The data is passed bit by bit in the register, and the
output remains disabled until the data is not passed to the data input.
 Sequential circuits
A sequential circuit is a logical circuit, where the output depends on the present
input and also on previous inputs and outputs .
Eg : Flip Flops , shift registers , counters etc.

While a combinational circuit is a function of present input only. A sequential

circuit is a combination of combinational circuit and a storage element. The
sequential circuits use current input variables and previous input variables
which are stored and provide the data to the circuit on the next clock cycle.

Sequential Circuits Block Diagram

Types of Sequential Circuits

The sequential circuits are classified in to two types.

 Synchronous Circuit
 Asynchronous Circuit
In synchronous sequential circuits, the state of device changes at discrete times
in response to a clock signal. In asynchronous circuits, the state of the device
changes in response to changing inputs.

Synchronous Circuits
In synchronous circuits, the inputs are pulses with certain restrictions on pulse
width and propagation delay. Thus synchronous circuits can be divided into
clocked and un-clocked or pulsed sequential circuits.

Synchronous Circuit

Clocked Sequential Circuit

The clocked sequential circuits have flip-flops or gated latches for its memory
elements. There is a periodic clock connected to the clock inputs of all the
memory elements of the circuit to synchronize all the internal changes of state.
Hence the operation of the circuit is controlled and synchronized by the
periodic pulse of the clock.
Asynchronous Circuits
An asynchronous circuit does not have a clock signal to synchronize its internal
changes of the state. Hence the state change occurs in direct response to
changes that occur in primary input lines. An asynchronous circuit does not
require the precise timing control from flip-flops.

Asynchronous Circuit

Asynchronous logic is more difficult to design and it has some problems

compared to synchronous logic. The main problem is that the digital memory
is sensitive to the order that their input signals arrive them, like, if two signals
arrive at a flip-flop at the same time, which state the circuit goes into can
depend on which signal gets to the logic gate first.

Asynchronous circuits are used in critical parts of synchronous systems where

the speed of the system is a priority, like as in microprocessors and digital
signal processing circuits.
Flip Flop Circuit

It is the basic storage element in sequential logic which stores a bit of

information i,e either 0 or 1 and fundamental building blocks of digital
electronic systems. They can be used to keep a record of the value of a variable.
Flip-flop is also used to control the functionality of a circuit.

Flip flop is said to be edge sensitive or edge triggered rather than being level triggered
like latches.

The R-S flip-flop is the simplest flip-flop. It has two outputs, one output is
the reverse of the other, and two inputs. The two inputs are Set and Reset.
The flip-flop basically uses NAND gates with an additional enable pin. The
circuit gives output only when the enable pin is high.

Block Diagram

SR Flip Flop Block Diagram

Circuit Diagram
 SR Flip Flop Circuit Diagram

Truth Table

Operation

S.N. Condition Operation

1 S = R = 0 : No
change
If S = R = 0 then output of NAND gates 3 and 4 are
forced to become 1.
Hence R' and S' both will be equal to 1. Since S' and
R' are the input of the basic S-R latch using NAND
gates, there will be no change in the state of outputs.

2 S = 0, R = 1, E = 1
Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1
the output of NAND-4 i.e. S' = 0.
Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset
condition.

3 S = 1, R = 0, E = 1
Output of NAND-3 i.e. R' = 0 and output of NAND-4
i.e. S' = 1.
Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1
 bar = 0. This is the reset condition.

4 S = 1, R = 1, E = 1
As S = 1, R = 1 and E = 1, the output of NAND gates
3 and 4 both are 0 i.e. S' = R' = 0.
Hence the Race condition will occur in the basic
NAND latch.

The name JK flip-flop is termed from the inventor Jack Kilby from texas
instruments. The basic S-R NAND flip-flop circuit has many advantages
and uses in sequential logic circuits but it suffers from two basic switching
problems.
 1. the Set = 0 and Reset = 0 condition (S = R = 0) must always be
avoided
 2. if Set or Reset change state while the enable (EN) input is high
the correct latching action may not occur
Then to overcome these two fundamental design problems with the SR flip-
flop design, the JK flip Flop was developed.
This simple JK flip Flop is the most widely used of all the flip-flop designs
and is considered to be a universal flip-flop circuit.

Block Diagram

Inputs Outputs

Circuit Diagram
 JK

Flip Flop Circuit

JK Flip Flop Truth Table

Inputs Outputs Comments

E/CLK J K Q Q

1 0 0 Q Q No Changes

1 0 1 0 1 Reset to 0

1 1 0 1 0 Set to 1

1 1 1 Q Q Toggling

Operation

SL.No. Condition Operation

1 J = K = 0 , E=1:
No change
If J = K = 0 then there will be no change in the state
of outputs , previous value of Q and Q will be retained
as it is

2 J = 0, K = 1, E = 1
Outputs Q = 0 and Q = 1 ie. Flip Flop will be in Reset
or Clear state
3 J = 1, K = 0, E = 1
Outputs Q = 1 and Q = 0 ie. Flip Flop will be in Set
State

4 J = 1, R = 1, E = 1
It sets and rese ts the flip Flop , if Q = 0 and Q = 1 and
if Q = 1 and Q = 0 , Flip Flop will be Toggling or Racing
Condition.

Delay Flip Flop /Data Flip Flp/D Flip Flop

Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter
connected between S and R inputs. It has only one input. The input data isappearing
at the output after some time. Due to this data delay between i/p and o/p, it is called
delay flip flop. S and R will be the complements of each other due to NAND inverter.
Hence S = R = 0 or S = R = 1, these input condition will never appear. This problem
is avoid by SR = 00 and SR = 1 conditions.

Block Diagram

Circuit Diagram
Truth Table

Q Q

Operation

S.N. Condition Operation

1 E=0
Latch is disabled. Hence no change in output.

2 E = 1 and D =
0
If E = 1 and D = 0 then S = 0 and R = 1. Hence irrespective of
the present state, the next state is Q = 0 and Q=1. This is the
reset condition.

3 E = 1 and D =
1
If E = 1 and D = 1, then S = 1 and R = 0. This will set the
latch and Q = 1 and Q=0 irrespective of the present state.

Toggle Flip Flop / T Flip Flop

Toggle flip flop is basically a JK flip flop with J and K terminals permanently
connected together. It has only input denoted by T as shown in the Symbol Diagram.
The symbol for positive edge triggered T flip flop is shown in the Block Diagram.

Symbol Diagram
Block Diagram

Truth Table

Q Q

Operation

S.N. Condition Operation

1 T = 0, J = K = The output Q and Q won't change

0

2 T = 1, J = K = Output will toggle corresponding to every leading edge of clock

1 signal.(Toggling)
 Applications of Flip Flop
 Frequency dividers.
 Counters.
 Storage registers.
 Shift registers.
 Data storage.
 Bounce elimination switch.
 Latch.
 Data transfer.