EXPERIMENT: 1 LOGIC GATES

AIM: To study and verify the truth table of logic gates

LEARNING OBJECTIVE:
 Identify various ICs and their specification. 

COMPONENTS REQUIRED:
 Logic gates (IC) trainer kit. 
 Connecting patch chords. 
 IC 7400, IC 7408, IC 7432, IC 7406, IC 7402, IC 7404, IC 7486 

THEORY:
The basic logic gates are the building blocks of more complex logic circuits. These logic
gates perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion,
Exclusive-OR, Exclusive-NOR. Fig. below shows the circuit symbol, Boolean function,
and truth. It is seen from the Fig that each gate has one or two binary inputs, A and B, and
one binary output, C. The small circle on the output of the circuit symbols designates the
logic complement. The AND, OR, NAND, and NOR gates can be extended to have more
than two inputs. A gate can be extended to have multiple inputs if the binary operation it
represents is commutative and associative.

These basic logic gates are implemented as small-scale integrated circuits (SSICs) or as part
of more complex medium scale (MSI) or very large-scale (VLSI) integrated circuits. Digital
IC gates are classified not only by their logic operation, but also the specific logic-circuit
family to which they belong. Each logic family has its own basic electronic circuit upon
which more complex digital circuits and functions are developed. The following logic
families are the most frequently used.

TTL Transistor-transistor logic

ECL Emitter-coupled logic
MOS Metal-oxide semiconductor
CMOS Complementary metal-oxide semiconductor

TTL and ECL are based upon bipolar transistors. TTL has a well established popularity among
logic families. ECL is used only in systems requiring high-speed operation. MOS and CMOS,
are based on field effect transistors. They are widely used in large scale integrated circuits
because of their high component density and relatively low power consumption. CMOS logic
consumes far less power than MOS logic. There are various commercial
Logic Design Laboratory Manual 2
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integrated circuit chips available. TTL ICs are usually distinguished by numerical
designation as the 5400 and 7400 series.

PROCEDURE:
1. Check the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Provide the input data via the input switches and observe the output on output LEDs
Logic Design Laboratory Manual 3
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VIVA QUESTIONS:

1. Why NAND & NOR gates are called universal gates?

2. Realize the EX – OR gates using minimum number of NAND gates.
3. Give the truth table for EX-NOR and realize using NAND gates?
4. What are the logic low and High levels of TTL IC’s and CMOS IC’s?
5. Compare TTL logic family with CMOS family?
6. Which logic family is fastest and which has low power dissipation?

EXPERIMENT: 2 REALIZATION OF A BOOLEAN FUNCTION.

AIM: To simplify the given expression and to realize it using Basic gates
and Universal gates

LEARNING OBJECTIVE:
To simplify the Boolean expression and to build the logic circuit.
Given a Truth table to derive the Boolean expressions and build the logic circuit
to realize it.

COMPONENTS REQUIRED:
IC 7400, IC 7408, IC 7432, IC 7406, IC 7402, Patch Cords & IC Trainer Kit.

THEORY:
Canonical Forms (Normal Forms): Any Boolean function can be written in disjunctive
normal form (sum of min-terms) or conjunctive normal form (product of max-terms).
A Boolean function can be represented by a Karnaugh map in which each cell corresponds
to a minterm. The cells are arranged in such a way that any two immediately adjacent cells
correspond to two minterms of distance 1. There is more than one way to construct a map
with this property.
Karnaugh Maps

For a function of two variables, say, f(x, y),

For a function of three variables, say, f(x, y, z)

For a function of four variables: f(w, x, y, z)

 Logic Design Laboratory Manual 4
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Realization of Boolean expression:

_ _ _ _ _ _ _ _ _ _ _ _ _ _
1) Y= A B C D A BC D ABC D A B C D A B C D A B C D  A B CD
AB
1
1
1
1 1 1 1
_ _

After simplifying using K-Map method we Y =A B + C D

get Realization using Basic gates TRUTH TABLE

INPUTS OUTPUT
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
Realization using NAND gates 0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0

Realization using NOR gates

Logic Design Laboratory Manual 5
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2) For the given Truth Table, realize a logical circuit using basic gates and NAND gates

Inputs Output
A B C D Y
0 0 0 0 1
0 0 0 1 1
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1

PROCEDURE:
Check the components for their working.
Insert the appropriate IC into the IC base.
Make connections as shown in the circuit diagram.
Provide the input data via the input switches and observe the output on output
LEDs Verify the Truth Table

RESULT: Simplified and verified the Boolean function using basic gates and universal gates

VIVA QUESTIONS:
1) What are the different methods to obtain minimal expression?
2) What is a Min term and Max term
3) State the difference between SOP and POS.
Logic Design Laboratory Manual 6
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4) What is meant by canonical representation?
5) What is K-map? Why is it used?
6) What are universal gates?
EXPERIMENT: 3 ADDERS AND SUBTRACTORS
AIM: To realize
i) Half Adder and Full Adder
ii) Half Subtractor and Full Subtractor by using Basic gates and NAND gates

LEARNING OBJECTIVE:
To realize the adder and subtractor circuits using basic gates and universal
gates To realize full adder using two half adders
To realize a full subtractor using two half subtractors

COMPONENTS REQUIRED:
IC 7400, IC 7408, IC 7486, IC 7432, Patch Cords & IC Trainer Kit.

THEORY:
Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and
B, is called a half-adder. Addition will result in two output bits; one of which is the sum bit, S,
and the other is the carry bit, C. The Boolean functions describing the half-adder are:
S =A ⊕ B C=AB

Full-Adder: The half-adder does not take the carry bit from its previous stage into account.
This carry bit from its previous stage is called carry-in bit. A combinational logic circuit that
adds two data bits, A and B, and a carry-in bit, Cin , is called a full-adder. The Boolean
functions describing the full-adder are:
S = (x ⊕ y) ⊕ Cin C = xy + Cin (x ⊕ y)

Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A -B ) produces a
difference bit D and a borrow out bit B-out. This operation is called half subtraction and the
circuit to realize it is called a half subtractor. The Boolean functions describing the half-
Subtractor are:
S =A ⊕ B C = A’ B

Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit value A
produces a difference bit D and a borrow out Br bit. This is called full subtraction. The
Boolean functions describing the full-subtracter are:
D = (x ⊕ y) ⊕ Cin Br= A’B + A’(Cin) + B(Cin)
Logic Design Laboratory Manual 7
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I. TO REALIZE HALF ADDER

TRUTH TABLE BOOLEAN EXPRESSIONS:

INPUTS OUTPUTS
S=A ⊕ B
A B S C C=A B
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
i) Basic Gates ii) NAND Gates

II. FULL ADDER

TRUTH TABLE
BOOLEAN EXPRESSIONS:
INPUTS OUTPUTS S= A ⊕ B ⊕ C
A B Cin S C
0 0 0 0 0 C=A B + B Cin + A Cin

0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

i)BASIC GATES
Logic Design Laboratory Manual 8
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ii) NAND GATES

III. HALF SUBTRACTOR

TRUTH TABLE BOOLEAN EXPRESSIONS:

INPUTS OUTPUTS D=A⊕ B

_
A B D Br Br = A B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Logic Design Laboratory Manual 9
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i)BASIC GATES ii) NAND Gates

IV. FULL SUBTRACTOR

TRUTH TABLE BOOLEAN EXPRESSIONS:

INPUTS OUTPUTS D= A ⊕ B ⊕ C
_ _
A B Cin D Br Br= A B + B Cin + A Cin
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

i) BASIC GATES
 Logic Design Laboratory Manual 10
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ii) To Realize the Full subtractor using NAND Gates only

PROCEDURE:
 Check the components for their working. 

 Insert the appropriate IC into the IC base. 
 Make connections as shown in the circuit diagram. 

 Verify the Truth Table and observe the outputs. RESULT:

The truth table of the above circuits is verified. VIVA

QUESTIONS: 

1) What is a half adder?
2) What is a full adder?
3) What are the applications of adders?
4) What is a half subtractor?
5) What is a full subtractor?
6) What are the applications of subtractors?
7) Obtain the minimal expression for above circuits.
8) Realize a full adder using two half adders
9) Realize a full subtractors using two half subtractors
EXPERIMENT: 4 PARALLEL ADDER AND SUBTRACTOR
AIM: To design and set up the following circuit using IC 7483.
i) A 4-bit binary parallel adder.
ii) A 4-bit binary parallel subtractor.

LEARNING OBJECTIVE:
To learn about IC 7483 and its internal structure.
To realize a subtractor using adder IC 7483

COMPONENTS REQUIRED:
IC 7483, IC 7486, Patch Cords & IC Trainer Kit.

THEORY:
The Full adder can add single-digit binary numbers and carries. The largest sum that can be
obtained using a full adder is 112. Parallel adders can add multiple-digit numbers. If full adders
are placed in parallel, we can add two- or four-digit numbers or any other size desired. Figure
below uses STANDARD SYMBOLS to show a parallel adder capable of adding two, two-digit
binary numbers The addend would be on A inputs, and the augend on the B inputs. For this
explanation we will assume there is no input to C0 (carry from a previous circuit)

To add 102 (addend) and 012 (augend), the addend inputs will be 1 on A2 and 0 on A1. The
augend inputs will be 0 on B2 and 1 on B1. Working from right to left, as we do in normal
addition, let’s calculate the outputs of each full adder. With A1 at 0 and B1 at 1, the output of
adder1 will be a sum (S1) of 1 with no carry (C1). Since A2 is 1 and B2 is 0, we have a sum
(S2) of 1 with no carry (C2) from adder1. To determine the sum, read the outputs (C2, S2, and
S1) from left to right. In this case, C2 = 0, S2 = 1, and S1 = 1. The sum, then, of 102 and 012
Logic Design Laboratory Manual 12
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is 0112. To add four bits we require four full adders arranged in parallel. IC 7483 is a 4- bit
parallel adder whose pin diagram is shown.

MSB LSB
Cin
INPUTS A3 A2 A1 A0
B B B B
3 2 1 0

OUTPUT Cout S3 S2 S1 S0

IC 7483 pin diagram

i) 4-Bit Binary Adder

An Example: 7+2=11 (1001)

 7 is realized at A3 A2 A1 A0 = 0111 
2 is realized at B3 B2 B1 B0 = 0010
Sum = 1001

ADDER CIRCUIT:
Logic Design Laboratory Manual 13
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PROCEDURE:
 Check all the components for their working. 
 Insert the appropriate IC into the IC base. 
 Make connections as shown in the circuit diagram. 
 Apply augend and addend bits on A and B and cin=0. 
Verify the results and observe the outputs. 
i) 4-BIT BINARY SUBTRACTOR.
Subtraction is carried out by adding 2’s complement of the subtrahend.
Example: 8 – 3 = 5 (0101)

 8 is realized at A3 A2 A1 A0 = 1000
 3 is realized at B3 B2 B1 B0 through X-OR gates = 0011
 Output of X-OR gate is 1’s complement of 3 = 1100
 2’s Complement can be obtained by adding Cin =1

Therefore
Cin = 1
A3 A2 A1 A0 = 1 0 0 0
B3 B2 B1 B0 = 1 1 0 0
S3 S2 S1 S0 = 0 1 0 1
Cout = 1 (Ignored)
Logic Design Laboratory Manual 14
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PROCEDURE:
 Check all the components for their working. 
 Insert the appropriate IC into the IC base. 
 Make connections as shown in the circuit diagram. 
 Apply Minuend and subtrahend bits on A and B and cin=1. 
Verify the results and observe the outputs. 

RESULTS: Verified the working of IC 7483 as adder and subtractor.

i) 4-BIT BINARY SUBTRACTOR.
Subtraction is carried out by adding 2’s complement of the subtrahend.
Example: 8 – 3 = 5 (0101)

 8 is realized at A3 A2 A1 A0 = 1000
 3 is realized at B3 B2 B1 B0 through X-OR gates = 0011
 Output of X-OR gate is 1’s complement of 3 = 1100
 2’s Complement can be obtained by adding Cin =1

Therefore
Cin = 1
A3 A2 A1 A0 = 1 0 0 0
B3 B2 B1 B0 = 1 1 0 0
S3 S2 S1 S0 = 0 1 0 1
Cout = 1 (Ignored)
Logic Design Laboratory Manual 14
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PROCEDURE:
 Check all the components for their working. 
 Insert the appropriate IC into the IC base. 
 Make connections as shown in the circuit diagram. 
 Apply Minuend and subtrahend bits on A and B and cin=1. 
Verify the results and observe the outputs. 

RESULTS: Verified the working of IC 7483 as adder and subtractor.

 BCD adder using two 7483 IC chip

 A BCD adder adds two BCD digits and produces output as a BCD digit. A BCD or
Binary Coded Decimal digit cannot be greater than 9.
 The two BCD digits are to be added using the rules of binary addition. If sum is less than
or equal to 9 and carry is 0, then no correction is needed. The sum is correct and in true
BCD form.
 But if sum is greater than 9 or carry =1, the result is wrong and correction must be done.
The wrong result can be corrected adding six (0110) to it.
 For implementing a BCD adder using a binary adder circuit IC 7483, additional
combinational circuit will be required, where the Sum output S3−S0

 is checked for invalid values from 10 to 15. The truth table and K-map for the same is as
shown:
 The Boolean expression is, Y=S3S2+S3S1
  The BCD adder is shown below. The output of the combinational circuit should be 1 if Cout
of adder-1 is high. Therefore Y is ORed with Cout of adder 1.

 The output of combinational circuit is connected to B1B2 inputs of adder-2 and B3=B1+0

as they are connected to ground permanently. This makes B3B2B1B0

 = 0110 if Y' = 1.

 The sum outputs of adder-1 are applied to A3A2A1A0

 of adder-2. The output of combinational circuit is to be used as final output carry and the
carry output of adder-2 is to be ignored.

Operations of: (011)BCD+(1001)BCD

Thus,

Cout = 1

S3S2S1S0=0000

Hence, for adder, inputs will be A3A2A1A0=0000

and B3B2B1B0=0110

This will give final output as Cout S3S2S1S0=10110

Therefore, (0111)BCD+(1001)BCD

= (00010110)BCD
EXPERIMENT: 7 MULTIPLEXER AND DEMULTIPLEXER
AIM: To design and set up the following circuit
1) To design and set up a 4:1 Multiplexer (MUX) using only NAND gates.
2) To design and set up a 1:4 Demultiplexer(DE-MUX) using only NAND gates.
3) To verify the various functions of IC 74153(MUX) and IC 74139(DEMUX).
4) To set up a Half/Full Adder and Half/Full Subtractor using IC 74153.

LEARNING OBJECTIVE:
To learn about various applications of multiplexer and de-multiplexer
To learn and understand the working of IC 74153 and IC 74139
To learn to realize any function using Multiplexer

THEORY:
Multiplexers are very useful components in digital systems. They transfer a large number of
information units over a smaller number of channels, (usually one channel) under the
control of selection signals. Multiplexer means many to one. A multiplexer is a circuit with
many inputs but only one output. By using control signals (select lines) we can select any
input to the output. Multiplexer is also called as data selector because the output bit
n
depends on the input data bit that is selected. The general multiplexer circuit has 2 input
signals, n control/select signals and 1 output signal.
De-multiplexers perform the opposite function of multiplexers. They transfer a small
number of information units (usually one unit) over a larger number of channels under the
control of selection signals. The general de-multiplexer circuit has 1 input signal, n
n
control/select signals and 2 output signals. De-multiplexer circuit can also be realized
using a decoder circuit with enable.

COMPONENTS REQUIRED:
IC 7400, IC 7410, IC 7420, IC 7404, IC 74153, IC 74139, Patch Cords & IC Trainer Kit.

i) 4:1 MULTIPLEXER

4:1
Inputs MUX
Y

E’
Select
inputs
Output Y= E’S1’S0’I0 + E’S1’S0I1 + E’S1S0’I2 + E’S1S0I3
Logic Design Laboratory Manual 22
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REALIZATION USING NAND GATES TRUTH TABLE

Select Enable Out

Inputs
Inputs Input puts

S1 S0 E I0 I1 I2 I3 Y
X X 1 X X X X 0
0 0 0 0 X X X 0
0 0 0 1 X X X 1
0 1 0 X 0 X X 0
0 1 0 X 1 X X 1
1 0 0 X X 0 X 0
1 0 0 X X 1 X 1
1 1 0 X X X 0 0
1 1 0 X X X 1 1

VERIFY IC 74153 MUX (DUAL 4:1 MULTIPLEXER)

Logic Design Laboratory Manual 23
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ii) DE-MUX USING NAND GATES
Enable Data Select
Outputs
Inputs Input Inputs

E D S1 S0 Y3 Y2 Y1 Y0
1 0 X X X X X X
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 1 0 0
0 1 1 1 1 0 0 0

VERIFICATION OF IC 74139 (DEMUX)

TRUTH TABLE

Inputs Outputs
Ea S1 S0 Y3 Y2 Y1 Y0
1 X X 1 1 1 1
0 0 0 1 1 1 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1
0 1 1 0 1 1 1
Logic Design Laboratory Manual 24
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HALF ADDER USING MUX:

DESIGN: TRUTH TABLE

SUM CARRY
I0 I1 I0 I1 Inputs Outputs
0 1 0 1 A B S C
2 3 2 3 0 0 0 0
A A’ 0 A
0 1 1 0
CIRCUIT: 1 0 1 0
1 1 0 1

FULL ADDER USING MUX:

DESIGN:
SUM CARRY

I0 I1 I3 I3 I0 I1 I3 I3
0 1 2 3 0 1 2 3
4 5 6 7 4 5 6 7
A A’ A’ A 0 A A 1

TRUTH TABLE
Inputs Outputs
A B C S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Logic Design Laboratory Manual 25
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FULL ADDER CIRCUIT

HALF SUBTRACTOR USING MUX:

DESIGN:

DIFFERENCE BORROW
I0 I1 I0 I1
0 1 0 1
2 3 2 3
A A’ 0 A’

CIRCUIT: TRUTH TABLE

Inputs Outputs
A B D Br
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
 Logic Design Laboratory Manual 26
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FULL SUBTRACTOR USING MUX:

DESIGN:
DIFFERENCE BORROW
I0 I1 I2 I3 I0 I1 I2 I3
0 1 2 3 0 1 2 3
4 5 6 7 4 5 6 7
A A’ A’ A 0 A’ A’ 1
TRUTH TABLE
Inputs Outputs
A B C D Br
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

PROCEDURE:
 Check all the components for their working. 
 Insert the appropriate IC into the IC base. 
 Make connections as shown in the circuit diagram. 
Verify the Truth Table and observe the outputs. 

RESULT: Adder and subtractor circuits are realized using multiplexer IC 74153.

VIVA QUESTIONS:

1) What is a multiplexer?
2) What is a de-multiplexer?
3) What are the applications of multiplexer and de-multiplexer?
4) Derive the Boolean expression for multiplexer and de-multiplexer.
5) How do you realize a given function using multiplexer
6) What is the difference between multiplexer & demultiplexer?
7) In 2n to 1 multiplexer how many selection lines are there?
8) How to get higher order multiplexers?
9) Implement an 8:1 mux using 4:1 muxes?
EXPERIMENT: 7 MULTIPLEXER AND DEMULTIPLEXER
AIM: To design and set up the following circuit
1) To design and set up a 4:1 Multiplexer (MUX) using only NAND gates.
2) To design and set up a 1:4 Demultiplexer(DE-MUX) using only NAND gates.
3) To verify the various functions of IC 74153(MUX) and IC 74139(DEMUX).
4) To set up a Half/Full Adder and Half/Full Subtractor using IC 74153.

LEARNING OBJECTIVE:
To learn about various applications of multiplexer and de-multiplexer
To learn and understand the working of IC 74153 and IC 74139
To learn to realize any function using Multiplexer

THEORY:
Multiplexers are very useful components in digital systems. They transfer a large number of
information units over a smaller number of channels, (usually one channel) under the
control of selection signals. Multiplexer means many to one. A multiplexer is a circuit with
many inputs but only one output. By using control signals (select lines) we can select any
input to the output. Multiplexer is also called as data selector because the output bit
n
depends on the input data bit that is selected. The general multiplexer circuit has 2 input
signals, n control/select signals and 1 output signal.
De-multiplexers perform the opposite function of multiplexers. They transfer a small
number of information units (usually one unit) over a larger number of channels under the
control of selection signals. The general de-multiplexer circuit has 1 input signal, n
n
control/select signals and 2 output signals. De-multiplexer circuit can also be realized
using a decoder circuit with enable.

COMPONENTS REQUIRED:
IC 7400, IC 7410, IC 7420, IC 7404, IC 74153, IC 74139, Patch Cords & IC Trainer Kit.

i) 4:1 MULTIPLEXER

4:1
Inputs MUX
Y

E’
Select
inputs
Output Y= E’S1’S0’I0 + E’S1’S0I1 + E’S1S0’I2 + E’S1S0I3
Logic Design Laboratory Manual 22
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REALIZATION USING NAND GATES TRUTH TABLE

Select Enable Out

Inputs
Inputs Input puts

S1 S0 E I0 I1 I2 I3 Y
X X 1 X X X X 0
0 0 0 0 X X X 0
0 0 0 1 X X X 1
0 1 0 X 0 X X 0
0 1 0 X 1 X X 1
1 0 0 X X 0 X 0
1 0 0 X X 1 X 1
1 1 0 X X X 0 0
1 1 0 X X X 1 1

VERIFY IC 74153 MUX (DUAL 4:1 MULTIPLEXER)

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ii) DE-MUX USING NAND GATES
Enable Data Select
Outputs
Inputs Input Inputs

E D S1 S0 Y3 Y2 Y1 Y0
1 0 X X X X X X
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 1 0 0
0 1 1 1 1 0 0 0

VERIFICATION OF IC 74139 (DEMUX)

TRUTH TABLE

Inputs Outputs
Ea S1 S0 Y3 Y2 Y1 Y0
1 X X 1 1 1 1
0 0 0 1 1 1 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1
0 1 1 0 1 1 1
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HALF ADDER USING MUX:

DESIGN: TRUTH TABLE

SUM CARRY
I0 I1 I0 I1 Inputs Outputs
0 1 0 1 A B S C
2 3 2 3 0 0 0 0
A A’ 0 A
0 1 1 0
CIRCUIT: 1 0 1 0
1 1 0 1

FULL ADDER USING MUX:

DESIGN:
SUM CARRY

I0 I1 I3 I3 I0 I1 I3 I3
0 1 2 3 0 1 2 3
4 5 6 7 4 5 6 7
A A’ A’ A 0 A A 1

TRUTH TABLE
Inputs Outputs
A B C S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Logic Design Laboratory Manual 25
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FULL ADDER CIRCUIT

HALF SUBTRACTOR USING MUX:

DESIGN:

DIFFERENCE BORROW
I0 I1 I0 I1
0 1 0 1
2 3 2 3
A A’ 0 A’

CIRCUIT: TRUTH TABLE

Inputs Outputs
A B D Br
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
 Logic Design Laboratory Manual 26
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FULL SUBTRACTOR USING MUX:

DESIGN:
DIFFERENCE BORROW
I0 I1 I2 I3 I0 I1 I2 I3
0 1 2 3 0 1 2 3
4 5 6 7 4 5 6 7
A A’ A’ A 0 A’ A’ 1
TRUTH TABLE
Inputs Outputs
A B C D Br
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

PROCEDURE:
 Check all the components for their working. 
 Insert the appropriate IC into the IC base. 
 Make connections as shown in the circuit diagram. 
Verify the Truth Table and observe the outputs. 

RESULT: Adder and subtractor circuits are realized using multiplexer IC 74153.

VIVA QUESTIONS:

1) What is a multiplexer?
2) What is a de-multiplexer?
3) What are the applications of multiplexer and de-multiplexer?
4) Derive the Boolean expression for multiplexer and de-multiplexer.
5) How do you realize a given function using multiplexer
6) What is the difference between multiplexer & demultiplexer?
7) In 2n to 1 multiplexer how many selection lines are there?
8) How to get higher order multiplexers?
9) Implement an 8:1 mux using 4:1 muxes?
EXPERIMENT: 9 DECODERS
AIM: To realize a decoder circuit using basic gates and to verify IC 74LS139

LEARNING OBJECTIVE:
To learn about working principle of decoder
To learn and understand the working of IC 74LS139
To realize using basic gates as well as universal gates

COMPONENTS REQUIRED:
IC74LS139, IC 7400, IC 7408, IC 7432, IC 7404, IC 7410, Patch chords, & IC Trainer Kit

THEORY:

A decoder is a combinational circuit that connects the binary information from ‘n’ input lines to
n
a maximum of 2 unique output lines. Decoder is also called a min-term generator/max-term
generator. A min-term generator is constructed using AND and NOT gates. The appropriate
output is indicated by logic 1 (positive logic). Max-term generator is constructed using NAND
gates. The appropriate output is indicated by logic 0 (Negative logic).
The IC 74139 accepts two binary inputs and when enable provides 4 individual active low
outputs. The device has 2 enable inputs (Two active low).

CIRCUIT DIAGRAM:

2:4 DECODER (MIN TERM GENERATOR):

TRUTH TABLE:

INPUT OUTPUT
A B Y0 Y1 Y2 Y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

BOOLAEN EXPRESSIONS:
Y 0  AB
Y1  AB
Y 2  AB
Y 3  AB
Logic Design Laboratory Manual 31
___________________________________________________________________________

CIRCUIT DIAGRAM:

2:4 DECODER (MAX TERM GENERATOR):

TRUTH TABLE:

INPUT OUTPUT
A B Y0 Y1 Y2 Y3
0 0 0 1 1 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0

CIRCUIT DIAGRAM:
PROCEDURE:
1. Make the connections as per the circuit diagram.
2. Change the values of G1, G2A, G2B, A, B, and C, using switches.
3. Observe status of Y0, to Y7 on LED’s.
4. Verify the truth table.

RESULT: Verified the Operation of 3 to 8 Decoder

VIVA QUESTIONS:
1. What are the applications of decoder?
2. What is the difference between decoder & encoder?
n
3. For n- 2 decoder how many i/p lines & how many o/p lines?
4. What are the different codes & their applications?
5. What are code converters?
6. Using 3:8 decoder and associated logic, implement a full adder?
7. Implement a full subtractor using IC 74138?
8. What is the difference between decoder and de-mux?
EXPERIMENT: 10 BCD TO 7-SEGMENT DECODER/DRIVER
AIM: To set up and test a 7-segment static display system to display numbers 0 to 9.

LEARNING OBJECTIVE:
To learn about various applications of decoder
To learn and understand the working of IC 7447
To learn about types of seven-segment display

COMPONENTS REQUIRED:
IC7447, 7-Segment display (common anode), Patch chords, resistor (1K ) & IC Trainer Kit

THEORY:

The Light Emitting Diode (LED) finds its place in many applications in these modern electronic
fields. One of them is the Seven Segment Display. Seven-segment displays contains the
arrangement of the LEDs in “Eight” (8) passion, and a Dot (.) with a common electrode, lead
(Anode or Cathode). The purpose of arranging it in that passion is that we can make any
number out of that by switching ON and OFF the particular LED's. Here is the block diagram of
the Seven Segment LED arrangement.

The Light Emitting Diode (LED), finds its place in many applications in this modern electronic
fields. One of them is the Seven Segment Display. Seven-segment displays contains the
arrangement of the LEDs in “Eight” (8) passion, and a Dot (.) with a common electrode, lead
(Anode or Cathode). The purpose of arranging it in that passion is that we can make any
number out of that by switching ON and OFF the particular LED's. Here is the block diagram of
the Seven Segment LED arrangement.

LED‟s are basically of two types-

Common Cathode (CC) -All the 8 anode legs uses only one cathode, which is common.
Common Anode (CA)-The common leg for all the cathode is of Anode type.

A decoder is a combinational circuit that connects the binary information from „n‟ input lines
n
to a maximum of 2 unique output lines. The IC7447 is a BCD to 7-segment pattern converter.
The IC7447 takes the Binary Coded Decimal (BCD) as the input and outputs the relevant 7
segment code.
 Logic Design Laboratory Manual 35
___________________________________________________________________________

CIRCUIT DIAGRAM:

TRUTH TABLE:

Decimal
BCD Inputs Output Logic Levels from IC 7447 to 7-segments number
display
D C B A a b c d e f g
0 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 1 0 0 1 1 1 1 1
0 0 1 0 0 0 1 0 0 1 0 2
0 0 1 1 0 0 0 0 1 1 0 3
0 1 0 0 1 0 0 1 1 0 0 4
0 1 0 1 0 1 0 0 1 0 0 5
0 1 1 0 1 1 0 0 0 0 0 6
0 1 1 1 0 0 0 1 1 1 1 7
1 0 0 0 0 0 0 0 0 0 0 8
1 0 0 1 0 0 0 1 1 0 0 9

PROCEDURE:
  Check all the components for their working. 
  Insert the appropriate IC into the IC base. 
  Make connections as shown in the circuit diagram. 
 Verify the Truth Table and observe the outputs. 

VIVA QUESTIONS:
1. What are the different types of LEDs?
2. Draw the internal circuit diagram of an LED.
3. What are the applications of LEDs?
Logic Design Laboratory Manual 36
___________________________________________________________________________

EXPERIMENT: 11 ENCODERS
AIM:
1. To set up a circuit of Decimal-to-BCD Encoder using IC 74147.
2. To design and set up a circuit of Hexadecimal-to-Binary Encoder using IC
3. 74148 Encoders and IC 74157 Multiplexer

LEARNING OBJECTIVE:
To learn about various applications of Encoders
To learn and understand the working of IC 74147 , IC 74148 & IC 74157
To learn to do code conversion using encoders

COMPONENTS REQUIRED:
IC 74147, IC 74148, IC 74157, Patch chords & IC Trainer Kit

THEORY:
An encoder performs a function that is the opposite of decoder. It receives one or more signals
in an encoded format and output a code that can be processed by another logic circuit. One of
the advantages of encoding data, or more often data addresses in computers, is that it reduces
the number of required bits to represent data or addresses. For example, if a memory has 16
different locations, in order to access these 16 different locations, 16 lines (bits) are required if
the addressing signals are in 1 out of n format. However, if we code the 16 different addresses

into a binary format, then only 4 lines (bits) are required. Such a reduction improves the speed
of information processing in digital systems.

CIRCUIT DIAGRAM:

1) DECIMAL-TO BCD ENCODER USING IC 74147.

TRUTH TABLE
INPUTS OUTPUTS
I1 I2 I3 I4 I5 I6 I7 I8 I9 A3 A2 A1 A0
1 1 1 1 1 1 1 1 0 0 1 1 0
X X X X X X X 0 1 0 1 1 1
X X X X X X 0 1 1 1 0 0 0
X X X X X 0 1 1 1 1 0 0 1
X X X X 0 1 1 1 1 1 0 1 0
X X X 0 1 1 1 1 1 1 0 1 1
X X 0 1 1 1 1 1 1 1 1 0 0
X 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1 1 1
Logic Design Laboratory Manual 37
___________________________________________________________________________

2) OCTAL TO BINARY ENCODER USING IC 74148. TRUTH TABLE

Inputs Outputs
E I I I I I I I I A A A G E
1 0 1 2 3 4 5 6 7 2 1 0 S 0

1 X X X X X X X X 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 1 0
0 X X X X X X X 0 0 0 0 0 1
0 X X X X X X 0 1 0 0 1 0 1
0 X X X X X 0 1 1 0 1 0 0 1
0 X X X X 0 1 1 1 0 1 1 0 1
0 X X X 0 1 1 1 1 1 0 0 0 1
0 X X 0 1 1 1 1 1 1 0 1 0 1
0 X 0 1 1 1 1 1 1 1 1 0 0 1
0 0 1 1 1 1 1 1 1 1 1 1 0 1

3) HEXADECIMAL TO BINARY ENCODER

 Logic Design Laboratory Manual 38
___________________________________________________________________________

TRUTH TABLE

INPUTS OUTPUTS
I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15 Y3 Y2 Y1 Y0
1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0
1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 1
1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0
1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 0
1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 1 1
1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 0 0
1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 0 1
1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 0
1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PROCEDURE:
  Check all the components for their working. 
  Insert the appropriate IC into the IC base. 
  Make connections as shown in the circuit diagram. 
 Verify the Truth Table and observe the outputs. 

VIVA QUESTIONS:
1. What is a priority encoder?
2. What is the role of an encoder in communication?
3. What is the advantage of using an encoder?
4. What are the uses of validating outputs?
Encoders
 Encoder

•An encoder is a combinational logic circuit that essentially

performs a “reverse” of decoder functions.
•An encoder accepts an active level on one of its inputs,
representing digit, such as a decimal or octal digits, and
converts it to a coded output such as BCD or binary.
•Encoders can also be devised to encode various symbols and
alphabetic characters.
•The process of converting from familiar symbols or numbers
to a coded format is called encoding.

2
•Most decoders accept an input code and produce a HIGH
•( or a LOW) at one and only one output line. In otherworlds ,
a decoder identifies, recognizes, or detects a particular code.
The opposite of this decoding process is called encoding and is
performed by a logic circuit called an encoder.
•An encoder has a number of input lines, only one of which
input is activated at a given time and produces an N-bit output
code,depending on which input is activated.

3
 General encoder diagram

4
Logic circuit for octal-to binary encoder [8-line-
3-line ]

5
 Truth table for octal-to binary encoder [8-line- 3-line ]

A low at any single input will produce the output binary code corresponding to that
input. For instance , a low at A3’ will produce O2 =0, O1=1 and O0 =1, which is
binary code for 3. Ao’ is not connected to the logic gates because the encoder
outputs
6 always be normally at 0000 when none of the inputs is LOW
 Design of 4-input Priority Encoder
( 4-line-to 2 line priority encoder) (1)...
• A priority encoder is an encoder that includes the priority
function
• If two or more inputs are equal to 1 at the same time, the
input having the highest priority will take precedence.
• Truth Table of a 4-input Priority Encoder:
Inputs Outputs
D0 D1 D2 D3 x y V
0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X X 1 0 1 0 1
X X X 1 1 1 1
7
 Design of 4-input Priority Encoder
( 4-line-to 2 line priority encoder) (2)...

• In addition to two outputs x, and y, the truth table has a

third output designated by V, which is a valid bit indicator
that is set 1 when one or more inputs are equal to 1. If all
inputs are 0, there is no valid input and V is equal to 0.
• X’s in the output column indicate don’t care conditions,
the X’s in the input columns are useful for representing a
truth table in condensed form.
• The higher the subscript number, the higher the priority
of the input. Input D3 has the highest priority, so
regardless of the values of the other inputs, when this
input is 1, the output for xy is 11 (binary 3)

8
 Design of 4-input Priority Encoder
( 4-line-to 2 line priority encoder) (3)...

V=D0+D1+D2+D3
K-Maps for 4-input Priority Encoder
9
 Design of 4-input Priority Encoder
( 4-line-to 2 line priority encoder) (4)

Logic Diagram for 4-input priority encoder

10
 Decimal-BCD priority encoder

•Encoder will produce a BCD output corresponding to the

highest-order decimal digit input that is active and will ignore
any other lower order active inputs.

•For instance if the input 6 and the 3 are active, the output
will be 1001, which is the inverse value of BCD output 0110
(which represents decimal 6)

11
 74147 decimal-BCD priority encoder

When A9’ is low, the output is 0110, which is

12
inverse of 1001 ( eq to 9 in BCD)
 Decimal- BCD switch decoder

The output of the decoder are inversed to produce the normal

13
BCD value
 The OctaltoBinary Priority Encoder-
Example

• The 74LS148 is a priority encoder that has eight

active LOW inputs and three activeLOW binary
outputs

• To enable the device, the EI (enable input) must

be LOW. It also has the EO (enable output) and
GS (group signal output) for expansion purposes.

14
 The OctaltoBinary Encoder

15
 The OctaltoBinary Encoder

• ActiveLOW enable input, a HIGH on the input forces all outputs

to their inactive state (HIGH).

• ActiveLOW enable output, the output pin goes LOW when all
inputs are inactive (HIGH) and is LOW.

• ActiveLOW group signal output, this output pin goes LOW

whenever any of the inputs are active (LOW) and is LOW.

16
 The 16 to4 Encoder

The 74LS148 can be expanded to a 16lineto4line encoder by

connecting the EO of the higherorder encoder to the EI of the
lowerorder encoder and negativeORing the corresponding
binary outputs as shown

17
 The 16 to4 Encoder

18
 Application example

A simplified keyboard encoder.

19
•When one of the keys is pressed, the decimal digit is encoded to the
corresponding BCD code

•The keys are represented by 10 push-button switches, each with a pull-up

resistor to V+. The pull-up resistor ensures that the line is HIGH when a key is
not depressed.

•When a key is depressed, the line is connected to ground, and a LOW is applied
to the corresponding encoder input.

•The zero key is not connected because the BCD output represents zero when
none of the other keys is depressed

•The BCD complement output of the encoder goes into a storage device, and
each successive BCD code is stored until the entire number has been entered
20
 Assignment - 19

Design a single encoder for following functions.

F1 = Σm(1, 3, 7, 15)
f2 = Σm(4,6,8,10)
 M74HC138

3 TO 8 LINE DECODER (INVERTING)

■ HIGH SPEED:
tPD = 13ns (TYP.) at VCC = 6V
■ LOW POWER DISSIPATION:
ICC = 4µA(MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY:
VNIH = V NIL = 28 % VCC (MIN.)
■ SYMMETRICAL OUTPUT IMPEDANCE: DIP SOP TSSOP
|IOH| = IOL = 4mA (MIN)
■ BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL ORDER CODES
■ WIDE OPERATING VOLTAGE RANGE: PACKAGE TUBE T&R
VCC (OPR) = 2V to 6V
DIP M74HC138B1R
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138 SOP M74HC138M1R M74HC138RM13TR
TSSOP M74HC138TTR
DESCRIPTION
The M74HC138 is an high speed CMOS 3 TO 8 inhibited and all the 8 outputs go high. Three
LINE DECODER fabricated with silicon gate enable inputs are provided to ease cascade
C2MOS technology. connection and application of address decoders
If the device is enabled, 3 binary select inputs (A, for memory systems.
B, and C) determine which one of the outputs will All inputs are equipped with protection circuits
go low. If enable input G1 is held low or either G2A against static discharge and transient excess
or G2B is held high, the decoding function is voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

July 2001 1/10

M74HC138

INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION

PIN No SYMBOL NAME AND FUNCTION

1, 2, 3 A, B, C Address Inputs
4, 5 G2A, G2B Enable Inputs
6 G1 Enable Input
9, 10, 11, 12, Y0 to Y7 Data Outputs
13, 14, 15,
7
8 GND Ground (0V)
16 VCC Positive Supply Voltage

TRUTH TABLE

INPUTS
OUTPUTS
ENABLE SELECT

G2B G2A G1 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X X L X X X H H H H H H H H
X H X X X X H H H H H H H H
H X X X X X H H H H H H H H
L L H L L L L H H H H H H H
L L H L L H H L H H H H H H
L L H L H L H H L H H H H H
L L H L H H H H H L H H H H
L L H H L L H H H H L H H H
L L H H L H H H H H H L H H
L L H H H L H H H H H H L H
L L H H H H H H H H H H H L
X : Don’t Care

LOGIC DIAGRAM

This logic diagram has not be used to estimate propagation delays

2/10
 M74HC138

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

VCC Supply Voltage -0.5 to +7 V
VI DC Input Voltage -0.5 to VCC + 0.5 V
VO DC Output Voltage -0.5 to VCC + 0.5 V
IIK DC Input Diode Current ± 20 mA
IOK DC Output Diode Current ± 20 mA
IO DC Output Current ± 25 mA
ICC or IGND DC VCC or Ground Current ± 50 mA
PD Power Dissipation 500(*) mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature (10 sec) 300 °C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit

VCC Supply Voltage 2 to 6 V
VI Input Voltage 0 to VCC V
VO Output Voltage 0 to VCC V
Top Operating Temperature -55 to 125 °C
Input Rise and Fall Time VCC = 2.0V 0 to 1000 ns
tr, tf VCC = 4.5V 0 to 500 ns
VCC = 6.0V 0 to 400 ns

3/10
M74HC138

DC SPECIFICATIONS

Test Condition Value

Symbol Parameter TA = 25°C -40 to 85°C -55 to 125°C Unit

VCC
(V)
Min. Typ. Max. Min. Max. Min. Max.
VIH High Level Input 2.0 1.5 1.5 1.5
Voltage 4.5 3.15 3.15 3.15 V
6.0 4.2 4.2 4.2
VIL Low Level Input 2.0 0.5 0.5 0.5
Voltage 4.5 1.35 1.35 1.35 V
6.0 1.8 1.8 1.8
VOH High Level Output 2.0 IO=-20 µA 1.9 2.0 1.9 1.9
Voltage IO=-20 µA
4.5 4.4 4.5 4.4 4.4
6.0 IO=-20 µA 5.9 6.0 5.9 5.9 V
4.5 IO=-4.0 mA 4.18 4.31 4.13 4.10
6.0 IO=-5.2 mA 5.68 5.8 5.63 5.60
VOL Low Level Output 2.0 IO=20 µA 0.0 0.1 0.1 0.1
Voltage IO=20 µA
4.5 0.0 0.1 0.1 0.1
6.0 IO=20 µA 0.0 0.1 0.1 0.1 V
4.5 IO=4.0 mA 0.17 0.26 0.33 0.40
6.0 IO=5.2 mA 0.18 0.26 0.33 0.40
II Input Leakage
6.0 VI = VCC or GND ± 0.1 ±1 ±1 µA
Current
ICC Quiescent Supply
6.0 VI = VCC or GND 4 40 80 µA
Current

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)

Test Condition Value

Symbol Parameter TA = 25°C -40 to 85°C -55 to 125°C Unit

VCC
(V) Min. Typ. Max. Min. Max. Min. Max.
tTLH tTHL Output Transition 2.0 30 75 95 110
Time 4.5 8 15 19 22 ns
6.0 7 13 16 19
tPLH tPHL Propagation Delay 2.0 60 125 155 190
Time (A, B, C - Y) 4.5 15 25 31 38 ns
6.0 13 21 26 32
tPLH tPHL Propagation Delay 2.0 56 120 150 180
Time (G, G - Y) 4.5 14 24 30 36 ns
6.0 12 20 26 31

4/10
 M74HC138

CAPACITIVE CHARACTERISTICS

Test Condition Value

Symbol Parameter TA = 25°C -40 to 85°C -55 to 125°C Unit

VCC
(V)
Min. Typ. Max. Min. Max. Min. Max.
CIN Input Capacitance 5.0 5 10 10 10 pF
CPD Power Dissipation
Capacitance (note 5.0 47 pF
1)
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC

TEST CIRCUIT

CL = 50pF or equivalent (includes jig and probe capacitance)

RT = ZOUT of pulse generator (typically 50Ω)

WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING OUTPUTS (f=1MHz; 50% duty cycle)

5/10
M74HC138

WAVEFORM 2: PROPAGATION DELAYS FOR NON-INVERTING OUTPUTS (f=1MHz; 50% duty cycle)

6/10
 M74HC138

Plastic DIP-16 (0.25) MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 0.77 1.65 0.030 0.065

b 0.5 0.020

b1 0.25 0.010

D 20 0.787

E 8.5 0.335

e 2.54 0.100

e3 17.78 0.700

F 7.1 0.280

I 5.1 0.201

L 3.3 0.130

Z 1.27 0.050

P001C

7/10
M74HC138

SO-16 MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 1.75 0.068
a1 0.1 0.2 0.003 0.007
a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45° (typ.)
D 9.8 10 0.385 0.393
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F 3.8 4.0 0.149 0.157
G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0.050
M 0.62 0.024
S 8° (max.)

PO13H

8/10
 M74HC138

TSSOP16 MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.

A 1.2 0.047

A1 0.05 0.15 0.002 0.004 0.006

A2 0.8 1 1.05 0.031 0.039 0.041

b 0.19 0.30 0.007 0.012

c 0.09 0.20 0.004 0.0089

D 4.9 5 5.1 0.193 0.197 0.201

E 6.2 6.4 6.6 0.244 0.252 0.260

E1 4.3 4.4 4.48 0.169 0.173 0.176

e 0.65 BSC 0.0256 BSC

K 0° 8° 0° 8°

L 0.45 0.60 0.75 0.018 0.024 0.030

A A2
K L
A1 b e
c E

E1

PIN 1 IDENTIFICATION
1
0080338D

9/10
M74HC138

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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10/10
 Experiment 5

Arithmetic Logic Unit (ALU)

Objectives:

To implement and test the circuits which constitute the arithmetic logic circuit (ALU).

Background Information:

The basic blocks of a computer are central processing unit (CPU), memory unit, and input/output unit. CPU
of the computer is basically the same as the brain of a human being. It contains all the registers, control
unit and the arithmetic logic unit (ALU). ALU considered as the most important subsystem in a digital
computer. An arithmetic logic unit (ALU) is a digital circuit which performs arithmetic, logic and shift
operations on two n-bit digital words. Functionally, an ALU can be divided up into three circuits: the
arithmetic circuit, the logic circuit and the shift circuit.

ALU arithmetic Circuit:

The arithmetic circuit performs typical arithmetic operations such as addition, subtraction and increment
or decrement by one. The basic component of an arithmetic circuit is the Full adder. By using a multiplexer
to control the data inputs to the adder, it is possible to obtain different types of arithmetic operations. In
this experiment we will implement a 4-bit arithmetic circuit, its logic diagram is shown in Figure 5-1. The
four multiplexers select either B, B', 0 or 1 for the Y inputs of the full adder. Depending on the selection
inputs and the input carry, the arithmetic circuit can generates the eight arithmetic micro operations listed
in Table 5-1.

select Output D
Input Y Micro operation
S1 S0 Cin D = A + Y + Cin
0 0 0 B A+B Add
0 0 1 B A+B+1 Add with Carry
0 1 0 B' A + B' Subtract with borrow
0 1 1 B' A–B Subtract
1 0 0 0 A Transfer A
1 0 1 0 A+1 Increment A by 1
1 1 0 1 A–1 Decrement A by 1
1 1 1 1 A Transfer A

Table 5-1 : Function table of the 4-bit arithmetic circuit

 Figure 5-1 : Circuit diagram of the 4-bit arithmetic circuit

Equipments:

1. 4x 4-to-1 MUXs (2x 74153 chips).

2. 1x 4-bit full adder (1x 74283 chip).
3. 5X Inverters (1x 7404 chip).
4. Logic Trainer.
5. Connection leads.

Procedures:

1. Bring all IC chips necessary to build the circuit from the IC cabinet.
2. Bring some connection leads with varying lengths.
3. Derive the wiring diagram for the logic diagram shown in Figure 5-1.
4. Insure that the power switch of the IC trainer is turned off.
 5. Plug the IC chips into the proper sockets.
6. Connect the voltage supply and ground lines to the chips.
7. Use the connection leads to connect the circuit according to the derived wiring diagram.
8. Once all connections have been done, turn on the power switch of the IC trainer .
9. Verify the circuit function for all micro operations listed in table 5-1.
10. After finishing the experiment, turn off the power switch, disconnect the wires, and take out the IC
chips from the trainer.

ALU Logic Circuit:

The ALU, logic circuit performs the basic logic micro operations: NOT, AND, OR and XOR. From these four
micro operations all known logic micro operations can be derived. Figure 5-2 shows the logic diagram for
one stage of logic circuit. The four gates generates the four logic operations and the multiplexer select the
desired operation as shown in Table 5-2.

S1 S0 Output Operation
0 0 AB AND
0 1 A+B OR
1 0 A⊕B XOR
1 1 A' Complement

Table 5-2 : Function table of the 2-bit logic circuit

Figure 5-2 : Circuit diagram of the 2-bit logic circuit

Equipments:

1. 1x 4-to-1 MUXs (1x 74153 chips).

2. 1x AND Gate (1x 7408 chip).
3. 1x OR Gate (1x 7432 chip).
4. 1x XOR Gate (1x 7486 chip).
5. 1x NOT Gate (1x 7404 chip).
6. Logic Trainer.
7. Connection leads.
Procedures:

1. Bring all IC chips necessary to build the circuit from the IC cabinet.
2. Derive the wiring diagram for the logic diagram shown in Figure 5-2.
3. Insure that the power switch of the IC trainer is turned off.
4. Plug the IC chips into the proper sockets.
5. Connect the voltage supply and ground lines to the chips.
6. Use the connection leads to connect the circuit according to the derived wiring diagram.
7. Once all connections have been done, turn on the power switch of the IC trainer.
8. Verify the circuit function.
9. After finishing the experiment, turn off the power switch, disconnect the wires, and take out the IC
chips from the trainer.

ALU Shift Circuit:

Shift circuit used to perform the shift micro operations. The contents of a register can be shifted serially to
the left or to the right. The shift circuit contains multiplexers as shown in Figure 5-3. when the select line is
0 the 4-bit input data are shifted right. When the select line is 1 the input data are shifted left. There are
two serial inputs one for shift left and other one for shift right. The function table shows the outputs of the
multiplexers in each case.

H3
S
H3 H2 H1 H0
0 IR A3 A2 A1
1 A2 A1 A0 IL

Table 5-3 : Function table of the 4-bit shift circuit

Figure 5-3 : Circuit diagram of the 4-bit shift circuit

Equipments:

1. 4x 2-to-1 MUXs (1x 74157 chip).

2. Logic Trainer.
3. Connection leads.

Procedures:

1. Bring the IC chip necessary to build the circuit from the IC cabinet.
2. Derive the wiring diagram for the logic diagram shown in Figure 5-3.
3. Insure that the power switch of the IC trainer is turned off.
4. Plug the IC chip into the proper socket.
5. Connect the voltage supply and ground lines to the chip.
6. Use the connection leads to connect the circuit according to the derived wiring diagram.
7. Once all connections have been done, turn on the power switch of the IC trainer.
8. Verify the circuit function according to its function table.
9. After finishing the experiment, turn off the power switch, disconnect the wires, take out the IC
chip from the trainer, put back everything you have used, close IC trainer and clean your table.