Analog and Digital Systems Design Laboratory

SRI SAIRAM COLLEGE OF ENGINEERING

ANEKAL, BENGALURU-562106

DEPARTMENT OF
ELECTRONICS & COMMUNICATION ENGINEERING

LAB MANUAL
FOR
ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY
(BECL305)
(III SEMESTER ECE)

Prepared by
Prof. ARIVARASI A

Prof. RADHIKA M

Programme Co-coordinator

1
 Analog and Digital Systems Design Laboratory SRI SAIRAM COLLEGE OF ENGINEERING, BENGALURU

ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY

Subject Code: BECL305 Total Hours: 40
Hours/Week: 3 hour Exam Hours: 03
Subject Code BECL305
CIE Marks 50
SEE Marks 50
Course objectives
This lab course will enable students to

• Understand the operation of electronic circuits and their working.

• Realize and test amplifier and oscillator circuits for the given specifications
• Realize the Op-amp circuits for the applications such as DAC, mathematical operations
• Design and test the combinational and sequential logic circuits for their functionalities
• Use the suitable ICs based on the specifications and functions
Course Outcomes
After studying this course, students will be able to:
CO1 Design and analyse BJT/FET amplifier and oscillator circuits.
Design and test Op-amp circuits realizing mathematical functions, DAC and
CO2
precisionrectifiers.
CO3 Design and test combinational circuits for the given specifications
CO4 Design and test the sequential logic circuits for the given specifications
CO5 Design and test specialized IC circuits such as 555 timer, power amplifier and
voltageregulators

2
 Analog and Digital Systems Design Laboratory SRI SAIRAM COLLEGE OF ENGINEERING, BENGALURU

List of the Experiments

Bloom’s
Sno Experiments Taxonomy
Cycle 1 Experiments (Analog circuits)
Design and set up the BJT common emitter voltage amplifier with and L1, L2, L3, L4
1 without feedback and determine the gain- bandwidth product, input and
output impedances.
Design and set-up BJT/FET L1, L2, L3, L4
2 i)Colpitts Oscillator ii) Crystal oscillator
Design Adder, Integrator, Differentiator andComparator circuits L1, L2, L3, L4
3 using OPAMP
4 Design 4-bit R-2R Op-Amp Digital to Analogconverter L1, L2, L3, L4
i) using 4-bit binary input from toggle switches
ii) by generating digital inputs using mod-16counter.
Cycle 2 Experiments (Digital circuits)
Design and implement (a) Half Adder and Full adder using basic gates and L1, L2, L3, L4
5 NAND gates (b) Half subtractorand full subtractor using NAND gates
(c) 4-variable function using IC74151 (8:1 Mux)
Realize (i) Binary to Gray code conversion and vice- versa (IC74139) L1, L2, L3, L4
6 (ii) BCD to Excess-3 code conversionand vice-versa.
a) Realize using NAND Gates: (i) Master-Slave JKFlip-flop (ii) D Flip- L1, L2, L3, L4
7 flop (iii) T Flip-flop
b) Realize the following shift register operations using IC7474/7495: (i)
SISO (ii) SIPO (iii) PIPO
(iv) PIPO (v) Ring counter (vi) Johnson counter
Design and realize a) Mod-N Synchronous UpCounter and Down Counter L1, L2, L3, L4
8 using 7476 JK Flip-flop
b) Mod-N Counter using IC 7490/7476 c)Synchronous Counter
using IC 74192

Cycle 3 Demonstration Experiments

9 Design and Test the second order Active Filters and plot the frequency L1, L2, L3, L4
response,
i) Low pass Filter ii) High pass Filter
10 Design and test the following using 555 timer i) Monostable L1, L2, L3, L4
Multivibrator ii) Astable Multivibrator
11 Design and test a regulated Power supply L1, L2, L3, L4
12 Design and test an audio amplifier by connecting a microphone input and L1, L2, L3, L4
observe the output using a loudspeaker

3
Analog and Digital Systems Design Laboratory

Experiment No. 1

BJT COMMON EMITTER VOLTAGE AMPLIFIER

Version 1
AIM: To conduct an experiment on CE-Amplifier without feedback and with feedback and to obtain
the performance parameters

COMPONENTS REQUIRED:

Apparatus and
Sl. No Range
components
01 NPN transistor, FET CL100

02 Resistors 220Ω,5.7KΩ,25KΩ,820Ω

03 Capacitors 0.47uF ,100 µf

04 VRPS 0-30Vdc 3A
05 Signal generator 10Hz to 1MHz
06 CRO for testing
07 Probes, wires

08 DRB 0 to 1MΩ

09 Breadboard

THEORY: -
In RC coupled amplifier the input capacitor is used to couple the input signal to the base of first
transistor. Since the coupling from one stage to next stage can be achieved by a coupling capacitor
followed by a connection to a shunt resistor such amplifiers are called resistance capacitance (RC)
coupled amplifiers. When an ac signal is applied to the input of the first stage it is amplified with a
phase reversal by the transistor. The frequency response is a graph of the gain (in decibels) versus the
frequency (in logarithmic scale). This characteristic can be subdivided into low, medium and high
frequency regions. In the low frequency range, the gain drops due to increasing reactance of coupling
capacitor, source capacitance and emitter capacitor. As the frequency increases, the capacitive reactance
reduce and the gain increases. After this if the frequency is increased further, i.e. in the high frequency
range, the gain drops due to the increased flow of the a.c signal through CE. To fix the boundaries of
frequency where the gain is relatively high and constant, 0.707Amid is chosen to be the voltage gain at
the cut-off levels. The corresponding frequencies f1 and f2 are generally called the corner, cut-off, band,
break or half power frequencies. The multiplier 0.707 is chosen because at this level the output power is
half the mid-band power output. This is illustrated in the model graph.

4
Analog and Digital Systems Design Laboratory

CIRCUIT DIAGRAM

Fig 1: CE Amplifier without feedback

DESIGN
Given: Vcc=10 V, Ic =5 mA, β=150
Assume VRE =Vcc/10=10/10=1 V
To find RE :
VE=IE*RE =1.2 V
RE = VE / Ic
= VE / IE (as IE =Ic)
=1V/5m
=200 ohm≈220Ω
RE =220Ω
To find Rc:
Choose VcE =Vcc/2=10/2=5 V
Apply KVL in CE loop:
Vcc-IcRc- VcE - IERE =0
10-(5m*Rc)-5-1=0
Rc=800ohm≈820Ω
To find R1 & R2:
VB = VBE+ VRE
VB =0.7+1=1.7V
Ic=β IB
IB = Ic/ β =5m/150=33µA
Take I2=10IB & I1=10IB+IB

5
Analog and Digital Systems Design Laboratory

R1= Vcc -VB/I1=25 KΩ ≈22KΩ

Let R2= VB/I2 =5 .7KΩ ≈5 .6KΩ
To find CE
Xc<RE/10
Let Xc= RE /10, at f=100Hz
1/(2π*f* CE )= RE /10=220Ω/10
Therefore
CE =72.3 µF
Choose CE ≈100 µF
PROCEDURE

1. Rig up the circuit as shown in the circuit diagram without connecting signal generator check the
biasing conditions i.e. VCC =10V i.e. check VCE,VBE,VE.

2. Connect the signal generator and set the input voltage constant 50mVp-p at 1KHz.

3. Now vary the input frequency from 100Hz and note the corresponding output voltage.

4. Plot the frequency v/s output voltage graph in decibel gain with frequency on X-axis and dB
gain on Y-axis and determine the bandwidth.

TABULAR COLUMN:

Output voltage Voltage Gain

Frequency f (Hz) Gain(dB) =20 log (Vo / Vi)
(VOP-P) Volts Vo / Vi

6
Analog and Digital Systems Design Laboratory

FREQUENCY RESPONSE:

To measure Zi

PROCEDURE:
❖ Connect the circuit as shown in above figure
❖ Set the following
• DRB to 0Ω
• Input sine wave amplitude to say 40 mV
• Input sine wave frequency to any mid frequency say 10 KHz.
❖ Measure amplitude of Vop-p. Let Vo=Va say
❖ Increase DRB (keeping Vi constant) till Vo=Va/2.The corresponding DRB gives the input
impedance Zi in RC coupled amplifier
To measure Zo:

PROCEDURE:
❖ Connect the circuit as shown in the above figure
❖ Set the following
• DRB to its maximum resistance value.
• Input sine wave amplitude to about 40 mV
• Input sine wave frequency to 10 KHz.
❖ Measure Vop-p. Let Vo=Vb
❖ Decrease DRB from its maximum value till Vo=Vb/2.The corresponding DRB gives the output
impedance Zo.
Input Resistance = Output Resistance =

Result:

7
Analog and Digital Systems Design Laboratory

Experiment No. 2 Colpitts Oscillator and Crystal Oscillator

Aim: To test the working of Colpitts Oscillator and Crystal Oscillator at RF range

COMPONENTS REQUIRED:

Sl. No Apparatus and components Range Quantity

01 Spring board 1
02 NPN transistor BC547 or BC107 1
220Ω, 5.6KΩ, 22KΩ,820Ω
03 Resistors 1
0.47µF, 100µF,
04 Capacitors 0.001µF 2+1+3

05 Inductor 4 mH 1
05 VRPS 0-30Vdc 3A 1
06 CRO for testing 1
07 Probes, wires 1
08 Multimeter for testing 1
09 Potentiometer 10 KΩ 1
10 Crystal 2Mhz 1

THEORY:
Colppits oscillator:

If the oscillator uses two capacitive and one inductive reactance in the feedback circuit
then it is called as colpitts oscillator. The working principle of Hartley and colpitts
oscillators is same,only difference is that the tank circuit is designed with two capacitors
and one inductor for providing oscillations. The function of all the components present
in the colpitts oscillator circuit is same as Hartley oscillator.

Design for Colpitts Oscillator, Crystal Oscillator, RC phase shift Oscillator:

Given Vcc=10 V, Ic =5 mA, β=150

Assume VRE
=Vcc/10=10/10=1 V
To find RE :
VE=IE*RE
=1.2 VRE =
VE / Ic
= VE / IE (as IE =Ic)
=1V/5m
=200 ohm≈220Ω
RE =220Ω
8
Analog and Digital Systems Design Laboratory

To find Rc:
Choose VcE
=Vcc/2=10/2=5 VApply
KVL in CE loop:
Vcc-IcRc- VcE -
IERE =010-
(5m*Rc)-5-1=0
Rc=800ohm≈820Ω

To find R1 & R2:

VB = VBE+
VRE VB
=0.7+1=1.7
V
Ic=β IB
IB = Ic/ β =5m/150=33µA
R1= Vcc -VB/10 IB=25 KΩ
≈22KΩLet R2= VB/9IB =5
.7KΩ ≈5 .6KΩ

To find CE
Let Xc= RE /10, at f=100Hz
1/(2π*f* CE )= RE
/10=220Ω/10
Therefore
CE =72.3 µF
Choose CE
≈100 µF
Tank circuit design

For Colpitts oscillator

Given f
=100KHzf =
1 / 2π√L Ceq
Let C1 = 0.001µF; C2 =0.002µF
Ceq = ( C1* C2 ) / ( C1 + C2 ) = 0.666nF
L = 1 / ( 4 π2 * 0.66nF * f 2 ) ≈
0.0038HL ≈3.8mH

PROCEDURE:

1. Rig up the circuit diagram as shown in the circuit diagram without the tank circuit and check the
biasing conditions with Vcc=10V i.e. check VCE,VBE and VE.

2. Connect the tank circuit and vary the 10K pot to get proper sine wave across the output
terminals and check the frequency of output waveform and compare it with the theoretical
value and tabulate the readings.

9
Analog and Digital Systems Design Laboratory

CIRCUIT DIAGRAM:

Fig2 : Colppits Oscillator

OUTPUT WAVEFORMS:
Output Waveforms colpitts oscillators is shown in the figure below.

Fig. Output waveform of COLPITTS oscillator

10
Analog and Digital Systems Design Laboratory

Colpitt’s Oscillator: f0 (observed) = Hz

f0 (designed) = Hz

CIRCUIT DIAGRAM:

Fig. Crystal oscillators

OUTPUT WAVE FORMS:

Fig. Output waveform of Crystal oscillators

RESULT:

1. The frequency of the given crystal is MHz

2. The frequency of the output waveform obtained practically is MHz.

11
Analog and Digital Systems Design Laboratory

Experiment No. 3 Adder, Differentiator, Integrator and Comparator

Aim: To design and conduct experiments on Adder, Differentiator and Integrator Circuits
COMPONENTS REQUIRED:

Sno Bread board 1

1. Regulated power supply 1
2. CRO 1
3. IC 741 1
4. Resistors 10k , 100K 1 each
5. Resistors 10k , 4
6. Resistors 1k , 2 each
7. Resistors 1.5 k , 150 , 3.3k ,2.2k , 1 each
8. Capacitor 0.01 F, 0.1 F 1 each
9. Function generator 1 Hz to 2MHz 1
1 Connecting wires
CIRCUIT DIAGRAMS:

ADDER: Rf = 10k R1 = R2 = 10k R = 3.3k

Fig 1. OP-AMP ADDER

If R1 = R2 = Rf = R, then

V0 = - (V1 + V2)

12
Analog and Digital Systems Design Laboratory

COMPARATOR: R, R = 1k (2 Nos.), R0 = 2.2k

Fig 2. COMPARATOR

Vo = +Vsat for Vi > Vref

= -Vsat for Vi < Vref

Practical Integrator Rf = 100k , R1 = 10K , Cf = 0.1 f

Fig 3. Integrator Circuit

13
Analog and Digital Systems Design Laboratory

Practical Differentiator Rf = 1.5 k , R1 = 150 , Cf = 0.1 f, C1 = 0.01 f

Fig 4. Differentiator circuit

Procedure:

ADDER:

1. Connect the circuit as shown in the adder circuit diagram (fig 1).
2. Apply the supply voltages of +15V to pin 7 and -15V to pin 4 of IC 741 respectively from IC Trainer
kit. Connect the ground to the ground point.
3. Apply DC voltage from regulated power supply to inputs V1 and V2.
4. Apply V1 = 1 V and Increase V2 from 0V to 5V in steps of 1V. Repeat the same for V1 = 3V and V1 =
5V.
5. Note down the Vo using Voltmeter.
6. Compare theoretical and practical values.

COMPARATOR:

1. Connect the circuit as shown in the figure 2.

2. Apply the supply voltages of +15V to pin 7 and -15V to pin 4 of IC 741 respectively from IC Trainer
kit. Connect the ground to the ground point.
3. Set the reference voltage as 1V DC.
4. Apply sine wave of 10Vp-p with1KHz frequency from the function generator as Vi.

14
Analog and Digital Systems Design Laboratory

5. Check the output in CRO and calculate the amplitude of the output wave form.
6. Plot the waveforms on graph sheets as shown in fig 4.
7. Compare the output wave form amplitude with input signal amplitude.
8. Change the reference voltage as -1V and repeat the experiment.

INTEGRATOR:

1. Connect the circuit as shown in fig 3.

2. Apply a symmetrical square wave of 2Vp-p amplitude and 1 KHz frequency.
3. Connect the input and output of the circuit to channel 1 and channel 2 of the CRO respectively and
observe the waveforms.
4. Draw the waveforms along with the levels on a graph.
5. Compare the practical values with theoretical values.
6. Repeat the same for sine-wave.

DIFFERENTIATOR:

1. Connect the circuit as shown in fig 4.

2. Apply a symmetrical triangular wave of 2Vp-p amplitude and 1KHz frequency.
3. Connect the input and output of the circuit to channel 1and channel 2 of the CRO respectively and
observe the waveforms.
4. Draw the waveforms along with the levels on a graph.
5. Compare the practical values with theoretical values.
6. Repeat the same for the sine-wave.
7. TABULAR FORM:

ADDER:

S.No D.C Voltage at input V1 (V) D.C Voltage at input V2 (V) D.C Voltage at Output Vo (V)
1
2
3
4

15
Analog and Digital Systems Design Laboratory

EXPECTED WAVEFORMS:

COMPARATOR:

Fig 5.Comparator Waveforms

Fig 6:Integrating square wave

16
Analog and Digital Systems Design Laboratory

Fig 7: Differentiator output for triangular wave

RESULT:

17
Analog and Digital Systems Design Laboratory

Experiment No: 4 Digital to Analog Converter (DAC)

Aim: To design and conduct experiment on Digital to Analog Converter

Components required: Bread board, Multi-meter, Signal generator, CRO with probes, Power supply,
Op-Amp µA741, Resistor = 1k Ω, 90k Ω, IC 7493, Connecting wires.
Theory:
The digital to analog converter accepts n-bit word b1, b2------------- bn in binary and
produce analog signal proportional to it. These are 4 digital input in a 4-bit DAC. Each digital
input requires an electrical signal representing either logic 1 or logic 0. The bn is the LSB and
b1 is the MSB.R-2R ladder DAC uses only 2 resistors values this avoids resistance spread
drawback of binary weighted DAC. In R-2R ladder DAC, reference voltage is applied to one of
the switch positions and other switch position is connected to ground.

Circuit Diagrams: R-2R DAC of 4-Bit:

Design:

Vout = - Itot * R

Put N= 4,

Hence - Itot = Do Vref + D1 Vref + D2 Vref + D3 Vref

16R 8R 4R 2R

Now Vout = - Rf Vref Do + D1 + D2 + D3

16R 8R 4R 2R

Let R = 1KΩ, Vref = 5V, Rf = 2R

18
Analog and Digital Systems Design Laboratory

Tabular Column:

Digital Values Theoretical Values Practical Values

Digital inputs
D3 D2 D1 D0 (Vout) (Vout)
0000 0 0V
0001 1 - 0.625V
0010 2 -1.25V
0011 3 -1.875V
0100 4 -2.5V
0101 5 -3.125V
0110 6 -3.75V
0111 7 -4.375V
1000 8 -5V
1001 9 -5.625V
1010 10 -6.25V
1011 11 -6.875V
1100 12 -7.5V
1101 13 -8.125V
1110 14 -8.75V
1111 15 -9.375V

Expected Graph:

Figure-2: Analog Output v/s binary input

19
Analog and Digital Systems Design Laboratory

Staircase Waveform using DAC

EXPECTED GRAPH:

Calculation:
Step width =
Step size =
No. of steps = 2no. of bit[N] – 1 =

20
 Analog and Digital Systems Design Laboratory

PROCEDURE:

1. Design the circuit as per the circuit specifications.

2. Rig up the circuit.
3. For logic1 input, connect the switch to Vref=5v and for logic 0 input, connect the switch
to ground.
4. For different combination of digital input note down the output voltage.
5. Verify Practical and theoretical voltage.
6. Connect the IC 7493 to the switches and obtain the staircase wave.
7. Note the step size and find the resolution.

Result:

24
 Analog and Digital Systems Design Laboratory

Experiment 5: HALF ADDER ANF FULL ADDER

AIM: a) To realize the Half/Full Adder using Basic Logic Gates and NAND gate and also verify the
results using truth table.
b) To realize the Half/Full Subtractor using Basic Logic Gates and NAND gate and also verify
the results using truth table.\
COMPONENTS REQUIRED:
The following components are needed to perform all the procedures:
IC Trainer kit, Patch chords, IC7408, IC7432, IC7404, IC7486, IC7400, IC7402
THEORY:
ADDER
An adder or summer is a digital circuit that performs addition of numbers. The half adder adds twosingle
binary digits A and B. It has two outputs, sum (S) and carry (C). A full adder adds three one-bit numbers,
often written as A, B, and Cin, A and B are the operands, and Cin.
SUBTRACTOR: A subtractor is a digital circuit that performs subtraction of numbers. The half-
subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs,
A (minuend) and Bin (subtrahend) and two outputs D (difference) and B (borrow). The full-subtractor is
a combinational circuit which is used to perform subtraction of three bits. It has three inputs, A
(minuend) and B (subtrahend) and C (subtrahend) and two outputs D (difference) and B out (borrow).
APPLICATIONS OF ADDERS AND SUBTRACTORS
Full adder reduces circuit complexity. It can be used to construct a ripple carry counter to add an n- bit
number. Thus it is used in the ALU also. It is used in Processor chip like Snapdragon, Exynousor Intel
pentium for CPU part which consists of ALU (Arithmetic Block unit). This Block is used to make
operations like Add, subtract, Multiply etc. A full adder adds binary numbers and accounts for values
carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as A, B, and Cin;
A and B are the operands, and Cin is a bit carried in from the previous less significant stage. The full
adder is usually a component in a cascade of adders, which add 8, 16, 32,etc. bit binary numbers.
PROCEDURE
• Collect the components necessary to accomplish this experiment.
• Plug the IC chip into the IC Trainer kit.
• Connect the supply voltage and ground lines to the chips. PIN7 = Ground and PIN14
=+5.
• Perform the other connections as shown in the circuit diagram.
• Once all connections have been done, turn on the power switch of the Trainer kit.
• Operate the switches and fill in the truth table.

• After finishing the experiment, turn off the power switch, disconnect the wires, take out all
IC chips from the trainer, put back everything you have used and clean your table.

25
 Analog and Digital Systems Design Laboratory

Table 5.1 Truth table represents HALF ADDER

A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Figure 5.1 Shows the circuit for half adder implemented using basic gates

Table 5.2 Truth table represents FULL ADDER

A B Cin SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Sum & Carry Expressions:

Figure Full adder implemented using Basic gates

26
Analog and Digital Systems Design Laboratory

Figure Full adder implemented using NAND gates

Table 5.3 Truth table represents HALF SUBTRACTOR

Figure Half subtractor implemented using basic gates

27
 Analog and Digital Systems Design Laboratory

Truth table represents of FULL SUBTRACTOR

Difference & Borrow Expressions:

Figure 5.5 Shows the circuit for full subtractor implemented using BASIC gates

28
 Analog and Digital Systems Design Laboratory

Figure 5.6 Shows the circuit for full subtractor implemented using NAND gates

Figure 5.7 Shows the circuit for full subtractor using NOR gates

c) 4-variable function using IC 74151(8:1MUX)

COMPONENTS REQUIRED: IC 74151, IC Trainer Kit, and Patch Chords

THEORY: Multiplexer is a combinational circuit that is one of the most widely used in digital
design. The multiplexer is a data selector which gates one out of several inputs to a single o/p. It has n
data inputs & one o/p line & m select lines where 2m= n. Depending upon the digital code applied at the
select inputs one out of n data input is selected & transmitted toa single o/p channel. Normally strobe
(E) input is incorporated which is generally active low which enables the multiplexer when it is LOW.
IC 74151A is an 8: 1 multiplexer which provides two complementary outputs Y & Y. The o/p Y is same
as the selected i/p & Y is its complement. The n: 1 multiplexer can be used to realize a ‘m’ variable
function. (2m= n, m is no. of select inputs). Multiplexer is considered to be a Data selector, based in this
phenomenon, a minimal Multiplexer circuit can be designed by transferring the information in the truth
tableto a K-map.

29
 Analog and Digital Systems Design Laboratory

Table 5c.1 Generalized truth table of 8:1 Multiplexer

Applications of Multiplexers: A Multiplexer is used in numerous applications like, where multiple data
can be transmitted using a single line.
Communication System – A Multiplexer is used in communication systems, allows transmission of data
such as audio & video data from different channels through a single line.
Telephone Network – A multiplexer is used in telephone networks to integrate the multipleaudio signals
on a single line of transmission.
PROCEDURE:
1) Connections are made to the respective pins of IC 74151. Switch on VCC for the power supply
2) Keep the E strobe pin active low
3) Apply various combinations of input according to the truth table.

30
 Analog and Digital Systems Design Laboratory

SYMBOL

Figure 5c.1 Symbol of 8:1 MUX

DESIGN:
Four variable functions:
Example: Let F (A,B,C,D) = Σ m(1,3,4,5,6,11,15), So D1, D3, D4 , D5, D6, D11 D15= 1 and the
other data bits are grounded as shown in the Circuit diagram below, Select Lines S2=B, S1=C,S0=D
The corresponding K MAP, Three Variable equation and Truth table is shown below

Figure 5b.4 K map for three variable functions

31
 Analog and Digital Systems Design Laboratory

IC74151 Pin Diagram

Logic Diagram:

Figure 5b.6 Circuit Diagram to implement Four Variable functions

32
 Analog and Digital Systems Design Laboratory

Table 5.2 Truth Table

Inputs Output
Decimal A B C D Y
Inputs
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 0
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 0
8 1 0 0 0 0
9 1 0 0 1 0
10 1 0 1 0 0
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 1

Result:

33
 Analog and Digital Systems Design Laboratory

Experiment 6: BINARY TO GRAY CONVERSION

AIM: a) Realize Binary to Gray Conversion using 74139

COMPONENTS REQUIRED: IC 74139, IC Trainer Kit, and Patch Chords

THEORY:
The 74139 (common variants 74LS139, 74HC139) is a dual 2-to-4-line decoder/demultiplexer
in the 7400 series. Each side of the chip is a decoder with an activelow enable from a 2-bit address to
four active low signals. The two decoders can be wiredindependently, or a /Y from one decoder can be
wired to the /E on the other to calculate more complex combinational logic functions.
Applications of Decoders:
1. Microprocessors Memory Systems: Selecting different banks of Memory
2. Microprocessors input/output systems: Selecting different devices

SYMBOL:

Figure 6a.1 Symbol of Dual 2:4 line Decoder

Table 6a.2 Binary to gray code conversions

Binary Code Gray Code
B2 B1 B0 G2 G1 G0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0

34
Analog and Digital Systems Design Laboratory

Figure 6a.2 Binary to Gray code conversion

Figure 6a.3 Logic Diagram using 74LS139

Gray to Binary Conversion

Figure 6a.4 Logic for converting Gray code to Binary

35
 Analog and Digital Systems Design Laboratory

Table 6a.2 Truth Table representing 3 bit Gray to Binary codes

Gray Code Binary Code
G2 G1 G0 B2 B1 B0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 1
1 0 1 1 1 0
1 1 0 1 0 0
1 1 1 1 0 1

Figure 6a.5 Logic Diagram for Gray to Binary code using 74LS139
Result:

36
Analog and Digital Systems Design Laboratory

b)BCD TO EXCESS-3 CODE CONVERSION

Aim: b) To realize BCD TO EXCESS-3 CODE CONVERSION AND VISE VERSA USING IC 7483

Theory:

Code converter is a combinational circuit that translates the input code word into a new
corresponding word. The excess-3 code digit is obtained by adding three to the corresponding BCD
digit. To Construct a BCD-to-excess-3-code converter with a 4-bit adderfeed BCD code to the 4- bit
adder as the first operand and then feed constant 3 as the second operand. The output is the
corresponding excess-3 code.
To make it work as a excess-3 to BCD converter, we feed excess-3 code as the first
operand and then feed 2's complement of 3 as the second operand. The output is the BCD code.

Truth Table:

37
Analog and Digital Systems Design Laboratory

Pin Diagram:

Logic Diagram:

38
Analog and Digital Systems Design Laboratory

b) To realize EXCESS-3 CODE to BCD conversion

Truth Table:

Logic Diagram:

39
Analog and Digital Systems Design Laboratory

Procedure:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Apply Excess-3-code code as first operand (A) and binary 3 as second operand
(B) and Cin=1 for realizing Excess-3-code to BCD.

Result:

40
Analog and Digital Systems Design Laboratory

EXPERIMENT 7
FLIP-FLOPS
Aim: a)To realize the following Flip-flops using NAND gate: Master slave JK , D and T Flip-
flops.
Components required: IC 7410, IC7400, Patch Cords
Theory:
A flip-flop is a circuit that has two stable states and can be used to store state information. A
flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied
to one or more control inputs and will have one or two outputs. It is the basic storage element
in sequential logic. Flip-flops and latches are a fundamental building block of digital
electronics systems used in computers, communications, and many other types of systems.
A flip–flop is a “bit bucket”; it holds a single binary bit .Flip flops are actually an application
of logic gates. With the help of Boolean logic we can create memory with them. Flip flops
can also be considered as the most basic idea of a Random Access Memory [RAM].
The most commonly used application of flip flops is in the implementation of a feedback
circuit. As a memory relies on the feedback concept, flip flops can be used to design it.
Procedure:

1. Make the connections as shown in the circuit diagrams.

2. Apply inputs as shown in the truth tables,
3. Check the outputs of the circuits; verify that they match with truth table.

41
Analog and Digital Systems Design Laboratory

42
Analog and Digital Systems Design Laboratory

43
Analog and Digital Systems Design Laboratory

SHIFT REGISTERS
Aim: 7.b)Realize the following shift registers using IC7495
(a) SISO (b) SIPO (c)PISO (d) PIPO (e) Ring and (f) Johnson Counter.

Components required: IC 7495, patch cords etc.

Theory:
• A shift register is a group of flip-flops (typically 4 or 8) that are arranged so that the values
stored in the flip-flops are shifted from one flip-flop to the next for every clock.
• Shift registers are used extensively in logic circuits to control digital displays.
• A classic example is numbers being typed into a calculator. As the numbers are entered, the
digits shift to the left one position. This shifting is controlled by a shift register.

(a).SERIAL INPUT SERIAL OUTPUT (SISO):

Procedure:
1. Connections are made as shown in the SISO circuit diagram.
2. Make sure the 7495 is operating in SISO mode by ensuring Pin 6 (Mode) is set to
LOW, and connect clock input to Clk 1(Pin 9).
3. The shift register is loaded with 4 bits of data one by one serially.
4. At the end of the 4thclock pulse, the first data ‘d0’ appears at QD.
5. Apply another clock pulse, to get the second data bit, ‘d1’ at QD. Applying yet
another clock pulse gets the third data bit, ‘d2’ at QD, and so on.

44
Analog and Digital Systems Design Laboratory

(b). SERIAL INPUT PARALLEL OUTPUT (SIPO/Right Shift):

Procedure:
1. Connections are made as shown in the SISO circuit diagram.
2. Make sure the 7495 is operating in SIPO mode by ensuring Pin 6 (Mode) is set to
LOW, and connect clock input to Clk 1(Pin 9).
3. Apply the first data at pin 1 (SD1) and apply one clock pulse. We observe that this
data appears at pin 13 (QA).
4. Now, apply the second data at SD1. Apply a clock pulse. We now observe that the
earlier data is shifted from QA to QB, and the new data appears at QA.
5. Repeat the earlier step to enter data, until all bits are entered one by one.
6. At the end of the 4th clock pulse, we notice that all 4 bits are available at the
parallel output pins QA through QD.

45
Analog and Digital Systems Design Laboratory

© PARALLEL INPUT SERIAL OUTPUT (PISO):

Procedure:
1. Connections are made as shown in the PISO circuit diagram.
2. Now apply the 4-bit data at the parallel I/P pins A, B, C, D (pins 2 through 5).
3. Keeping the mode control M on HIGH, apply one clock pulse. The data applied at
the parallel input pins A, B, C, D will appear at the parallel output pins QA, QB, QC,
QD respectively.
4. Now set the Mode Control M to LOW, and apply clock pulses one by one. Observe
the data coming out in a serial mode at QD.
5. We observe now that the IC operates in PISO mode with parallel inputs being
transferred to the output side serially.

(e). PARALLEL INPUT PARALLEL OUTPUT (PIPO):

Procedure:
1. Connections are made as shown in the PIPO mode circuit diagram.
2. Set Mode Control M to HIGH to enable Parallel transfer.
3. Apply the 4 data bits as input to pins A, B, C, D.
4. Apply one clock pulse at Clk 2 (Pin 8).
5. Note that the 4 bit data at parallel inputs A, B, C, D appears at the
Parallel output pins QA, QB, QC, QD respectively.

46
Analog and Digital Systems Design Laboratory

(e). Ring Counter and (f) Johnson Counter

47
Analog and Digital Systems Design Laboratory

Theory:
A ring counter is a circular shift register which is initiated such that only one of its flip-flops is the
state one while others are in their zero states.
A ring counter is a Shift Register with the output of the last one connected to the input of the first,
that is, in a ring. Typically, a pattern consisting of a single bit is circulated so the state repeats
every n clock cycles if n flip-flops are used. It can be used as a cycle counter of n states.
A Johnson counter (or switch tail ring counter, twisted-ring counter, walking-ring counter, or
Moebius counter) is a modified ring counter, where the output from the last stage is inverted and
fed back as input to the first stage. The register cycles through a sequence of bit-patterns, whose
length is equal to twice the length of the shift register, continuing indefinitely. These counters find
specialist applications, including those similar to the decade counter, digital-to-analog conversion,
etc. They can be implemented easily using D- or JK-type flip-flops.
Procedure:
1. Make the connections as shown in the respective circuit diagram.
2. Initial condition is set by setting up the circuit as shown in the figure.
3. Apply clock and observe the output after each clock pulse, record the observationsand verify
that they match the expected outputs from the truth table.
4. Repeat the same procedure as above for the Johnson Counter circuit and verify itsoperation.

Result:

48
Analog and Digital Systems Design Laboratory

EXPERMENT 8: COUNTERS
Realize
i) Design Mod – N Synchronous Up Counter & Down Counter using 7476 JK Flip-flop
ii) Mod-N Counter using IC7490 / 7476
iii) Synchronous counter using IC74192
Aim: i) Design Mod – N Synchronous Up Counter & Down Counter using 7476 JK Flip-flop

Theory: Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known
counter. Counter is the widest application of flip-flops. It is a group of flip-flops with a clock signal
applied. Counters are of two types.

• Asynchronous or ripple counters.

• Synchronous counters.
Synchronous counters
If the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such a counter
is called as synchronous counter.

Pin Diagram:

49
 Analog and Digital Systems Design Laboratory

Logic Diagram: Binary 4-bit Synchronous Up Counter

Truth Table: Up Counter

50
Analog and Digital Systems Design Laboratory

Logic Diagram: Binary 4-bit Synchronous Down Counter

Truth Table:

CLK QD QC QB QA
0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
5 1 0 1 0
6 1 0 0 1
7 1 0 0 0
8 0 1 1 1
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
15 0 0 0 0

51
Analog and Digital Systems Design Laboratory

ii) Realization of MOD – N Counters Using IC7490

Pin Diagram of IC7490:

Internal Diagram:

Truth Table:

R1 R2 S1 S2 Qd Qc Qb Qa

H H L X L L L L

H H X L L L L L

X L H H 1 0 0 1

L X L X MOD-2 COUNTER

X L X L MOD-5 COUNTER

52
Analog and Digital Systems Design Laboratory

(a) 7490 AS MOD-2 / MOD-5 COUNTER

(b) 7490 AS MOD-10 COUNTER

(c) 7490 AS MOD-8 COUNTER

53
Analog and Digital Systems Design Laboratory

(d) 7490 AS MOD-6 COUNTER

ii) Synchronous counter using IC74192

Procedure:
1) Rig up the circuit as shown in the diagram.
2) Apply the inputs to these counters as per the Truth table and observe the o/pverify with the
truth table.

54
Analog and Digital Systems Design Laboratory

Logic diagram: Count up from 3 to 8

Truthtable

55
Analog and Digital Systems Design Laboratory

Truth Table:

Result: Realized truth table of all Counters.

56
Analog and Digital Systems Design Laboratory

Experiments 9: Design of active second order low pass and high pass filters.
Aim:
a) To design Second order active low pass filter for cut-off frequency of
fc=1KHz & pass band gain of Av=2 and hence plot its frequency Response curve.

b) To design Second order active high pass filter for cut-off frequency of
fc=2KHz & pass band gain of Av=2 and hence plot its frequency Response curve.

Apparatus Required: Bread board, Multi-meter, Signal generator, CRO with probes, Power supply,
Op-Amp µA741, Resistor = 1k Ω, 8.2k Ω, 16k Ω, Capacitor = 0.01μ F, Connecting wires.
Second order Low Pass Filter:
A low-pass filter is a filter that passes low-frequency signals but attenuates (reduces the
amplitude of) signals with frequencies higher than the cutoff frequency. The actual amount of
attenuation for each frequency varies from filter to filter. The Low-pass filter can be made by using
single resistor in series with a non-polarized capacitor connected across a sinusoidal input signal such
filters are called passive filters. The main disadvantage of passive filters is that the amplitude of the
output signal is less than that of the input signal, ie, the gain is never greater than unity and that the load
impedance affects the filters characteristics. With passive filter circuits containing multiple stages, this
loss in signal amplitude called "Attenuation" can become quiet severe, this can be overcome by using
active filters.
Design
Gain of non inverting Amplifier is given by
R
A = 1+ f ,Av=2,
v R
Assume R=1 KΩ, therefore Rf = 1k

Filter Design:
fC = 2kHz
fc=1/2π√(R1R2C1C2)
let R1=R2,C1=C2
fC = 12R C
1 1
Let C1 = 0.01µf
R1 = 7.95k choose R1 = 8.2k

57
Analog and Digital Systems Design Laboratory

Circuit Diagram:

Tabular column:
Input voltage Vi = ...............volts

Frequency(Hz) Vo (v) Gain=Vo/Vi Avdb =20log Vo/Vi

Roll off = −(G1 − G2 ) dB/Decade

Second order High pass Butterworth Filter:
The second order high pass filter is similar to low pass filter, except resistor and capacitor positions are
interchanged.

58
Analog and Digital Systems Design Laboratory

At higher frequencies XC1 and XC2 are much smaller than R1 and R2 consequently; C1, C2,
R1 and R2 have no significant effect on the circuit. The output voltage is then equal to the input, giving
voltage gain of 1.At lower frequencies, the effect of C2 and R2 causes the output to fall off at the rate
of 20 dB per decade as the frequency decreases. A phase lead is produced by C2 and R2 and a phase
lag is generated by R1 combined with C1 and C2.So, feedback via R1 produces a further roll-off of
20dB/decade and the total roll-off rate is 40dB per decade.

Filter design:
Gain of non inverting Amplifier is given by
R
f = 1kHz A = 1+ f ,
C v R
Since Av = 2
fC = 1
2 R1R2C1C2

Assume R = 1k
Rf = 1k
Let R1= R2, C1 = C2

Let C1 = 0.01µf

R1 =15.915k, R1=16k

Circuit Diagram

59
Analog and Digital Systems Design Laboratory

Input voltage Vi = ............... volts

Frequency(Hz) Vo (v) Gain=Vo/Vi Avdb =20log Vo/Vi

Roll off = −(G1 − G2 ) dB/Decade =

Procedure:
Second order LPF:
1. Design circuit as per the specifications given.
2. Apply sine wave input signal of 0.5Vpp.
3. Check the gain of non-inverting amplifier by keeping the frequency of the input signal in the
VOut _ Max
pass band of the filter. Note down the output voltage
4. Varying the input frequency from 0 Hz in steps of 50 Hz un-till output voltage reduces to
VOut _ Max fC
0.707 , the corresponding frequency is cut-off frequency and tabulate the readings in
tabular column.

To find the Roll-off factor:

5. Keeping the input signal amplitude constant, adjust the input frequency at 10 fC Note down the
fC fC
output signal amplitude. The difference in the gain of the filter at and 10 gives the Roll-off
factor.

60
Analog and Digital Systems Design Laboratory

6. Calculate the gain in terms of dB.

7. Plot the graph of gain versus frequency.

1.8 Procedure:
1.8.1 Second order HPF:
1. Design circuit as per the specifications given.
2. Apply sine wave input signal of 0.5Vpp.
3. Check the gain of non-inverting amplifier by keeping the frequency of the input signal in the
VOut _ Max
pass band of the filter. Note down the output voltage
VOut _ Max
4. Reduce the input frequency from 5kHz in steps un-till output voltage reduces to 0.707 ,

the corresponding frequency is cut-off frequency fC and tabulate the readings in tabular column.

1.8.2 To find the Roll-off factor:

5. Keeping the input signal amplitude constant, adjust the input frequency at 0.1 fC Note down the
fC and 0.1 fC gives the Roll-
output signal amplitude. The difference in the gain of the filter at
off factor.
6. Calculate the gain in terms of dB.
7. Plot the graph of gain versus frequency.
Expected graph:
Frequency Response of Low Pass Filter:

Frequncy response of High Pass Filter:

61
Analog and Digital Systems Design Laboratory

Result:
a) The second order low pass filter is designed and frequency response is plotted. Practical cut-off
frequency found to be .
b) The second order high pass filter is designed and frequency response is plotted. Practical cut-off
frequency found to be .

62
Analog and Digital Systems Design Laboratory

Experiments 10:
Monostable Multivibrator
Aim: a) Design and test the Monostable multivibrator for given frequency and duty cycle usingIC
555.
Apparatus Required:
Bread board, Multi-meter, Signal generator, CRO with probes, Power supply, IC 555, Diode0A79,
Op-Amp µA741, Resistor = 10k Ω, 90k Ω, Connecting wires.
Theory:
The Monostable multivibrator has one stable output state. Its output voltage may be highas low
and its stays in the normal state until triggered which triggered the output switches to opposite state for
a time dependent on circuit components. An operational amplifiers as 555 timer monostable
multivibrator circuit can be used to perform the experiment. The circuit acts as a frequency divider. The
circuit acts as driver bydividing the input trigger frequencyto timer.

Circuit Diagrams:

63
Analog and Digital Systems Design Laboratory

Design:
W = 1ms

Input high pass:

W = 1.1RC
Rin Cin<< 1/fin
Let C = 0.47µf
fin= frequency of trigger points
➔ R = 1.9kΩ
1/fin =T
tp < T
C = 0.1µf -> Rin = 470Ω

Procedure:
1. Rig up the circuit as shown in figure.
2. Switch on the DC power supply adjusted at 5Volts.
3. Measure the voltage across the capacitor and trace it using CRO.
4. Measure output voltage at pin 3.
5. Trace the output obtained in CRO.

Expected Graph:

64
Analog and Digital Systems Design Laboratory

Tabular Column:

Theoretical Value Practical Value

Ton 1msec

Toff 1msec

2/3 * Vcc 3.33V

Result:

Monostable Multivibrator is designed and tested for given frequency and waveforms are plotted
in the graph.

65
Analog and Digital Systems Design Laboratory

b) Astable multivibrator
Aim: Design and test the Astable multivibrator for given frequency and duty cycle using IC
555.
Apparatus Required: Bread board, Multi-meter, Signal generator, CRO with probes,
Power supply, IC 555, Diode 0A79, Op-Amp µA741, Resistor = 10k Ω, 90k Ω, Connecting
wires.
Theory:
An Astable multivibrator is a circuit that is continuously switching its output voltage
between high and low levels. It has no stable state when the circuit low levels. It has no stable
state when the circuit output is at positive saturation level. Current flows into the capacitor,
charging it positive at the top, until reaches Vc. The upper trigger point of Schmitt circuit. The
output then rapidly switches to the op-amp negative saturation level. Now current flows from
the capacitors removing its positive charge and recharging with opposite polarity. This continues
until Va arrives at the Schmitt lower trigger point.

CIRCUIT DIAGRAMS:
Astable Multivibrator for Duty Cycle 50% & <50%

66
Analog and Digital Systems Design Laboratory

Design:
Case 1: For Duty Cycle = 50% Case 2: For Duty Cycle < 50%
D = 50 % & T = 1msec D < 50 % (say 25%) & T = 1msec
Ton = 0.5 * T = 0.5 * 1msec = 0.5msec. D = Ton/T, Hence Ton = 0.25msec
Toff = 1 – 0.5msec = 0.5msec. & Toff = 0.75msec
Also Ton =0.693(R1+R2) C Also Ton =0.693(R1+R2) C
For symmetrical waveform R1 = R2 = R For symmetrical waveform
R1=R2=R
Ton = Toff = 0.5ms = 0.693RC R1=Ton/0.693C & R2=Toff/0.693C
Assume C = 0.1µf, Hence R = 3.6kΩ Assume C = 0.1µf,
R1 = R2 = 3.6kΩ R1 = 3.6kΩ & R2 = 10.82kΩ

Case 3: For Duty Cycle > 50%

D > 50 % (say 75%) & T = 1msec
D = Ton/T, Hence Ton = 0.75msec & Toff = 0.25msec
Also Ton =0.693(R1+R2) C & Toff = 0.693 R2 C
Assume C = 0.1µf, Hence R2 = 3.6kΩ & R1 = 7.2kΩ

Astable Multivibrator for Duty Cycle >50%

Procedure:
1 Rig up the circuit as per the circuit diagram.
2 Switch on the DC power supply adjusted at 5Volts.
3 Measure Vc voltage across capacitor at pin 6 and trace it.
4 Measure output voltage at pin 3 and trace it.
5 Repeat step3 and step4 without diode for different duty cycles

67
Analog and Digital Systems Design Laboratory

Tabular Column
Astable
Multivibrator

Duty Cycle Theoretical Value Practical Value

Ton = 0.5msec Ton =
Toff = 0.5msec Toff =
50 %
1/3 * Vcc = 1/3 (5) = 1.66V 1/3 * Vcc =
2/3 * Vcc = 2/3 (5) = 3.33V 2/3 * Vcc =
Ton = 0.5msec Ton =
Toff = 0.5msec Toff =
<50 % (say 25%)
1/3 * Vcc = 1/3 (5) = 1.66V 1/3 * Vcc =
2/3 * Vcc = 2/3 (5) = 3.33V 2/3 * Vcc =
Ton = 0.5msec Ton =
Toff = 0.5msec Toff =
>50 %(say 75%)
1/3 * Vcc = 1/3 (5) = 1.66V 1/3 * Vcc =
2/3 * Vcc = 2/3 (5) = 3.33V 2/3 * Vcc =

Expected Graph:

Conclusion:
Astable Multivibrator is operated for 50% , 25% & 75% duty cycles are theoretical & practicalvoltages
of Vcc/3 and 2Vcc/3 are verified and duty cycle is also verified practically.

68
Analog and Digital Systems Design Laboratory

Experiment No: 11 DESIGN & SIMULATION OF REGULATED POWER SUPPLY

Aim: To design and simulate regulated power supply using PSpice.

APPARATUS REQUIRED: PC loaded with PSpice tool

THEORY:

A regulated DC voltage source is obtained from a AC voltage source is easily by rectification.

AC voltage is of 230V r.m.s. is easily available. This voltage is step downed by a transformer.
Then rectified by diodes. If a center taped transformer is used only two diode is sufficient for full
wave-rectification. If transformer is not a center taped bridge rectifier is used. After rectification
the voltage is DC but contains high ripple. A LC or RC filter is used at the output to filter the
high ripple voltage. Now this voltage can be used for DC supply. But this DC source is not
regulated means if the input AC voltage changes output also changes. To get a regulated output
zener diode regulation and Voltage Regulator may be used
PROCEDURE:
1. Design your circuit in schematics. This can be divided into following substeps. 1). First
insert all the parts without considering their values (for example, place a resistor without
considering the resistance value of it, etc.).
2. Make the necessary rotations for the parts and move the parts to appropriate locations.
3. Make all the necessary wire connections.
4. Mark the nodes you are interested in with labels.
5. Set the values for all the parts, for example, the resistance values of resistors, the width
(W) and length (L) of transistor, etc.
6. Define the SPICE model for NPN and PNP transistors.
7. Setup analysis to tell SPICE what simulation you need (transient analysis, DC sweep,
etc.)
8. Run the simulation. Observe the simulation results (traces of signals) in OrCAD PSpice

69
Analog and Digital Systems Design Laboratory

CIRCUIT DIAGRAM:

SIMULLATION RESULT:

1
Analog and Digital Systems Design Laboratory

Experiment 12: Audio Amplifier with Single Transistor

Aim: To design and test audio amplifier by connecting a microphone input and observe the output
using a loud speaker.
Components list:

Name Value Qty.

Q1: Power Transistor TIP35C, D718, BLD123D, C5200, MJE13007, C2625, etc. 1
LS1: Speaker 5-10W 1

R1: Resistor 1KΩ 1

C1: Non-polar Capacitor 0.1uF 1

C2: Polar Capacitor 47uF 25V 1

C3: Polar Capacitor 4.7uF 50V 1
Stereo 3 Pole Male Jack 3.5mm 1

DC Power Supply 3.7-12V 1

Single transistor Audio amplifier Circuit diagram

The schematic of a simple single transistor audio amplifier circuit shown below.

2
Analog and Digital Systems Design Laboratory

Circuit explanation
The Audio amplifier circuit is constructed using a single Transistor and Resistor, Capacitors. The
Transistor acts as an amplifier by amplifying the audio input signal. This is a Class A power
amplifier.
When a DC bias voltage is applied across the Emitter-Base (VEB) junction of transistor, it remains
in a forward-biased condition that can be maintained irrespective of the low audio signal’s polarity.
So, the transistor always biased in ON state. Thus, during a complete cycle of the audio input signal,
the transistor produces minimum distortion in the maximum amplitude of the audio output signal,
and we hear loud audio/music from the Audio speaker.

Audio Speaker Working Explanation.

The transistor must have a high collector current (IC). I used a TIP3055 N-type transistor for this
amplifier, it is a 70V power transistor along with a 15A of collector current.
You can use any of these: TIP35C, D718, BLD123D, C5200, MJE13007, C2625, etc.
Pin configuration of SOME transistors may be different from TIP3055, check pin configuration
before you use it in the circuit. It is mandatory to connect a large aluminum heatsink with
Transistor to accommodate heat dissipation!!!
The resistor R1 is used as a base resistor which is providing sufficient base current to drive the
transistor in saturation point.
C1 capacitor is used for noise canceling and improving the audio amplifying.
A capacitor C2 is used for isolating the transistor base with the input supply source so that the base
voltage or current could not affect the audio input source. Also, it blocks DC and only passes AC
from the audio input.
C3 capacitor is used to improve the audio Bass and audio quality of the Speaker.
This amplifier can drive a 5W to 10W D loudspeaker (I used a 5W 8Ω
Speaker).
The operating input voltage of this audio amplifier is 3.7V to 12V DC, and a 3.5mm Stereo 3 Pole
Male Jack (Pins connection according to the diagram) used to plug into the female jack of the audio
source device.

Result: