DDHDL

2/13/2015
Digital Design & Hardware

Description Language
(DDHDL)
Department of Electronics & Communication Engineering, MIT, Manipal
Outline
Course Overview
Reference Books
Introduction
Moores law
Technology generation
Why integrated circuits?
Programmable Logic Devices(PLD)
Logic Circuit implementation using PLD
S. K. Tiwari (Asst. Prof.) Department of Electronics & Communication Engineering, MIT, Manipal
Shailendra Kumar Tiwari (Asst. Prof)
2/13/2015
Module01
Digital System implementation using MSI/LSI

PLDs & Combinational and Seq. Circuit implementation using PLDs.
ASICs, FPGA and CPLDs ACTEL, XILINX and ALTERA Logic
modules
Programmable I/O cells, ASIC Design flow & Simulation hierarchy
Module02
Testing Combinational Circuit Fault Table ,Boolean difference method

, Path Sensitization, D-Algorithm, PODEM, Fault-collapsing technique.
Testing sequential circuits
Design-for-test(DFT) and Y-Chart.
Module03
Course Overview
VHDL modeling concepts-syntax, Data types, Delay and delay models

Sequential modeling, Structural modeling & Dataflow modeling
Subprograms, Packages ,Writing test benches
Reference Books
1. M.J.S.Smith (1997),Application Specific Integrated
Circuits, Addison Wesley.
2. Alexander Miczo(1987) , Digital logic testing and
simulation , John Wiley & Sons.
3. Vishwani D. Agrawal (2002) Essentials Of Electronic
Testing For Digital, Memory And Mixed-signal Vlsi
Circuits Kluwer Academic Publishers
4. J.Bhaskar (2002) , VHDL Primer , 3rd edition, Addison
Wesley Longman Singapore Pvt Ltd.
Prerequisite
Prerequisite for this course is DIGITAL LOGIC DESIGN.
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The first electronic Computer
Introduction
Intel 4004 Microprocessor
Intel, 1971.
2,300 transistors (12mm2)
740 KHz operation
(10m PMOS technology)
Intel Core 2 Microprocessor
Intel, 2006.
291,000,000 transistors
(143mm2)
3 GHz operation
(65nm CMOS technology)
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Moores law.
In 1965, Gordon Moore noted that the number of
transistors on a chip doubled every 18 to 24
months.
He made a prediction that semiconductor
technology will double its effectiveness every 18
months
Moores law.
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Technology generation
Generation Level
Small Scale
Integration
Medium Scale
Integration
Large Scale
Integration
Very Large Scale
Integration
Ultra Large Scale
Integration
Super Large Scale
Integration
Year
Number of
Transistors
DRAM
integration
1950s
Less than 102
1960s
102 to 103
1970s
103 to 105
4K, 16 K, 64 K
1980s
105 to 107
256 K, 1M, 4M
1990s
107 to 109
2000s
More than 109
16 M, 64 M,
256M
1 Gb, 4Gb and
above
Why integrated circuits?

Integration of a large function of large no of logic devices
on a single chip provides the following advantage
Less area or increased volume, and therefore
compactness.
Less power consumption.
Less testing requirement at the system level.
Higher reliability mainly due to improved on chip
interconnection.
Higher speed due to significant reduced interconnection
length.
Significant cost saving.
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Definition: A Programmable Logic Device (PLD) is a chip
that is manufactured with a programmable configuration,
enabling it to serve in many arbitrary applications
M N P PLD
Programmable logic arrays (PLAs) implement two-level

combinational logic in sum-of-products (SOP) form. To
implement the sequential logic we need additional memory
element i.e. Flip-Flops.

Types of the ANDOR structured programmable
logic devices are
1. Programmable read-only memory (PROM)
2. Programmable logic array (PLA)
3. Programmable array logic (PAL)
PLD
AND Plane
OR Plane
PROM
Fixed
Programmable
PLA
Programmable
Programmable
PAL
Programmable
Fixed
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PLD Notation
Programmable(Fig. a to f )
Fixed(Fig. g and h)
Slide No 15
Read Only Memory

Types of ROM
1.PROM
2.EPROM
3.EEPROM or E2PROM
4.MASK Programmable ROM
Advantage
1. Ease of Design
2. Design can be changed, modified rapidly
3. Faster than discrete MSI/SSI circuit
Disadvantage
1. Non-utilization of complete hardware
2. Increased power requirement
3. Increased size for large number of input
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Lecture-02
Outline
Review of Lecture 01
PROM
PLA
PAL
Example Problems
Programmable Read Only Memory
Slide-13
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Programmable Logic Array
Programmable Logic Array

Advantage
1. Logic function is implemented with minimum hardware.
2. Comparatively less power dissipation.
Disadvantage
1. We have two degree of freedom i.e. AND plane and OR
plane both are programmable therefore it is difficult to
program.
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Programmable Array Logic

Advantage
1. The OR array is fixed and hence it is
easy to program.
2. Less expensive.
3. Speed is high in PAL than PLA
Disadvantage
1. Common product term can not be used
more than once.
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PAL Outputs
1.
2.
3.
4.
5.
6.
7.
OR gate
NOR gate
EXOR gate
EXNOR gate
Registered output
Registered output with enable
Programmable Input/output

1
CLOCK
VC
C
2
INPU
T
16 R 4
9
10
GN
D
Enabl
e
20
18
19
17
14
13
12
Programmable I/O
Pin
4 Registered Output
Programmable I/O
Pin
11
16 Inputs
R Registered output
4 Outputs
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Lecture-03 & 04
Example Problem
Implement the following functions using PROM, PLA and PAL.
F0= A + BC
F1= AC+AB
F2= BC+AB
F3= BC+AB
Example Problem-1
One input one-output sequence detector that produces an
output value 1 every time the sequence 0101 is detected and
an output value 0 at all other times. For example, if the input
sequence is 010101 then the corresponding output sequence
is 000101.
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Solution-1
Alternate approach
Solution-1
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Example Problem-2
An application of PROM is to realize lookup
table for an arithmetic function. Using PROM
of smallest appropriate size draw the logic
diagram in PLD notation for a PROM
realization
of
the
look-up
table
corresponding to the decimal arithmetic
expression f(x)= 2x+2 for 0x6. where f(x)
and x are expressed in binary.
Solution-2
f(x)= 2x+2
x2
x1
x0
f(x)
y3
y2
y1
y0
10
12
14
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Example Problem-3
A coffee machine operates only after you have inserted Rs 15.

The machine has a single slot that accept only Rs. 5 coins
only one coin at a time. A sensor indicates to control the value of
coin inserted. If the total amount is equal to Rs 15 the machine
dispense a single cup of coffee. The given memory element is
JK flip flop (Use Moor model)
In=0
In=0
In=1
A/0
A= No Coin.
B= Rs 5 Coin
C= Rs 10 coins
D= Rs 15 Coins
B/0
In=1
In=1
D/1
C/0
In=0
Moor Machine output depends only on the current state

Solution-3
J
Q+
Q+
15
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Solution-3
Current I/P Next State O/P
State
Q1 Q0
Q1+
Q0+
J1
K1
J0
K0
J0=C
K0=C+Q1
J1=CQ0
K1=Q0
Z=Q1Q0
Example Problem-4 & Solution
In a car security system, we usually want to connect the siren in such a way that the
siren will activate when it is triggered by one or more sensors. In addition, there will be a
master switch to turn the system on or off. Let us assume that there is a car door switch
D, a vibration detector switch V, and the master switch M. We will use the convention
that when the door is opened D = 1, otherwise, D = 0. Similarly, when the car is being
shaken, V = 1, otherwise, V = 0. Thus, we want the siren S to turn on, that is, set S = 1,
when either D = 1 or V = 1, or when both D = 1and V = 1, but only for when the system
is turned on, that is, when M = 1. However, when we turn off the system, and either enter
or drive the car, we do not want the siren to turn on. Hence, when M = 0, it does not
matter what values D and V have, the siren should remain off.
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Design a code converter that converts BCD messages into Excess3 code. The converter has four input lines carrying signals labeled w, x , y, and
z, and four output lines carrying signals f1, f2, f3, and f4.
Example Problem-6
Let the sine function be sin(x), where 0 x < 1. The angle x will be described by four
binary digits x1, x2, x3, x4, where x1 has weight 1/2 , x2 weight 1/4 , and so on. Thus,
for example, to specify an angle of 45, the input x must equal 1/4 , i.e., x = 0100. To
specify an angle of 30, x must equal 1/6 . However, it is impossible to represent this
value precisely with four bits; the closest possible value is 3 /16 or x = 0011.
Similarly the number z = z1z2z3z4 such that 0 z < 1, z1 has weight , z2 has weight
, and so on. The sine of 30 is equal to 0.5. Hence, the output values in row x = 0011
are specified to be z = 1000. Similarly, the sine of 45 is 0.707. Clearly, the closest output
value would be z = 1011, which is equal to 0.6875. In a similar manner, the entire truth
table is constructed.
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Solution-6
Example Problem-7& Solution

Braille is a system which allows a blind person to read
alphanumeric by feeling a pattern of raised dots () given in
Design a circuit that converts BCD to Braille and implement the
same PLA
A
0
0
0
0
0
0
0
0
1
1
Input
B C
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
D
0
1
0
1
0
1
0
1
0
1
Output
W X Y Z

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Implement the F=acd + bcd+ab+bc using ALTERA MAX structure. Given
programmable switch is EPROM based and PAL contains fixed 3-wide array
OR plane and sharable expander term of 2-wide array AND plane.(2009,2011)
Previous Semester Exam Questions
Implement a sequence detector to detect an overlapping sequence 1010

using PLA and D flip-flop.(2011).
Design a 1011 sequence detector using PROM and D-FF. Overlapping is
allowed (2010)
Design a 0110 sequence detector using PLA and D-FF. Overlapping is
allowed.(2010)
Implement 1010 overlapping sequence detector using D-FF and PLA .
(2009).
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Based on class notes problem,

Implement Example problem 1 to 8 &
Previous Semester Exam Questions
using
PROM
PLA
PAL
Lecture-05
What is an ASIC?
Why ASICs?
Classification of ASIC
Full Custom ASIC
Semi Custom ASIC
Gate array based ASIC
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What is an ASIC?
ASICs are silicon chips that have been designed for
a specific application.
An ASIC is NOT software programmable to
perform different tasks.
ICs that are not ASICs are :
DRAM, SRAM
Silicon Die
ICs which are ASICs:

Baseband processor in
mobile phone
Chipsets in PCs
MPEG encoders/ decoders
Why ASICs?
Design Requirements
Technology-driven:
Greater Complexity
Increased Performance
Higher Density
Lower Power Dissipation
Market-driven:
Shorter Time-to-Market (TTM)
Cheaper with the competition
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ASICs are fabricated on a circular silicon wafer.

The fabrication process remains the same, but
the architecture makes ASICs to be divided into
types.
Classification of ASICs
Full Custom
ASICs
ASIC
Semi Custom
ASICs
Cell Based
(CBIC)
MASK gate
array
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Full Custom ASIC

When engineers have a specific application to be
designed and they are bothered about the performance,
speed, power and cost, they go for designing Full Custom
ASIC.
The circuit is partitioned into a collection of sub-circuits
according to some criteria such as functionality. Which
are laid out specifically for one chip.
Every transistor is designed and drawn by hand.
Typically only way to design analog portions of ASICs.
Usually used for layout of microprocessors.
Full-custom design is very time consuming; thus the
method is inappropriate for very large circuits, unless
performance is of utmost importance
Full Custom ASIC
0.35 is the
channel length
of
smallest
MOS transistor
Actual 0.35 full-custom layout

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Semi Custom ASIC

A semi-custom ASIC, also known as a cell-based ASIC,
uses pre-designed logic cells (AND gates, OR gates,
Multiplexers, Flip-flops etc.) known as standard cells.
Simpler than full-custom design.
Only the placement of the standard cells and the
interconnection is done in a semi-custom ASIC.
However, the standard cells can be placed anywhere on
the silicon die.
Possibly megacells , megafunctions , full-custom blocks ,
system-level macros( SLMs ), fixed blocks , cores , or
Functional Standard Blocks ( FSBs ). Eg. Microprocessor,
multiplier, etc.
Semi Custom ASIC

All mask layers are customized - transistors and
interconnect
Automated buffer sizing, placement and routing
Custom blocks can be embedded
Manufacturing lead time is about eight weeks.
Semicustom ASIC
Layout of the standard Cell
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Semi Custom ASIC
Semi Custom ASIC

Row end cell - The power buses are
connected to additional vertical rails using
row end cell
Feedthrough-It is a piece of metal that is
used to pass a signal through a cell.
Power cells-If the row of standard cells are
long then vertical power rails can also be
run through metal 2 through the cell row
using special power cells
Spacer cells-The width of each standard
cell is adjusted so that they will be aligned
using spacer cells
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Gate-Array Based ASICs

In a gate-array-based ASIC, the transistors are predefined on the
silicon wafer.
The predefined pattern of transistors is called the base array.
The smallest element that is replicated to make the base array is
called the base or primitive cell.
The top level interconnect between the transistors is defined by the
designer in custom masks - Masked Gate Array (MGA)
Design is performed by connecting predesigned and characterized
logic cells from a library (macros).
After validation, automatic placement and routing are typically used
to convert the macro-based design into a layout on the ASIC using
primitive cells.
Types of MGAs:
Channeled Gate Array
Channelless Gate Array
Structured Gate Array

Channeled Gate Array
Only the interconnect is customized.
The interconnect uses predefined
spaces between rows of base cells.
Manufacturing lead time is between
two days and two weeks.
Channel gate-array die
Channelless Gate Array

There are no predefined areas set
aside for routing, routing is over the
top of the gate-array devices.
Achievable logic density is higher
than for channeled gate arrays.
Manufacturing lead time is between
two days and two weeks.
Sea-Of-Gates (SOG) array die
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Structured Gate Array
Only the interconnect is
customized
Custom blocks (the same for each
design) can be embedded
These can be complete blocks
such as a processor or memory
array, or
An array of different base cells
better suited to implementing a
specific function
Manufacturing lead time is
between two days and two weeks.
Gate array die with embedded block
Useful Definition:
1. Standard Parts: Some digital ICs
and its analog
counterparts (analog/digital converters) are standard parts
or ICs. Designers can use it from the data book or buy it
from distributers
and They can use it for different
microelectronics systems.
2. Glue Logic: Function implementation using standard ICs
and then implementation of remaining function with one or
two custom ICs.
3. Application Specific Standard Products (ASSPs): The
IC that might or might not considered as an ASIC are the
controller chip for a PC, it is used for an specific application
but sold to many different vendors
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Example Problem-09
A Cell Based ASIC is using AND gate as standard Cells and
two 2 to 4 decoder as fixed block. Implement a 4 to 16 decoder.

Implement the sum of fulladder using Mask Gate Array ASICs.
Consider the base cell of 2:1 MUX and in one base array only 3
base cells are fabricated. Show the customization steps before
and after defining the Mask. (2010)
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Implement the difference of fullsubtractor using Mask Gate Array
ASICs. Consider the base cell of NAND gate (2-input) and in one
base array only 3 base cells are fabricated. Show the
customization steps before and after defining the Mask.(2009)
ASIC Applications
The application field for ASICs could, in theory, be
considered endless. Here are a few applications :
Aerospace subsystems and sensors

Wireless communication systems
Medical instrumentation
Telecommunications products
Consumer electronics, CDs, digital synthesizers, minidiscs
Computer products, graphics cards, MPEG
technology.
Etc.
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Refer ASIC by M J Smith for Explanation
ASIC Design Flow
End Sem. 2008, 2010

Link for ASIC By M. J. Smith
http://iroi.seu.edu.cn/books/asics/Book2/CH07/C
H07.1.htm#pgfId=1300
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Field Programmable Gate Array(FPGA)

One step above the PLD in complexity. It is usually
large and more complex than PLD.
The word Field in the name refers to the ability of the
gate array to be programmed for a particular function
by the user instead of by the manufacturer of the
device. In other word device can be programmed on
the field or site.
The word Array is used to denote a series of columns
and rows of the gates that can be configured by the
end user.
FPGA Architectures
Symmetrical Array
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
Hierarchical (CPLD)
Sea-of-Gates
PLD
PLD
PLD
PLD
PLD
PLD
PLD
PLD
LB Logic Block also called CLB

(Configurable Logic Block)
Row-based
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Features of commercially available FPGAs

Company
General
Architecture
Logic Block Type
Programmi
ng
Technology
ACTEL
Row based
Mux Based
Anti-fuse
Xilinx
Symmetric
Array
Look-Up Table(LUT)
Static RAM
Altera
Hierarchical
PLD
PLD Block
EPROM
Algorotronix
Sea-of-gates
Mux and basic gates Static RAM
AMD
Hierarchical
PLD
PLD Block
EEPROM
Shannons Expansion Theorem

Using Shannons Expansion Theorem we expand the
Boolean F in terms of Boolean variable A
F=A.F(A=1) + A.F(A=0)
Example
F=AB+ABC+ABC
F=A(BC)+A(B+BC)
OR,
F=B(A+AC)+B(AC)
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Shannons Expansion Theorem
Verify the table all entries are not correct
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ACT 1 Simple Logic Module
ACT 1 Simple Logic Module

Multiplexer-based
logic
module.
Logic
functions
implemented
by
interconnecting
signals
from the routing tracks to
the data inputs and select
lines of the multiplexers.
Inputs can also be tied to a
logical 1 or 0, since these
signals
are
always
available in the routing
channel.
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2 to 1 MUX using ACT 1 Logic Module

8 Input combinational
function
2-to-1 Multiplexer
Y = A S + B S
A
B
S
0
1
3 input AND gate ACT 1 Logic Module

Implementation of a
three-input AND gate
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SR Latch using ACT 1 Logic Module

Implementation of S-R
Latch
Qnext = S + R'Q
=S+RQ(S+S)
=S+RQS+RQS
Qnext = S + R'Q
=S(R+R)+RQ
=SR+SR+RQ
Implement using ACT1 LM

JK Flip Flop
Qnext = K'Q + JQ
T Flip Flop
Qnext = TQ' + T'Q
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Architecture of ACTEL FPGA
The Actel ACT family interconnect scheme shown in

previous slide is similar to a channeled gate array.
The channel routing uses dedicated rectangular areas
of fixed size within the chip called wiring channels (or
just channels ).
The horizontal channels run across the chip in the
horizontal direction. In the vertical direction there are
similar vertical channels that run over the top of the
basic logic cells, the Logic Modules
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Horizontal and Vertical Channel Architecture(ACTEL)
Each track holds one wire. The capacity of a fixed wiring

channel is equal to the number of tracks it contains.
Figure(previous Slide)
shows a detailed view of the
channel and the connections to each Logic Modulethe
input stubs and output stubs
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Poly-Silicon Diffusion Antifuse
An antifuse is the opposite of a regular fuse.

an antifuse is normally an open circuit until you force a
programming current through it (about 5 mA).
In a polydiffusion antifuse the high current density causes a
large power dissipation in a small area, which melts a thin
insulating dielectric between polysilicon and diffusion
electrodes and forms a thin (about 20 nm in diameter),
permanent, and resistive silicon link
Poly-Silicon Diffusion Antifuse

Figure shows a polydiffusion antifuse
with an oxidenitrideoxide ( ONO )
dielectric sandwich of: silicon dioxide
(SiO 2 ) grown over the n -type antifuse
diffusion, a silicon nitride (Si 3 N 4 ) layer,
and another thin SiO 2 layer.
The layered ONO dielectric results in a
tighter spread of blown antifuse
resistance values than using a singleoxide dielectric.
antifuse polysilicon
ONO dielectric
n+ antifuse diffusion
2
The effective electrical thickness is

equivalent to 10nm of SiO 2 (Si 3 N 4
has a higher dielectric constant than
SiO 2 , so the actual thickness is less
than 10 nm)
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Metal-Metal Antifuse
Figure shows a QuickLogic metalmetal antifuse ( ViaLink )

The link is an alloy of tungsten, titanium, and silicon with a bulk
resistance of about 500 cm.
Advantages
Connections to a metalmetal antifuse are direct to
metalthe wiring layers. Connections from a poly
diffusion antifuse to the wiring layers require extra
space and create additional parasitic capacitance.
Direct connection to the low-resistance metal layers
makes it easier to use larger programming currents to
reduce the antifuse resistance
40
http://klabs.org/richcontent/fpga_content/pa
ges/notes/antifuse_notes.htm
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Universal Logic Gate: Multiplexer

4-to-1 Multiplexer
Y = AS0S1 + BS0S1 + CS0S1 + DS0S1
NOT
OR
Correction
required
AND
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ACT 2 and ACT 3 Logic Modules

The C-Module for combinational logic
Actel introduced S-Modules (sequential) which basically
add a flip-flop to the MUX based C-Module
ACT 2 S-Module
ACT 3 S-Module
ACT 2 Logic Module: C-Mod

8-input combinational
function
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ACT 2 Logic Module: C-Mod

Example of a
Logic Function
Implemented with
the Combinatorial
Logic Module
ACT 3 Logic Module: S-Mod

Sequential Logic
Module
Up to 7-input function
plus D-type flip-flop
with clear
The storage element
can be either a
register or a latch.
It can also be
bypassed so the logic
module can be used
as a Combinatorial
Logic Module
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Transparent Latch
Transparent Latch connects the input to the output.
1. If we apply high signal to select line and input is equal to output then
it is transparent high latch.
2. If we apply low signal to select line and input is equal to output then it
is transparent Low latch.
ACT 2 and ACT 3 Logic Modules

The equivalent circuit of the SE
(sequential element)
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Case 1
C2=0, C1=1 and Clr=1
Transparent Low Latch.
Case 2
C2=CLK, C1=0 and Clr=1
Positive edge triggered
Xilinx 3000 series FPGA
Xilinx XC3020
CLB is basic building block
64 Configurable Logic Block.
64 input output interface Block
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Xilinx 3000 series FPGA CLB
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Flip-flops with Clock Enable
Xilinx 3000 series FPGA Mode

1. FG Mode
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2. F Mode
3. FGM Mode
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A Two-Input Lookup Table

LUTs can be implemented using MUXs
We do not normally care about the
implementation, just the functioning
x1
0/1
0/1
0/1
x1 x2
f1
0
0
1
1
1
0
0
1
0
1
0
1
x1
1
0
0/1
1
(b) f 1 = x1 x2 + x1 x2
x2
(a) Circuit for a two-input LUT
f1
x2
(c) Storage cell contents in the LUT
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A Three-Input LUT
A simple
extension of
the two-input
LUT leads to
the figure at
right
Again, at this
point we are
interested in
function and
not form
x1
x2
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
x3
Look-Up Table(LUT)
Input
Output
Address
Decoder
SRAM
Cells
MuxTree
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Inclusion of a Flip-Flop with a LUT

A Flip-Flop can be selected for inclusion or not
Latches the LUT output
Select
In1
In2
In3
In4
Out1
Flip-flop
D Q
LUT
Clock
Select
In1
In2
In3
In4
Flip-flop
D Q
LUT
Clock
can
program to
bypass the
FF
Out2
can
program to
bypass the
FF
Implement the following function with Xilinx CLB

1. F= xy+z;
2. Y= ab+c
3. Z=abc;
4. G=F+YZ
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In Fig Q1A implement the following function using respective blocks F1=
(ABCDE) F2= (ACD+BCD+AB+BC) F3= F1.F2
i. Find the no. of CLBs and LUTs required to implement F3
ii. Show the SRAM contents of Xilinx XC 3000.
iii. Draw the entire layout for ACT-2, PAL(three wide OR gate) and
Xilinx- XC3000 with proper routing between different blocks.
Programmable Interconnect
General-purpose Interconnects
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Direct Interconnects Between Adjacent CLBs
Vertical and Horizontal Long Lines
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Uses of Tristate Buffers
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Configuration Memory Cell(SRAM)
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Altera Complex Programmable Logic Device
58
2/13/2015

Macrocell for EMP7032, 7064, and 7096 Devices
59
2/13/2015

Sharable Expanders
60
2/13/2015

Parallel Expanders
61
2/13/2015
EPROM
62
2/13/2015
Programmable I/O cells
63
2/13/2015
DC Output
DC Output
64
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DC Output
DC Output
65
2/13/2015
AC Output
DC Input
66
2/13/2015
DC Input
DC Input
Noise Margin
67
2/13/2015
DC Input
Noise Margin
AC Input
Metastability
68

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2/13/2015

Digital Design & Hardware

Department of Electronics & Communication Engineering, MIT, Manipal

Shailendra Kumar Tiwari (Asst. Prof)

Digital System implementation using MSI/LSI

Testing Combinational Circuit Fault Table ,Boolean difference method

VHDL modeling concepts-syntax, Data types, Delay and delay models

Shailendra Kumar Tiwari (Asst. Prof)

The first electronic Computer

Intel 4004 Microprocessor

Intel Core 2 Microprocessor

Shailendra Kumar Tiwari (Asst. Prof)

Shailendra Kumar Tiwari (Asst. Prof)

Less than 102

More than 109

Why integrated circuits?

Shailendra Kumar Tiwari (Asst. Prof)

Programmable Logic Devices(PLD)

Programmable logic arrays (PLAs) implement two-level

Programmable Logic Devices(PLD)

Shailendra Kumar Tiwari (Asst. Prof)

Read Only Memory

Shailendra Kumar Tiwari (Asst. Prof)

Programmable Read Only Memory

Shailendra Kumar Tiwari (Asst. Prof)

Programmable Logic Array

Programmable Logic Array

Shailendra Kumar Tiwari (Asst. Prof)

Programmable Array Logic

Programmable Array Logic

Shailendra Kumar Tiwari (Asst. Prof)

Programmable Array Logic

Shailendra Kumar Tiwari (Asst. Prof)

Shailendra Kumar Tiwari (Asst. Prof)

Shailendra Kumar Tiwari (Asst. Prof)

Shailendra Kumar Tiwari (Asst. Prof)

A coffee machine operates only after you have inserted Rs 15.

Moor Machine output depends only on the current state

Shailendra Kumar Tiwari (Asst. Prof)

Example Problem-4 & Solution

Shailendra Kumar Tiwari (Asst. Prof)

Example Problem-5 & Solution

Shailendra Kumar Tiwari (Asst. Prof)

Example Problem-7& Solution

Shailendra Kumar Tiwari (Asst. Prof)

Example Problem-8 & Solution

Previous Semester Exam Questions

Implement a sequence detector to detect an overlapping sequence 1010

Shailendra Kumar Tiwari (Asst. Prof)

Based on class notes problem,

Shailendra Kumar Tiwari (Asst. Prof)

ICs which are ASICs:

Shailendra Kumar Tiwari (Asst. Prof)

ASICs are fabricated on a circular silicon wafer.

Shailendra Kumar Tiwari (Asst. Prof)

Full Custom ASIC

Full Custom ASIC

Actual 0.35 full-custom layout