FDMF6823C — Extra-Small, High-Performance, High-Frequency DrMOS Module

April 2012

FDMF6823C — Extra-Small, High-Performance,

High-Frequency DrMOS Module
Benefits Description
 Ultra-Compact 6x6mm PQFN, 72% Space-Saving The XS™ DrMOS family is Fairchild’s next-generation,
Compared to Conventional Discrete Solutions fully optimized, ultra-compact, integrated MOSFET plus
driver power stage solution for high-current, high-
 Fully Optimized System Efficiency
frequency, synchronous buck DC-DC applications. The
 Clean Switching Waveforms with Minimal Ringing FDMF6823C integrates a driver IC, two power
MOSFETs, and a bootstrap Schottky diode into a
 High-Current Handling
thermally enhanced, ultra-compact 6x6mm package.
Features With an integrated approach, the complete switching
power stage is optimized with regard to driver and
 Over 93% Peak-Efficiency MOSFET dynamic performance, system inductance,
 High-Current Handling: 50A and power MOSFET RDS(ON). XS™ DrMOS uses
®
Fairchild's high-performance PowerTrench MOSFET
 High-Performance PQFN Copper-Clip Package technology, which dramatically reduces switch ringing,
 3-State 5V PWM Input Driver eliminating the need for snubber circuit in most buck
converter applications.
 Skip-Mode SMOD# (Low-Side Gate Turn Off) Input
A driver IC with reduced dead times and propagation
 Thermal Warning Flag for Over-Temperature delays further enhances the performance. A thermal
Condition warning function warns of a potential over-temperature
 Driver Output Disable Function (DISB# Pin) situation. The FDMF6823C also incorporates a Skip
Mode (SMOD#) for improved light-load efficiency. The
 Internal Pull-Up and Pull-Down for SMOD# and FDMF6823C also provides a 3-state 5V PWM input for
DISB# Inputs, Respectively compatibility with a wide range of PWM controllers.
 Fairchild PowerTrench® Technology MOSFETs for
Clean Voltage Waveforms and Reduced Ringing Applications
 Fairchild SyncFET™ (Integrated Schottky Diode)  High-Performance Gaming Motherboards
Technology in Low-Side MOSFET
 Compact Blade Servers, V-Core and Non-V-Core
 Integrated Bootstrap Schottky Diode DC-DC Converters
 Adaptive Gate Drive Timing for Shoot-Through  Desktop Computers, V-Core and Non-V-Core
Protection DC-DC Converters
 Under-Voltage Lockout (UVLO)  Workstations
 Optimized for Switching Frequencies up to 1MHz  High-Current DC-DC Point-of-Load Converters
 Low-Profile SMD Package  Networking and Telecom Microprocessor Voltage
Regulators
 Fairchild Green Packaging and RoHS Compliance
 Based on the Intel® 4.0 DrMOS Standard
 Small Form-Factor Voltage Regulator Modules

Ordering Information

Part Number Current Rating Package Top Mark

FDMF6823C 50A 40-Lead, Clipbond PQFN DrMOS, 6.0mm x 6.0mm Package FDMF6823C

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FDMF6823C • Rev. 1.0.2
 FDMF6823C — Extra-Small, High-Performance, High-Frequency DrMOS Module
Typical Application Circuit

V5V VIN
3V ~ 16V
CVDRV CVIN

VDRV VCIN VIN

DISB# DISB# RBOOT

BOOT

PWM
CBOOT
FDMF6823C PHASE
OFF
SMOD#
ON
VSWH VOUT
LOUT
Open-Drain THWN#
Output
COUT
CGND PGND

Figure 1. Typical Application Circuit

DrMOS Block Diagram

VDRV BOOT VIN

VCIN UVLO Q1
HS Power
DBoot MOSFET

DISB#
GH Level-Shift GH
Logic
10µA
30kΩ

VCIN PHASE

RUP_PWM Dead-Time
Input Control VSWH
PWM 3-State
Logic
RDN_PWM VDRV

GL
GL
Logic
THWN# VCIN 30kΩ
Q2
Temp. LS Power
MOSFET
Sense

10µA

CGND SMOD# PGND

Figure 2. DrMOS Block Diagram

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FDMF6823C • Rev. 1.0.2
 FDMF6823C — Extra-Small, High-Performance, High-Frequency DrMOS Module
Pin Configuration

Figure 3. Bottom View Figure 4. Top View

Pin Definitions
Pin # Name Description
When SMOD#=HIGH, the low-side driver is the inverse of the PWM input. When
1 SMOD# SMOD#=LOW, the low-side driver is disabled. This pin has a 10µA internal pull-up current
source. Do not add a noise filter capacitor.
2 VCIN IC bias supply. Minimum 1µF ceramic capacitor is recommended from this pin to CGND.
Power for the gate driver. Minimum 1µF ceramic capacitor is recommended to be connected as
3 VDRV
close as possible from this pin to CGND.
Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a
4 BOOT
bootstrap capacitor from this pin to PHASE.
5, 37, 41 CGND IC ground. Ground return for driver IC.
6 GH For manufacturing test only. This pin must float; it must not be connected to any pin.
7 PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin.
No connect. The pin is not electrically connected internally, but can be connected to VIN for
8 NC
convenience.
9 - 14, 42 VIN Power input. Output stage supply voltage.
15, 29 - Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point
VSWH
35, 43 for the adaptive shoot-through protection.
16 – 28 PGND Power ground. Output stage ground. Source pin of the low-side MOSFET.
36 GL For manufacturing test only. This pin must float; it must not be connected to any pin.
Thermal warning flag, open collector output. When temperature exceeds the trip limit, the
38 THWN#
output is pulled LOW. THWN# does not disable the module.
Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are
39 DISB# held LOW). This pin has a 10µA internal pull-down current source. Do not add a noise filter
capacitor.
40 PWM PWM signal input. This pin accepts a three-state 5V PWM signal from the controller.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FDMF6823C • Rev. 1.0.2
 FDMF6823C — Extra-Small, High-Performance, High-Frequency DrMOS Module
Absolute Maximum Ratings
Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VCIN Supply Voltage Referenced to CGND -0.3 6.0 V
VDRV Drive Voltage Referenced to CGND -0.3 6.0 V
VDISB# Output Disable Referenced to CGND -0.3 6.0 V
VPWM PWM Signal Input Referenced to CGND -0.3 6.0 V
VSMOD# Skip Mode Input Referenced to CGND -0.3 6.0 V
VGL Low Gate Manufacturing Test Pin Referenced to CGND -0.3 6.0 V
VTHWN# Thermal Warning Flag Referenced to CGND -0.3 6.0 V
VIN Power Input Referenced to PGND, CGND -0.3 25.0 V
Referenced to VSWH, PHASE -0.3 6.0 V
VBOOT Bootstrap Supply
Referenced to CGND -0.3 25.0 V
Referenced to VSWH, PHASE -0.3 6.0 V
VGH High Gate Manufacturing Test Pin
Referenced to CGND -0.3 25.0 V
VPHS PHASE Referenced to CGND -0.3 25.0 V
Referenced to PGND, CGND (DC Only) -0.3 25.0 V
VSWH Switch Node Input
Referenced to PGND, <20ns -8.0 28.0 V
Referenced to VDRV 22.0 V
VBOOT Bootstrap Supply
Referenced to VDRV, <20ns 25.0 V
ITHWN# THWN# Sink Current -0.1 7.0 mA
fSW=300kHz, VIN=12V, VO=1.0V 50
IO(AV) Output Current(1) A
fSW=1MHz, VIN=12V, VO=1.0V 45
θJPCB Junction-to-PCB Thermal Resistance 2.7 °C/W
TA Ambient Temperature Range -40 +125 °C
TJ Maximum Junction Temperature +150 °C
TSTG Storage Temperature Range -55 +150 °C
Human Body Model, JESD22-A114 2000
ESD Electrostatic Discharge Protection V
Charged Device Model, JESD22-C101 2500
Note:
1. IO(AV) is rated using Fairchild’s DrMOS evaluation board, at TA = 25°C, with natural convection cooling. This rating
is limited by the peak DrMOS temperature, TJ = 150°C, and varies depending on operating conditions and PCB
layout. This rating can be changed with different application settings.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Typ. Max. Unit

VCIN Control Circuit Supply Voltage 4.5 5.0 5.5 V
VDRV Gate Drive Circuit Supply Voltage 4.5 5.0 5.5 V
(2)
VIN Output Stage Supply Voltage 3.0 12.0 16.0 V
Note:
2. Operating at high VIN can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes
during MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must
remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the “Application
Information” and “PCB Layout Guidelines” sections of this datasheet for additional information.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FDMF6823C • Rev. 1.0.2
 Electrical Characteristics

FDMF6823C — Extra-Small, High-Performance, High-Frequency DrMOS Module

Typical values are VIN = 12V, VCIN = 5V, VDRV = 5V, and TA = TJ = +25°C unless otherwise noted.
Symbol Parameter Condition Min. Typ. Max. Unit
Basic Operation
IQ Quiescent Current IQ=IVCIN+IVDRV, PWM=LOW or HIGH or Float 2 mA
VUVLO UVLO Threshold VCIN Rising 2.9 3.1 3.3 V
VUVLO_Hys UVLO Hysteresis 0.4 V
PWM Input (VCIN = VDRV = 5V ±10%)
RUP_PWM Pull-Up Impedance VPWM=5V 10 kΩ
RDN_PWM Pull-Down Impedance VPWM=0V 10 kΩ
VIH_PWM PWM High Level Voltage 3.04 3.55 4.05 V
VTRI_HI 3-State Upper Threshold 2.95 3.45 3.94 V
VTRI_LO 3-State Lower Threshold 0.98 1.25 1.52 V
VIL_PWM PWM Low Level Voltage 0.84 1.15 1.42 V
tD_HOLD-OFF 3-State Shut-Off Time 160 200 ns
VHiZ_PWM 3-State Open Voltage 2.20 2.50 2.80 V
tPWM-OFF_MIN PWM Minimum Off Time 120 ns
PWM Input (VCIN = VDRV = 5V ±5%)
RUP_PWM Pull-Up Impedance VPWM=5V 10 kΩ
RDN_PWM Pull-Down Impedance VPWM=0V 10 kΩ
VIH_PWM PWM High Level Voltage 3.22 3.55 3.87 V
VTRI_HI 3-State Upper Threshold 3.13 3.45 3.77 V
VTRI_LO 3-State Lower Threshold 1.04 1.25 1.46 V
VIL_PWM PWM Low Level Voltage 0.90 1.15 1.36 V
tD_HOLD-OFF 3-State Shut-Off Time 160 200 ns
VHiZ_PWM 3-State Open Voltage 2.30 2.50 2.70 V
tPWM-OFF_MIN PWM Minimum Off Time 120 ns
DISB# Input
VIH_DISB High-Level Input Voltage 2 V
VIL_DISB Low-Level Input Voltage 0.8 V
IPLD Pull-Down Current 10 µA
PWM=GND, Delay Between DISB# from
tPD_DISBL Propagation Delay 25 ns
HIGH to LOW to GL from HIGH to LOW
PWM=GND, Delay Between DISB# from
tPD_DISBH Propagation Delay 25 ns
LOW to HIGH to GL from LOW to HIGH
SMOD# Input
VIH_SMOD High-Level Input Voltage 2 V
VIL_SMOD Low-Level Input Voltage 0.8 V
IPLU Pull-Up Current 10 µA
PWM=GND, Delay Between SMOD# from
tPD_SLGLL Propagation Delay 10 ns
HIGH to LOW to GL from HIGH to LOW
PWM=GND, Delay Between SMOD# from
tPD_SHGLH Propagation Delay 10 ns
LOW to HIGH to GL from LOW to HIGH

Continued on the following page…

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FDMF6823C • Rev. 1.0.2
 Electrical Characteristics

FDMF6823C — Extra-Small, High-Performance, High-Frequency DrMOS Module

Typical values are VIN = 12V, VCIN = 5V, VDRV = 5V, and TA = TJ = +25°C unless otherwise noted.
Symbol Parameter Condition Min. Typ. Max. Unit
Thermal Warning Flag
TACT Activation Temperature 150 °C
TRST Reset Temperature 135 °C
RTHWN Pull-Down Resistance IPLD=5mA 30 Ω
250ns Timeout Circuit
SW=0V, Delay Between GH from HIGH to
tD_TIMEOUT Timeout Delay 250 ns
LOW and GL from LOW to HIGH

High-Side Driver (fSW = 1000kHz, IOUT = 30A, TA = +25°C)

RSOURCE_GH Output Impedance, Sourcing Source Current=100mA 1 Ω
RSINK_GH Output Impedance, Sinking Sink Current=100mA 0.8 Ω
tR_GH Rise Time GH=10% to 90% 10 ns
tF_GH Fall Time GH=90% to 10% 10 ns
GL Going LOW to GH Going HIGH,
tD_DEADON LS to HS Deadband Time 15 ns
1.0V GL to 10% GH
PWM LOW Propagation PWM Going LOW to GH Going LOW,
tPD_PLGHL 20 30 ns
Delay VIL_PWM to 90% GH
PWM HIGH Propagation PWM Going HIGH to GH Going HIGH,
tPD_PHGHH 30 ns
Delay (SMOD# =0) VIH_PWM to 10% GH (SMOD# =0, ID_LS>0)
Exiting 3-State Propagation PWM (From 3-State) Going HIGH to GH
tPD_TSGHH 30 ns
Delay Going HIGH, VIH_PWM to 10% GH

Low-Side Driver (fSW = 1000kHz, IOUT = 30A, TA = +25°C)

RSOURCE_GL Output Impedance, Sourcing Source Current=100mA 1 Ω
RSINK_GL Output Impedance, Sinking Sink Current=100mA 0.5 Ω
tR_GL Rise Time GL=10% to 90% 20 ns
tF_GL Fall Time GL=90% to 10% 10 ns
SW Going LOW to GL Going HIGH,
tD_DEADOFF HS to LS Deadband Time 15 ns
2.2V SW to 10% GL
PWM-HIGH Propagation PWM Going HIGH to GL Going LOW,
tPD_PHGLL 10 25 ns
Delay VIH_PWM to 90% GL
Exiting 3-State Propagation PWM (From 3-State) Going LOW to GL
tPD_TSGLH 20 ns
Delay Going HIGH, VIL_PWM to 10% GL
Boot Diode
VF Forward-Voltage Drop IF=20mA 0.3 V
VR Breakdown Voltage IR=1mA 22 V

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FDMF6823C • Rev. 1.0.2
 FDMF6823C — Extra-Small, High-Performance, High-Frequency DrMOS Module
V IH_PWM

V IL_PWM
PWM

GL 90%

1.0V
10%

90%
GH
to
VSWH 10% 1.2V
t D_TIMEOUT
(250ns Timeout)

VSWH 2.2V

t PD PHGLL
t PD_PLGHL

t D_DEADON t D_DEADOFF

Figure 5. PWM Timing Diagram

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FDMF6823C • Rev. 1.0.2
 FDMF6823C — Extra-Small, High-Performance, High-Frequency DrMOS Module
Typical Performance Characteristics
Test Conditions: VIN=12V, VOUT=1V, VCIN=5V, VDRV=5V, LOUT=250nH, TA=25°C, and natural convection cooling,
unless otherwise specified.
50 11
300kHz VIN = 12V, VDRV & VCIN = 5V, VOUT = 1V
45 10
500kHz
40 9 800kHz
Module Output Current, IOUT (A)

Module Power Loss, PLMOD (W)

FSW = 300kHz 8 1000kHz
35
7
30
6
25
FSW = 1000kHz 5
20
4
15 3
10 2

5 VIN = 12V, VDRV & VCIN = 5V, VOUT = 1V 1

0 0
0 25 50 75 100 125 150 0 5 10 15 20 25 30 35 40 45
PCB Temperature, T PCB (°C) Module Output Current, IOUT (A)

Figure 6. Safe Operating Area Figure 7. Power Loss vs. Output Current
1.5 1.08
VIN = 12V, VDRV & VCIN = 5V, VOUT = 1V, IOUT = 30A VDRV & VCIN = 5V, VOUT = 1V, FSW = 300kHz, IOUT = 30A

1.4
1.06
Normalized Module Power Loss

Normalized Module Power Loss

1.3
1.04

1.2

1.02
1.1

1.00
1.0

0.9 0.98
100 200 300 400 500 600 700 800 900 1000 1100 4 6 8 10 12 14 16 18
Module Switching Frequency, FSW (kHz) Module Input Voltage, VIN (V)

Figure 8. Power Loss vs. Switching Frequency Figure 9. Power Loss vs. Input Voltage
1.15 1.8
VIN = 12V, VOUT = 1V, FSW = 300kHz, IOUT = 30A
1.7
1.10
1.6
Normalized Module Power Loss
Normalized Module Power Loss

1.5
1.05
1.4

1.3
1.00
1.2

0.95 1.1

1.0
VIN = 12V, VDRV & VCIN = 5V, FSW = 300kHz, IOUT = 30A
0.90 0.9
4.0 4.5 5.0 5.5 6.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Driver Supply Voltage, VDRV & VCIN (V) Module Output Voltage, VOUT (V)

Figure 10. Power Loss vs. Driver Supply Voltage Figure 11. Power Loss vs. Output Voltage

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FDMF6823C • Rev. 1.0.2
 FDMF6823C — Extra-Small, High-Performance, High-Frequency DrMOS Module
Typical Performance Characteristics
Test Conditions: VIN=12V, VOUT=1V, VCIN=5V, VDRV=5V, LOUT=250nH, TA=25°C, and natural convection cooling,
unless otherwise specified.
1.01 45
VIN = 12V, VDRV & VCIN = 5V, FSW = 300kHz, VOUT = 1V, IOUT = 30A VIN = 12V, VDRV & VCIN = 5V, VOUT = 1V, IOUT = 0A
40

Driver Supply Current, IDRV & ICIN (mA)

1.00
Normalized Module Power Loss

35

30
0.99

25

0.98
20

15
0.97
10

0.96 5
200 250 300 350 400 450 500 100 200 300 400 500 600 700 800 900 1000 1100
Output Inductor, LOUT (nH) Module Switching Frequency, FSW (kHz)

Figure 12. Power Loss vs. Output Inductor Figure 13. Driver Supply Current vs. Switching
Frequency
17 1.04
VIN = 12V, VOUT = 1V, FSW = 300kHz, IOUT = 0A VIN = 12V, VDRV & VCIN = 5V, VOUT = 1V
16
1.03
Driver Supply Current, IDRV & ICIN (mA)

Normalized Driver Supply Current

15
1.02
FSW = 300kHz
14
1.01
13

1.00
12
FSW = 1000kHz
0.99
11

10 0.98
4.0 4.5 5.0 5.5 6.0 0 5 10 15 20 25 30 35 40 45
Driver Supply Voltage, VDRV & VCIN (V) Module Output Current, IOUT (A)

Figure 14. Driver Supply Current vs. Driver Supply Figure 15. Driver Supply Current vs. Output Current
Voltage
3.2 4.5
TA = 25°C
UVLOUP VIH_PWM
4.0
3.1
PWM Threshold Voltage, VPWM (V)
Driver IC Supply Voltage, VCIN (V)

3.5
VTRI_HI
3.0
3.0 VHIZ_PWM

2.9 2.5

2.0
2.8
VTRI_LO
1.5
2.7
1.0 VIL_PWM
UVLODN
2.6 0.5
-55 0 25 55 100 125 150 4.50 4.75 5.00 5.25 5.50
Driver IC Junction Temperature, T J (oC) Driver IC Supply Voltage, VCIN (V)

Figure 16. UVLO Threshold vs. Temperature Figure 17. PWM Threshold vs. Driver Supply Voltage

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FDMF6823C • Rev. 1.0.2
 FDMF6823C — Extra-Small, High-Performance, High-Frequency DrMOS Module
Typical Performance Characteristics
Test Conditions: VCIN=5V, VDRV=5V, TA=25°C, and natural convection cooling, unless otherwise specified.
4.5 2.2
VCIN = 5V TA = 25°C
4.0

SMOD# Threshold Voltage, VSMOD (V)

VIH_PWM VIH_SMOD#
2.0
PWM Threshold Voltage, VPWM (V)

3.5
VTRI_HI
3.0
1.8
VHIZ_PWM
2.5

2.0 1.6
VIL_SMOD#
1.5 VTRI_LO
1.4
1.0 VIL_PWM

0.5 1.2
-55 0 25 55 100 125 150 4.50 4.75 5.00 5.25 5.50
Driver IC Junction Temperature, T J (oC) Driver IC Supply Voltage, VCIN (V)

Figure 18. PWM Threshold vs. Temperature Figure 19. SMOD# Threshold vs. Driver Supply
Voltage
2.2 -9.0
VCIN = 5V VCIN = 5V
SMOD# Threshold Voltage, VSMOD (V)

-9.5
SMOD# Pull-Up Current, IPLU (uA)

2
VIH_SMOD#
-10.0
1.8

-10.5

1.6
-11.0

1.4 VIL_SMOD#
-11.5

1.2 -12.0
-55 0 25 55 100 125 150 -55 0 25 55 100 125 150
Driver IC Junction Temperature, T J (oC) Driver IC Junction Temperature, T J (oC)

Figure 20. SMOD# Threshold vs. Temperature Figure 21. SMOD# Pull-Up Current vs. Temperature
2.2 2.2
TA = 25°C VCIN = 5V
VIH_DISB#
DISB# Threshold Voltage, VDISB (V)

DISB# Threshold Voltage, VDISB (V)

2.0 2.0
VIH_DISB#

1.8 1.8

1.6 1.6
VIL_DISB#

VIL_DISB#
1.4 1.4

1.2 1.2
4.50 4.75 5.00 5.25 5.50 -55 0 25 55 100 125 150
Driver IC Supply Voltage, VCIN (V) Driver IC Junction Temperature, T J (oC)

Figure 22. DISB# Threshold vs. Driver Supply Figure 23. DISB# Threshold vs. Temperature
Voltage

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FDMF6823C • Rev. 1.0.2
 FDMF6823C — Extra-Small, High-Performance, High-Frequency DrMOS Module
Typical Performance Characteristics
Test Conditions: VCIN=5V, VDRV=5V, TA=25°C, and natural convection cooling, unless otherwise specified.

12.0 500
VCIN = 5V IF = 20mA
450
11.5
DISB# Pull-Down Current, IPLD (uA)

Boot Diode Forward Voltage, VF (mV)

400
11.0
350

10.5 300

250
10.0
200

9.5
150

9.0 100
-55 0 25 55 100 125 150 -55 0 25 55 100 125 150
Driver IC Junction Temperature, T J (oC) Driver IC Junction Temperature, T J (oC)

Figure 24. DISB# Pull-Down Current vs. Figure 25. Boot Diode Forward Voltage vs.
Temperature Temperature

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FDMF6823C • Rev. 1.0.2
 Functional Description

FDMF6823C — Extra-Small, High-Performance, High-Frequency DrMOS Module

The FDMF6823C is a driver-plus-FET module optimized Three-State PWM Input
for the synchronous buck converter topology. A single
The FDMF6823C incorporates a three-state 5V PWM
PWM input signal is all that is required to properly drive
input gate drive design. The three-state gate drive has
the high-side and the low-side MOSFETs. Each part is
both logic HIGH level and LOW level, along with a
capable of driving speeds up to 1MHz.
three-state shutdown window. When the PWM input
VCIN and Disable (DISB#) signal enters and remains within the three-state window
for a defined hold-off time (tD_HOLD-OFF), both GL and GH
The VCIN pin is monitored by an Under-Voltage Lockout are pulled LOW. This enables the gate drive to shut
(UVLO) circuit. When VCIN rises above ~3.1V, the driver down both high-side and low-side MOSFETs to support
is enabled. When VCIN falls below ~2.7V, the driver is features such as phase shedding, which is common on
disabled (GH, GL=0). The driver can also be disabled by multi-phase voltage regulators.
pulling the DISB# pin LOW (DISB# < VIL_DISB), which
holds both GL and GH LOW regardless of the PWM Exiting Three-State Condition
input state. The driver can be enabled by raising the
When exiting a valid three-state condition, the
DISB# pin voltage HIGH (DISB# > VIH_DISB).
FDMF6823C follows the PWM input command. If the
Table 1. UVLO and Disable Logic PWM input goes from three-state to LOW, the low-side
MOSFET is turned on. If the PWM input goes from
UVLO DISB# Driver State three-state to HIGH, the high-side MOSFET is turned
0 X Disabled (GH, GL=0) on. This is illustrated in Figure 27. The FDMF6823C
design allows for short propagation delays when exiting
1 0 Disabled (GH, GL=0) the three-state window (see Electrical Characteristics).
1 1 Enabled (see Table 2)
Low-Side Driver
1 Open Disabled (GH, GL=0)
The low-side driver (GL) is designed to drive a ground-
Note: referenced, low-RDS(ON), N-channel MOSFET. The bias
3. DISB# internal pull-down current source is 10µA. for GL is internally connected between the VDRV and
CGND pins. When the driver is enabled, the driver's
output is 180° out of phase with the PWM input. When
Thermal Warning Flag (THWN#)
the driver is disabled (DISB#=0V), GL is held LOW.
The FDMF6823C provides a thermal warning flag
(THWN#) to warn of over-temperature conditions. The High-Side Driver
thermal warning flag uses an open-drain output that The high-side driver (GH) is designed to drive a floating
pulls to CGND when the activation temperature (150°C) N-channel MOSFET. The bias voltage for the high-side
is reached. The THWN# output returns to a high- driver is developed by a bootstrap supply circuit
impedance state once the temperature falls to the reset consisting of the internal Schottky diode and external
temperature (135°C). For use, the THWN# output bootstrap capacitor (CBOOT). During startup, VSWH is held
requires a pull-up resistor, which can be connected to at PGND, allowing CBOOT to charge to VDRV through the
VCIN. THWN# does NOT disable the DrMOS module. internal diode. When the PWM input goes HIGH, GH
begins to charge the gate of the high-side MOSFET (Q1).
During this transition, the charge is removed from CBOOT
135°C Reset 150°C and delivered to the gate of Q1. As Q1 turns on, VSWH
Temperature Activation rises to VIN, forcing the BOOT pin to VIN + VBOOT, which
HIGH Temperature
provides sufficient VGS enhancement for Q1. To complete
THWN# the switching cycle, Q1 is turned off by pulling GH to
Logic Normal Thermal VSWH. CBOOT is then recharged to VDRV when VSWH falls to
State Operation Warning PGND. GH output is in-phase with the PWM input. The
high-side gate is held LOW when the driver is disabled or
LOW the PWM signal is held within the three-state window for
longer than the three-state hold-off time, tD_HOLD-OFF.
TJ_driver IC

Figure 26. THWN Operation

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FDMF6823C • Rev. 1.0.2
 HIGH, Q2 begins to turn off after a propagation delay

FDMF6823C — Extra-Small, High-Performance, High-Frequency DrMOS Module

Adaptive Gate Drive Circuit (tPD_PHGLL). Once the GL pin is discharged below 1.0V,
The driver IC advanced design ensures minimum Q1 begins to turn on after adaptive delay tD_DEADON.
MOSFET dead-time, while eliminating potential shoot- To preclude overlap during the HIGH-to-LOW transition
through (cross-conduction) currents. It senses the state (Q1 off to Q2 on), the adaptive circuitry monitors the
of the MOSFETs and adjusts the gate drive adaptively voltage at the GH-to-PHASE pin pair. When the PWM
to ensure they do not conduct simultaneously. Figure 27 signal goes LOW, Q1 begins to turn off after a
provides the relevant timing waveforms. To prevent propagation delay (tPD_PLGHL). Once the voltage across
overlap during the LOW-to-HIGH switching transition GH-to-PHASE falls below 2.2V, Q2 begins to turn on
(Q2 off to Q1 on), the adaptive circuitry monitors the after adaptive delay tD_DEADOFF.
voltage at the GL pin. When the PWM signal goes

V IH_PWM V IH_PWM V IH_PWM

V TRI_HI V IH_PWM
tD_HOLD-OFF V TRI_HI

V IL_PWM V TRI_LO
V IL_PWM
tR_GH tF_GH
PWM

90%
GH
to 10%
VSWH

V IN

CCM DCM DCM

V OUT
2.2V
VSWH

tR_GL tF_GL
GL
90% 90%
1.0V 10% 10%

tPD_PHGLL tPD_PLGHL tPD_TSGHH tD_HOLD-OFF t PD_TSGHH tD_HOLD-OFF tPD_TSGLH

tD_DEADON tD_DEADOFF
Enter Exit Enter Exit Enter Exit
3-state 3-state 3-state 3-state 3-state 3-state

Notes:
tPD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal. Example (tPD_PHGLL – PWM going HIGH to LS VGS (GL) going LOW)
tD_xxx = delay from IC generated signal to IC generated signal. Example (tD_DEADON – LS VGS (GL) LOW to HS VGS (GH) HIGH)

PWM Exiting 3-state

tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS tPD_TSGHH = PWM 3-state to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS
tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS tPD_TSGLH = PWM 3-state to LOW to LS VGS rise, VIL_PWM to 10% LS VGS
tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (SMOD# held LOW)

SMOD# Dead Times

tPD_SLGLL = SMOD# fall to LS VGS fall, VIL_SMOD to 90% LS VGS tD_DEADON = LS VGS fall to HS VGS rise, LS-comp trip value (~1.0V GL) to 10% HS VGS
tPD_SHGLH = SMOD# rise to LS VGS rise, VIH_SMOD to 10% LS VGS tD_DEADOFF = VSWH fall to LS VGS rise, SW-comp trip value (~2.2V VSWH) to 10% LS VGS

Figure 27. PWM and 3-StateTiming Diagram

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FDMF6823C • Rev. 1.0.2
 FDMF6823C — Extra-Small, High-Performance, High-Frequency DrMOS Module
When the SMOD# pin is pulled HIGH, the synchronous
Skip Mode (SMOD#) buck converter works in Synchronous Mode. This mode
The Skip Mode function allows for higher converter allows for gating on the Low Side MOSFET. When the
efficiency when operated in light-load conditions. When SMOD# pin is pulled LOW, the low-side MOSFET is
SMOD# is pulled LOW, the low-side MOSFET gate gated off. If the SMOD# pin is connected to the PWM
signal is disabled (held LOW), preventing discharge of controller, the controller can actively enable or disable
the output capacitors as the filter inductor current SMOD# when the controller detects light-load condition
attempts reverse current flow – known as “Diode from output current sensing. Normally this pin is active
Emulation” Mode. LOW. See Figure 28 for timing delays.

Table 2. SMOD# Logic

DISB# PWM SMOD# GH GL

0 X X 0 0
1 3-State X 0 0
1 0 0 0 0
1 1 0 1 0
1 0 1 0 1
1 1 1 1 0
Note:
4. The SMOD# feature is intended to have a short propagation delay between the SMOD# signal and the low-side FET VGS
response time to control diode emulation on a cycle-by-cycle basis.

SMOD#

V IH_SMOD
V IL_SMOD

V IH_PWM V IH_PWM

V IL_PWM
PWM

90%
GH
to 10%
10%
VSWH

DCM
V OUT
2.2V CCM CCM
VSWH

GL
90%

1.0V 10% 10%

tPD_PHGLL tPD_PLGHL
tPD_SLGLL tPD_PHGHH tPD_SHGLH

tD_DEADON tD_DEADOFF Delay from SMOD# going Delay from SMOD# going
LOW to LS VGS LOW HIGH to LS V GS HIGH

HS turn -on with SMOD# LOW

Figure 28. SMOD# Timing Diagram

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FDMF6823C • Rev. 1.0.2
 FDMF6823C — Extra-Small, High-Performance, High-Frequency DrMOS Module
Application Information
VCIN Filter
Supply Capacitor Selection
The VDRV pin provides power to the gate drive of the
For the supply inputs (VCIN), a local ceramic bypass high-side and low-side power MOSFET. In most cases,
capacitor is recommended to reduce noise and to it can be connected directly to VCIN, the pin that
supply the peak current. Use at least a 1µF X7R or X5R provides power to the logic section of the driver. For
capacitor. Keep this capacitor close to the VCIN pin and additional noise immunity, an RC filter can be inserted
connect it to the GND plane with vias. between the VDRV and VCIN pins. Recommended
Bootstrap Circuit values would be 10Ω and 1µF.
The bootstrap circuit uses a charge storage capacitor Power Loss and Efficiency
(CBOOT), as shown in Figure 30. A bootstrap capacitance Measurement and Calculation
of 100nF X7R or X5R capacitor is usually adequate. A
series bootstrap resistor may be needed for specific Refer to Figure 30 for power loss testing method.
applications to improve switching noise immunity. The Power loss calculations are:
boot resistor may be required when operating above
PIN=(VIN x IIN) + (V5V x I5V) (W) (1)
15VIN and is effective at controlling the high-side
MOSFET turn-on slew rate and VSHW overshoot. RBOOT PSW=VSW x IOUT (W) (2)
values from 0.5 to 3.0Ω are typically effective in POUT=VOUT x IOUT (W) (3)
reducing VSWH overshoot.
PLOSS_MODULE=PIN - PSW (W) (4)
PLOSS_BOARD=PIN - POUT (W) (5)
EFFMODULE=100 x PSW/PIN (%) (6)
EFFBOARD=100 x POUT/PIN (%) (7)
V5V A A VIN
I5V RVCIN IIN
CVDRV CVCIN CVIN

VDRV VCIN

VIN
DISB# DISB#
RBOOT
PWM BOOT

Input PWM

FDMF6823C
FDM 67 5 CBOOT
OFF
SMOD#
VSWH IOUT
ON
A
Open - PHASE
LOUT
Drain THWN#
VOUT
Output CGND PGND V VSW COUT

Figure 29. Block Diagram With VCIN Filter

V5V A A VIN
I5V IIN
CVDRV CVIN

VDRV VCIN VIN

DISB# DISB#
RBOOT
PWM BOOT

Input PWM
FDMF6823C
FDM 5 CBOOT
OFF
SMOD#
VSWH
IOUT
ON
A
Open- PHASE
LOUT
Drain THWN#

Output CGND PGND V VSW COUT

Figure 30. Power Loss Measurement

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FDMF6823C • Rev. 1.0.2
 FDMF6823C — Extra-Small, High-Performance, High-Frequency DrMOS Module
PCB Layout Guidelines
Figure 31 and Figure 32 provide an example of a proper noise issues due to ground bounce or high positive
layout for the FDMF6823C and critical components. All and negative VSWH ringing. Inserting a boot
of the high-current paths, such as VIN, VSWH, VOUT, resistance lowers the DrMOS efficiency. Efficiency
and GND copper, should be short and wide for low versus noise trade-offs must be considered. RBOOT
inductance and resistance. This aids in achieving a values from 0.5Ω to 3.0Ω are typically effective in
more stable and evenly distributed current flow, along reducing VSWH overshoot.
with enhanced heat radiation and system performance.
8. The VIN and PGND pins handle large current
Recommendations for PCB Designers transients with frequency components greater than
100MHz. If possible, these pins should be connected
1. Input ceramic bypass capacitors must be placed
directly to the VIN and board GND planes. The use
close to the VIN and PGND pins. This helps reduce
of thermal relief traces in series with these pins is
the high-current power loop inductance and the input
discouraged since this adds inductance to the power
current ripple induced by the power MOSFET
path. This added inductance in series with either the
switching operation.
VIN or PGND pin degrades system noise immunity
2. The VSWH copper trace serves two purposes. In by increasing positive and negative VSWH ringing.
addition to being the high-frequency current path
from the DrMOS package to the output inductor, it 9. GND pad and PGND pins should be connected to
serves as a heat sink for the low-side MOSFET in the GND copper plane with multiple vias for stable
the DrMOS package. The trace should be short and grounding. Poor grounding can create a noise
wide enough to present a low-impedance path for transient offset voltage level between CGND and
the high-frequency, high-current flow between the PGND. This could lead to faulty operation of the gate
DrMOS and inductor. The short and wide trace driver and MOSFETs.
minimizes electrical losses as well as the DrMOS 10. Ringing at the BOOT pin is most effectively
temperature rise. Note that the VSWH node is a high- controlled by close placement of the boot capacitor.
voltage and high-frequency switching node with high Do not add an additional BOOT to the PGND
noise potential. Care should be taken to minimize capacitor. This may lead to excess current flow
coupling to adjacent traces. Since this copper trace through the BOOT diode.
acts as a heat sink for the lower MOSFET, balance
using the largest area possible to improve DrMOS 11. The SMOD# and DISB# pins have weak internal
cooling while maintaining acceptable noise emission. pull-up and pull-down current sources, respectively.
These pins should not have any noise filter
3. An output inductor should be located close to the capacitors. Do not to float these pins unless
FDMF6823C to minimize the power loss due to the absolutely necessary.
VSWH copper trace. Care should also be taken so the
inductor dissipation does not heat the DrMOS. 12. Use multiple vias on the VIN and VOUT copper
® areas to interconnect top, inner, and bottom layers
4. PowerTrench MOSFETs are used in the output to distribute current flow and heat conduction. Do
stage and are effective at minimizing ringing due to not put many vias on the VSWH copper to avoid
fast switching. In most cases, no VSWH snubber is extra parasitic inductance and noise on the
required. If a snubber is used, it should be placed switching waveform. As long as efficiency and
close to the VSWH and PGND pins. The selected thermal performance are acceptable, place only
resistor and capacitor need to be the proper size for one VSWH copper on the top layer and use no vias
power dissipation. on the VSWH copper to minimize switch node
5. VCIN, VDRV, and BOOT capacitors should be parasitic noise. Vias should be relatively large and
placed as close as possible to the VCIN-to-CGND, of reasonably low inductance. Critical high-
VDRV-to-CGND, and BOOT-to-PHASE pin pairs to frequency components, such as RBOOT, CBOOT, RC
ensure clean and stable power. Routing width and snubber, and bypass capacitors; should be located
length should be considered as well. as close to the respective DrMOS module pins as
possible on the top layer of the PCB. If this is not
6. Include a trace from the PHASE pin to the VSWH pin feasible, they can be connected from the backside
to improve noise margin. Keep this trace as short as through a network of low-inductance vias.
possible.
7. The layout should include the option to insert a
small-value series boot resistor between the boot
capacitor and BOOT pin. The boot-loop size,
including RBOOT and CBOOT, should be as small as
possible. The boot resistor may be required when
operating above 15VIN and is effective at controlling
the high-side MOSFET turn-on slew rate and VSHW
overshoot. RBOOT can improve noise operating
margin in synchronous buck designs that may have

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FDMF6823C • Rev. 1.0.2
 FDMF6823C — Extra-Small, High-Performance, High-Frequency DrMOS Module
Figure 31. PCB Layout Example (Top View)

Figure 32. PCB Layout Example (Bottom View)

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FDMF6823C • Rev. 1.0.2
 Physical Dimensions

FDMF6823C — Extra-Small, High-Performance, High-Frequency DrMOS Module

B PIN#1
0.10 C INDICATOR
6.00
2X A 5.80

4.50
30 21
31
20
6.00 2.50 0.40

0.65
0.25
1.60
0.10 C 11
2X 40
1 10
TOP VIEW SEE 0.60 0.35
DETAIL 'A' 0.50 TYP 0.15
2.10
2.10
LAND PATTERN
FRONT VIEW 0.10 C A B RECOMMENDATION
4.40±0.10 0.05 C
(2.20) 0.30
0.40 21 30 0.20 (40X)
31
0.50 20
(0.70) 2.40±0.10 0.20
PIN #1 INDICATOR
1.50±0.10 0.50 (40X)
0.30
40
11
0.40 10 1
2.00±0.10 2.00±0.10
(0.20) 0.50
(0.20) NOTES: UNLESS OTHERWISE SPECIFIED
BOTTOM VIEW
A) DOES NOT FULLY CONFORM TO JEDEC
REGISTRATION MO-220, DATED
1.10 MAY/2005.
0.90
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
0.10 C OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
0.08 C 0.30 0.05 E) DRAWING FILE NAME: PQFN40AREV2
0.20 0.00 C
SEATING
DETAIL 'A' PLANE
SCALE: 2:1

Figure 33. 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0mm Package

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FDMF6823C • Rev. 1.0.2
 FDMF6823C — Extra-Small, High-Performance, High-Frequency DrMOS Module

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FDMF6823C • Rev. 1.0.2