MP8765

MP8765
24V, 6A High Efficiency

Synchronous Step-down Converter
The Future of Analog IC Technology
DESCRIPTION FEATURES
The MP8765 is a fully integrated high frequency • Wide 5V to 24V Operating Input Range
synchronous rectified step-down switch mode • 6A Continuous Output Current
converter. It offers very compact solutions to • PFM/PWM Mode Selectable
achieve 6A continuous output current over a • Low RDS(ON) Internal Power MOSFETs
wide input supply range with excellent load and • Proprietary Switching Loss Reduction
line regulation. The MP8765 operates at high Technique
efficiency over a wide output current load range. • 1% Reference Voltage
Constant-On-Time (COT) control mode • 7ms Internal Soft Start
provides fast transient response and eases loop • Output Discharge
stabilization. • 500kHz Switching Frequency
Under voltage lockout is internally set as 4.6 V, • Hiccup OCP Protection and Thermal
An open drain power good signal indicates the Shutdown
output is within its nominal voltage range. • Auto Retry OVP Protection
• Output Adjustable from 0.604V to 5.5V
Full protection features include OCP and thermal
shut down. APPLICATIONS
The converter requires minimum number of • Laptop Computer
external components and is available in QFN16 • Tablet PC
(3mmx3mm) package. • Networking Systems
• Personal Video Recorders
• Flat Panel Television and Monitors
• Distributed Power Systems
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
MP8765 Rev. 1.01 www.MonolithicPower.com 1

2/10/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
MP8765 ─ 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number* Package Top Marking
MP8765GQ QFN16(3x3mm) AHR
* For Tape & Reel, add suffix –Z (e.g.MP8765GQ-Z)
PACKAGE REFERENCE
TOP VIEW
AGND EN FB VCC BST
14 13 12 11 10
VIN 1
15 SW 9 SW
PGND 2
16 SW SW
8
3 4 5 6 7
NC PG NC MODE VOUT
(5)
ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance θJA θJC
Supply Voltage VIN .......................................24V QFN16 (3mmx3mm) ............... 70 ...... 15 ... °C/W
VSW ............................................. -0.3V to 24.3V Notes:
VSW (30ns) ........................................ -3V to 28V 1) Exceeding these ratings may damage the device.
2) Refer to “Configuring the EN Control”.
VSW (5ns) .......................................... -6V to 28V 3) The maximum allowable power dissipation is a function of the
VBST ..................................................VSW + 5.5V maximum junction temperature TJ(MAX), the junction-to-
VEN ...............................................................12V ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
Enable Current IEN(2)................................ 2.5mA any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-
All Other Pins ............................. –0.3V to +5.5V TA)/θJA. Exceeding the maximum allowable power dissipation
(3) will cause excessive die temperature, and the regulator will go
Continuous Power Dissipation (TA=+25°) into thermal shutdown. Internal thermal shutdown circuitry
QFN16...……………………….…..…………1.8W protects the device from permanent damage.
4) The device is not guaranteed to function outside of its
Junction Temperature .............................. 150°C operating conditions.
Lead Temperature ................................... 260°C 5) Measured on JESD51-7, 4-layer PCB.
Storage Temperature ............... -65°C to +150°C
(4)
Recommended Operating Conditions
Supply Voltage VIN ............................. 5V to 22V
Output Voltage VOUT................... 0.604V to 5.5V
Enable Current IEN................................... 1mA
Operating Junction Temp. (TJ). -40°C to +125°C

ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = 25°C, unless otherwise noted.
Parameters Symbol Condition Min Typ Max Units
Supply Current
Supply Current (Shutdown) IIN VEN = 0V 0 1 μA
Supply Current (Quiescent) IIN VEN = 2V, VFB = 0.65V 100 160 200 μA
MOSFET
High-side Switch On Resistance HSRDS-ON 38 mΩ
Low-side Switch On Resistance LSRDS-ON 15 mΩ
Switch Leakage SW LKG VEN = 0V, VSW = 0V 0 1 μA
Current Limit
Low-side Valley Current Limit ILIMIT TJ = 25°C 6 6.6 7.6 A
Mode Pin
PWM Mode Threshold VMODE H 2 V
PFM Mode Threshold VMODE L 0.4 V
Pull-up Current IMODE PU 2.5 μA
Switching frequency and minimum off timer
Switching frequency FS 400 500 600 kHz
(6)
Minimum Off Time TOFF 300 ns
Over-voltage Protection
OVP Threshold VOVP 125% 130% 135% VREF
OVP Delay TOVPDEL 2 μs
Reference And Soft Start
Reference Voltage VREF 598 604 610 mV
Feedback Current IFB VFB = 604mV 10 50 nA
Soft Start Time TSS 6 7 8 ms
Enable And UVLO
Enable Input Low Voltage VILEN 1.15 1.25 1.35 V
Enable Hysteresis VEN-HYS 100 mV
VEN = 2V 3
Enable Input Current IEN μA
VEN = 0V 0
VCC Under Voltage Lockout
VCCVth 4.6 4.85 V
Threshold Rising
VCC Under Voltage Lockout
VCCHYS 480 mV
Threshold Hysteresis

ELECTRICAL CHARACTERISTICS (continued)

VIN = 12V, TJ = 25°C, unless otherwise noted.
Parameters Symbol Condition Min Typ Max Units
VCC Regulator
VCC Regulator VCC 4.8 5.1 5.3 V
VCC Load Regulation Icc=5mA 5 %
Power Good
FB Rising (Good) PGVth-Hi 95

FB Falling (Fault) PGVth-Lo 85
%VREF
FB Rising (Fault) PGVth-Hi 115
FB Falling (Good) PGVth-Lo 105
Power Good Lower to High Delay PGTd 0.5 ms
Power Good Sink Current
VPG Sink 4mA 0.4 V
Capability
Power Good Leakage Current IPG LEAK VPG = 3.3V 12 μA
Thermal Protection
(6)
Thermal Shutdown TSD 150 °C
(6)
Thermal Shutdown Hysteresis 25 °C
Note:
6) Guaranteed by design.

TYPICAL PERFORMANCE CHARACTERISTICS

Performance waveforms are tested on the evaluation board of the Design Example section.
VIN=12V, VOUT =1.05V, L=1.2µH, PFM Mode, TJ=+25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS (continued)






PIN FUNCTIONS
PIN # Name Description
Supply Voltage. The IN pin supplies power for internal MOSFET and regulator. The
MP8765 operate from a +5V to +22V input rail. An input capacitor is needed to
1 VIN
decouple the input rail. Use wide PCB traces and multiple vias to make the
connection.
2 PGND Power Ground. Use wide PCB traces and multiple vias to make the connection
Power good output, the output of this pin is an open drain signal and is high if the
4 PG output voltage is higher than 95% of the nominal voltage. There is a delay from FB ≥
95% to PGOOD goes high.
3, 5 NC
PFM/PWM mode selection pin. Float MODE pin or pull it higher than 2V, MP8765
6 MODE always works in force PWM mode; Connecting MODE pin to ground enables PFM
mode at light load condition.
VOUT pin is used to sense the output voltage of the Buck regulator, connect this pin
7 VOUT
to the output capacitor of the regulator directly.
Switch Output. Connect this pin to the inductor and bootstrap capacitor. This pin is
driven up to the VIN voltage by the high-side switch during the on-time of the PWM
8,9
duty cycle. The inductor current drives the SW pin negative during the off-time. The
Exposed SW
on-resistance of the low-side switch and the internal diode fixes the negative
Pad 15, 16
voltage. Use wide and short PCB traces to make the connection. Try to minimize the
area of the SW pattern.
Bootstrap. A capacitor connected between SW and BS pins is required to form a
10 BST
floating supply across the high-side switch driver.
Internal 5V LDO output. The driver and control circuits are powered from this
voltage. Decouple with a minimum 1µF ceramic capacitor as close to the pin as
11 VCC
possible. X7R or X5R grade dielectric ceramic capacitors are recommended for their
stable temperature characteristics.
Feedback. An external resistor divider from the output to GND, tapped to the FB pin,
12 FB sets the output voltage. It is recommended to place the resistor divider as close to
FB pin as possible. Vias should be avoided on the FB traces.
Enable pin. EN is a digital input that turns the regulator on or off. Drive EN high to
13 EN turn on the regulator, drive it low to turn it off. Connect EN with VIN through a pull-up
resistor or a resistive voltage divider for automatic startup. Do not float this pin.
Analog ground. The internal reference is referred to AGND. Connect the GND of the
14 AGND
FB divider resistor to AGND for better load regulation.

BLOCK DIAGRAM
Figure 1—Functional Block Diagram

OPERATION
PWM Operation When the output current is high and the inductor
current is always above zero amps, it is called
The MP8765 is fully integrated synchronous
continuous-conduction-mode (CCM). The CCM
rectified step-down switch mode converter.
mode operation is shown in Figure 2 shown.
Constant-on-time (COT) control is employed to
When VFB is below VREF, HS-MOSFET is turned
provide fast transient response and easy loop
on for a fixed interval which is determined by
stabilization. At the beginning of each cycle, the
one-shot on-timer. When the HS-MOSFET is
high-side MOSFET (HS-FET) is turned ON when
turned off, the LS-MOSFET is turned on until
the feedback voltage (VFB) is below the
next period.
reference voltage (VREF), which indicates
insufficient output voltage. The ON period is In CCM mode operation, the switching frequency
determined by both the output voltage and input is fairly constant and it is called PWM mode.
voltage to make the switching frequency fairy
Light-Load Operation
constant over input voltage range.
With the load decrease, the inductor current
After the ON period elapses, the HS-FET is decrease too. Once the inductor current touch
turned off, or becomes OFF state. It is turned ON zero, the operation is transition from continuous-
again when VFB drops below VREF. By conduction-mode (CCM) to discontinuous-
repeating operation this way, the converter conduction-mode (DCM).
regulates the output voltage. The integrated low-
side MOSFET (LS-FET) is turned on when the The light load operation is shown in Figure 3.
HS-FET is in its OFF state to minimize the When VFB is below VREF, HS-MOSFET is turned
conduction loss. There will be a dead short on for a fixed interval which is determined by
between input and GND if both HS-FET and LS- one-shot on-timer. When the HS-MOSFET is
FET are turned on at the same time. It’s called turned off, the LS-MOSFET is turned on until the
shoot-through. In order to avoid shoot-through, a inductor current reaches zero. In DCM operation,
dead-time (DT) is internally generated between the VFB does not reach VREF when the inductor
HS-FET off and LS-FET on, or LS-FET off and current is approaching zero. The LS-FET driver
HS-FET on. turns into tri-state (high Z) whenever the inductor
current reaches zero. A current modulator takes
An internal compensation is applied for COT over the control of LS-FET and limits the inductor
control to make a more stable operation even current to less than -1mA. Hence, the output
when ceramic capacitors are used as output capacitors discharge slowly to GND through LS-
capacitors, this internal compensation will then FET. As a result, the efficiency at light load
improve the jitter performance without affect the condition is greatly improved. At light load
line or load regulation. condition, the HS-FET is not turned ON as
Heavy-Load Operation frequently as at heavy load condition. This is
called skip mode.
At light load or no load condition, the output
drops very slowly and the MP8765 reduces the
switching frequency naturally and then high
efficiency is achieved at light load.
Figure 2—Heavy Load Operation

Figure 3—Light Load Operation

As the output current increases from the light VNOISE

VS LOPE 2
load condition, the time period within which the V FB

current modulator regulates becomes shorter. V REF
The HS-FET is turned ON more frequently.
Hence, the switching frequency increases
correspondingly. The output current reaches the HS D river
critical level when the current modulator time is Jitter

zero. The critical level of the output current is
determined as follows: Figure 5—Jitter in Skip Mode
(VIN − VOUT ) × VOUT Operating without external ramp
IOUT = (1)
2 × L × FSW × VIN The traditional constant-on-time control scheme
It turns into PWM mode once the output current is intrinsically unstable if output capacitor’s ESR
exceeds the critical level. After that, the switching is not large enough as an effective current-sense
frequency stays fairly constant over the output resistor. Ceramic capacitors usually can not be
current range. used as output capacitor.
PFM/PWM Mode Selection To realize the stability, the ESR value should be
The MP8765 has a MODE pin which provides chosen as follow:
selectable operation mode for light load. Floating TSW T
the MODE pin or pulling it higher than 2V will set + ON
MP8765 always work at force PWM mode. RESR ≥ 0.7 × π 2 (2)
COUT
Connecting MODE pin to ground enables PFM
(Pulse Frequency Modulation) mode at light load TSW is the switching period.
condition. MP8765 skips some pulses for PFM The MP8765 has built in internal ramp
mode and achieves the light load power save. compensation to make sure the system is stable
Jitter and FB Ramp Slope even without the help of output capacitor’s ESR;
and thus the pure ceramic capacitor solution can
Jitter occurs in both PWM and skip modes when
be applicant. The pure ceramic capacitor solution
noise in the VFB ripple propagates a delay to the
can significantly reduce the output ripple, total
HS-FET driver, as shown in Figures 4 and 5.
BOM cost and the board area.
Jitter can affect system stability, with noise
immunity proportional to the steepness of VFB’s Figure 6 shows a typical output circuit in PWM
downward slope. However, VFB ripple does not mode without an external ramp circuit. Turn to
directly affect noise immunity. application information section for design steps
VNOISE V S L O PE1 without external compensation.
SW
VFB
L Vo
VREF
R1 ESR
FB
HS D river
J itter R2 CAP
Figure 4—Jitter in PWM Mode
Figure 6—Simplified Circuit in PWM Mode

without External Ramp Compensation

When using a large-ESR capacitor on the output, TSW T

+ ON -RESRCOUT
add a ceramic capacitor with a value of 10uF or 0.7 × π 2 Io × 10-3
-Vslope1 ≥ VOUT + (7)
less to in parallel to minimize the effect of ESL. 2 × L × COUT TSW -Ton
Operating with external ramp compensation Io is the load current.
The MP8765 is usually able to support ceramic
In skip mode, the downward slope of the VFB
output capacitors without external ramp, however,
ripple is the same whether the external ramp is
in some of the cases, the internal ramp may not
used or not. Figure 8 shows the simplified circuit
be enough to stabilize the system, and external
of the skip mode when both the HS-FET and LS-
ramp compensation is needed. Skip to
FET are off.
application information section for design steps
with external ramp compensation. Vo
SW L Vo
R4 C4 R1 ESR
FB
R1
IR4 IC 4
Ro
R9 I FB
Cout
Ceramic R2
FB
R2
Figure 8—Simplified Circuit in skip Mode

Figure 7—Simplified Circuit in PWM Mode
with External Ramp Compensation The downward slope of the VFB ripple in skip
mode can be determined as follow:
Figure 7 shows a simplified external ramp
compensation (R4 and C4) for PWM mode, with − VREF (8)
VSLOPE2 =
HS-FET off. Chose R1, R2, R9 and C4 of the ((R1 + R2 ) // Ro) × COUT
external ramp to meet the following condition:
Where Ro is the equivalent load resistor.
1 1 ⎛ R × R2 ⎞ As described in Figure 5, VSLOPE2 in the skip
< ×⎜ 1 + R9 ⎟ (3)
2π × FSW × C 4 5 ⎝ R1 + R 2 ⎠ mode is lower than that is in the PWM mode, so
it is reasonable that the jitter in the skip mode is
Where: larger. If one wants a system with less jitter
during light load condition, the values of the VFB
IR4 = IC4 + IFB ≈ IC4 (4) resistors should not be too big, however, that will
And the Vramp on the VFB can then be estimated decrease the light load efficiency.
as: Configuring the EN Control
VIN − VOUT R1 // R2 (5) EN is used to enable or disable the whole chip.
VRAMP = × TON × Pull En high to turn on the regulator and pull EN
R4 × C4 R1 // R2 + R9
low to turn it off. Do not float the pin.
The downward slope of the VFB ripple then For automatic start-up the EN pin can be pulled
follows up to input voltage through a resistive voltage
− VRAMP − VOUT (6) divider. Choose the values of the pull-up resistor
VSLOPE1 = =
Toff R 4 × C4 (Rup from Vin pin to EN pin) and the pull-down
resistor (Rdown from EN pin to GND) to
As can be seen from equation 6, if there is determine the automatic start-up voltage:
instability in PWM mode, we can reduce either
R4 or C4. If C4 can not be reduced further due to
limitation from equation 3, then we can only
reduce R4. For a stable PWM operation, the
Vslope1 should be design follow equation 7.

(Rup + Rdown ) Power Good (PGOOD)

VIN−START = 1.35 × (V) (9)
Rdown The MP8765 has power-good (PGOOD) output
For example, for Rup=150kΩ and used to indicate whether the output voltage of the
Rdown=51kΩ,the VIN−START is set at 5.32V. Buck regulator is ready or not. The PGOOD pin
is the open drain of a MOSFET. It should be
To avoid noise, a 10nF ceramic capacitor from connected to VCC or other voltage source through
EN to GND is recommended. a resistor (e.g. 100k). After the input voltage is
There is an internal Zener diode on the EN pin, applied, the MOSFET is turned on so that the
which clamps the EN pin voltage to prevent it PGOOD pin is pulled to GND before SS is ready.
from running away. The maximum pull up current After FB voltage reaches 95% of REF voltage,
assuming a worst case 12V internal Zener clamp the PGOOD pin is pulled high after a delay. The
should be less than 1mA. PGOOD delay time is 0.5ms.
Therefore, when EN is driven by an external logic When the FB voltage drops to 85% of REF
signal, the EN voltage should be lower than 12V; voltage, the PGOOD pin will be pulled low.
when EN is connected with VIN through a pull-up Hiccup Over Current Protection
resistor or a resistive voltage divider, the
MP8765 has cycle-by-cycle over current limiting
resistance selection should ensure the maximum
control. The current-limit circuit employs a
pull up current less than 1mA.
"valley" current-sensing algorithm. The part uses
If using a resistive voltage divider and VIN higher the Rds(on) of the low side MOSFET as a
than 12V, the allowed minimum pull-up resistor current-sensing element. If the magnitude of the
Rup should meet the following equation: current-sense signal is above the current-limit
VIN -12V 12V threshold, the PWM is not allowed to initiate a
- =1mA (10) new cycle.
Rup Rdown
Especially, just using the pull-up resistor Rup(the The trip level is fixed internally. The inductor
pull-down resistor is not connected), the current is monitored by the voltage between GND
pin and SW pin. GND is used as the positive
VIN-START is determined by input UVLO, and the current sensing node so that GND should be
minimum resistor value is: connected to the source terminal of the bottom
V -12V MOSFET.
Rup = IN (W) (11)
1mA Since the comparison is done during the high
A typical pull-up resistor is 499kΩ. side MOSFET OFF and low side MOSFET ON
Soft Start state, the OC trip level sets the valley level of the
inductor current. Thus, the load current at over-
The MP8765 employs soft start (SS) mechanism
current threshold, IOC, can be calculated as
to ensure smooth output during power-up. When
follows:
the EN pin becomes high, the internal reference
voltage ramps up gradually; hence, the output ΔIinductor
voltage ramps up smoothly, as well. Once the IOC = I _ limit + (12)
2
reference voltage reaches the target value, the
soft start finishes and it enters into steady state In an over-current condition, the current to the
operation. load exceeds the current to the output capacitor;
thus the output voltage tends to fall off. The
If the output is pre-biased to a certain voltage output voltage drops until VFB is below the Under-
during startup, the IC will disable the switching of Voltage (UV) threshold—typically 60% below the
both high-side and low-side switches until the reference. Once UV is triggered, the MP8765
voltage on the internal reference exceeds the enters hiccup mode to periodically restart the part.
sensed output voltage at the FB node. This protection mode is especially useful when
the output is dead-shorted to ground, and greatly

reduces the average short circuit current to Figure 9—Adjustable UVLO

alleviate thermal issues and protect the regulator.
Thermal Shutdown
The MP8765 exits the hiccup mode once the
over-current condition is removed. Thermal shutdown is employed in the MP8765.
The junction temperature of the IC is internally
Over Voltage Protection (OVP) monitored. If the junction temperature exceeds
MP8765 monitors a resistor divided feedback the threshold value (typical 150ºC), the converter
voltage to detect over voltage. When the shuts off. This is a non-latch protection. There is
feedback voltage becomes higher than 115% of about 25ºC hysteresis. Once the junction
the target voltage, the controller will enter temperature drops to about 125ºC, it initiates a
Dynamic Regulation Period. During this period, SS.
the LS is on until the LS current goes to -2.5A, Output Discharge
this will then discharge the output and try to keep
it within the normal range. Part will exit this MP8765 discharges the output when EN is low,
regulation period when feedback voltage is or the controller is turned off by the protection
decreased to below 105% of the reference functions (UVP & OCP, OCP, OVP, UVLO, and
voltage. If the dynamic regulation can not limit thermal shutdown). The part discharges outputs
the increasing of the Vout, once the feedback using an internal 6Ω MOSFET which is
voltage becomes higher than 130% of the connected to VOUT and GND. The external low-
feedback voltage, the HS turns off and the LS side MOSFET is not turned on for the output
works at saturated mode as a current source to discharge operation to avoid the possibility of
discharge the output. This state will keep on until causing negative voltage at the output.
the feedback voltage drops to below 115% of the
reference voltage.
UVLO Protection
The MP8765 has under-voltage lock-out
protection (UVLO). When the VCC voltage is
higher than the UVLO rising threshold voltage,
the part will be powered up. It shuts off when the
VIN voltage is lower than the UVLO falling
threshold voltage. This is non-latch protection.
The part is disabled when the VCC voltage falls
below 4.6V. If an application requires a higher
under-voltage lockout (UVLO), use the EN pin as
shown in Figure 9 to adjust the input voltage
UVLO by using two external resistors. It is
recommended to use the enable resistors to set
the UVLO falling threshold (VSTOP) above 4.6V.
The rising threshold (VSTART) should be set to
provide enough hysteresis to allow for any input
supply variations.
IN
RUP EN Comparator
RDOWN EN

APPLICATION INFORMATION
Setting the Output Voltage---without external If the system is not stable enough when low ESR
compensation ceramic capacitor is used in the output, an
For applications that electrolytic capacitor or POS external voltage ramp should be added to FB
capacitor with a controlled output of ESR is set through resistor R4 and capacitor C4.The output
as output capacitors, or the internal voltage is influenced by ramp voltage VRAMP
compensation is enough for a stable operation besides R divider as shown in Figure 11. The
when ceramic capacitors is used, then the VRAMP can be calculated as shown in equation 7.
external compensation is not need.. The output R2 should be chosen reasonably, a small R2 will
voltage is set by feedback resistors R1 and R2. lead to considerable quiescent current loss while
As Figure 10 shows. too large R2 makes the FB noise sensitive. It is
SW recommended to choose a value within 5kΩ-
L Vo
100kΩ for R2.Typically, set the current through
R2 between 5-30uA will make a good balance
FB
R1 ESR
between system stability and also the no load
loss. And the value of R1 then is determined as
R2
POSCAP
follow:
R2 (14)
R= 1
VFB(AVG) R2
-
Figure10—Simplified Circuit of POS Capacitor (VOUT -VFB(AVG) ) R4 +R9
First, choose a value for R2. R2 should be The VFB(AVG) is the average value on the FB,
chosen reasonably, a small R2 will lead to VFB(AVG) varies with the Vin, Vo, and load
considerable quiescent current loss while too condition, etc., its value on the skip mode would
large R2 makes the FB noise sensitive. It is be lower than that of the PWM mode, which
recommended to choose a value within 5kΩ- means the load regulation is strictly related to the
100kΩ for R2.Typically, set the current through VFB(AVG). Also the line regulation is related to the
R2 between 5-30uA will make a good balance VFB(AVG). If one wants to gets a better load or line
between system stability and also the no load regulation, a lower Vramp is suggested, as long
loss. Then R1 is determined as follow with the as the criterion shown in equation 8 can be met.
output ripple considered: For PWM operation, VFB(AVG) value can be
1 deduced from the equation below.
VOUT − ΔVOUT − VREF
R1 = 2 ⋅ R2 (13) 1 R1 //R2
VREF VFB(AVG) = VREF + VRAMP × (15)
2 R1 //R2 + R9
ΔVOUT is the output ripple.
Usually, R9 is set to 0Ω, and it can also be set
Setting the Output Voltage---with external following equation 14 for a better noise immunity.
compensation It should also set to be 5 times smaller than
SW
R1//R2 to minimize its influence on Vramp.
L Vo 1
R9 = (16)
2π× C4 × 2FSW
FB R4 C4 R1 Using equation 13 to calculate the R1 can be
R9 complicated. To simplify the calculation, a DC-
Ceramic
blocking capacitor Cdc can be added to filter the
R2
DC influence from R4 and R9. Figure 12 shows
a simplified circuit with external ramp
compensation and a DC-blocking capacitor. With
Figure11—Simplified Circuit of Ceramic this capacitor, R1 can easily be obtained by
Capacitor

using the simplified equation for PWM mode IOUT

operation: ICIN = (19)
2
1
(VOUT − VREF − VRAMP )
2 (17) For simplification, choose the input capacitor with
R1 = R2
1 an RMS current rating greater than half of the
VREF + VRAMP maximum load current.
2
Cdc is suggested to be at least 10 times larger The input capacitance value determines the input
than C4 for better DC blocking performance, and voltage ripple of the converter. If there is an input
should also not larger than 0.47uF considering voltage ripple requirement in the system, choose
start up performance. In case one wants to use the input capacitor that meets the specification.
larger Cdc for a better FB noise immunity,
combined with reduced R1 and R2 to limit the The input voltage ripple can be estimated as
Cdc in a reasonable value without affecting the follows:
system start up. Be noted that even when the IOUT V V
Cdc is applied, the load and line regulation are ΔVIN = × OUT × (1 − OUT ) (20)
still Vramp related. FSW × CIN VIN VIN
SW
L Vo Under worst-case conditions where VIN = 2VOUT:
1 I
ΔVIN = × OUT (21)
FB R4 C4 R1
4 FSW × CIN
Cdc
Ceramic
Output Capacitor
R2
The output capacitor is required to maintain the
DC output voltage. Ceramic or POSCAP
capacitors are recommended. The output voltage
Figure12—Simplified Circuit of Ceramic ripple can be estimated as:
Capacitor with DC blocking capacitor
VOUT V 1
Input Capacitor ΔVOUT = × (1 − OUT ) × (RESR + ) (22)
FSW × L VIN 8 × FSW × COUT
The input current to the step-down converter is
In the case of ceramic capacitors, the impedance
discontinuous and therefore requires a capacitor
at the switching frequency is dominated by the
to supply the AC current to the step-down
capacitance. The output voltage ripple is mainly
converter while maintaining the DC input voltage.
caused by the capacitance. For simplification, the
Ceramic capacitors are recommended for best
output voltage ripple can be estimated as:
performance and should be placed as close to
the VIN pin as possible. Capacitors with X5R and VOUT V (23)
ΔVOUT = × (1 − OUT )
X7R ceramic dielectrics are recommended 8 × FSW × L × COUT
2
VIN
because they are fairly stable with temperature
fluctuations. The output voltage ripple caused by ESR is very
small. Therefore, an external ramp is needed to
The capacitors must also have a ripple current stabilize the system. The external ramp can be
rating greater than the maximum input ripple generated through resistor R4 and capacitor C4.
current of the converter. The input ripple current
can be estimated as follows: In the case of POSCAP capacitors, the ESR
dominates the impedance at the switching
VOUT V frequency. The ramp voltage generated from the
ICIN = IOUT × × (1 − OUT ) (18)
VIN VIN ESR is high enough to stabilize the system.
Therefore, an external ramp is not needed. A
The worst-case condition occurs at VIN = 2VOUT, minimum ESR value around 12mΩ is required to
where: ensure stable operation of the converter. For

PCB Layout Guide

simplification, the output ripple can be
1. The high current paths (GND, IN, and SW)
approximated as:
should be placed very close to the device
VOUT V with short, direct and wide traces.
ΔVOUT = × (1 − OUT ) × RESR (24)
FSW × L VIN 2. Put the input capacitors as close to the IN
and GND pins as possible.
Maximum output capacitor limitation should be 3. Put the decoupling capacitor as close to the
also considered in design application. MP8765 VCC and GND pins as possible. Place the
has an around 7ms soft-start time period. If the Cap close to AGND if the distance is long.
output capacitor value is too high, the output And place >3 Vias if via is required to reduce
voltage can’t reach the design value during the the leakage inductance.
soft-start time, and then it will fail to regulate. The
4. Keep the switching node SW short and away
maximum output capacitor value Co_max can be
from the feedback network.
limited approximately by:
5. The external feedback resistors should be
CO _ MAX = (ILIM _ AVG − IOUT ) × Tss / VOUT (25) placed next to the FB pin. Make sure that
there is no via on the FB trace.
Where, ILIM_AVG is the average start-up current
6. Keep the BST voltage path (BST, C3, and
during soft-start period. Tss is the soft-start time.
SW) as short as possible.
Inductor 7. Keep the IN and GND pads connected with
The inductor is necessary to supply constant large copper to achieve better thermal
current to the output load while being driven by performance. Add several Vias with
the switched input voltage. A larger-value 10mil_drill/18mil_copper_width close to the
inductor will result in less ripple current that will IN and GND pads to help on thermal
result in lower output ripple voltage. However, a dissipation.
larger-value inductor will have a larger physical 8. Four-layer layout is strongly recommended to
footprint, higher series resistance, and/or lower achieve better thermal performance.
saturation current. A good rule for determining Note:
the inductance value is to design the peak-to- Please refer to the PCB Layout Application Note for more details.
peak ripple current in the inductor to be in the
range of 30% to 40% of the maximum output
current, and that the peak inductor current is
below the maximum switch current limit. The
inductance value can be calculated by:
VOUT V (26)
L= × (1 − OUT )
FSW × ΔIL VIN
Where ΔIL is the peak-to-peak inductor ripple

current.
The inductor should not saturate under the
maximum inductor peak current, where the peak
inductor current can be calculated by:
VOUT V
ILP = IOUT + × (1 − OUT ) (27)
2FSW × L VIN

A G ND KL E V IN
C O N N E CT T O P G N D
AG N D
EN
14 13 12 11 10
V IN SW
1
15 SW 9
16 SW 8
3 4 5 6 7
MOD E
PG V O UT
GN D V OU T
Figure 13—Recommend Layout

Recommend Design Example The detailed application schematic is shown in
Figure 14 when low ESR caps are used. The
A design example is provided below when the
typical performance and circuit waveforms have
ceramic capacitors are applied:
been shown in the Typical Performance
Table 1—Design Example Characteristics section. For more possible
VOUT Cout L R4 C4 R9 R1 R2 applications of this device, please refer to related
(V) (F) (μH) (Ω) (F) (Ω) (kΩ) (kΩ) Evaluation Board Data Sheets.
1.05 22μx2+47μ 1.2 1M 220p 499 63.4 82
5.0 22μx3 2 1M 220p 499 150 18

TYPICAL APPLICATION
Figure 14 — Typical Application Circuit with Low ESR Ceramic Output Capacitor
VIN=6.5-22V, VOUT=1.05V, IOUT=6A
Figure 15 — Typical Application Circuit with Low ESR Ceramic Output Capacitor
VIN=7-22V, VOUT=5V, IOUT=6A

PACKAGE INFORMATION
QFN16 (3X3mm)
PIN 1 ID
MARKING PIN 1 ID
0.10x45° TYP.
PIN 1 ID
INDEX AREA
TOP VIEW BOTTOM VIEW
SIDE VIEW
NOTE:
0.10x45°
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT
INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.


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MP8765

24V, 6A High Efficiency

MP8765 Rev. 1.01 www.MonolithicPower.com 1

* For Tape & Reel, add suffix –Z (e.g.MP8765GQ-Z)

MP8765 Rev. 1.01 www.MonolithicPower.com 2

MP8765 Rev. 1.01 www.MonolithicPower.com 3

ELECTRICAL CHARACTERISTICS (continued)

FB Rising (Good) PGVth-Hi 95

MP8765 Rev. 1.01 www.MonolithicPower.com 4

TYPICAL PERFORMANCE CHARACTERISTICS

MP8765 Rev. 1.01 www.MonolithicPower.com 5

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

MP8765 Rev. 1.01 www.MonolithicPower.com 6

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

MP8765 Rev. 1.01 www.MonolithicPower.com 7

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

MP8765 Rev. 1.01 www.MonolithicPower.com 8

MP8765 Rev. 1.01 www.MonolithicPower.com 9

Figure 1—Functional Block Diagram

MP8765 Rev. 1.01 www.MonolithicPower.com 10

Figure 2—Heavy Load Operation

MP8765 Rev. 1.01 www.MonolithicPower.com 11

As the output current increases from the light VNOISE

load condition, the time period within which the V FB

critical level when the current modulator time is Jitter

Figure 4—Jitter in PWM Mode

Figure 6—Simplified Circuit in PWM Mode

MP8765 Rev. 1.01 www.MonolithicPower.com 12

When using a large-ESR capacitor on the output, TSW T

Figure 8—Simplified Circuit in skip Mode

MP8765 Rev. 1.01 www.MonolithicPower.com 13

(Rup + Rdown ) Power Good (PGOOD)

MP8765 Rev. 1.01 www.MonolithicPower.com 14

reduces the average short circuit current to Figure 9—Adjustable UVLO

MP8765 Rev. 1.01 www.MonolithicPower.com 15

MP8765 Rev. 1.01 www.MonolithicPower.com 16

using the simplified equation for PWM mode IOUT

MP8765 Rev. 1.01 www.MonolithicPower.com 17

PCB Layout Guide

Where ΔIL is the peak-to-peak inductor ripple

MP8765 Rev. 1.01 www.MonolithicPower.com 18

Figure 13—Recommend Layout

MP8765 Rev. 1.01 www.MonolithicPower.com 19

MP8765 Rev. 1.01 www.MonolithicPower.com 20

TOP VIEW BOTTOM VIEW

RECOMMENDED LAND PATTERN

MP8765 Rev. 1.01 www.MonolithicPower.com 21

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