LN3C63

High Performance Current Mode PWM Controller

Cycle Turning+

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For,
Adaptor & Charger
Offline Power Supply
Open Frame Power
DVD&DVB Player
Auxiliary Power for PC
etc...…..

© 2008 LIEMIC Semiconductor Co.,Ltd.

LN3C63AD
REV: 1.0.0

Free Datasheet http://www.datasheet4u.net/

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GENERAL DESCRIPTION technique together with soft switching control at the

LN3C63 is a highly integrated current mode PWM totem pole gate drive output.
control IC optimized for high performance, low
standby power and cost effective offline flyback Tone energy at below 20kHz is minimized in the
converter applications in less than 35W range. design and audio noise is eliminated during
PWM switching frequency at normal operation is operation. LN3C63 is offered in SOT23-6, SOP8
externally programmable and trimmed to tight range. and DIP8 packages.
At no load or light load condition, the IC operates in
extended ‘burst mode’ to minimize switching loss. FEATURES
Lower standby power and higher conversion
efficiency is thus achieved. VDD low startup u LIEMIC Proprietary Cycle Turning Technology
current and low operating current contribute to a for Improved EMI Performance.
reliable power on startup design with LN3C63. A u Extended Burst Mode Control For Improved
large value resistor could thus be used in the startup Efficiency and Minimum Standby Power Design
circuit to minimize the standby power. The internal u Audio Noise Free Operation
slope compensation improves system large signal u External Programmable PWM Switching
stability and reduces the possible sub-harmonic Frequency
oscillation at high PWM duty cycle output. u Internal Synchronized Slope Compensation
Leading-edge blanking on current sense input u Low VDD Startup Current and Low Operating
removes the signal glitch due to snubber circuit Current
diode reverse recovery and thus greatly reduces the u Leading Edge Blanking on Current Sense Input
external component count and system cost in the u VDD Over Voltage Clamp and Under Voltage
design. LN3C63 offers complete protection Lockout with Hysteresis (UVLO)
coverage with automatic self-recovery feature u Gate Output Maximum Voltage Clamp (18V)
including Cycle-by-Cycle current limiting (OCP), u Line Input Compensated Over Universal Input
over load protection (OLP), VDD over voltage clamp Voltage Range.
and under voltage lockout (UVLO). The Gate-drive u Cycle-by-Cycle Over-current Threshold Setting
output is clamped to maximum 18V to protect the For Constant Output Power Limiting Over
power MOSFET. Excellent EMI performance is Universal Input Voltage Range.
achieved with LIEMIC proprietary Cycle Turning u Overload Protection (OLP)

APPLICATIONS PACKAGE DESCRIPTION

u Offline AC/DC flyback converter Part Description T.R.Rating

u Battery Charger
LN3C63D DIP8 Pb Free 90℃/W
u Power Adaptor
u Set-Top Box Power Supplies LN3C63M SOP8 Pb Free 150℃/W
u Open-frame SMPS LN3C63P SOT23-6 Pb Free 200℃/W

ORDER INFOMANTION
LN3C63 X X
| | |_____ Packing Type: T:TUBE; R:Tape & Reel
| |________ Package Type: D:DIP8; M:SOP8; P:SOT23-6
|______________ LIEMIC N Series AC/DC Controller

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PIN CONFIGURATION

PIN ASSIGNMENTS

Pin Number
Pin Name Function Description
SOP8 & DIP8 SOT23-6
1 6 GATE O Totem-pole drive output for the power MOSFET.
2 5 VDD P Chip DC power supply pin
3 / NC /
Current sense input pin. Connected to MOSFET
4 4 SENSE I
current sensing resistor node.
Internal Oscillator frequency setting pin. A resistor
5 3 RI I connected between RI and GND sets the PWM
frequency.
6 / NC /
Feedback input pin. The PWM duty cycle is
7 2 FB I determined by voltage level into this pin and SENSE
pin input.
8 1 GND P Ground

MARKING INFOMATION

YY: Year Code, 01-99à2001-2099

LN3C63
63YYWW WW: Week Code, 01-52 Week
YYWWZ
Z: Other Information

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ABSOLUTE MAXIMUM RATINGS *

VDD DC Supply Voltage ·························································································································· 28V
VDD Clamp Voltage ································································································································· 28V
VDD DC Clamp Current ························································································································ 10mA
VFB Input Voltage··························································································································· -0.3 to 7V
VSENSE Input Voltage to Sense Pin······························································································· -0.3 to 7V
VRI Input Voltage to RI Pin·············································································································· -0.3 to 7V
Min/Max Operating Junction Temperature TJ ·············································································· -20 to 150℃
Min/Max Storage Temperature Tstg ···························································································· -55 to 160℃
ESD INFORMATION:
HBM Human Body Model ···················································································································2.5KV
MM Machine Model ····························································································································· 200V
Note: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
These are stress ratings only, functional operat ion of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not im plied. Exposure to absolute maximum-rated conditions for ex tended
periods may affect device reliability.

RECOMMENDED OPERATING CONDITION

Symbol Parameter Min Type Max Unit
VDD VDD Supply Voltage 10 25 V
RI RI Resistor Value 100 KΩ
TA Operating Ambient Temperature -20 85 ℃

BLOCK DIAGRAM

VDD

REF
UVLO

S Q
VDD
Driver GATE
R Q

V OC_REF

Line
OC L.E.B. Sense
RI OSC Compensation
VF

Slope
Cycle Compensation
Turning
PWM

OLP

GND Burst
FB
Contraller

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ELECTRICAL CHARACTERISTICS
(TA = 25℃ if not otherwise noted)
Supply Voltage (VDD)

Symbol Parameter Test Conditions Min Typ Max Unit

VDD=12.5V,RI=100K,Measure
IQS VDD Start up Current 3 20 uA
Leakage current into VDD

IQ Operation Current VDD=16V,RI=100KΩ,VFB=3V 1.4 mA

VSTART 7.8 8.8 9.8 V

UVLO Threshold Voltage FB=0
VSTOP 13 14 15 V

VDD_CL VDD Zener Voltage IVDD=10mA 28 V

Feedback Input Section(FB Pin)

Symbol Parameter Test Conditions Min Typ Max Unit

AVCS PWM Input Gain VFB / Vcs 2.0 V/V

VFB VFB Open Loop Voltage VFB=Open 4.8 V

IFB_S FB short current FB=0 0.8 mA

Zero Duty FB Threshold

VTHMIN VDD = 16V,RI=100KΩ 0.75 V
Voltage
Power Limiting FB
VTHMAX VDD = 16V,RI=100KΩ 3.7 V
Threshold Voltage
Power limiting Debounce
TDMAX VDD = 16V,RI=100KΩ 35 mS
Time

ZFB FB Input Impedance 6 KΩ

DMAX Maximum Duty Cycle VDD=18V,RI=100KΩ,FB=3V,CS=0 75 %

Current Sense Input(Sense Pin)

Symbol Parameter Test Conditions Min Typ Max Unit

TLEB Leading edge blanking RI = 100 KΩ 300 nS

ZCS CS Input Impedance 40 KΩ

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TOCP OCP Delay VDD=16V,CS>VTH_OC,FB=3.3V 75 nS

VTHOCP OCP Threshold Voltage FB=3.3V, RI=100 KΩ 0.70 0.75 0.80 V

Oscillator

Symbol Parameter Test Conditions Min Typ Max Unit

Normal Oscillation
FOSC RI = 100 KΩ 60 65 70 kHz
Frequency
Frequency Temperature VDD = 16V,RI=100KΩ, TA=-20℃
ΔFOSC_T 5 %
Stability to 100 ℃
Frequency Voltage
ΔF OSC_V VDD = 12-25V,RI=100KΩ 5 %
Stability

RI Operating RI Range 50 100 150 KΩ

VRI RI open voltage 2 V

Burst Mode Base

FOSC_min VDD = 16V, RI = 100KΩ 22 kHz
Frequency

Gate Drive Output

Symbol Parameter Test Conditions Min Typ Max Unit

VOL Output Low Level VDD = 16V, Io = -20 mA 0.8 V

VOH Output High Level VDD = 16V, Io = 20 mA 10 V

VO_CL Output Clamp Voltage 18 V

T_r Output Rising Time VDD = 16V, CL = 1nF 220 nS

T_f Output Falling Time VDD = 16V, CL = 1nF 70 nS

+
Cycle Turning

Symbol Parameter Test Conditions Min Typ Max Unit

ΔFOSC Cycle Turning range RI=100KΩ -2 +2 kHz

TCT Cycle Turning Time RI=100KΩ 15 mS

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CHARACTERIZATION PLOTS
(VDD = 16V, RI = 100 KΩ, TA = 25℃ condition applies if not otherwise noted.)

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OPERATION DESCRIPTION threshold level. Device enters Burst Mode control.

The LN3C63 is a highly integrated PWM The Gate drive output switches only when VDD
controller IC optimized for offline flyback converter voltage drops below a preset level and FB input is
applications in sub 30W power range. The extended active to output an on state. Otherwise the gate
burst mode control greatly reduces the standby drive remains at off state to minimize the switching
power consumption and helps the design easily loss and reduces the standby power consumption to
meet the international power conservation the greatest extend. The frequency control also
requirements. eliminates the audio noise at any loading conditions.
Startup Current and Start up Control Oscillator Operation
Startup current of LN3C63 is designed to be A resistor connected between RI and GND sets
very low so that VDD could be charged up above the constant current source to charge/discharge the
UVLO threshold level and device starts up quickly. A internal cap and thus the PWM oscillator frequency
large value startup resistor can therefore be used to is determined. The relationship between RI and
minimize the power loss yet provides reliable startup switching frequency follows the below equation
in application. For AC/DC adaptor with universal within the specified RI in Kohm range at nominal
input range design, a 2 M startup resistor could be loading operational condition.
used together with a VDD capacitor to provide a fast
6500
startup and low power dissipation solution. Fosc = （kHz）
RI ( KΩ)
Operating Current
The Operating current of LN3C63 is low at Current Sensing and Leading Edge Blanking
1.4mA. Good efficiency is achieved with LN3C63 Cycle-by-Cycle current limiting is offered in
low operating current together with extended burst LN3C63 current mode PWM control. The switch
mode control features. current is detected by a sense resistor into the
+
Cycle Turning for EMI improvement sense pin. An internal leading edge blanking circuit
+
The Cycle Turning /jittering (switching chops off the sense voltage spike at initial MOSFET
frequency modulation) is implemented in LN3C63. on state due to Snubber diode reverse recovery so
The oscillation frequency is modulated with a that the external RC filtering on sense input is no
random source so that the tone energy is spread out. longer required. The current limit comparator is
The spread spectrum minimizes the conduction disabled and thus cannot turn off the external
band EMI and therefore reduces system design MOSFET during the blanking period. PWM duty
challenge. cycle is determined by the current sense input
Extended Burst Mode Operation voltage and the FB input voltage.
At zero load or light load condition, majority of Internal Synchronized Slope Compensation
the power dissipation in a switching mode power Built-in slope compensation circuit adds voltage
supply is from switching loss on the MOSFET ramp onto the current sense input voltage for PWM
transistor, the core loss of the transformer and the generation. This greatly improves the close loop
loss on the snubber circuit. The magnitude of power stability at CCM and prevents the sub-harmonic
loss is in proportion to the number of switching oscillation and thus reduces the output ripple
events within a fixed period of time. Reducing voltage.
switching events leads to the reduction on the power Gate Drive
loss and thus conserves the energy. LN3C63 self LN3C63 Gate is connected to an external
adjusts the switching mode according to the loading MOSFET gate for power switch control. Too weak
condition. At from no load to light/medium load the gate drive strength results in higher conduction
condition, the FB input drops below burst mode and switch loss of MOSFET while too strong gate

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F r e e D a t a s h e e t
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drive output compromises the EMI. A good tradeoff power limit over the universal input voltage range
is achieved through the built-in totem pole gate with recommended reference design.
design with right output strength and dead time At overload condition when FB input voltage
control. The low idle loss and good EMI system exceeds power limit threshold value for more than
design is easier to achieve with this dedicated TD_PL, control circuit reacts to shut down the output
control scheme. An internal 18V clamp is added for power MOSFET. Device restarts when VDD voltage
MOSFET gate protection at higher than expected drops below UVLO limit.
VDD input. VDD is supplied by transformer auxiliary
Protection Controls winding output. It is clamped when VDD is higher
Good power supply system reliability is than threshold value. The power MOSFET is shut
achieved with its rich protection features including down when VDD drops below UVLO limit and
Cycle-by-Cycle current limiting (OCP), Over Load device enters power on start-up sequence
Protection (OLP) and over voltage clamp, Under thereafter.
Voltage Lockout on VDD (UVLO).
With LIEMIC Proprietary technology, the OCP
threshold tracks PWM Duty cycles and is line
voltage compensated to achieve constant output

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PACKAGE MECHANICAL DATA

SOT23-6

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8-Pin Plastic DIP

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RIGHT TO MAKE CHANGES

LIEMIC Semiconductor Corp. reserves the right to make corrections, modifications, enhancements,
improvements and other changes to its products and ser vices at any time and to discontinue any product or
service without notice. Customers should obtain the latest relevant information before placing orders and
should verify that such information is current and complete.
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LIEMIC Semiconductor Corp. warrants performance of its hardware products to the specifications
applicable at the time of sale in accordance with its standard warranty. Testing and other quality control
techniques are used to the extent it deems necessary to support this warranty. Except where mandated by
government requirements, testing of all parameters of each product is not necessarily performed. LIEMIC
Semiconductor Corp. assumes no liability for application assistance or customer product design. Customers
are responsible for their products and applications using LIEMIC’s components, data sheet and application
notes. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
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