JN RM 2001 Integrated Peripherals API 2v0

Jennic
TECHNOLOGY FOR A CHANGING WORLD
Integrated Peripherals API

Reference Manual
JN-RM-2001
Revision 2.0
13-Feb-2007
Jennic
Disclaimer
The contents of this document are subject to change without notice. Customers are advised to consult with JENNIC commercial representatives before
ordering.
The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended for
incorporation in devices for actual use. Also, JENNIC is unable to assume responsibility for infringement of any patent rights or other rights of third
parties arising from the use of this information or circuit diagrams.
No license is granted by its implication or otherwise under any patent or patent rights of JENNIC Ltd
“Typical” parameters that are provided in this document may vary in different applications and performance may vary over time. All operating
parameters must be validated for each customer application by the customer’s own technical experts.
CAUTION:
Customers considering the use of our products in special applications where failure or abnormal
operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy
controls, vehicle operating controls, medical devices for life support, etc.) are requested to
consult with JENNIC representatives before such use. JENNIC customers using or selling
products incorporating JENNIC IP for use in such applications do so at their own risk and agree
to fully indemnify JENNIC for any damages resulting from such improper use or sale.
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Contents
Disclaimer 2
Contents 3
About this Manual 7
Organisation 7
Conventions 7
Definitions, Acronyms and Abbreviations 8
1 Introduction 9
1.1 Scope 9
1.2 Intended readership 9
2 API Description 10
2.1 General 10
2.1.1 u32AHI_Init 10
2.2 Interrupt Handling 10
2.3 System Control 13
2.3.1 u8AHI_PowerStatus 13
2.3.2 vAHI_MemoryHold 14
2.3.3 vAHI_CpuDoze 14
2.3.4 vAHI_PowerDown 14
2.3.5 vAHI_Sleep (JN513x Only) 15
2.3.6 vAHI_ProtocolPower 15
2.3.7 vAHI_HighPowerModuleEnable (JN513x Only) 15
2.3.8 vAHI_ExternalClockEnable (JN513x Only) 16
2.3.9 vAHI_CPUClockDoublerEnable (JN513x Only) 16
2.3.10 vAHI_AntennaDiversityOutputEnable (JN513x Only) 16
2.3.11 vAHI_SysCtrlRegisterCallback 17
2.3.12 vAHI_SwReset 17
2.4 Wake Timers 18
2.4.1 vAHI_WakeTimerEnable 18
2.4.2 vAHI_WakeTimerStart 18
2.4.3 vAHI_WakeTimerStop 18
2.4.4 u8AHI_WakeTimerStatus 19
2.4.5 u32AHI_WakeTimerCalibrate 19
2.4.6 u8AHI_WakeTimerFiredStatus 19
2.5 Analogue Peripherals 20
2.5.1 vAHI_ApConfigure 20
2.5.2 bAHI_APRegulatorEnabled 21
2.5.3 vAHI_APRegisterCallback 21
2.6 ADC 22
2.6.1 vAHI_AdcEnable 22
2.6.2 vAHI_AdcStartSample 22
2.6.3 bAHI_AdcPoll 23
2.6.4 u16AHI_AdcRead 23
2.6.5 vAHI_AdcDisable 23
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2.7 DACs 24
2.7.1 vAHI_DacEnable 24
2.7.2 bAHI_DacPoll 24
2.7.3 vAHI_DacOutput 25
2.7.4 vAHI_DacDisable 25
2.8 Comparators 26
2.8.1 vAHI_CompEnable 26
2.8.2 vAHI_ComparatorEnable (JN513x Only) 27
2.8.3 vAHI_CompDisable 27
2.8.4 vAHI_CompIntEnable 28
2.8.5 vAHI_CompWakeEnable 28
2.8.6 u8AHI_CompStatus 28
2.8.7 u8AHI_CompWakeStatus 28
2.9 DIO 29
2.9.1 vAHI_DioSetDirection 29
2.9.2 vAHI_DioSetOutput 30
2.9.3 u32AHI_DioReadInput 30
2.9.4 u8AHI_DioSetByte 30
2.9.5 u8AHI_DioReadByte 31
2.9.6 vAHI_DioSetPullup 31
2.9.7 vAHI_DioInterruptEdge 31
2.9.8 vAHI_DioInterruptEnable 32
2.9.9 u32AHI_DioInterruptStatus 32
2.10 UARTs 33
2.10.1 vAHI_UartEnable 33
2.10.2 vAHI_UartDisable 34
2.10.3 vAHI_UartSetClockDivisor 34
2.10.4 vAHI_UartSetControl 35
2.10.5 vAHI_UartSetInterrupt 36
2.10.6 vAHI_UartSetRTSCTS (JN513x Only) 36
2.10.7 vAHI_UartReset 37
2.10.8 u8AHI_UartReadLineStatus 37
2.10.9 u8AHI_UartReadModemStatus 38
2.10.10 u8AHI_UartReadInterruptStatus 38
2.10.11 vAHI_UartWriteData 38
2.10.12 u8AHI_UartReadData 39
2.10.13 vAHI_Uart0RegisterCallback 39
2.10.14 vAHI_Uart1RegisterCallback 39
2.11 Timers 40
2.11.1 vAHI_TimerEnable 40
2.11.2 vAHI_TimerClockSelect 41
2.11.3 vAHI_TimerStartSingleShot 41
2.11.4 vAHI_TimerStartRepeat 42
2.11.5 vAHI_TimerStartDeltaSigma 42
2.11.6 vAHI_TimerStartCapture 43
2.11.7 vAHI_TimerReadCapture 43
2.11.8 vAHI_TimerStop 43
2.11.9 vAHI_TimerDIOControl (JN513x Only) 43
2.11.10 u8AHI_TimerFired 44
2.11.11 vAHI_Timer0RegisterCallback 44
2.11.12 vAHI_Timer1RegisterCallback 44
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2.12 Tick Timer 45
2.12.1 vAHI_TickTimerInit 45
2.12.2 vAHI_TickTimerWrite 45
2.12.3 vAHI_TickTimerIntPendClr 45
2.12.4 bAHI_TickTimerIntStatus 45
2.12.5 vAHI_TickTimerConfigure 46
2.12.6 vAHI_TickTimerIntEnable 46
2.12.7 u32AHI_TickTimerRead 46
2.12.8 vAHI_TickTimerInterval 46
2.13 Serial Peripheral Interface 47
2.13.1 vAHI_SpiConfigure 47
2.13.2 vAHI_SpiReadConfiguration 48
2.13.3 vAHI_SpiRestoreConfiguration 48
2.13.4 vAHI_SpiSelect 48
2.13.5 vAHI_SpiStop 49
2.13.6 vAHI_SpiStartTransfer32 49
2.13.7 u32AHI_SpiReadTransfer32 49
2.13.12 bAHI_SpiPollBusy 50
2.13.13 vAHI_SpiWaitBusy 51
2.13.14 vAHI_SpiRegisterCallback 51
2.14 Serial Interface (2 Wire) 52
2.14.1 vAHI_SiConfigure 52
2.14.2 vAHI_SiSetCmdReg 53
2.14.3 vAHI_SiWriteData8 53
2.14.4 vAHI_SiWriteSlaveAddr 54
2.14.5 u8AHI_SiReadData8 54
2.14.6 bAHI_SiPollBusy 54
2.14.7 bAHI_SiPollTransferInProgress 54
2.14.8 bAHI_SiPollRxNack 55
2.14.9 bAHI_SiPollArbitrationLost 55
2.14.10 vAHI_SiRegisterCallback 55
2.15 Intelligent Peripheral Mode 56
2.15.1 vAHI_IpEnable 56
2.15.2 bAHI_IpSendData 56
2.15.3 bAHI_IpReadData 57
2.15.4 bAHI_IpTxDone 57
2.15.5 bAHI_IpRxDataAvailable 57
2.15.6 vAHI_IpRegisterCallback 57
2.16 Flash 58
2.16.1 bAHI_FlashInit (JN513x Only) 58
2.16.2 bAHI_FlashErase 58
2.16.3 bAHI_FlashEraseSector (JN513x Only) 58
2.16.4 bAHI_FlashProgram 59
2.16.5 bAHI_FullFlashProgram (JN513x Only) 59
2.16.6 bAHI_FlashRead 60
2.16.7 bAHI_FullFlashRead (JN513x Only) 60
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2.17 eFuse (JN513x Only) 61
2.17.1 bAHI_eFuseBlow 61
2.17.2 bAHI_eFuseReadBank 61
References 62
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About this Manual
This manual describes the software Application Programming Interface (API) to the peripheral
devices on the JN5121 and JN513x single-chip IEEE 802.15.4 compliant wireless
microcontrollers. This is known as the Integrated Peripherals API. It details the calls that may
be made through the API in order to set up, control and respond to events generated by the
peripheral blocks, such as UARTs, general-purpose IO lines and timers among others. Setting
up and using power saving modes are also covered.
The software invoked by this API is present in the on-chip ROM. This API does not include
support for the IEEE 802.15.4 MAC hardware built into the device; this hardware is controlled
using the MAC software stack that is built into the on-chip ROM. Readers are recommended to
refer to [1] for further information on the use of this feature.
Note 1: This manual was previously known as the Hardware Peripheral Library Reference
Manual.
Note 2: This manual covers both the JN5121 and JN513x versions of the Integrated Peripherals
API. Some of the API functions described in this manual are for the JN513x only - these are
clearly marked.
Organisation
This document consists of two chapters.
• Chapter 1 gives a brief overview of the scope of the manual
• Chapter 2 describes in detail the calls available to control each feature of the device
Conventions
Code fragments or function prototypes are represented by Courier typeface. When referring
to constants or functions defined in the code they are emboldened, like so.
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Definitions, Acronyms and Abbreviations
ACL Access Control List
ADC Analogue to Digital Converter
AES Advanced Encryption Standard
AHI Application Hardware Interface
API Application Programming Interface
CPU Central Processor Unit
CTS Clear-To-Send
DAC Digital to Analogue Converter
DIO Digital Input Output
FIFO First-In, First-Out queue
MAC Medium Access Control
PAN Personal Area Network
PIB PAN Information Base
PWM Pulse Width Modulation
RAM Random Access Memory
RTS Ready-To-Send
SPI Serial Peripheral Interface
UART Universal Asynchronous Receiver Transmitter
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1 Introduction
1.1 Scope
This document describes the Application Programming Interface (API) for the JN5121/JN513x
hardware peripherals – the Integrated Peripherals API. Its functionality is as follows:
• System Controller
• Wake timers
• Analogue to digital converter (ADC)
• Digital to analogue converters (DACs)
• Comparators
• Digital Input/Output (DIO)
• Universal asynchronous receiver-transmitters (serial ports) (UARTs)
• Timers
• Serial Peripheral Interface (SPI)
• Serial Interface (2 Wire)
• Tick Timer
• External FLASH memory
Note 1: This API was previously known as the Hardware Peripheral Library or the Hardware
API.
Note 2: This manual covers both the JN5121 and JN513x versions of the Integrated Peripherals
API. Some of the API functions described in this manual are for the JN513x only - these are
clearly marked.
This API (sometimes referred to in this document as the AHI) provides a thin layer above the
registers used to control the JN5121/JN513x peripherals, by encapsulating several register
accesses into one function call and hence making it easier to use the peripherals without having
to acquire detailed knowledge of their operation.
This document does not describe the Baseband Controller, Modem or Radio, as these are
driven by the 802.15.4 Stack API, which is always provided with the JN5121 and JN513x
devices. The 802.15.4 Stack API is described in [1].
This document does not describe the API for features found on evaluation kit boards such as
sensors or display panels, although the buttons and LEDs on the evaluation kit boards are
connected to the GPIO pins on the JN5121/JN513x chip. The API for evaluation kit board
features is described in [2].
1.2 Intended readership

It is assumed that the reader has a reasonable knowledge of ‘C’ programming.
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2 API Description
The API is described in terms of the functions it provides, and these are grouped by peripheral.
The functions are defined in AppHardwareApi.h.
Note: There are small differences in the Integrated Peripherals API for the JN5121 and JN513x
chips. Some API functions are for the JN513x only - these are clearly marked in the section
headings.
2.1 General
2.1.1 u32AHI_Init
Declaration PUBLIC uint32 u32AHI_Init(void);
Inputs None
Outputs 0 if initialisation failed, otherwise a 32-bit version number (most significant 16 bits
are main revision, least significant 16 bits are minor revision)
Description Used to initialise the AHI. This should be called after every reset or wake-up and
before any other AHI calls are made. Note that the application API should have
been initialised before this function is called, and the call to initialise the
application API includes a parameter to register a function to call whenever an
interrupt from the peripherals occurs, see following section for details.
2.2 Interrupt Handling

Interrupts from peripheral devices are handled by a set of device-specific callbacks. These can
be set within the Integrated Peripherals API by using the appropriate callback registration
routines. For example the user can write their own UART interrupt handler and then register this
routine using the vAHI_Uart0RegisterCallback function. All device-specific callback functions
registered must have the following prototype:
PRIVATE void vHwDeviceIntCallback(uint32 u32DeviceId, uint32 u32ItemBitmap)
The device ID, u32DeviceId, is an enumerated value indicating the peripheral that generated
the interrupt, as follows:
Enumeration Interrupt Source Callback registration function
E_AHI_DEVICE_TICK_TIMER Tick Timer vAHI_TickTimerInit
E_AHI_DEVICE_SYSCTRL System controller vAHI_SysCtrlRegisterCallback
E_AHI_DEVICE_AES Encryption engine See JN-RM-2013-AES-
Coprocessor-API
E_AHI_DEVICE_UART0 UART 0 vAHI_Uart0RegisterCallback
E_AHI_DEVICE_UART1 UART 1 vAHI_Uart1RegisterCallback
E_AHI_DEVICE_TIMER0 Timer 0 vAHI_Timer0RegisterCallback
E_AHI_DEVICE_TIMER1 Timer 1 vAHI_Timer1RegisterCallback
E_AHI_DEVICE_SPIM SPI master vAHI_SpiRegisterCallback
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E_AHI_DEVICE_SI Serial Interface (2 wire) vAHI_SiRegisterCallback
E_AHI_DEVICE_INTPER Intelligent peripheral vAHI_IpRegisterCallback
E_AHI_DEVICE_ANALOGUE Analogue peripherals vAHI_APRegisterCallback
The item bitmap, u32ItemBitmap, has a bit set for each individual interrupt source within the
peripheral, as described in the tables below.
Before calling the callback function, the library clears the source of the interrupt, so there is no
danger of the same interrupt causing the processor to enter a state of permanently trying to
handle the same interrupt due to a malformed callback function. This also means that it is
possible to have a NULL callback function.
The UARTs are the exception to this rule; when generating a ‘receive data available’ or ‘timeout
indication’ interrupt, the UARTs will only clear the interrupt when the data is read from the UART
receive buffer. It is therefore vital that if UART interrupts are to be enabled, the callback
function handles the ‘receive data available’ and ‘timeout indication’ interrupts by reading the
data from the UART before returning.
Note that if the Application Queue API is being used, the issue with UART interrupts is handled
by the API, so the application does not have to cope with it. See [3] for more information about
the Application Queue API.
The item bitmaps are defined as follows:
TickTimer
Mask (Bit) Description
0 Single source for Tick Timer interrupt, therefore returns 1 every time
System Controller
E_AHI_SYSCTRL_COMP_MASK (29) Comparator events
E_AHI_SYSCTRL_WK1_MASK (27) Wake Timer events
E_AHI_SYSCTRL_WK0_MASK (26)
E_AHI_DIO20_INT (20) Digital IO events
E_AHI_DIO19_INT (19)
E_AHI_DIO18_INT (18)
.
.
E_AHI_DIO0_INT (0)
UART (Item bitmap is identical for both UARTs)

E_AHI_UART_TIMEOUT_MASK (6) Timeout indication
E_AHI_UART_RXLINE_MASK (3) Receive line status
E_AHI_UART_RXDATA_MASK (2) Receive data available
E_AHI_UART_TX_MASK (1) Transmit FIFO empty
E_AHI_UART_MODEM_MASK (0) Modem status
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Timers (Item bitmap is identical for both timers)
E_AHI_TIMER_RISE_MASK (1) Interrupt status, generated on timer rising edge, end of low period - will be
non-zero if interrupt for timer output going high has been set
E_AHI_TIMER_PERIOD_MASK (0) Interrupt status, generated on timer falling edge, end of period - will be
non-zero if interrupt for timer period complete has been set
Serial Interface (2-wire)

E_AHI_SI_RXACK_MASK (7) Asserted if no acknowledge is received from the addressed slave
E_AHI_SI_BUSY_MASK (6) Asserted if a START signal is detected
Cleared if a STOP signal is detected
E_AHI_SI_AL_MASK (5) Asserted to indicate loss of arbitration
E_AHI_SI_ACK_CTRL_MASK (2) Acknowledge control:
0 indicates sent ACK
1 indicates sent NACK
E_AHI_SI_TIP_MASK (1) Asserted to indicate transfer in progress
E_AHI_SI_INT_STATUS_MASK (0) Interrupt status; interrupt indicates loss of arbitration or that byte transfer
has completed
SPI Master
E_AHI_SPIM_TX_MASK (1) Asserted to indicate transfer has completed
Intelligent Peripheral
E_AHI_IP_INT_STATUS_MASK (6) Asserted to indicate transaction has completed, i.e slave select goes high
and TXGO or RXGO has gone low
E_AHI_IP_TXGO_MASK (1) Asserted when TX data is copied to the internal buffer and cleared when it
has been sent out.
E_AHI_IP_RXGO_MASK (0) Asserted when device is ready to receive state and cleared when data RX
is complete.
Analogue Peripherals
E_AHI_AP_INT_STATUS_MASK (0) Asserted to indicate capture complete or new sample ready
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2.3 System Control
The system controller provides control for the CPU and memory power and sleep operation.
There are two significant blocks in the system controller. The 32kHz domain runs from a simple
oscillator and is designed for very low power sleep states. Whilst sleeping, the CPU does not
run and relies on an interrupt to wake it up. The interrupt can be generated externally or from
within the 32kHz domain. Later sections describe the ways in which interrupts can be
generated within the chip, using the wake timers to generate events within the 32kHz domain or
the DIO pins for external stimuli.
The 16MHz domain is used to run the CPU and several peripherals (security engine, ADC,
DACs, UARTs, timers and SPI master) and is used when the chip is fully operational. In this
mode the 32kHz clock still runs and can be calibrated against the 16MHz clock to improve
timing accuracy.
The application is stored in flash memory, and the contents are loaded into RAM when the
device powers up. The RAM is powered by its own regulator, separate from the regulator for
the CPU. This allows the RAM to remain powered when the CPU is asleep and powered down.
This is useful for short sleep periods, when the time taken to re-load the RAM from flash is
significant when compared to the sleep time. Alternatively, for longer sleep periods, the
memory power may be removed as well, reducing the sleep current consumption.
In addition, there are two other power domains, one for analogue peripherals and the other (the
protocol domain) for the modem, encryption coprocessor, radio and baseband controller. The
analogue power domain is switched on if the analogue peripherals are in use.
As well as the normal sleep mode, it is possible to enter a deep sleep. In this state both the
16MHz and 32kHz clock domains are turned off and the device can only be woken by the
device reset line being pulled low.
A final low power mode is doze mode, in which the CPU remains powered but the 16MHz clock
to it is stopped. This uses more power than sleep mode but requires less time to restart. The
CPU is brought out of doze mode by an interrupt (note that a tick timer interrupt cannot be used
to bring the CPU out of doze mode).
2.3.1 u8AHI_PowerStatus
Declaration PUBLIC uint8 u8AHI_PowerStatus(void);
Inputs None
Outputs uint8 containing power domain control settings
bit 0: 1 if chip has completed a sleep-wake up cycle
bit 1: If 1 after wake up, memory contents were retained during sleep
bit 2: 1 if analogue power domain is switched on
bit 3: 1 if protocol power domain is switched on
Description Returns the power domain settings for the JN5121/JN513x, as described above.
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2.3.2 vAHI_MemoryHold
Declaration PUBLIC void vAHI_MemoryHold(bool_t bHoldDuringSleep);
Inputs bool_t TRUE to power memory during sleep

bHoldDuringSleep FALSE to remove power from memory during sleep
Outputs None
Description Determines whether the memory will remain powered during the next sleep
period.
2.3.3 vAHI_CpuDoze
Declaration PUBLIC void vAHI_CpuDoze(void);
Inputs None
Outputs None
Description Causes the CPU to stop operating until an interrupt occurs. The CPU clock will be
disabled during sleep to minimise power consumption, although other modules will
still be operational. The function returns when the CPU re-starts.
2.3.4 vAHI_PowerDown
Declaration PUBLIC void vAHI_PowerDown(bool_t bDeepNotNormalSleep);
Inputs bool_t TRUE for the sleep to be deep sleep (device only
bDeepNotNormalSleep awakes through a reset)
FALSE for normal sleep (device wakes after
interrupt or reset)
Outputs None
Description Sends the device to sleep. In normal sleep mode, all parts of the device are
inactive or powered down apart from the 32 kHz oscillator and those parts of the
system controller used for wake up. In deep sleep, even these are powered
down. This function does not return. When the device restarts, it will begin
processing at the reset vector.
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2.3.5 vAHI_Sleep (JN513x Only)
Declaration PUBLIC void vAHI_Sleep(teAHI_SleepMode sSleepMode);
Inputs teAHI_SleepMode One of:

sSleepMode
E_AHI_SLEEP_OSCON_RAMON
32 kHz oscillator on and RAM on
E_AHI_SLEEP_OSCON_RAMOFF
32 kHz oscillator on and RAM off
E_AHI_SLEEP_OSCOFF_RAMON
32 kHz oscillator off and RAM on
E_AHI_SLEEP_OSCOFF_RAMOFF
32 kHz oscillator off and RAM off
E_AHI_SLEEP_DEEP
Deep sleep (all components off)
Outputs None
Description Sends the JN513x chip to sleep, allowing the 32 kHz oscillator and the RAM to be
individually left on or switched off, as required. When in normal sleep mode, the
device wakes after an interrupt or a reset. When in deep sleep mode, the device
wakes only after a reset. When the JN513x restarts, it will begin processing at the
cold start or warm start entry point. This function does not return.
2.3.6 vAHI_ProtocolPower
Declaration PUBLIC void vAHI_ProtocolPower(bool_t bOnNotOff);
Inputs bool_t bOnNotOff TRUE to turn the protocol power domain on.
FASLE to turn the protocol power domain off.
Outputs None
Description Control the regulator that supplies the protocol domain (the radio, modem
baseband and encryption coprocessor).
2.3.7 vAHI_HighPowerModuleEnable (JN513x Only)

Declaration PUBLIC void vAHI_HighPowerModuleEnable(bool_t bRFTXEn,
bool_t bRFRXEn);
Inputs bool_t bRFTXEn TRUE to enable high power module transmitter

FALSE to disable high power module transmitter
bool_t bRFRXEn TRUE to enable high power module receiver
FALSE to disable high power module receiver
Outputs None
Description Allows the transmitter and receiver sections of a high power module to be
individually enabled or disabled.
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2.3.8 vAHI_ExternalClockEnable (JN513x Only)

Declaration PUBLIC void vAHI_HighPowerModuleEnable(bool_t bExClockEn);
Inputs bool_t bExClockEn TRUE to enable external clock input

FALSE to disable external clock input
Outputs None
Description Enables the use of an external source for the 32 kHz clock.
2.3.9 vAHI_CPUClockDoublerEnable (JN513x Only)

Declaration PUBLIC void vAHI_ClockDoublerEnable(bool_t bClockDoublerEn);
Inputs bool_t bClockDoublerEn TRUE to enable clock doubler

FALSE to disable clock doubler
Outputs None
Description Enables or disables the CPU clock doubler which allows the JN513x CPU, RAM
and ROM to run at twice the normal frequency of the 16 MHz CPU clock – that is,
32 MHz.
2.3.10 vAHI_AntennaDiversityOutputEnable (JN513x Only)

Declaration PUBLIC void vAHI_AntennaDiversityOutputEnable
(bool_t bOddRetryOutEn,
bool_t bEvenRetryOutEn);
Inputs bool_t bOddRetryOutEn TRUE to enable output on DIO12

FALSE to disable output on DIO12
bool_t bEvenRetryOutEn TRUE to enable output on DIO13
FALSE to disable output on DIO13
Outputs None
Description Supports the provision of an alternative antenna in case of a transmission failure.
DIO12 and DIO13 are each associated with an antenna, and are used to indicate
whether a transmission retry on the corresponding antenna is required. When both
DIOs are enabled for this feature, DIO13 goes high for the first transmission. If no
acknowledgement is received, the need for a first retry of the transmission is
indicated by DIO12 going high (DIO13 goes low). If required, a second retry is
indicated by DIO13 going high (DIO12 goes low). Subsequently, all odd numbered
retries are requested using DIO12 and all even numbered retries are requested
using DIO13. The application must choose the antenna for each retry accordingly.
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2.3.11 vAHI_SysCtrlRegisterCallback
Declaration PUBLIC void vAHI_SysCtrlRegisterCallback(PR_HWINT_APPCALLBACK
prSysCtrlCallback);
Inputs PR_HWINT_APPCALLBACK Pointer to function that is to be called when a

prSysCtrlCallback system control interrupt occurs.
Outputs None
Description Registers an application callback that will be called when the system control
interrupt (caused by wake timer, comparator and DIO events) is triggered.
2.3.12 vAHI_SwReset
Declaration PUBLIC void vAHI_SwReset (void);
Inputs None
Outputs None
Description Generates an internal reset when called, which completely re-starts the system.
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2.4 Wake Timers

The wake timers are normally used to time sleep periods and can be programmed to generate
interrupts when the timeout period has completed. However, they can also be used whilst the
CPU is running. There is another set of timers with more functionality that can operate only
whilst the CPU is running; see Section 2.11.
The wake timers run at a nominal 32kHz but to minimise complexity and hence power
consumption, they may run at up to 30% fast or slow depending on temperature, supply voltage
and manufacturing tolerance. A self-calibration facility is provided to time the 32kHz clock
against the 16MHz clock if accurate timing is required.
2.4.1 vAHI_WakeTimerEnable
Declaration PUBLIC void vAHI_WakeTimerEnable(uint8 u8Timer,
bool_t bIntEnable);
Inputs uint8 u8Timer Timer identity:

E_AHI_WAKE_TIMER_0 or
E_AHI_WAKE_TIMER_1
bool_t TRUE to enable interrupt when timer fires
bIntEnable FALSE to disable interrupt
Outputs None
Description Prepares a wake timer for use, enabling the associated interrupt if desired.
2.4.2 vAHI_WakeTimerStart
Declaration PUBLIC void vAHI_WakeTimerStart(uint8 u8Timer, uint32 u32Count);

E_AHI_WAKE_TIMER_1
uint32 u32Count Count time in 32kHz periods, i.e. 32 is 1 millisecond
Outputs None
Description Starts a wake timer to time for the specified interval.
2.4.3 vAHI_WakeTimerStop
Declaration PUBLIC void vAHI_WakeTimerStop(uint8 u8Timer);

E_AHI_WAKE_TIMER_1
Outputs None
Description Stops a wake timer. No interrupt will be generated.
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2.4.4 u8AHI_WakeTimerStatus
Declaration PUBLIC uint8 u8AHI_WakeTimerStatus(void);
Inputs None
Outputs uint8 Bitmap:
Returned value logical ANDed with E_AHI_WAKE_TIMER_MASK_0 will be
non-zero if wake timer 0 is running
non-zero if wake timer 1 is running
Description Returns a bitmap where the relevant bits are set to show which timers are active.
It is possible to have more than one timer active at once. Note that a timer remains
active after the timed interval has completed.
2.4.5 u32AHI_WakeTimerCalibrate
Declaration PUBLIC uint32 u32AHI_WakeTimerCalibrate(void);
Inputs None
Outputs uint32 Returned value shows the calibration offset from the ideal, measured
against the 16MHz clock. The ideal result would be 10000 decimal. A
lower value means that the 32kHz clock is running fast and a higher
value means it is running slow.
Description Performs a calibration of the 32kHz clock against the more accurate 16MHz clock.
The returned value can be used to adjust the time interval values used to program
the wake timers.
Note that the 32kHz clock has a tolerance of +/-30%.
2.4.6 u8AHI_WakeTimerFiredStatus
Declaration PUBLIC uint8 u8AHI_WakeTimerFiredStatus(void);
Inputs None
non-zero if wake timer 0 has fired
non-zero if wake timer 1 has fired
Description Returns a bitmap where the relevant bits are set to show which timers have fired.
Any fired timer status is cleared as a result of this call.
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2.5 Analogue Peripherals
This section refers to shared functionality used by both the ADC, DAC and comparator.
2.5.1 vAHI_ApConfigure
Declaration PUBLIC void vAHI_ApConfigure(bool_t bAPRegulator,
bool_t bIntEnable,
uint8 u8SampleSelect,
uint8 u8ClockDivRatio,
bool_t bRefSelect);
Inputs bool_t bAPRegulator Enable/disable analogue peripheral regulator
E_AHI_AP_REGULATOR_ENABLE
E_AHI_AP_REGULATOR_DISABLE
bool_t bIntEnable Enable/disable interrupt when conversion/capture
completes
E_AHI_AP_INT_ENABLE
E_AHI_AP_INT_DISABLE
uint8 u8SampleSelect Select sample period in divided clock
E_AHI_AP_SAMPLE_2
E_AHI_AP_SAMPLE_4
E_AHI_AP_SAMPLE_6
E_AHI_AP_SAMPLE_8
uint8 u8ClockDivRatio Clock divide ratio
E_AHI_AP_CLOCKDIV_2MHZ
E_AHI_AP_CLOCKDIV_1MHZ
E_AHI_AP_CLOCKDIV_500KHZ
E_AHI_AP_CLOCKDIV_250KHZ
Currently only E_AHI_AP_CLOCKDIV_500KHZ is

recommended
bool_t bRefSelect Select reference voltage
E_AHI_AP_EXTREF
E_AHI_AP_INTREF
Outputs None
Description Allows access to sample period and sampling rate for both ADC and DAC
operations as well as enabling interrupts and selecting reference voltage.
The analogue peripheral regulator also supplies power for comparator
configuration functions.
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2.5.2 bAHI_APRegulatorEnabled
Declaration PUBLIC void bAHI_APRegulatorEnabled();
Inputs None
Outputs bool_t TRUE if powered up, FALSE if still waiting
Description This function should be called after enabling the AP regulator to ensure it has
powered up. When the analogue peripheral regulator is enabled, it will take a little
while to start up. This period varies from 31.25usec – 218.75usec.
2.5.3 vAHI_APRegisterCallback
Declaration PUBLIC void vAHI_APRegisterCallback(PR_HWINT_APPCALLBACK
prApCallback)
Inputs PR_HWINT_APPCALLBACK Pointer to function that is to be called when the

prApCallback Analogue Peripherals interrupt occurs.
Outputs None
Description Registers an application callback that will be called when the Analogue Peripherals
interrupt is triggered.
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2.6 ADC
The ADC provides a single 12-bit analogue-to-digital converter that can be switched between 6
different sources (4 pins on the device, an internal temperature sensor and a battery/power
supply source) and can convert continuously or in single shot mode.
2.6.1 vAHI_AdcEnable
Declaration PUBLIC void vAHI_AdcEnable(bool_t bContinuous,
bool_t bInputRange,
uint8 u8Source);
Inputs bool_t bContinuous Enable/disable continuous conversions

E_AHI_ADC_CONTINUOUS
E_AHI_ADC_SINGLE_SHOT
bool_t bInputRange Set input range to either 0V – Vref or 0V – 2Vref
E_AHI_AP_INPUT_RANGE_2
uint8 u8Source Source for conversions:
E_AHI_ADC_SRC_ADC_1 ADC1 input pin
E_AHI_ADC_SRC_TEMP Temperature sensor
E_AHI_ADC_SRC_VOLT Voltage monitor
Outputs None
Description Enables the ADC and sets the operating mode.
2.6.2 vAHI_AdcStartSample
Declaration PUBLIC void vAHI_AdcStartSample(void);
Inputs None
Outputs None
Description Sets the ADC to start a sample in single shot mode. When complete an interrupt
will be triggered if enabled, otherwise use the bAHI_AdcPoll() routine to poll for
completion.
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2.6.3 bAHI_AdcPoll
Declaration PUBLIC bool_t bAHI_AdcPoll(void);
Inputs None
Outputs bool_t TRUE if busy in single shot mode
Description Determines if ADC is busy performing a conversion
2.6.4 u16AHI_AdcRead
Declaration PUBLIC uint16 u16AHI_AdcRead(void);
Inputs None
Outputs uint16 Most recent ADC conversion result
Description Reads the most recent ADC conversion result. The value is 12 bits wide.
2.6.5 vAHI_AdcDisable
Declaration PUBLIC void vAHI_AdcDisable (void);
Inputs None
Outputs None
Description Disable the ADC.
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2.7 DACs
There are two 11-bit Digital-to-Analogue converters on the JN5121/JN513x. These output to
dedicated pins on the chip.
2.7.1 vAHI_DacEnable
Declaration PUBLIC void vAHI_DacEnable(uint8 u8Dac,
bool_t bInputRange,
bool_t bRetainOutput,
uint16 u16InitialVal);
Inputs uint8 u8Dac DAC identity:

E_AHI_AP_DAC_1 or
E_AHI_AP_DAC_2
bool_t bInputRange Set input range to either 0V – Vref or 0V – 2Vref
bool_t bRetainOutput Retain DAC output for DAC specified
E_AHI_DAC_RETAIN_ENABLE
E_AHI_DAC_RETAIN_DISABLE
uint16 u16InitialVal Initial value to use for conversion - lowest 11bits are
used only
Outputs None
Description Enables a DAC and sets the operating mode.
2.7.2 bAHI_DacPoll
Declaration PUBLIC bool_t bAHI_DacPoll (void);
Inputs None
Outputs bool_t returns TRUE if busy, FALSE when complete
Description Determines if the DAC is busy performing a conversion. A short delay (approx
2μs) after polling and determining the DAC has completed is included to prevent
lockups when further calls are made to the DAC.
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2.7.3 vAHI_DacOutput
Declaration PUBLIC void vAHI_DacOutput(uint8 u8Dac, uint16 u16Value);

E_AHI_AP_DAC_1 or
E_AHI_AP_DAC_2
uint16 u16Value Value to use as output. Lowest 11 bits are valid
Outputs None
Description Sets the value for a DAC to output.
2.7.4 vAHI_DacDisable
Declaration PUBLIC void vAHI_DacDisable (uint8 u8Dac);

E_AHI_AP_DAC_1 or
E_AHI_AP_DAC_2
Outputs None
Description Disable the specified DAC.
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2.8 Comparators
There is one comparator on the JN5121 chip and two comparators on the JN513x chip. A
comparator can be programmed to provide an interrupt when the difference between its inputs
changes sense, and can also be used to wake the chip from sleep. The inputs to the
comparator use dedicated pins on the chip.
Note: If the comparator is to be used to wake the device from sleep mode then the DAC output
option cannot be used as the analogue power domain is turned off when the device enters sleep
mode.
Note: It is necessary to enable the analogue peripheral regulator when configuring the
Comparator, although it can be disabled once configuration is complete.
2.8.1 vAHI_CompEnable
Declaration PUBLIC void vAHI_CompEnable(uint8 u8Hysteresis,
uint8 u8SignalSelect);
Inputs uint8 u8Hysteresis Hysteresis setting, controllable from 0 to +/-20mV:

E_AHI_COMP_HYSTERESIS_0MV
uint8 u8SignalSelect Signal select to compare against comparator '+' pin
E_AHI_COMP_SEL_EXT comparator '-' pin
E_AHI_COMP_SEL_DAC DAC2 output
E_AHI_COMP_SEL_BANDGAP fixed bandgap voltage
Outputs None
Description Enables the comparator and sets the hysteresis setting to use.
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2.8.2 vAHI_ComparatorEnable (JN513x Only)
Declaration PUBLIC void vAHI_ComparatorEnable(uint8 u8Comparator,
uint8 u8Hysteresis,
uint8 u8SignalSelect);
Inputs uint8 u8Comparator Comparator identity:

E_AHI_AP_COMPARATOR_1 or
E_AHI_AP_COMPARATOR_2
uint8 u8Hysteresis Hysteresis setting, controllable from 0 to +/-20mV:
uint8 u8SignalSelect Signal select to compare against comparator '+' pin
E_AHI_COMP_SEL_EXT comparator '-' pin
E_AHI_COMP_SEL_DAC related DAC output
E_AHI_COMP_SEL_BANDGAP fixed bandgap voltage
Outputs None
Description Enables the specified comparator and sets the hysteresis setting to use. Note that
the same hysteresis setting is used for both comparators, so if this function is
called several times for different comparators, only the hysteresis value from the
final call will be used.
2.8.3 vAHI_CompDisable
Declaration PUBLIC void vAHI_CompDisable(void);
Inputs None
Outputs None
Description Disables the specified comparator.
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2.8.4 vAHI_CompIntEnable
Declaration PUBLIC void vAHI_CompIntEnable(bool_t bIntEnable,
bool_t bRisingNotFalling);
Inputs bool_t bIntEnable TRUE to enable interrupt

FALSE to disable interrupt
bool_t TRUE for interrupt on rising edge
bRisingNotFalling FALSE for interrupt on falling edge
Outputs None
Description Enables the interrupt for the comparator, and the edge on which the interrupt is
triggered. The interrupt can be used to wake the device from sleep, and as a
normal interrupt.
2.8.5 vAHI_CompWakeEnable
Declaration PUBLIC void vAHI_CompWakeEnable(bool_t bIntEnable,
bool_t bRisingNotFalling);
Inputs bool_t bIntEnable TRUE to enable interrupt

FALSE to disable interrupt
bool_t bRisingNotFalling TRUE for interrupt on rising edge
FALSE for interrupt on falling edge
Outputs None
Description Enables a changing state on the comparator to be used to wake the device, either
from CPU doze or normal sleep, or to disable this feature.
2.8.6 u8AHI_CompStatus
Declaration PUBLIC uint8 u8AHI_CompStatus(void);
Inputs None
Outputs uint8 Returned value will be non-zero if comparator is ‘high’
Description Returns the status of the comparator. The status is non-zero if one input is higher
than the other and zero if it is lower.
2.8.7 u8AHI_CompWakeStatus
Declaration PUBLIC uint8 u8AHI_CompWakeStatus(void);
Inputs None
Outputs bool_t Returned value will be non-zero if comparator wake-up interrupt has
occurred.
Description Returns the wake-up interrupt status of the comparator. The value is cleared after
reading.
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2.9 DIO
The JN5121/JN513x chip has 21 general purpose digital input/output pins, herein referred to as
DIO pins. In addition to normal operation, when configured as inputs they can be used to
generate interrupts and to wake the device from sleep.
Each DIO pin can be individually configured. However, the DIO pins are shared with other
peripherals and are not available when those peripherals are enabled. These pins are as
follows:
DIO pin Shared with
0 SPI slave select 1
4-7 UART 0
8-10 Timer 0
11-13 Timer 1
14-15 Serial interface
16 IP data in
17-20 UART 1
2.9.1 vAHI_DioSetDirection
Declaration PUBLIC void vAHI_DioSetDirection(uint32 u32Inputs,
uint32 u32Outputs);
Inputs uint32 Bitmask: each of bits 0-20 corresponds to a DIO pin. A bit
u32Inputs set means that the bit will become an input. Bits 21-31 are
ignored.
uint32 Bitmask: each of bits 0-20 corresponds to a DIO pin. A bit
u32Outputs set means that the bit will become an output. Bits 21-31 are
ignored.
Outputs None
Description Sets the direction for DIO pins as either input or output. Not all DIO pins have to
be defined (in other words, u32Inputs logical AND with u32Outputs does not
have to have all of bits 0 to 20 set). Any DIO pins that aren’t defined by a call to
this function will be left in their previous state. If a bit is set in both u32Inputs and
u32Outputs, it will default to becoming an input. If a DIO is assigned to another
peripheral and that peripheral is enabled, this call will not affect that bit.
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2.9.2 vAHI_DioSetOutput
Declaration PUBLIC void vAHI_DioSetOutput(uint32 u32On, uint32 u32Off);
Inputs uint32 u32On Bitmask: each of bits 0-20 corresponds to a DIO pin. A bit
set means that the bit will be set on. Bits 21-31 are ignored.
uint32 u32Off Bitmask: each of bits 0-20 corresponds to a DIO pin. A bit
set means that the bit will be set off. Bits 21-31 are ignored.
Outputs None
Description Sets whether a DIO output is on or off. Not all DIO pins have to be defined (in
other words, u32On logical AND with u32Off does not have to have all of bits 0 to
20 set). Any DIO pins that aren’t defined by a call to this function will be left in
their previous state. If a bit is set in both u32On and u32Off, it will default to being
off. This call has no effect on DIO pins that aren’t defined as outputs (see
vAHI_DioSetDirection()). If a DIO is assigned to another peripheral and that
peripheral is enabled, this call will not affect that bit.
2.9.3 u32AHI_DioReadInput
Declaration PUBLIC uint32 u32AHI_DioReadInput(void);
Inputs None
Outputs uint32 Bitmask: each of bits 0-20 corresponds to a DIO pin. The bit will be set if
the input is high or 0 if the input is low. Bits 21-31 are always 0.
Description Returns the value of each of the DIO input pins. The value is not valid for DIO
pins that are assigned as outputs or which are assigned to another enabled
peripheral.
2.9.4 u8AHI_DioSetByte
Declaration PUBLIC void u8AHI_DioSetByte(bool_t bDIOSelect, uint8
u8DataByte);
Inputs bool bDIOSelect Selects which DIO lines are used to output the byte:
0 selects DIO 0-7
1 selects DIO 8-15
uint8 8DataByte The byte to output on the DIO pins.
Outputs None
Description Outputs a byte on either DIO 0-7 or DIO 8-15.
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2.9.5 u8AHI_DioReadByte
Declaration PUBLIC uint8 u8AHI_DioReadByte(bool_t bDIOSelect);
Inputs bool bDIOSelect Selects which DIO lines are used to read the input byte:
0 selects DIO 0-7
1 selects DIO 8-15
uint8 8DataByte The byte read from DIO 0-7 or DIO 8-15
Outputs None
Description Reads a byte on either DIO 0-7 or DIO 8-15.
2.9.6 vAHI_DioSetPullup
Declaration PUBLIC void vAHI_DioSetPullup(uint32 u32On, uint32 u32Off);
Inputs uint32 u32On Bitmask: each of bits 0-20 corresponds to a DIO pin. A bit
set means that the pull up will be turned on. Bits 21-31 are
ignored.
uint32 u32Off Bitmask: each of bits 0-20 corresponds to a DIO pin. A bit
set means that the pull up will be turned off. Bits 21-31 are
ignored.
Outputs None
Description Sets the pullups on the DIO pins as on or off. These can be set independently of
whether the pins are inputs or outputs.
2.9.7 vAHI_DioInterruptEdge
Declaration PUBLIC void vAHI_DioInterruptEdge (uint32 u32Rising,
uint32 u32Falling);
Inputs uint32 Bitmask: each of bits 0-20 corresponds to a DIO pin. A bit set
u32Rising means that the interrupt will be triggered by a rising edge on
the input. Bits 21-31 are ignored.
uint32 Bitmask: each of bits 0-20 corresponds to a DIO pin. A bit set
u32Falling means that the interrupt will be triggered by a falling edge on
the input. Bits 21-31 are ignored.
Outputs None
Description Sets whether a DIO input, when set to generate an interrupt, will generate it on a
rising or a falling edge. Not all DIO pins have to be defined (in other words,
u32Rising logical AND with u32Falling does not have to have all of bits 0 to 20
set). Any DIO pins that aren’t defined by a call to this function will be left in their
previous state. If a bit is set in both u32Rising and u32Falling, it will default to
rising edge. This call has no effect on DIO pins that aren’t defined as inputs (see
vAHI_DioSetDirection()). If a DIO is assigned to another peripheral and that
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peripheral is enabled, this call will not affect that bit.
2.9.8 vAHI_DioInterruptEnable
Declaration PUBLIC void vAHI_DioInterruptEnable (uint32 u32Enable,
uint32 u32Disable);
Inputs uint32 Bitmask: each of bits 0-20 corresponds to a DIO pin. A bit
u32Enable set means that the interrupt s enabled for that pin. Bits 21-
31 are ignored.
uint32 Bitmask: each of bits 0-20 corresponds to a DIO pin. A bit
u32Disable set means that the interrupt is disabled for that pin. Bits 21-
31 are ignored.
Inputs None
Outputs None
Description Sets whether a DIO input will generate an interrupt. Not all DIO pins have to be
defined (in other words, u32Enable logical AND with u32Disable does not have
to have all of bits 0 to 20 set). Any DIO pins that aren’t defined by a call to this
function will be left in their previous state. If a bit is set in both u32Enable and
u32Disable, it will default to disabling the interrupt. This call has no effect on DIO
pins that aren’t defined as inputs (see vAHI_DioSetDirection()). If a DIO is
assigned to another peripheral and that peripheral is enabled, this call will not
affect that bit.
DIO interrupts can also be used to wake the device from sleep mode.
2.9.9 u32AHI_DioInterruptStatus
Declaration PUBLIC uint32 u32AHI_DioInterruptStatus(void);
Inputs None
Outputs uint32 Bitmask: each of bits 0-20 corresponds to a DIO pin. The bit will be set if
an interrupt associated with the pin has triggered. Bits 21-31 are always
0.
Outputs None
Description Returns the interrupt status of each of the DIO input pins. The value is not valid
for DIO pins that are assigned as outputs or which are assigned to another
enabled peripheral. After reading, the value is cleared.
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2.10 UARTs
There are two 16550-compatible UARTs. Each can be enabled independently. UART0 is also
used for the debugger.
DIO Pins
The UARTs use the DIO pins as follows:
UART 0 UART 1 Function
DIO pin DIO pin
4 17 Clear to send input
5 18 Request to send output
6 19 Transmit data output
7 20 Receive data input
Receive FIFO Interrupt Operation

Receiver interrupts for the UARTs are enabled using vAHI_UartSetInterrupt().
The “receive data available interrupt” is issued when the FIFO reaches its programmed trigger
level. It is cleared as soon as the FIFO drops below its programmed trigger level. The FIFO
trigger level can be set to 1, 4, 8 or 14 bytes using vAHI_UartSetInterrupt().
The function u8AHI_UartReadInterruptStatus() can be used to get the “receive data
available status”. This is set when the FIFO trigger level is reached and, like the interrupt, it is
cleared when the FIFO drops below the trigger level.
When Receiver FIFO interrupts are enabled, timeout interrupts also occur. A FIFO timeout
interrupt will occur if the following conditions exist:
• At least one character is in the FIFO
• No character has entered the FIFO during a time interval in which at least four
characters could potentially have been received
• Nothing has been read from the FIFO during a time interval in which at least four
characters could potentially have been read
When a timeout interrupt occurs, it is cleared and the timer is reset by reading a character from
the receive FIFO.
2.10.1 vAHI_UartEnable
Declaration PUBLIC void vAHI_UartEnable(uint8 u8Uart);
Inputs uint8 u8Uart UART identity: E_AHI_UART_0 or E_AHI_UART_1

Outputs None
Description Enables the specified UART. Note that UART0 uses DIO 4-7 and UART1 uses
DIO 17-20.
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2.10.2 vAHI_UartDisable
Declaration PUBLIC void vAHI_UartDisable(uint8 u8Uart);
Inputs uint8 u8Uart UART identity: E_AHI_UART_0 or E_AHI_UART_1

Outputs None
Description Disables the specified UART.
2.10.3 vAHI_UartSetClockDivisor
Declaration PUBLIC void vAHI_UartSetClockDivisor(uint8 u8Uart,
uint8 u8BaudRate);
Inputs uint8 u8Uart UART identity:

E_AHI_UART_0 or
E_AHI_UART_1
uint8 Desired baud rate:
u8BaudRate E_AHI_UART_RATE_4800
E_AHI_UART_RATE_9600
Outputs None
Description Sets the baud rate for a UART.
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2.10.4 vAHI_UartSetControl
Declaration PUBLIC void vAHI_UartSetControl(uint8 u8Uart,
bool_t bEvenParity,
bool_t bEnableParity,
uint8 u8WordLength,
bool_t bOneStopBit,
bool_t bRtsValue);

E_AHI_UART_0 or
E_AHI_UART_1
bool_t bEvenParity Can take values:
E_AHI_UART_EVEN_PARITY
E_AHI_UART_ODD_PARITY
bool_t bEnableParity Can take values:

E_AHI_UART_PARITY_ENABLE
E_AHI_UART_PARITY_DISABLE
uint8 u8WordLength Can take values:

E_AHI_UART_WORD_LEN_5 Word is 5 bits
bool_t bOneStopBit TRUE for one stop bit, FALSE for 1.5 or 2 stop bits,
depending on word length, enumerated as:
E_AHI_UART_1_STOP_BIT
E_AHI_UART_2_STOP_BITS
bool_t bRtsValue Can take values:

E_AHI_UART_RTS_HIGH
E_AHI_UART_RTS_LOW
Outputs None
Description Sets various control bits for a UART. Note that RTS cannot be controlled
automatically, but only set or cleared under software control.
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2.10.5 vAHI_UartSetInterrupt
Declaration PUBLIC void vAHI_UartSetInterrupt(uint8 u8Uart,
bool_t bEnableModemStatus,
bool_t bEnableRxLineStatus,
bool_t bEnableTxFifoEmpty,
bool_t bEnableRxData,
uint8 u8FifoLevel);

E_AHI_UART_0 or
E_AHI_UART_1
bool_t TRUE to enable modem status interrupt (e.g. CTS
bEnableModemStatus change detected)
bool_t TRUE to enable RX line status interrupt (e.g.
bEnableRxLineStatus framing error, parity error)
bool_t TRUE to enable interrupt when TX FIFO empty
bEnableTxFifoEmpty
bool_t bEnableRxData TRUE to enable interrupt when RX data seen
uint8 u8FifoLevel Number of received words required to trigger an

RX data interrupt. Can take values:
E_AHI_UART_FIFO_LEVEL_1
Outputs None
Description Enables or disables the interrupts generated by a UART, and sets the receive
FIFO level.
2.10.6 vAHI_UartSetRTSCTS (JN513x Only)

Declaration PUBLIC void vAHI_UartSetRTSCTS(uint8 u8Uart,
bool_t bRTSCTSEn);

E_AHI_UART_0 or
E_AHI_UART_1
bool_t bRTSCTSEn TRUE to enable RTS/CTS flow
FALSE to disable RTS/CTS flow
Outputs None
Description Enables or disables RTS/CTS flow on the selected UART.
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2.10.7 vAHI_UartReset
Declaration PUBLIC void vAHI_UartReset(uint8 u8Uart,
bool_t bTxReset,
bool_t bRxReset);

E_AHI_UART_0 or
E_AHI_UART_1
bool_t bTxReset TRUE puts the transmit FIFO into reset
bool_t bRxReset TRUE puts the receive FIFO into reset
Outputs None
Description Resets the transmit and receive FIFOs. The currently transferring character is not
affected. Once put into reset, the FIFOs will remain in reset until a subsequent
call to this function with the resets set to FALSE.
Sets the FIFO trigger level to single byte trigger. FIFO interrupt trigger level can be
set via vAHI_UartSetInterrupt().
2.10.8 u8AHI_UartReadLineStatus
Declaration PUBLIC uint8 u8AHI_UartReadLineStatus(uint8 u8Uart);

E_AHI_UART_0 or
E_AHI_UART_1
E_AHI_UART_LS_ERROR bit will be set if a parity error, framing
error or break indication has been received
E_AHI_UART_LS_TEMT bit will be set if the transmit shift register
is empty
E_AHI_UART_LS_THRE bit will be set if the transmit FIFO is
empty
E_AHI_UART_LS_BI bit will be set if a break indication has been
received (line held low for a whole character)
E_AHI_UART_LS_FE bit will be set if a framing error has been
received
E_AHI_UART_LS_PE bit will be set if a parity error has been
received
E_AHI_UART_LS_OE bit will be set if a receive overrun has
occurred, ie the receive buffer is full but another character
arrives
E_AHI_UART_LS_DR bit will be set if there is data in the receive
FIFO
Description Returns line status information. Note that E_AHI_UART_LS_ERROR,
E_AHI_UART_LS_BI, E_AHI_UART_LS_FE, E_AHI_UART_LS_PE and
E_AHI_UART_LS_OE are cleared after reading.
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2.10.9 u8AHI_UartReadModemStatus
Declaration PUBLIC uint8 u8AHI_UartReadModemStatus(uint8 u8Uart);

E_AHI_UART_0 or
E_AHI_UART_1
Returned value logical ANDed with E_AHI_UART_MS_DCTS will
be non-zero if the CTS input has changed.
Description Returns modem status information.
2.10.10 u8AHI_UartReadInterruptStatus
Declaration PUBLIC uint8 u8AHI_UartReadInterruptStatus(uint8 u8Uart);

E_AHI_UART_0 or
E_AHI_UART_1
Outputs uint8 Bit 0 0 if more interrupts pending, 1 if no more interrupts
pending
Bits1-3 E_AHI_UART_INT_MODEM: Modem status interrupt
E_AHI_UART_INT_TX: Transmit FIFO empty interrupt
E_AHI_UART_INT_RXDATA: RX data available interrupt
E_AHI_UART_INT_RXLINE: RX line status interrupt
E_AHI_UART_INT_TIMEOUT: Timeout interrupt
Description Returns a pending interrupt. Interrupts are returned one at a time, so there may
have to be multiple calls to this function. If interrupts are enabled, the interrupt
handler processes this activity and posts each interrupt to the queue or callback.
2.10.11 vAHI_UartWriteData
Declaration PUBLIC void vAHI_UartWriteData(uint8 u8Uart, uint8 u8Data);

E_AHI_UART_0 or
E_AHI_UART_1
uint8 u8Data Word to transmit
Outputs None
Description Places a word on the transmit FIFO for transmission.
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2.10.12 u8AHI_UartReadData
Declaration PUBLIC uint8 u8AHI_UartReadData(uint8 u8Uart);

E_AHI_UART_0 or
E_AHI_UART_1
Outputs uint8 Received word
Description Returns a single word read from the receive FIFO. If the FIFO is empty the value
is not valid. See u8AHI_UartReadLineStatus() to see how to tell if the FIFO is
empty.
2.10.13 vAHI_Uart0RegisterCallback
Declaration PUBLIC void vAHI_Uart0RegisterCallback(PR_HWINT_APPCALLBACK
prUart0Callback)
Inputs PR_HWINT_APPCALLBACK Pointer to function that is to be called when UART0

prUart0Callback interrupt occurs.
Outputs None
Description Registers an application callback that will be called when the Uart 0 interrupt is
triggered
2.10.14 vAHI_Uart1RegisterCallback
Declaration PUBLIC void vAHI_Uart1RegisterCallback(PR_HWINT_APPCALLBACK
PrUart1Callback)
Inputs PR_HWINT_APPCALLBACK Pointer to function that is to be called when UART1

prUart1Callback interrupt occurs.
Outputs None
Description Registers an application callback that will be called when the Uart 1 interrupt is
triggered
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2.11 Timers
The timers are distinct from the wake timers and can be used both as conventional timers or as
delta-sigma timers to provide a basic DAC function, or can be used to time an input signal. The
timers have a clock select option to choose either the internal 16MHz clock or an external
source. Timer 0 uses DIO 8-10 and timer 1 uses DIO 11-13.
Timer 0 Timer 1 Function
DIO pin DIO pin
8 11 Clock/gate input
9 12 Capture input
10 13 PWM output
2.11.1 vAHI_TimerEnable
Declaration PUBLIC void vAHI_TimerEnable(uint8 u8Timer,
uint8 u8Prescale,
bool_t bIntRiseEnable,
bool_t bIntPeriodEnable,
bool_t bOutputEnable);

E_AHI_TIMER_0 or
E_AHI_TIMER_1
uint8 u8Prescale Prescale value to use with clock
bool_t TRUE to enable interrupts from this timer when the output
bIntRiseEnable goes high
bool_t TRUE to enable interrupts from this timer when the timer
bIntPeriodEnable period has completed and the output goes low
bool_t TRUE to enable the output of the timer to appear on the
bOutputEnable associated PWM output pin
Outputs None
Description Enables a timer and sets parameters for it. The prescale value is used to divide
the clock (see vAHI_TimerClockSelect), the division value being (2u8Prescale),
with a maximum value of 16. Timer 0 uses DIO 8-10 and timer 1 uses DIO 11-13.
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2.11.2 vAHI_TimerClockSelect
Declaration PUBLIC void vAHI_TimerClockSelect(uint8 u8Timer,
bool_t bExternalClock,
bool_t bGateControl);

E_AHI_TIMER_0 or
E_AHI_TIMER_1
bool_t TRUE to use external clock, FALSE to use internal
bExternalClock 16MHz clock
bool_t bGateControl TRUE to gate the output pin when the gate input is high.
FALSE to gate the output pin when the gate input is
low.
Outputs None
Description Sets the clock selection as internal or external clock, and output gating when the
internal clock is used.
2.11.3 vAHI_TimerStartSingleShot
Declaration PUBLIC void vAHI_TimerStartSingleShot(uint8 u8Timer,
uint16 u16Hi,
uint16 u16Lo);

E_AHI_TIMER_0 or
E_AHI_TIMER_1
uint16 u16Hi Number of clock periods after starting a timer before the
output goes high.
uint16 u16Lo Number of clock periods after starting a timer before the
output goes low.
Outputs None
Description Starts a single shot timeout. The output goes low until u16Hi clock periods have
passed, after which it goes high until u16Lo clock periods after the timer was
started. If an interrupt is enabled, it will be triggered at the low-high transition and
again at the high-low transition.
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2.11.4 vAHI_TimerStartRepeat
Declaration PUBLIC void vAHI_TimerStartRepeat(uint8 u8Timer,
uint16 u16Hi,
uint16 u16Lo);

E_AHI_TIMER_0 or
E_AHI_TIMER_1
uint16 u16Hi Number of clock periods after starting a timer before the
output goes high.
uint16 u16Lo Number of clock periods after starting a timer before the
output goes low. Effectively the time period of the whole
cycle.
Outputs None
Description Starts a repeating timer. The output goes low until u16Hi clock periods have
passed, after which it goes high until u16Lo clock periods after the timer was
started. The process repeats until it is stopped (see vAHI_TimerStop). If an
interrupt is enabled, it will be triggered at the low-high transition and again at the
high-low transition.
2.11.5 vAHI_TimerStartDeltaSigma
Declaration PUBLIC void vAHI_TimerStartDeltaSigma(uint8 u8Timer,
uint16 0x0000,
uint16 u16Hi,
bool_t bRtzEnable);

E_AHI_TIMER_0 or E_AHI_TIMER_1
uint16 0x0000 Fixed null value
uint16 u16Hi Number of clock periods during a cycle when the output
will be high
bool_t bRtzEnable TRUE for return-to-zero operation
Outputs None
Description Starts a delta-sigma operation. This is used to emulate a simple DAC if a resistor-
capacitor network is placed between the output DIO pin and ground. The output
will have a fixed frequency of (16 MHz)/216. During an output period, u16Hi
determines the number of 16-MHz clock cycles for which the output is high.
If return-to-zero is enabled, each high bit will be followed by a low bit. This
improves linearity if the rise and fall times of the output are different to one
another.
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2.11.6 vAHI_TimerStartCapture
Declaration PUBLIC void vAHI_TimerStartCapture(uint8 u8Timer);

Outputs None
Description Sets the timer to ‘capture’ mode. In this mode, an incoming signal is timed for
how long it spends low and how long high. These values are placed in registers to
be read later. See vAHI_TimerReadCapture.
2.11.7 vAHI_TimerReadCapture
Declaration PUBLIC void vAHI_TimerReadCapture(uint8 u8Timer,
uint16 *pu16Hi,
uint16 *pu16Lo);

Outputs uint16 *pu16Hi Clock period at which a low-high transition occurred
uint16 *pu16Lo Clock period at which a high-low transition occurred
Description Stops the timer and provides the result from a ‘capture’. The values returned are
offsets from when the capture was originally started, so if trying to capture a
periodic signal it will not be possible to obtain the period if more than one cycle
has occurred.
2.11.8 vAHI_TimerStop
Declaration PUBLIC void vAHI_TimerStop(uint8 u8Timer);

Outputs None
Description Stops the specified timer.
2.11.9 vAHI_TimerDIOControl (JN513x Only)

Declaration PUBLIC void vAHI_TimerDIOControl(uint8 u8Timer,
bool_t bDIOEnable);

bool_t bDIOEnable TRUE to enable the associated DIO
FALSE to disable the associated DIO
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Outputs None
Description Each timer has a DIO associated with it, which the timer can control/observe. This
function enables or disables the DIO (if disabled, the DIO can be used as a
GPIO).
2.11.10 u8AHI_TimerFired
Declaration PUBLIC uint8 u8AHI_TimerFired(uint8 u8Timer);
Inputs uint8 Timer identity:

u8Timer E_AHI_TIMER_0 or E_AHI_TIMER_1
Returned value logical ANDed with E_AHI_TIMER_INT_PERIOD will
be non-zero if interrupt for timer period complete has been set
Returned value logical ANDed with E_AHI_TIMER_INT_RISE will
be non-zero if interrupt for timer output going high has been set
Description Returns interrupt status of timer. Clears interrupt status after reading it.
2.11.11 vAHI_Timer0RegisterCallback
Declaration PUBLIC void vAHI_Timer0RegisterCallback(PR_HWINT_APPCALLBACK
PrTimer0Callback)
Inputs PR_HWINT_APPCALLBACK Pointer to function that is to be called when Timer 0

prTimer0Callback interrupt occurs.
Outputs None
Description Registers an application callback that will be called when Timer 0 interrupt is
triggered.
2.11.12 vAHI_Timer1RegisterCallback
Declaration PUBLIC void vAHI_Timer1RegisterCallback(PR_HWINT_APPCALLBACK
PrTimer1Callback)
Inputs PR_HWINT_APPCALLBACK Pointer to function that is to be called when Timer 1

prTimer1Callback interrupt occurs.
Outputs None
Description Registers an application callback that will be called when Timer 1 interrupt is
triggered.
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2.12 Tick Timer
The JN5121/JN513x contains a hardware timer which can be used for generating timing
interrupts to software. It may be used to implement regular events such as ticks for software
timers or an operating system, as a high-precision timing reference or can be used to implement
system monitor timeouts as used in a watchdog timer.
Note: The tick timer cannot be used to bring the CPU out of doze mode.
2.12.1 vAHI_TickTimerInit
Declaration PUBLIC void vAHI_TickTimerInit(PR_HWINT_APPCALLBACK
prTickTimerCallback);
Inputs PR_HWINT_APPCALLBACK Pointer to interrupt callback routine

prTickTimerCallback
Outputs None
Description Registers a callback with the Tick Timer.
Note: The callback routine will be run under interrupt context and so care must be
taken for it to return to the main program in a timely manner.
2.12.2 vAHI_TickTimerWrite
Declaration PUBLIC void vAHI_TickTimerWrite(uint32 u32Count);
Inputs uint32 u32Count Tick Timer counter value (0 - 0xFFFFFFFF)
Outputs None
Description Set the current value of the Tick Timer counter, can be used to reset the timer to
zero or any other point.
2.12.3 vAHI_TickTimerIntPendClr
Declaration PUBLIC void vAHI_TickTimerIntPendClr(void);
Inputs None
Outputs None
Description Clear any pending Tick Timer interrupt
2.12.4 bAHI_TickTimerIntStatus
Declaration PUBLIC bool_t bAHI_TickTimerIntStatus(void);
Inputs None
Outputs bool_t TRUE if an interrupt is pending, FALSE otherwise
Description Returns the current interrupt status of the Tick Timer
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2.12.5 vAHI_TickTimerConfigure
Declaration PUBLIC void vAHI_TickTimerConfigure(uint8 u8Mode);
Inputs uint8 u8Mode Tick Timer mode:

E_AHI_TICK_TIMER_DISABLE (Disable tick timer)
E_AHI_TICK_TIMER_RESTART (Restart timer when match
occurs)
E_AHI_TICK_TIMER_STOP (Stop timer when match
occurs)
E_AHI_TICK_TIMER_CONT (Timer does not stop when
match occurs)
Outputs None
Description Set the operating mode of the Tick Timer
2.12.6 vAHI_TickTimerIntEnable
Declaration PUBLIC void vAHI_TickTimerIntEnable(bool_t bIntEnable);
Inputs bool_t bIntEnable TRUE to enable the Tick Timer interrupt, FALSE to disable
it
Outputs None
Description Enable/disable Tick Timer interrupt
2.12.7 u32AHI_TickTimerRead
Declaration PUBLIC uint32 u32AHI_TickTimerRead(void);
Inputs None
Outputs uint32 Value of the Tick Timer counter
Description Returns the current value of the Tick Timer counter
2.12.8 vAHI_TickTimerInterval
Declaration PUBLIC void vAHI_TickTimerInterval(uint32 u32Interval);
Inputs uint32 u32Interval Interval measured in 16Mhz clock ticks (0 -

0x0FFFFFFF)
Outputs None
Description Set interval between Timer 'ticks'
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2.13 Serial Peripheral Interface
The SPI master can be used to talk to up to five attached peripherals, including the flash
memory. It can transfer 8, 16 or 32 bits without software intervention and can keep the slave
select lines asserted between transfers when required, to enable longer transfers to be
performed.
As well as dedicated pins for data in, data out, clock and slave select 0, the SPI master can be
configured to enable up to 4 more slave select lines which appear on DIO 0 to 3. Slave select 0
is assumed to be connected to flash memory and is read during the boot sequence.
2.13.1 vAHI_SpiConfigure
Declaration PUBLIC void vAHI_SpiConfigure(uint8 u8SlaveEnable,
bool_t bLsbFirst,
bool_t bTxNegEdge,
bool_t bRxNegEdge,
uint8 u8ClockDivider,
bool_t bInterruptEnable,
bool_t bAutoSlaveSelect);
Inputs uint8 u8SlaveEnable Number of extra SPI slaves to control, valid values are
0 to 4 and higher values are truncated to 4. By default,
there is 1 SPI slave (the flash memory) with a
dedicated IO pin for its select line. Up to four more
select lines can be set, which use DIO pins 0 to 3.
bool_t bLsbFirst TRUE to transfer data in the order that the least
significant bit is transferred first.
bool_t bTxNegEdge TRUE for transmit data to change on the positive edge
of the clock, and therefore to be sampled by the slave
device on the negative edge of the clock.
bool_t bRxNegEdge TRUE for received data to be sampled on the negative
edge of the clock, and therefore to be changed by the
slave device on the positive edge.
uint8 u8ClockDivider The 16-MHz base clock is divided by 2u8ClockDivider
bool_t TRUE to enable interrupt when an SPI transfer has
bInterruptEnable completed.
bool_t TRUE for the programmed slave select line or lines
bAutoSlaveSelect (see vAHI_SpiSelect()) to be automatically asserted
at the start of a transfer and de-asserted when the
transfer completes. FALSE for the slave select lines to
reflect the value set by vAHI_SpiSelect() directly.
Outputs None
Description Enables and sets the SPI master. Depending on how many additional slaves are
enabled, can use DIO pins 0 to 3. For instance, if 2 additional slaves are enabled,
DIO 0 and 1 will be assigned for this.
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2.13.2 vAHI_SpiReadConfiguration
Declaration PUBLIC void vAHI_SpiReadConfiguration(tSpiConfiguration
*ptConfiguration)
Inputs TSpiConfiguration Pointer to SPI configuration data type

*ptConfiguration
Outputs None
Description Reads and returns the current configuration of the SPI bus. To be used on a
system where the SPI bus is used in multiple configurations to enable the state to
be restored after use using the function vAHI_SpiRestoreConfiguration.
2.13.3 vAHI_SpiRestoreConfiguration
Declaration PUBLIC void vAHI_SpiRestoreConfiguration(tSpiConfiguration
*ptConfiguration)
Inputs TSpiConfiguration Pointer to SPI configuration data type

*ptConfiguration
Outputs None
Description Restores the SPI bus configuration using the packed value previously generated
by a call to vAHI_SpiReadConfiguration.
2.13.4 vAHI_SpiSelect
Declaration PUBLIC void vAHI_SpiSelect(uint8 u8SlaveMask);
Inputs uint8 u8SlaveMask Bitmask, one bit per slave select line
Outputs None
Description Sets the active slave select line or lines to use. The slave select lines are asserted
immediately if automatic slave select is disabled, or during transfers otherwise.
The number of valid bits in u8SlaveMask depends on the setting of
u8SlaveEnable in a prior call to vAHI_SpiConfigure(), as follows:
u8SlaveEnable Valid bits in u8SlaveMask
0 Bit 0
1 Bits 0, 1
2 Bits 0, 1, 2
3 Bits 0, 1, 2, 3
4 Bits 0, 1, 2, 3, 4
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2.13.5 vAHI_SpiStop
Declaration PUBLIC void vAHI_SpiStop(void);
Inputs None
Outputs None
Description Clears any active slave select lines. Has the same effect as
vAHI_SpiSelect(0).
2.13.6 vAHI_SpiStartTransfer32
Declaration PUBLIC void vAHI_SpiStartTransfer32(uint32 u32Out);
Inputs uint32 u32Out 32 bits of data to transmit

Outputs None
Description Starts a 32-bit transfer using the SPI master. It is assumed that
vAHI_SpiSelect() has been called to set which slave or slaves to communicate
with. If interrupts are enabled for the SPI master, an interrupt will be generated
when the transfer has completed.
2.13.7 u32AHI_SpiReadTransfer32
Declaration PUBLIC uint32 u32AHI_SpiReadTransfer32(void);
Inputs None
Outputs uint32 Received data
Description Called after a 32-bit SPI transfer has completed, this routine returns the received
data.

Outputs None
Description Starts a 16-bit transfer using the SPI master. It is assumed that
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Inputs None
Outputs uint16 Received data (16 bits)
Description Called after a 16-bit SPI transfer has completed, this routine returns the received
data.

Outputs None
Description Starts an 8-bit transfer using the SPI master. It is assumed that
Inputs None
Outputs uint8 Received data (8 bits)
Description To be called after an 8-bit SPI transfer has completed, this returns the received
data.
2.13.12 bAHI_SpiPollBusy
Declaration PUBLIC bool_t bAHI_SpiPollBusy(void);
Inputs None
Outputs bool_t TRUE if the SPI master is performing a transfer
Description Can be used to poll the SPI master to tell if it is currently busy.
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2.13.13 vAHI_SpiWaitBusy
Declaration PUBLIC void vAHI_SpiWaitBusy(void);
Inputs None
Outputs None
Description Call only returns when the SPI master has completed a transfer.
2.13.14 vAHI_SpiRegisterCallback
Declaration PUBLIC void vAHI_SpiRegisterCallback(PR_HWINT_APPCALLBACK
prSpiCallback)
Inputs PR_HWINT_APPCALLBACK Pointer to function that is to be called when
prSpiCallback SPI master interrupt occurs.
Outputs None
Description Registers an application callback that will be called when the SPI Master interrupt
is triggered.
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2.14 Serial Interface (2 Wire)
The 2-wire serial interface, when enabled, uses DIO 14 as a clock and DIO 15 as a bidirectional
data line. It is logic compatible with similar interfaces such as I2C and SMbus.
2.14.1 vAHI_SiConfigure
Declaration PUBLIC void vAHI_SiConfigure(bool_t bSiEnable,
bool_t bInterruptEnable,
uint16 u16PreScaler);
Inputs bool_t bSiEnable TRUE to enable the interface

bool_t bInterruptEnable TRUE to enable the serial interface interrupt
Outputs uint16 u16PreScaler Clock prescaler 16 bits wide. Operating frequency
is 16 / [(u16PreScaler + 1) * 5] MHz
Description Configures the Serial Interface (2 wire), this function needs to be called before any
other.
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2.14.2 vAHI_SiSetCmdReg
Declaration PUBLIC void vAHI_SiSetCmdReg(bool_t bSetSTA,
bool_t bSetSTO,
bool_t bSetRD,
bool_t bSetWR,
bool_t bSetAckCtrl,
bool_t bSetIACK)
Inputs bool_t bSetSTA Generate START condition

E_AHI_SI_START_BIT
E_AHI_SI_NO_START_BIT
bool_t bSetSTO Generate STOP condition

E_AHI_SI_STOP_BIT
E_AHI_SI_NO_STOP_BIT
bool_t bSetRD Read from slave

E_AHI_SI_SLAVE_READ
E_AHI_SI_NO_SLAVE_READ
bool_t bSetWR Write to slave

E_AHI_SI_SLAVE_WRITE
E_AHI_SI_NO_SLAVE_WRITE
bool_t bSetAckCtrl Acknowledge control:

E_AHI_SI_SEND_ACK
E_AHI_SI_SEND_NACK
bool_t bSetIACK Interrupt Acknowledge, set to clear pending Ack

E_AHI_SI_IRQ_ACK
E_AHI_SI_NO_IRQ_ACK
Outputs None
Description Issue Commands to the interface bus.
2.14.3 vAHI_SiWriteData8
Declaration PUBLIC void vAHI_SiWriteData8(uint8 u8Out);
Inputs uint8 u8Out 8-bit data to transmit

Outputs None
Description Write a single data byte to the TX register of the 2 wire serial interface.
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2.14.4 vAHI_SiWriteSlaveAddr
Declaration PUBLIC void vAHI_SiWriteSlaveAddr(uint8 u8SlaveAddress,
bool_t bReadStatus)
Inputs uint8 u8SlaveAddress 7 bit slave address

bool_t bReadStatus TRUE to set bit0 to 1 indicating a read
FALSE to set bit0 to 0 indicating a write
Outputs None
Description Configures the Serial Interface (2 wire), this function needs to be called before any
other.
2.14.5 u8AHI_SiReadData8
Declaration PUBLIC uint8 u8AHI_SiReadData8(void)
Inputs None
Outputs uint8 Contents of the Rx register
Description Read data sent to us over the Si bus.
2.14.6 bAHI_SiPollBusy
Declaration PUBLIC bool_t bAHI_SiPollBusy(void)
Inputs None
Outputs bool_t TRUE if busy
Description Check to see if the serial interface is busy - could be in use by another master.
2.14.7 bAHI_SiPollTransferInProgress
Declaration PUBLIC bool_t bAHI_SiPollTransferInProgress(void)
Inputs None
Outputs bool_t TRUE if a transfer is in progress
Description Check to see if a transfer is in progress.
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2.14.8 bAHI_SiPollRxNack
Declaration PUBLIC bool_t bAHI_SiPollRxNack(void)
Inputs None
Outputs bool_t TRUE if RX NACK has occurred
FALSE if ACK has occurred correctly
Description Check to see if an NACK has occurred.
2.14.9 bAHI_SiPollArbitrationLost
Declaration PUBLIC bool_t bAHI_SiPollArbitrationLost (void)
Inputs None
Outputs bool_t TRUE if arbitration loss has occurred
Description Check to see if arbitration loss has occurred.
2.14.10 vAHI_SiRegisterCallback
Declaration PUBLIC void vAHI_SiRegisterCallback(PR_HWINT_APPCALLBACK
prSiCallback)
Inputs PR_HWINT_APPCALLBACK Pointer to function that gets called when a Serial

prSiCallback Interface interrupt occurs.
Outputs None
Description Registers an application callback that will be called when the Serial Interface
interrupt is triggered
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2.15 Intelligent Peripheral Mode
The intelligent peripheral interface is a SPI slave interface and uses pins shared with other DIO
signals. The interface is designed to allow message passing and data transfer. Data received
and transmitted on the IP interface is copied directly to and from a dedicated area of memory
without intervention from the CPU. This memory area, the intelligent peripheral memory block,
contains 64 32-bit word receive and transmit buffers.
For more details about the data message format, please refer to the Datasheet (JN-DS-JN5121
or JN-DS-JN513x). The Integrated Peripherals API library calls allow a simple access to the
slave functionality in the JN5121/JN513x device.
2.15.1 vAHI_IpEnable
Declaration PUBLIC void vAHI_IpEnable(bool_t bTxEdge,
bool_t bRxEdge,
bool_t bEndian)
Inputs bool_t bTxEdge Select the clock edge that TX data is sampled on
E_AHI_IP_TXPOS_EDGE (data sampled on +ve edge)
E_AHI_IP_TXNEG_EDGE (data sampled on -ve edge)
bool_t bRxEdge Select the clock edge that RX data is sampled on
E_AHI_IP_RXPOS_EDGE (data sampled on +ve edge)
E_AHI_IP_RXNEG_EDGE (data sampled on -ve edge)
bool_t bEndian Select byte order of data over the IP interface
E_AHI_IP_BIG_ENDIAN data RX/TX format
E_AHI_IP_LITTLE_ENDIAN data RX/TX format
Outputs None
Description Initialise and enable IP mode
2.15.2 bAHI_IpSendData
Declaration PUBLIC bool_t bAHI_IpSendData(uint8 u8Length,
uint8 *pau8Data)
Inputs uint8 u8Length length of data to send (in 32 bit words)

uint8 *pau8Data pointer to data buffer
Outputs bool_t TRUE for success, FALSE for unable to send
Description Copies data to internal TX buffer, ready to be sent when master device initiates
transfer, the IP_INT pin is also asserted to indicate to the master that data is ready
to be sent. Function assumes data in buffer is LSB first (Little Endian) for values
greater than a byte can store.
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2.15.3 bAHI_IpReadData
Declaration PUBLIC bool_t bAHI_IpReadData(uint8 *pu8Length,
uint8 *pau8Data)
Inputs uint8 *pu8Length pointer to write length of data received (in words)
uint8 *pau8Data pointer to buffer to copy data into
Outputs bool_t TRUE for data read, FALSE for unable to read
Description Read data received from SPI Master, data in pau8Data buffer is stored LSB first.
2.15.4 bAHI_IpTxDone
Declaration PUBLIC bool_t bAHI_IpTxDone(void)
Inputs None
Outputs bool_t TRUE if Tx complete FALSE if incomplete

Description Check to see if data copied to TX buffer has been sent to the SPI Master yet.
2.15.5 bAHI_IpRxDataAvailable
Declaration PUBLIC bool_t bAHI_IpRxDataAvailable(void)
Inputs None
Outputs bool_t TRUE if Rx buffer has data FALSE if not

Description Check to see if data has been copied to internal RX buffer by the SPI Master.
2.15.6 vAHI_IpRegisterCallback
Declaration PUBLIC void vAHI_IpRegisterCallback(PR_HWINT_APPCALLBACK
prIpCallback)
Inputs PR_HWINT_APPCALLBACK Pointer to function that is called when an Intelligent

prIpCallback Peripheral interrupt occurs.
Outputs None
Description Registers an application callback that will be called when the Intelligent Peripheral
interrupt is triggered.
The Interrupt is triggered when either a TX or RX transaction has completed
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2.16 Flash
This section describes functions for erasing and programming a sector of a 128-Kbyte Flash
device (in the case of the JN5121, this is the top sector of the M25P10 Flash device).
2.16.1 bAHI_FlashInit (JN513x Only)

Declaration PUBLIC bool_t bAHI_FlashInit(teFlashChipType flashType,
tSPIflashFncTable *pCustomFncTable);
Inputs teFlashChipType The type of Flash device – one of:

flashType
E_FL_CHIP_ST_M25P10_A
E_FL_CHIP_SST_25VF010
E_FL_CHIP_ATMEL_AT25F512
E_FL_CHIP_CUSTOM
tSPIflashFncTable If custom Flash device is used (E_FL_CHIP_CUSTOM),
*pCustomFncTable this is a pointer to the custom function table. If a supported
Flash device is used, set to NULL.
Outputs bool_t TRUE if initialisation was successful
FALSE if initialisation failed
Description Selects the Flash device to be used – one of three supported devices or a custom
device. In the latter case, a custom function table must be supplied.
2.16.2 bAHI_FlashErase
Declaration PUBLIC bool_t bAHI_FlashErase(void);
Inputs None
Outputs bool_t TRUE if sector erase was successful
FALSE if sector erase failed
Description Erases the 32-Kbyte sector of the Flash memory used to store application data, by
setting all bits to 1. Does not affect sectors containing application code.
2.16.3 bAHI_FlashEraseSector (JN513x Only)

Declaration PUBLIC bool_t bAHI_FlashEraseSector(uint8 u8Sector);
Inputs uint8 u8Sector The number of the sector to be erased: integer in range 0
to 3.
Outputs bool_t TRUE if sector erase was successful
FALSE if sector erase failed
Description Erases the specified 32-Kbyte sector of Flash memory by setting all bits to 1. The
Flash device consists of four 32-Kbyte sectors, numbered 0 to 3.
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2.16.4 bAHI_FlashProgram
Declaration PUBLIC bool_t bAHI_FlashProgram(uint16 u16Addr,
uint16 u16Len,
uint8 *pu8Data);
Inputs uint16 u16Addr Address of first Flash memory byte to be programmed

(offset from start of 32-Kbyte block).
uint16 u16Len Number of bytes to be programmed: integer in range 1 to
0x8000.
uint8 *pu8Data Pointer to start of data block to be written.
Outputs bool_t TRUE if write was successful
FALSE if write failed or input parameters were invalid
Description Programs a block of Flash memory by clearing the appropriate bits from 1 to 0.
This mechanism does not allow bits to be set from 0 to 1. It is only possible to set
bits to 1 by erasing the entire sector – therefore, before using this function, you
must call the function bAHI_FlashErase(). The Flash sector allocated to
application data is a continuous block of 32 Kbytes. The address given is an offset
within this area, i.e. it starts at 0.
2.16.5 bAHI_FullFlashProgram (JN513x Only)

Declaration PUBLIC bool_t bAHI_FullFlashProgram(uint32 u32Addr,
uint16 u16Len,
uint8 *pu8Data);
Inputs uint32 u32Addr Address of first Flash memory byte to be programmed.

uint16 u16Len Number of bytes to be programmed: integer in range 1 to
0x8000.
uint8 *pu8Data Pointer to start of data block to be written.
Outputs bool_t TRUE if write was successful
FALSE if write failed or input parameters were invalid
Description Programs a block of Flash by clearing the appropriate bits from 1 to 0. This
mechanism does not allow bits to be set from 0 to 1. It is only possible to set bits
to 1 by erasing the entire sector – therefore, before using this function, you must
call the function bAHI_FlashEraseSector(). The address given is an offset within
this area, i.e. it starts at 0.
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2.16.6 bAHI_FlashRead
Declaration PUBLIC bool_t bAHI_FlashRead(uint16 u16Addr, uint16 u16Len,
uint8 *pu8Data)
Inputs uint16 u16Addr Address of first Flash memory byte to be read (offset from
start of 32-Kbyte block)
uint16 u16Len Number of bytes to be read: integer in range 1 to 0x8000.
uint8 *pu8Data Pointer to start of buffer to receive read data.
Outputs bool_t TRUE if read was successful
FALSE if read failed or input parameters were invalid
Description Reads data from application data area of Flash memory. The Flash sector
allocated to application data is a continuous block of 32 Kbytes. The address
given is an offset within this area, i.e. it starts at 0. The function returns without
reading anything if input values are invalid (e.g. try to read beyond end of sector).
2.16.7 bAHI_FullFlashRead (JN513x Only)

Declaration PUBLIC bool_t bAHI_FullFlashRead(uint32 u32Addr, uint16 u16Len,
uint8 *pu8Data)
Inputs uint16 u32Addr Address of first Flash memory byte to be read

uint16 u16Len Number of bytes to be read: integer in range 1 to 0x8000.
uint8 *pu8Data Pointer to start of buffer to receive read data.
Outputs bool_t TRUE if read was successful
FALSE if read failed or input parameters were invalid
Description Reads data from Flash memory. The function returns without reading anything if
input values are invalid (e.g. try to read beyond end of sector).
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2.17 eFuse (JN513x Only)
The JN513x chip features three eFuse memory banks, numbered 0 to 2. This is a bank of
memory that is only one-time programmable. Individual memory bits are stored in terms of fuses
that can be blown (1) or not blown (0). The following functions allow this memory to be written
(once only) and read.
Note: All fuses are intact before the eFuse bank is programmed – therefore, the bank contains
all binary 0s. The bank is programmed by blowing the fuses that are to represent binary 1s.
2.17.1 bAHI_eFuseBlow
Declaration PUBLIC bool_t bAHI_eFuseBlow(uint8 u8FuseNum,
uint8 u8Bank);
Inputs uint8 u8FuseNum Identifier of fuse: value in range 0 to 127.

uint8 u8bank Identifier of eFuse bank: value in range 0 to 2.
Outputs bool_t TRUE if fuse successfully blown
FALSE if fuse not blown
Description Blows the specified fuse in the specified eFuse bank of the JN513x. A blown fuse
represents the bit value 1.
2.17.2 bAHI_eFuseReadBank
Declaration PUBLIC bool_t bAHI_eFuseReadBank(uint8 u8Bank,
uint32 *pu32Buffer);
Inputs uint8 u8Bank Identifier of eFuse bank: value in range 0 to 2.

uint32 Pointer to 16-byte buffer to receive read data.
*pu32Buffer
Outputs bool_t TRUE if eFuse bank read successfully
FALSE if fuse not blown
Description Reads the specified eFuse bank of the JN513x and places the read data into the
specified buffer.
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References
[1] Jennic 802.15.4 Stack API Reference Manual (JN-RM-2002)
[2] Jennic Board API Reference Manual (JN-RM-2003)
[3] Jennic Application Queue API Reference Manual (JN-RM-2025)
[4] Jennic 802.15.4 Home Sensor Demonstration User Guide (JN-UG-3032)
[5] Jennic ZigBee Home Sensor Demonstration User Guide (JN-UG-3033)
62 © Jennic 2007 JN-RM-2001 (v2.0) 13-Feb-2007

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Revision History
Version Date Description
1.0 12-Sep-2005 Released
1.1 19-Sep-2005 Changes to Analogue Peripherals, Added Tick Timer description
1.2 14-Nov-2005 Correction to sense of parameters txNegEdge and RxNegEdge in SPIconfigure
Correct naming of u32AHI_Init().
Updated document style.
Corrected definition of u8Prescale in vAHI_TimerEnable()
1.3 13-Jan-2006 Minor updates
1.4 13-Jan-2006 Updated for v3 of JN5121
1.5 07-Mar-2006 Correction to vAHI_ApConfigure, and removed DioWake functions
1.6 30-Mar-2006 Added comment about use of tick timer in doze mode plus other minor updates
1.7 06-Jul-2006 Updated template, added interrupt item bitmap descriptions
IP mode added
References to NVRAM changed to LPRAM
vAHI_SwReset() and vAHI_DriveResetOut() added
Resolution and ADC changed
ADC clock Divider changed
References to Comp2 removed
Declaration for vAHI_DioSetPullup corrected
Clarification of some vAHI_SpiConfigure parameters
1.8 24-Jul-2006 Change to table in Section 2.9 “DIO”
1.9 05-Oct-2006 Name of library changed to Integrated Peripherals API.
Mentions of LPRAM and NVRAM removed.
ADC resolution changed.
Description of vAHI_TickTimerInit() modified (does not enable interrupts).
Description of operation of Receive FIFO interrupts for the UARTs added.
Description of vAHI_UartReset() modified.
u8AHI_DioSetByte() and u8AHI_DioReadByte() added.
1.10 09-Nov-2006 Description of vAHI_SiWriteData8() modified.
COMP0 and COMP1 in enumerated values changed to COMP.
2.0 13-Feb-2007 Added JN513x functionality.
Corrected description of function vAHI_TimerStartDeltaSigma().
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Jennic

TECHNOLOGY FOR A CHANGING WORLD

Integrated Peripherals API

2 © Jennic 2007 JN-RM-2001 (v2.0) 13-Feb-2007

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8 © Jennic 2007 JN-RM-2001 (v2.0) 13-Feb-2007

1.2 Intended readership

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2.2 Interrupt Handling

10 © Jennic 2007 JN-RM-2001 (v2.0) 13-Feb-2007

UART (Item bitmap is identical for both UARTs)

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Serial Interface (2-wire)

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Inputs bool_t TRUE to power memory during sleep

14 © Jennic 2007 JN-RM-2001 (v2.0) 13-Feb-2007

Inputs teAHI_SleepMode One of:

2.3.7 vAHI_HighPowerModuleEnable (JN513x Only)

Inputs bool_t bRFTXEn TRUE to enable high power module transmitter

JN-RM-2001 (v2.0) 13-Feb-2007 © Jennic 2007 15

2.3.8 vAHI_ExternalClockEnable (JN513x Only)

Inputs bool_t bExClockEn TRUE to enable external clock input

2.3.9 vAHI_CPUClockDoublerEnable (JN513x Only)

Inputs bool_t bClockDoublerEn TRUE to enable clock doubler

2.3.10 vAHI_AntennaDiversityOutputEnable (JN513x Only)

Inputs bool_t bOddRetryOutEn TRUE to enable output on DIO12

16 © Jennic 2007 JN-RM-2001 (v2.0) 13-Feb-2007

Inputs PR_HWINT_APPCALLBACK Pointer to function that is to be called when a

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2.4 Wake Timers

Inputs uint8 u8Timer Timer identity:

Inputs uint8 u8Timer Timer identity:

Inputs uint8 u8Timer Timer identity:

18 © Jennic 2007 JN-RM-2001 (v2.0) 13-Feb-2007

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Inputs bool_t bAPRegulator Enable/disable analogue peripheral regulator

Currently only E_AHI_AP_CLOCKDIV_500KHZ is

20 © Jennic 2007 JN-RM-2001 (v2.0) 13-Feb-2007

Inputs PR_HWINT_APPCALLBACK Pointer to function that is to be called when the

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Inputs bool_t bContinuous Enable/disable continuous conversions

22 © Jennic 2007 JN-RM-2001 (v2.0) 13-Feb-2007

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Inputs uint8 u8Dac DAC identity:

24 © Jennic 2007 JN-RM-2001 (v2.0) 13-Feb-2007

Inputs uint8 u8Dac DAC identity:

Inputs uint8 u8Dac DAC identity:

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Inputs uint8 u8Hysteresis Hysteresis setting, controllable from 0 to +/-20mV:

26 © Jennic 2007 JN-RM-2001 (v2.0) 13-Feb-2007

Inputs uint8 u8Comparator Comparator identity:

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Inputs bool_t bIntEnable TRUE to enable interrupt

Inputs bool_t bIntEnable TRUE to enable interrupt