VLSI

ms of power considerations for the NOR and NAND circuits. TECHNOLOGY &DESIGN
sansistors are cut off, little power is consumed by either circuit. When When one or both
ucting, static power dissipation cannot be neglected. The NANDgate both are drivers
.aring only one of the four possible input conditions. The NOR gate dissipates
three of the four input states. One advantage of the NOR gate is that power
consumes
power
the during
connected source terminals of
all the drivers are grounded. So source and substrate can be
transistors (enhancement/depletion) the digital circuits can easily be directly usingAlsenMO_
requirement of only one depletion transistor reduces the chip area. Thoughfabricated.
(W/L) of the depletion transistor is more than that of the driver the aspert
not significantly increased. transistors the chip
area is
4.4.3 Transistor Sizing
The size of the device are usually based on the
reference inverter design. The referen oa
inverter for nMOS logic design is the inverter with depletion
mode load. Fig. 4.25 shows the reference inverter and we
will see how the sizing of the driver transistor
Mártver and
the depletion load transistor Mond has been done.
Assuming as usual Vpp=5V,VL=0.25 V
VTload =-3 V, VOH =5V and Vrdrtyer =1V. oVout
The operating voltage of the load with Vout = VoL is VinO
Vos = VpD - VoL =5-0.25 =4.75V. Moriver
Now we see that for the load transistor

Vps> Vcs- VTload Fig. 4.25. Reference inverter

(inverter with depletion load).
So the MOSFET operates in saturation
by
region. The drain current of load device is given

Ips load (VGs- VIload)

Joad
W
(VTioad) ..(158)
Aoad
Using Vcs =0.
Now we calculate the threshold voltage of the
load
Vmld=-3 V, y=0.5 V, 2¢p =0.6 V, K=25 LA/V byas using the substrate effect using
VTload =-3+0.5 (V0.25 +0.6 -N0.6) =-2.93 V.
Substituting in eqn. 158 we have (with Ips load 50 LA)
50 x 10-625x 10-6 W 1
2
Aoad
(-2.93)? 2.15
Aoad
CMOSBASIC CIRCUITS 4.46

Thesize of the driver transistor which is asimple enhancement mode transistor can be
carriedout
If the input Vin= Von=5 Vthen the output is low V VoL =0.25V.
asfollows.
- 0.25 V<5-1 =4= Vcs - Vrdriver (VGs = VoH). So the drain current is
Now Vps=Vo,
and we write
linearregion
Ips driver =k
Ariver
Vcs-VTdriver Vps2
Substitutingthe given values and using Ips driver =50 u A we have
W 0.25
50x 106= 25 x 106| L 5-1-
2
0.25.
Ariver
W 2.06
L Ariver
the sizes calculated above
Sothe reference inverter is chosen with
2.06 and =

1 2.15
driver Joad
must be chosen to ensure that the gate
In logicdesign the size of the various transistors
meetsthe desired logic level and power specification.
load is conducting current when the
Tf we take the case of two input NOR gate the
voltages are exactly the same as the reference
transistor Aor B is conducting alone so the current travelling the same conduction path
inverter. When both A and B are conducting the
and B) simultaneously so the drivers can also be treated as the driver of the
(through A
same that of the
ratio of both the load and the two drivers are
W
reference inverter. So the
is different. Depending on the number
reference inverter. In case of NAND gates the situation path. Though the size of the load device
current has to take the conduction
of inputs the inverter but the size of the driver changes.
remains the same as that of the reference
number of inputs are two the conduction path is through two transistors. If the
If the
is through three transistors and so on.
number of inputs are three then the conduction path
to calculate the size of the driver. This method
We will discuss only the approximate method remnain same and it mnakes the circuit design and
is valid since the size of all the transistors
NAND gate, for both the input
fabrication process a little bit easier. Considering a two-input state. The combined on-resistance
transistors. A and Bconducting, the output is in the low
resistor when conducting). Rm is
willnow be equivalent to 2 Rm (The MOSFET behaves as a
alone. To obtain the low level output
the on-resistance of the individual transistors conductingreference inverter. This is so because
the transistors A and B must be twice as large as the
W That is
on-resistance is inversely proportional to the ratio of the transistor.
L

Vps 1 ..(159)
Ron Ips
VGs- VT driver Vos
2
 4.46 VLSI
TECHNOLOGY &

When Similarly
if the driver transistors
number of inputs is three, then threetransistors will be will be
DESIGN
all the inputs are high then thethree series connected ON and used
as resistors. The on resistance will be 3 Ron and SO e
ratios of the driver behave
Used in three inputs NAND gate will be thrice as the W
ratio of the reference: transistors
inverter.
Example 14. Discuss the sizing of the various transistors in a four input NAND gate
the reference inverter. In the reference inverter the W
ratio of the depletion load
based on
and the
transistor is 3/1
thedriver transistor is 2/1. Also draw the schematic of the gate.
Solution. Afour input NAND gate using depletion load gate can be drawn as in
Fig.E4.6

Fig. E4.6.

When all the transistors are ON then the total on resistance becomes 4R.So if the driver
of the referernce inverter has
Zthent
Jref
of the drivers and in NAND gate will
be

=4
Jref

So the drivers will have the size of 8/1.