Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011)

Non Overlapping Clock Generator for Switched Capacitor Circuits

in Bio-Medical Applications

Ashis Kumar Mal Rishi Todani

Department of ECE Department of ECE
NIT Durgapur NIT Durgapur
Durgapur, INDIA - 713209 Durgapur, INDIA - 713209
[email protected] [email protected]
Telephone: +91-343-2755226

Abstract the key building blocks of an SC circuit. Numerous

techniques for clock generation are proposed in [6]–
Switched capacitor circuits have become a popu- [9]. Standard method for NOC generation is given in
lar method for implementing mixed signal blocks in [3]. The use of transmission gate (TG) between two
standard CMOS technologies. Non-Overlapping Clock inverters to realize more delay is also proposed in [7].
(NOC) generator is a key building block of switched In this paper, it is proposed to use an Inverted In-
capacitor circuits. Standard NOC circuits use simple verter (exchanging the position of NMOS and PMOS)
inverters to realize delays. For high to moderate fre- followed by a static CMOS inverter as an invert-
quencies, the number of inverters required is nominal. ing circuit. The proposed inverter has a larger delay
But for low frequency applications like Bio-Medical because of two primary reasons. Firstly, even when
Signal Processing, the number of inverters increase the input to the inverted inverter is rail to rail, the
drastically affecting the area and power budget. In this output voltage swing is not rail to rail but less by one
work it is proposed to use an inverter in inverted form threshold voltage on both side. Therefore, the effective
along with a simple inverter as an inverting circuit to gate voltage swing of the following inverter is between
realize significant delay with lesser number of tran- VDD −VT n and |VT p |. Since the inverter transistors are
sistors. Simulation results suggest that the proposed not allowed to turn off during the input excursion, the
inverter is area and power efficient. switching delay increases. When input to the proposed
inverter is high (say VDD ), then the input to the inverter
is VDD − VT n . At this point, both, the pull-up and the
Index Terms pull-down paths are active and the NMOS experiences
reduced gate voltage. This reduces the discharging
Non-overlapping clock generator, switched capaci-
current and thus, the delay is more than a static CMOS
tor circuits, bio-medical, inverter delay, delay calcula-
inverter with rail to rail input swing. Similar arguments
tion, CMOS inverter, Mixed signal VLSI, layout
can be made for increased delay during charging or
when the input to the proposed inverter is logic 0.
1. Introduction
2. Signal Swing of Inverted Inverter
Switched capacitor (SC) techniques have become the
default choice for analog and mixed signal design in Ring oscillator using proposed inverter is as shown
CMOS VLSI [1]–[3]. Analog blocks like SC integra- in Fig. 1. We can consider the inverted inverter as
tors, filters and comparators and mixed signal blocks a pass gate where the drain terminal of NMOS is
like analog to digital converters (ADC), sigma delta connected to VDD and a logic high input activates this
modulators and sampled analog architectures [4], [5] gate. Similarly, the drain of PMOS is grounded and
employ SC circuits extensively. SC circuits offer sev- this gate is activated by a logic low input.
eral advantages like high accuracy and low temperature Using the principles of pass transistor logic [10],
invariance. Non overlapping clock generator is one of when the input to this inverted inverter is VDD , the

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Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011)

odd number of proposed inverters

Proposed Inverter Proposed Inverter

out

buffer

Inverted Inverter Inverted Inverter

Inverter Inverter

Figure 1. Ring Oscillator using Proposed Inverter

NMOS pass gate is activated and the output ≈ VDD −

VT n , where VT n represents the threshold voltage of 1.8 Proposed Inverter
Static CMOS Inverter
the inverter with body voltage ≈ VDD −VT n . Similarly 1.6
the output of this inverted inverter ≈ |VT p | when the
1.4
PMOS is activated by a logic low input. Here also,
Output Voltage (V)
|VT p | represents the threshold voltage of the PMOS 1.2

transistor with substrate bias of |VT p | which will be 1

quite higher than |VT p0 |. In a typical 180 nm process, 0.8

with VDD = 1.8 V, and VT n0 = −VT p0 = 0.4 V, the
0.6
output voltage swing of the inverted inverter will be
0.4
around 0.4 V to 1.4 V.
0.2

3. Inverted Inverter and Inverter Cascade 0

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Input Voltage (V)
In this section we qualitatively analyze the behavior
of the proposed inverter circuit. As already discussed Figure 2. VTC of the proposed inverting circuit
earlier, the output voltage swing of the inverted inverter
is less by one threshold voltage on both sides. It
should however be noted that the output swing of the
static CMOS inverter is not affected much even if this Fig.2 shows the VTC of the proposed inverting
degraded logic swing is its input. This is primarily due circuit and static CMOS inverter. The VTC of a static
to the fact that, the static CMOS inverter offers a good CMOS inverter shows that the gain region extends
gain (−dVO /dt > 1) between VIL and VIH . Roughly from 0.503 V to 0.817 V. Thus, the minimum voltage
speaking, this is behavior starts when NMOS is turned that can be regarded logic 0 is 0.503 V and if applied
ON, and lasts up to when PMOS is turned OFF. This to the inverter, an output close to 1.8 V (VDD ) will be
represents the entire input range except from 0 to VT n produced. Similarly, if an input greater than 0.807 V
and VDD − |VT p | to VDD . The regions where the voltage is applied, it will be regarded as logic 1 and output
transfer characteristics (VTC) is flat, the inverter offers close to 0 V will be obtained. Thus, the inverter is
no gain. As a result, the inverter is capable of restoring capable of restoring the output signal swing of inverted
the signal level from |VT p | to VDD − VT n to almost inverter, approximately 0.4 V to 1.4V, to almost rail to
rail to rail. However, such restoration of the signal rail. However, it may be noted that, such restoration of
swing is possible only when the VTC of the inverted logic swing will be difficult if we cascade two inverted
inverter is having a positive slope close to 1. This inverters driving a static CMOS inverter. Using the
is more or less true as the inverted inverter may be theory of pass transistor logic, if output of one gate
viewed as kind of push-pull source follower with a is driving another pass gate, the signal will suffer a dc
gain ≈ 1(Av = 1/(1 + η )). shift of 2VT which will eventually reduce the effective

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Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011)

swing to 2|VT p | to VDD − 2VTn . Thus, combining two

inverted inverter with a static CMOS inverter to intro-
duce more delay will not work as it will reduce the τ pHL = t1 + t2 (5)
logic swing beyond the gain region of the inverter and (4CloadVT n )/kn Cload /kn VDD
= + ln
logic level restoration becomes difficult. (VDD − 2VTn )2 (VDD − 2VTn ) 3VDD − 4VTn
(6)
Cload /kn 4VT n VDD
4. Delay Calculation = + ln
(VDD − 2VTn ) (VDD − 2VTn ) 3VDD − 4VTn
(7)
In this section we will attempt to calculate the delay
[11]–[14] of the proposed inverter and thus try to Similarly, the low-to-high delay is estimated as
estimate the delay of a ring oscillator made using odd
number of such blocks. The delay of the proposed Cload /k p 4|VT p | VDD
inverting circuit is compared to the delays offered by τ pLH = + ln
VDD − 2|VT p | VDD − 2|VT p | 3VDD − 4|VT p |
TG - inverter combination [7] and two cascaded static (8)
CMOS inverter. The delay of the inverter with full logic swing is
compared with the delay of the inverter with degraded
4.1. Inverter Delay input levels. For comparison, the process parameters
given in [15] is used. Analytically it is found that,
τ p (average propagation delay) of normal inverter is
The delay of the inverter is of two types. A high-to- 1.3 ns and that of inverter with weak logic input
low delay (τ pHL ) when output is changing from high is 1.8 ns. Thus, it is concluded that the degraded
to low and a low to high delay (τ pLH ) when output input swing has increased the delay primarily due to
is changing from low to high. The delay expressions the reduced overdrive voltage applied across the gate-
can be found in [10] for rail to rail input and output source terminal of the transistors.
swing. In our case, these equations need modification
as the input voltages applied are either |VT p | for logic
low and VDD − VT n for logic high. 4.2. Delay of Inverted Inverter
When NMOS is in saturation with input VGS =
(VDD −VT n ), load discharges with the following equa- Principles of pass transistor circuits [10] are used
tion. to analyze the behavior of the inverted inverter. When
input of the inverted inverter is high (VDD ), the NMOS
transistor is ON and acts as pass transistor to transfer
VDD−2VT n  the logic high input to the output. Thus, during logic 1
1
t1 = −Cload dVout (1) transfer the charging of the capacitor is done through
iDn NMOS in saturation. To simplify our analysis, we
VDD
(4Cload VT n ) neglect the substrate bias effect at this point. Thus,
= (2)
kn (VDD − 2VTn 2 )

2Cload 0.5VDD dV
τiLH = (9)
It is assumed that VDD − 2VT n > 0.5VDD and the kn VT p (VDD − V − VT n )2
output will discharge further through NMOS transistor 2Cload 1 1
operating in the linear region. Let this interval be t2 so = −
kn 0.5VDD − VT n VDD − |VT p | − VTn
that, (10)

  Where, τiLH is the delay to charge the load capacitor

 DD
0.5V
from |VT p | to 0.5VDD , which represents 50 % point
dVout
t2 = −Cload   of the output swing. However, it may be recalled that
kn (VDD − 2VTn )Vout − 0.5Vout
2
VDD −2VT n |VT p | here should incorporate the effect of substrate
(3) bias. An approximate effect of substrate bias can be
 
Cload /kn VDD incorporated if we consider the average of the threshold
= ln (4)
(VDD − 2VTn ) 3VDD − 4VTn voltage swing due to the source voltage swing.
During logic 0 transfer, it is clear that PMOS tran-
Combining t1 and t2 , the total delay becomes, sistor is ON and NMOS transistor is OFF. Using the

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Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011)

Table 1. Delay Comparision

Proposed Inverter Static CMOS 35

analytical results
Inverter with TG Inverter Simulation results
Transistor Count 4 4 4 30
τ 6.52 ns 181.56 ps 144.23 ps

frequency of Oscillation (MHz)

25

same analogy, the high-to-low delay can be expressed 20

as
 0.5VDD
2C dV 15
τiHL = load (11)
kp VDD −VT n (V − |VT p |)2
10
2Cload 1 1
= −
kp 0.5VDD − |VT p | VDD − |VT n | − |VT p |
5
(12) 4 6 8 10 12 14 16 18 20 22
No. of Stages

Using the 180 nm process parameters [15], the delay

of the inverted inverter is calculated. It is found that Figure 3. Plot for frequency of oscillation for given
τiLH is 2.8 and τiHL is 3.4 ns, the average being 3.1 ns. number of stages
Both the numbers are quite large compared to the static
CMOS inverter. Therefore, it is evident that inverted
inverter combined with static CMOS inverter will offer
more delay than two static CMOS inverters in series.
The delay of the proposed inverter can be calculated 1.8
without buffer
as, with buffer
1.6

τLH (tot) = τ pLH + τiLH (13) 1.4

τHL (tot) = τ pHL + τiHL (14) 1.2
Voltage (V)

1
5. Simulation Results
0.8

Simulation was carried out in Cadence using propri- 0.6

etary 180nm CMOS process.
0.4
Table 1 clearly shows that the proposed inverter
0.2
circuit offers a much larger delay as compared to
cascaded static CMOS inverter and inverter combined 0
0 0.5 1 1.5 2 2.5 3 3.5
with transmission gate. The frequency of oscillation Time (s) x 10
−6

for a ring oscillator is given by

Figure 4. Ring oscillator response with and without
1 buffer
fosc = (15)
2nτ p
where τ p is the average propagation delay and n is the
number of delay stages in series. Fig. 3 depicts the
Table 2. Frequency Comparison of Ring Oscillator
frequency of oscillation when the proposed inverter
is used in a ring oscillator. It can be seen that the Proposed Inverter Static
analytical results follow the simulation results. Table 2 Inverter with TG CMOS Inverter
shows that ring oscillator implemented using proposed Frequency 30.64 MHz 30.77 MHz 30.67 MHz
inverter is area and power efficient as compared to No. of Stages 5 179 453
static CMOS inverter, with or without TG and the os- Trans. Count 20 716 906
cillating waveform is shown in Fig. 4. Table 3 tabulates Pdc 158.7 μ W 5.73 mW 14.5 mW
the frequency of oscillation and power consumption of Pavg 111.5 μ W 99.6 μ W 113.4 μ W
a ring oscillator using different number of stages of the
proposed inverter circuit.

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Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011)

Table 3. Ring Oscillator simulation using

proposed delay block

No. of Stages 5 7 9
Freq. of Oscillation 27.7 MHz 20.82 MHz 16.49 MHz
Transistor Count 24 32 40
Pdc 201.6 μ W 265.1 μ W 328.5 μ W
Pavg 135.3 μ W 150.8 μ W 165.9 μ W

Table 4. Transistor count comparison for NOC

Generation

Non Overlap Proposed Inverter Static

Period Inverter with TG CMOS Inverter
8.03 ns 20 350 440
15.33 ns 28 672 868 Figure 6. Layout of NOC generator used in an
22.53 ns 36 1012 1300 integrator
29.60 ns 44 1340 1730
Table 5. NOC Simulation Using Proposed Inverter

Stages Simulation Results Analytical Results

The benefits in transistor count, which directly rep- 80 272 ns 248 ns
resents area and affects power, to achieve a given
non-overlap period when using the proposed inverter
can be seen in Table 4. Fig. 5 is a plot of transistor 180 x 60 μ m2 . Simulation results are tabulated in
count difference per delay block of NOC generator Table 5.
implemented using static CMOS inverter only and
proposed inverting circuit versus the required non-
6. Conclusion
overlap period. It is evident that as the non-overlap
period requirement increases, the benefits drawn from This paper presents a new inverting circuit based on
this proposed circuit also increases. inverted inverter, which offers more delay as compared
The layout of a NOC generator, shown in Fig. 6, two static CMOS inverters in cascade and even trans-
was designed using proprietary 180 nm CMOS process mission gate - inverter combination. When simulated in
[16], [17]. 84 stages of the proposed block was used a ring oscillator, the proposed inverting circuit is found
in the delay chain which took up an area of around to be area and power efficient. Extensive simulation for
performance comparison is carried out and tabulated.
Finally, an NOC generator is designed to generator two
1800 phase non-overlapping clock and simulation results are
presented.
1600
Transistor count difference per stage

1400
Acknowlwdgements
1200 The authors gracefully acknowledge Dr. Debashis
Datta, Ministry of Communication and Information
1000
Technology, Govt. of India, for extending the SMDP
project at NIT Durgapur. Prof. Anindya Sundar Dhar
800
(E & ECE), IIT Kharagpur is thanked for all kind of
600 support, whenever approached over phone/email. The
present SMDP chair and Head of ECE department at
400
5 10 15 20 25 30
NIT Durgapur is also thanked. Prof. Swapna Banerjee,
Non−Overlap Period (ns) SMDP chair of IIT Kharagpur, and Prof. Qureshi (EE),
IIT Kanpur, are also acknowledged for extending to us
Figure 5. Plot showing area benefits with increase the chip design opportunity. Dr. Pradip Mandal (E &
in non-overlap period ECE), IIT Kharagpur is also thanked for entertaining

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Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011)

us at night in technical discussions. Finally, authors [8] Nicodimus Retdian, Shigetaka Takagi, Nobou Fujii,
express their sincere gratitude to all above for giving “Voltage controlled ring oscillator with wide tuning
us encouragement and time. range and fast voltage swing,” IEEE Asia Pacific Con-
ference on ASIC 2002, November 2002, pp. 201–204.
This paper would not have been possible without
the support of our parents, who allowed us to work [9] Yasuhiro Ogasahara, Masanori Hashimoto,
overnight. Prof. Swapan Bhattacharya, Director, NIT Takao Onoye, “All digital ring oscillator based
Durgapur, is thanked for his encouraging words. Dr. macro for sending synamic supply noise waveform,”
Mal also acknowledges his teachers Late Sri. Kanai IEEE Journal of Solid-State Circuits, vol. 44, no. 6,
June 2006, pp. 1745–1755.
Lal Samui, Prof. R. Saran (IIT Kanpur) and Prof. S. K.
Lahiri (IIT Kharagpur). The authors also acknowledge [10] S. M. Kang, Y. Leblebici, CMOS Digital Integrated
Kanchan Maji, Project Engineer SMDP II, for his Circuits, Analysis and Design, McGraw-Hill Publishing
assistance. Company Limited, 2003.

[11] Saiz-Vela, A., Miribel-Catala, P., Colomer, J., Puig-

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