APPLICATION NOTE

www.onsemi.com

Understanding Power
MOSFET Avalanche
Operation and Associated
UIS (UIL) Data Sheet Ratings
AND90158/D
In the off state, a power MOSFET’s body diode structure avalanche voltage measured at a low avalanche current,
is designed to block a minimum drain to source voltage typically 250 mA or 1 mA, and at junction temperature =
value. The breakdown, or avalanche, of the MOSFET body 25°C. BVdss data over a junction temperature range, or
diode indicates the electric field across the reverse biased BVdss temperature coefficient value, is often provided on
body diode is such that significant current flows between data sheet as well. This is important to note as power
drain and source terminals. Typical blocking state leakage MOSFET avalanche voltage is strong function of both
currents are on the order of tens of picoamperes to hundreds junction temperature and avalanche current. Figure 1 shows
of nanoamperes. In avalanche, MOSFET drain, or source, BVdss values for three temperatures as a function of
currents range from microamperes to hundreds of amperes avalanche current for a 30 V rated device. Table 1 below lists
depending on circuit conditions. The breakdown, or “BV”, range of typical avalanche voltage ranges for different
rating is typically the minimum blocking voltage for the power MOSFET BV ratings−measured at high avalanche
MOSFET device (e.g., 30 V) defined over a given current (amperes) and elevated junction temperatures (at or
temperature range (often the full operating junction near maximum rated junction temperature).
temperature range). The data sheet BVdss value is the device

Figure 1. Avalanche Voltage as Function of Junction Temperature and Avalanche Current for a 30 V Rated
MOSFET Device

© Semiconductor Components Industries, LLC, 2022 1 Publication Order Number:

April, 2022 − Rev. 0 AND90158/D
 AND90158/D

Table 1. Typical Ranges of Avalanche Voltages at Vav = avalanche voltage (Vds). Vav is often not constant
High Tj and High Iav Conditions for Different BV during avalanche (since Iav and Tj change); Vav is usually
Classes the average Vds magnitude measured during time in
Rated DV (V) Vav (V)
avalanche
30 44−47
tav = time in avalanche, typically defined as the time
required for Iav to decrease from Ipk to zero; that is the
40 55−59
time for the energy stored in the inductor to decrease to
60 85−90 zero.
80 115−120 Tj = MOSFFET junction temperature, often simply noted
100 140−150 as the maximum temperature on or near die surface.
Tj (intrinsic) = MOSFET junction temperature where
The power function (avalanche voltage * avalanche device junction becomes a conductor (thermally
current) of a MOSFET operating in avalanche can be of any generated carriers swamp dopant carriers); at this
form. This application note covers a specific avalanche temperature the MOSFET typically fails with
power function that forms the basis of avalanche ratings characteristic of permanent drain to source to gate short.
found on power MOSFET data sheets. MOSFET data sheets energy (E, or sometimes listed as Eav or Eas) = the time
typically specify avalanche ratings under the synonymous integral of the avalanche power function; for a pure
terms “UIS” or “UIL” meaning “Unclamped Inductive triangular function in avalanche, E= 1/2 *Vav*Ipk*tav
Switch−off” or “Unclamped Inductive Load”. That is,
power MOSFET avalanche ratings apply to the resultant
Vds and Id (these terms assume an n−channel MOSFET,
otherwise Vsd and Is for p−channel MOSFET) waveforms
when a MOSFET driving an unclamped load is switched off.
Figure 2 shows the basic circuit and Figure 3 shows device
waveforms. Going forward we continue to assume a
n−channel MOSFET and define terms as:
Iav = avalanche current
Ipk = maximum avalanche current= value when
MOSFET is switched off
Ipk (fail) = maximum avalanche current when MOSFET
fails (drain to source to gate short) Figure 2. Basic Unclamped Inductive Switch Off
Circuit. DUT (Device Under Test) is Power
Jpk, Jpk (fail): Ipk value scaled to die active area, in units
MOSFET Device. Triangle Form Represents
A/area2
Gate Drive Circuit.
Die active area: area of MOSFET die containing active
MOSFET structures; some percentage of total die area

Figure 3. Unclamped Inductive Switch−off Waveforms for MOSFET DUT. Energy Function is the Integral of
the Power Function.

www.onsemi.com
2
 AND90158/D

Power MOSFETs configured in high−side configuration short circuit faults (often very high Ipk and low tav), and
(see Figure 4) can avalanche, depending on gate drive switch node overshoot in converter and inverter topologies.
conditions. If the gate driver at switch−off brings the gate Avalanche events on MOSFETs can also result from
and source potentials together so that Vgs << Vth, then the transients on the supply line (for example alternator load
source potential can drop to the necessary negative value for dump); avalanche operation does not necessarily require
the device to avalanche. However, if the gate drive at switch−off of unclamped inductive loads. However, UIS
switch−off brings the gate potential to zero, the source (UIL) data found in power MOSFET data sheets can often
potential can decrease to a negative value only to the point be useful to evaluate these avalanche events, depending on
where the device turns back on. That is, Vgs becomes the composition of the avalanche power function.
positive and reaches the value necessary for avalanche In general, MOSFET UIS capability is determined by
current to flow while the device is in saturation (typically subjecting device samples to avalanche pulses until failure.
slightly greater than Vth, depending on Iav magnitude and Most often, a fixed inductor value is selected and peak
device gain). In this case the MOSFET is operating in current thru the inductor is incremented until the DUT
saturation during the time in clamp (as the inductor stored (device under test) fails (characterized by a drain to source
energy decreases to zero). This “self−active” clamp to gate short). Sufficient time is allowed between each Ipk
operation mode affords a potential issue, thermal runaway, increment to ensure the DUT junction temperature returns
a subject not covered in this application note. to initial conditions prior to next avalanche pulse. Initial
junction temperature is controlled either by oven, forced air,
or heater block. Generally, UIS data is collected at Tj(initial)
= 25 °C, and at least one elevated initial junction temperature
(e.g., 100 °C). The test circuit can be configured so that the
DUT is either used to ramp current the inductor load or
connected as diode (Vgs= 0 V) and a higher avalanche
switch is used to ramp and switch−off inductor current.
Compare the circuits in Figure 5. There are two potential
issues to consider when using the DUT as the MOSFET
switch to ramp current into the conductor. First, during the
time the current increases to Ipk the MOSFET DUT is
Figure 4. Basic High−side Configured Unclamped
dissipating power (typically = I2*Rds(on)) so the device can
Inductive Load Switch−off Circuit self−heat thereby increasing Tj(initial) at switch−off. This
can be mitigated by ensuring sufficient Vgs gate voltage to
Most applications do not switch−off MOSFETs to reduce Rds(on) and using as high as possible supply voltage
unclamped loads by design. However, there are some in order to minimize time required to reach Ipk (time from
applications that by design do switch unclamped inductive 0 A to Ipk = L*Ipk/Vsupply). The second issue is gate drive
loads. Examples include some fuel injection systems, ABS sink capability during switch−off. If the device is switched
dump coils, and low cost, low power solenoid loads where off slowly, some of the stored inductor energy is dissipated
cost of clamping diode can be eliminated. More often, in the switching transition. If switched off slowly enough,
application avalanche issues and possible resultant device avalanche can be avoided. In general, power MOSFET data
failures result from switch−off of unclamped stray sheet UIS specifications assume a hard switch−off event,
inductances of PCB traces and cable wiring, ESL of resistors ensuring nearly all the inductor stored energy is dissipated
and capacitors, and package interconnect inductance of by the MOSFET in avalanche operation.
transistors and diodes. Examples include switch−off from

Figure 5. Left Circuit is Basic Self−driven UIS Test Circuit. Right Circuit is Test Circuit where DUT is
configured as Diode and Secondary Switch (SW) controls Inductor Current. Vav (SW) >> Vav (DUT).

www.onsemi.com
3
 AND90158/D

The UIS data collected is a set of Ipk(fail) and associated importance and insight regarding power MOSFET UIS
tav operating points for several different inductor values. capability being a thermal base failure is discussed later.
From this data set, an Ipk(fail) vs tav curve, for a given The Ipk(fail) versus tav data is de−rated to generate the
Tj(initial) is generated (see Figure 6). The data should fit data sheet plot, which may be considered a SOA (safe
well to a power function of the form Ipk = A*tav-a, where operating area) for power MOSFET unclamped inductive
A is a constant and the a exponent magnitude is usually on switch−off avalanche operation (see Figure 7). If the
the order of 0.5. This is significant because it indicates a application Ipk and tav operating point is below the Ipk vs
likelihood that the Ipk fail operating points represent tav curve and the initial Tj for the curve, then the device is
thermal based failures. The power function Ipk = A*tav-a safe to operate. From a thermal perspective this could be
can be rewritten as A(1/a) = Ipk (1/a) *tav. If a = 0.5, we get done for any number of avalanche pulses if each pulse
the result Ipk2*tav = constant. This is a typical expression begins at a junction temperature state at or below the stated
for modeling mechanical fuse (those that open due to Tj(initial) value. However repetitive avalanche pulses may
material reaching melting point) current and time to open result in MOSFET parameter shifts due to a HCI (hot carrier
(melt) characteristics. In this sense, the power function Ipk injection) mechanism depending on device technology and
= A*Ipk−a can indicate a thermal failure mechanism. The operating conditions. Repetitive avalanche is discussed later
in this application note.

Figure 6. Ipk(fail) Data as Function of Time in Avalanche at Two Initial Junction Temperatures

www.onsemi.com
4
 AND90158/D

Figure 7. Ipk(fail) vs tav Data of Figure 6 De−rated to Form Data Sheet Ipk vs tav SOA Plot

To de−rate the Ipk(fail) data, the Ipk (fail) value is lowered energy ratings, if one measured with an infinitely small
to some percentage (X) of original value, and tav is adjusted inductor (tav approaches zero) and infinitely large inductor
for the new Ipk value for the inductance value used in the (tav approaches infinity). The energy dissipated in UIS
measurement of Ipk(fail). Adjusted tav is given by: avalanche pulse for a power MOSFET increases as tav
tav(de−rated) = L*Ipk(fail)*X/Vav. The de−rated Ipk increases. (see Figure 8). Any single UIS avalanche rating
function is given by Ipk = B*tav-a, where the new de−rated can be taken as any Ipk, tav operating point that lies on the
coefficient, B, can be calculated from: B= A*X*(1/X)−a, Ipk vs tav SOA curve, for some given Tj(initial) value.
where X is the de−rating percentage. The X value is Some reasons why one operating point is selected over
generally conservative and may range from approximately another for a data sheet “maximum” rating include selection
50 % −75 % across the industry. of operating point as the same used to screen the device at
In addition to the Ipk vs tav plot, most power MOSFET end of line test, or for marketing or customer purposes to
data sheets include a single UIS energy rating, often listed indicate some desired energy level. The key point, when
in the table of maximum values. This is a bit misleading, as comparing one device UIS capability to another, is to
it should be obvious (E= 0.5 Vav*Ipk*tav) that a power compare the Ipk vs tav plot data at the same Tj(initial)
MOSFET can theoretically have an infinite number of temperature and not compare single UIS rating values.

www.onsemi.com
5
 AND90158/D

Figure 8. Data from Figure 7 Data Translated to Energy as Function of Time in Avalanche. UIS Energy
Increase as tav Increases.

Several design and associated wafer processing attributes A/mm2, which is the Ipk(fail) value divided by the device
are utilized to affect power MOSFET UIS capability. Chief active area for individual MOSFET samples. This affords
among these is design and processing of the source metal the ability to include Ipk(fail) vs tav data from any number
contact (which is discussed later) but discussion of these of different MOSFET samples with different die active areas
attributes is not necessary to understand the main goal for (in this case ranging from ~ 1 mm2 to 13 mm2). Moreover,
any power MOSFET design, regarding UIS capability, is to Figure 9 shows data for three significantly different 60 V
ensure the device fails thermally. That is the energy MOSFET technologies each with similar avalanche voltage
dissipated in the device due to avalanche operation is limited characteristics. It is clear from this data that these different
only by the thermal capability of the device for that specific MOSFET technologies with similar avalanche voltage
power function. MOSFET devices of similar BV characteristics exhibit the same UIS capability scaled to die
characteristics (that is same or similar avalanche voltage) active area (or to be more accurate, active die volume).
and of similar thermal capability will have similar UIS Figure 10 displays Jpk(fail data as a function of time in
capability. Since typical UIS avalanche times in real world avalanche for three different sets of data representing three
applications (and listed on data sheet plots) are usually less different BV ratings. Figure 10 illustrates that a lower BV
than one millisecond, and therefore heat flow is not rated (lower Vav) device has increased Jpk capability at a
appreciably affected by external thermal boundary given time in avalanche compared to higher BV devices.
conditions; the primary thermal constraint is MOSFET die However, if the data from Figure 10 are plotted in terms of
active area and thickness. Therefore, it is expected that Ipk energy (fail) density (in J/mm2), it shows energy density
(fail) capability as a function of tav should scale to die active approximately follows the same function regardless of
area within a MOSFET technology and within similar technology and BV rating, further supporting the position
technologies. In fact, this is shown to be true, see Figure 9. that MOSFET UIS capability is scalable to active die active
The y−axis of Figure 9 is labeled as Jpk(fail), in units of volume (see Figure 11).

www.onsemi.com
6
 AND90158/D

Figure 9. Peak Avalanche Current Density at Failure as Function of tav Data for Three Different 60 V Rated
MOSFET Technologies

Figure 10. Peak Avalanche Current Density at Fail vs tav Data for Multiple MOSFET Technologies at Three
Different BV Ratings

www.onsemi.com
7
 AND90158/D

Figure 11. Energy Density at Failure vs tav Data Calculated from Figure 10 Data. This Energy Density
Function is approximately the same for any BV Rated Product.

There is an exception to the position that MOSFET UIS resulting in rapid device failure. The key is to realize that the
capability is limited only by thermal capability of the p−doped region has some resistance level and therefore at
MOSFET device for any condition. At higher avalanche some avalanche current density the p−n junction will
current densities, the MOSFET device can fail well below forward bias so that that npn transistor is activated.
an expected thermal based Jpk(fail) value. That is the Ipk vs Figure 13 shows Jpk(fail) data at low avalanche times
tav plot on a data sheet cannot be extrapolated ad infinitum compared to greater avalanche times where device Jpk
to higher Ipk and lower tav values. The reason for this is failures are clearly intrinsic thermal based. Thus, any power
illustrated in Figure 12. The p-doped region, n−doped source MOSFET must have a maximum limit to peak avalanche
region, and the n−doped drift (epi) region of the MOSFET current. This is true even if a data sheet does not list or show
structure form a npn transistor. The base to emitter junction a maximum UIS Ipk value. The maximum Ipk limitation in
of this npn transistor, formed by the p−doped region and the avalanche may be an issue in applications designed to
n−doped source region is shorted by the front metal. shut−off from very high magnitude short circuit currents.
Therefore, the source metal contact is a key design and MOSFETs can fail in avalanche at shutoff due to small stray
process parameter for MOSFET UIS capability. If the npn inductance in PCB or supply line wiring even though the
is activated, because the base to emitter is forward biased, avalanche energy is significantly below that necessary for
significant avalanche current will crowd at the defect site intrinsic thermal failure.

www.onsemi.com
8
 AND90158/D

Figure 12. Simplified Cross Section Drawing of Shielded Gate MOSFET Structure showing Internal npn BJT
Structure. Dashed Arrows represent Avalanche Current.

Figure 13. Peak Avalanche Current Density vs. tav for 40 V Rated Product showing Non Thermal Failures
at Low Avalanche Times and High Peak Current Density

www.onsemi.com
9
 AND90158/D

A power MOSFET may be operated in avalanche Usually, BVdss parameter shift occurs and stabilizes with
repeatedly, provided each avalanche event is within safe the first few hundred to thousand repetitive avalanche
operating limits (Ipk, tav, Tj(initial)). That said, trench based cycles, but the delta magnitude is typically less than ±3 V,
MOSFET technologies (predominate in industry today) can which in most cases does not present an application issue.
exhibit DC parameter shifts due to repetitive avalanche Idss can increase significantly (from nanoampere range to
operation due to an effect akin to hot carrier injection. single microampere range) over millions to hundreds of
Figure 14 illustrates this; during avalanche there maybe millions of repetitive avalanche cycles. Mobility in the
high current density in the drift (n−epi) region which is under channel can be affected by repetitive avalanche HCI effects,
high electric field (the drift or mesa, region is fully depleted). resulting in Rds(on) increase at the same time Vth decreases,
In trench structures the gate and shield oxides are adjacent again over millions to hundreds of millions of repetitive
to the high current avalanche current flow, and the high avalanche cycles. Whether these parameters change
electric field can knock charge carriers into the gate and significantly or not and by how much depends on the
shield oxides, depending on operating conditions. This is not repetitive avalanche operating conditions (average and peak
the case for planar technology structure during avalanche junction temperature, change in junction temperature,
operation. In general, planar MOSFET structures are avalanche current density, time in avalanche, and number of
immune to repetitive avalanche HCI effects. avalanche cycles). In general, these parameter shifts do not
The MOSFET DC parameters affected by repetitive result in physical device failure, but obviously parameter
avalanche HCI effects include BVdss (avalanche voltage), shifts of the right type, magnitude, and direction can
Idss (off −state drain to source leakage current), Vth (gate to possibly result in end application issues. Figure 15 displays
source threshold voltage), and Rds(on) (on−state drain to examples of parameter shift data (delta from initial
source resistance). Igss (off−state gate to source leakage measurement) for trench MOSFET technology device
current) is not affected by repetitive avalanche operation. operated in repetitive avalanche conditions.

Figure 14. Simplified Cross Section Diagrams of a Planar MOSFET Structure (left) and a Shielded Gate
MOSFET Structure (right). Dashed Lines represent Avalanche Current Flow.

www.onsemi.com
10
 AND90158/D

Figure 15. DC Parameter Shift as Function of Repetitive Avalanche Cycles Data for a Trench Technology MOSFET

The key point regarding power MOSFET avalanche UIS (UIL) is a specific form of MOSFET avalanche
operation is there is no defined method to specify power operation, resultant from switch−off of an unclamped
MOSFET repetitive avalanche capability ratings. Any inductive load. Power MOSFETs are designed and
repetitive avalanche rating found on a data sheet should manufactured so the UIS avalanche operation is limited only
include operating condition assumptions and define the by device thermal capability or by maximum peak
methodology to determine the functional capability limit avalanche current density. Power MOSFET UIS capability
(e.g., number of cycles to reach some percentage change in is best presented by the Ipk as a function of tav SOA plot.
some DC parameter). As a general design rule, repetitive Single UIS energy ratings should not be compared between
avalanche operation should be avoided, as preferred circuit devices unless test operating conditions (Ipk, Vav, L, tav, and
design practice. Of course, this cannot always be practiced; Tj(initial) are known and understood. Devices with same or
as mentioned earlier in this application note, real world similar avalanche voltage functions and same or similar
applications exist that require the MOSFET to avalanche thermal capability will have same UIS capability to failure,
repetitively by design. In these cases, determination of a but de−rating factors for Ipk vs tav SOA plots can vary
MOSFET suitability to the repetitive avalanche operation is across industry. Safe repetitive avalanche operation is
best evaluated empirically, using the application operating possible, although DC parameter shifts can occur depending
conditions. on operating conditions.

www.onsemi.com
11
 AND90158/D

onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT: TECHNICAL SUPPORT
Email Requests to: [email protected] North American Technical Support: Europe, Middle East and Africa Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 00421 33 790 2910
onsemi Website: www.onsemi.com Phone: 011 421 33 790 2910 For additional information, please contact your local Sales Representative

◊ www.onsemi.com
12