Program : B.

Tech
Subject Name: Electronic Devices
Subject Code: EC-304
Semester: 3rd
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Subject Name- Electronics Device Subject Code: EC303

Unit V
FET construction- JFET: Construction, n-channel and p-channel, transfer and drain characteristics,
parameters, Equivalent model and voltage gain, analysis of FET in CG, CS and CD configuration.
Enhancement and Depletion MOSFET drain and transfer Characteristics. Unijunction Transistor
(UJT) and Thyristors: UJT: Principle of operation, characteristics, UJT relaxation oscillator.
--------------------------------------------------------------------------------------------------------------------

5.1. Field Effect Transistor (FET):

A bipolar junction transistor (BJT) is a current controlled device i.e., output characteristics of the device
are controlled by base current and not by base voltage. However, in a field effect transistor (FET), the
output characteristics are controlled by input voltage (i.e., electric field) and not by input current. This is
probably the biggest difference between BJT and FET.

There are two basic types of field effect transistors:

(i) Junction field effect transistor (JFET)

(ii) Metal oxide semiconductor field effect transistor (MOSFET)

The FET is a three terminal device like the BJT, but operates by a different principle. The three terminals
are called the source, drain, and gate. The voltage applied to the gate controls the current flowing in the
source-drain channel. No current flows through the gate electrode, thus the gate is essentially insulated
from the source-drain channel. Because no current flows through the gate, the input impedance of the
FET is extremely large (in the range of 1010–1015 Ω). The large input impedance of the FET makes them
an excellent choice for amplifier inputs. The two common families of FETs, the junction FET (JFET) and
the metal oxide semiconductor FET (MOSFET) differ in the way the gate contact is made on the source-
drain channel.

5.2. JFET

In the JFET the gate-channel contact is a reverse biased pn junction. The gate-channel junction of the
JFET must always be reverse biased otherwise it may behave as a diode. All JFETs are depletion mode
devices—they are on when the gate bias is zero (VGS = 0). Two versions of the symbols are in common
use. The symbols in the top row depict the source and drain as being symmetric. This is not generally
true. Slight asymmetries are built into the channel during manufacturing which optimize the performance
of the FET. Thus it is necessary to distinguish the source from the drain. In this class we will use the
asymmetric symbols found on the bottom row, which depict the gate nearly opposite the source. The
designation n-channel means that the channel is n doped and the gate is p doped. The p-channel is
complement of n- channel.

N-channel P-channel
D D

G G

S S

Figure.5.1. Symbol and schematic of JFET

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5.2.1. Basic Operation of JFET:

Figure 5.2 shows dc bias voltages applied to an n-channel JFET. VDS provides a drain-to-source voltage
and supplies current from drain to source. VGG sets the reverse-bias voltage between the gate and the
source. The JFET is always operated with the gate-source pn junction reverse-biased. Reverse-biasing of
the gate-source junction with a negative gate voltage produces a depletion region along the pn junction,
which extends into the n channel and thus increases its resistance by decreasing the channel width. The
channel width and the channel resistance can be controlled by varying the gate voltage, there by
controlling the amount of drain current I D Figure 5.2, illustrates this concept when VGG = VGS.

The JFET has two distinct modes of operation: the variable-resistance mode, and the pinch-off mode. In
the variable-resistance mode the JFET behaves like a resistor whose value is controlled by VGS. In the
pinch-off mode, the channel has been heavily constricted with most of the drain-source voltage drop
occurring along the narrow and therefore high-resistance part of the channel near the depletion regions.

At small values of VDS (in the range of a few tenths of a volt), the curves of constant VGS show a linear
relationship between VDS and ID. This is the variable-resistance region of the graph. As VDS increases,
each of the curves of constant VGS enters a region of nearly constant ID. This is the pinch-off region,
where the JFET can be used as a linear voltage and current amplifier.

At VGS=0, the current through the JFET reaches a maximum known as IDSS , the current from Drain to
Source with the gate Shorted to the source. If VGS goes positive for this N-channel JFET, the PN junction
becomes conducting and the JFET becomes just a forward-biased diode.

5.2.2. Drain characteristics of JFET: The curve drawn between drain current ID and drain-source
voltage VDS with gate-to source voltage VGS as the parameter is called the drain or output
characteristic. This characteristic is analogous to collector characteristic of a BJT.

Figure.5.2. JFET drain characteristics with shorted Gate

Figure.5.3. JFET drain characteristics at different values of VGS

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It is observed that as the negative gate bias voltage is increased

(1) The maximum saturation drain current becomes smaller because the conducting channel now
becomes narrower.
The equation that relates the current ID with the voltage VGS is known as the Schockley equation that
is given by:

where Vp is the pinch-off voltage and IDSS is the saturation current.

This current (IDSS) is defined as the value of the current ID when VGS = 0, and this feature is often
used to obtain a constant value current source (IDSS). This equation at the ID and VGS plane represent
a parabola displaced in Vp.

(2) Pinch-off voltage is reached at a lower value of drain current I D than when VGS = 0. When an
external bias of, say – 1 V is applied between the gate and the source, the gate-channel junctions are
reverse-biased even when drain current, ID is zero. Hence the depletion regions are already
penetrating the channel to a certain extent when drain-| source voltage, VDS is zero. Due to this
reason, a smaller voltage drop along the channel (i.e. smaller than that for V GS = 0) will increase the
depletion regions to the point where 1 they pinch-off the current. Consequently, the pinch-off voltage
VP is reached at a lower 1 drain current, I D when VGS = 0.
(3) The ohmic region portion decreases.
(4) Value of drain-source voltage VDS for the avalanche breakdown of the gate junction is reduced.
Value of drain-source voltage, VDS for breakdown with the increase in negative bias voltage is
reduced simply due to the fact that gate-source voltage, VGS keeps adding to the I reverse bias at the
junction produced by current flow.

5.2.3. Transfer Characteristic of JFET

The transfer characteristic for a JFET can be determined experimentally, keeping drain-source
voltage, VDS constant and determining drain current, I D for various values of gate-source voltage, VGS. The
curve is plotted between gate-source voltage, VGS and drain current, ID, as illustrated in fig. 5.4. It is similar
to the transconductance characteristic of a vacuum tube or a transistor. It is observed that
(i) Drain current decreases with the increase in negative gate-source bias
(ii) Drain current, ID = IDSS when VGS = 0
(iii) Drain current, ID = 0 when VGS = VD

Figure.5.4. transfer characteristics

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5.3. FET configurations:

There are three basic configurations for a single stage FET amplifier:

 Common source (CS) configuration: The common source circuit provides a medium input and
output impedance levels. Both current and voltage gain can be described as medium, but the
output is the inverse of the input, i.e. 180° phase change. This provides a good overall


performance and as such it is often thought of as the most widely used configuration.
Common gate (CG) configuration: This transistor configuration provides low input impedance
while offering a high output impedance. Although the voltage is high, the current gain is low
and the overall power gain is also low when compared to the other FET circuit configurations
available. The other salient feature of this configuration is that the input and output are in


phase.
Source follower (SF) or common Drain configuration: This FET configuration is also known as
the source follower. The reason for this is that the source voltage follows that of the gate.
Offering high input impedance and low output impedance it is widely used as a buffer. The
voltage gain is unity, although current gain is high. The input and output signals are in phase.

5.4. JFET Biasing: The purpose of biasing is to select the proper dc gate-to-source voltage to
establish a desired value of drain current and, thus, a proper Q-point. Three types of bias are
self-bias, voltage-divider bias, and Fixed bias.

5.4.1. Self-Bias: Self-bias is the most common type of JFET bias. JFET must be operated such
that the gate source junction is always reverse-biased. This condition requires a negative VGS
for an n-channel JFET. This can be achieved using the self-bias arrangements shown in figure
here. The gate resistor, RG, does not affect the bias because it has essentially no voltage drop
across it; and therefore the gate remains at 0 V. RG is necessary only to force the gate to be at 0
V and to isolate an ac signal from ground in amplifier applications. For the n-channel JFET as
shown in the figure, Is produces a voltage drop across Rs and makes the source positive with
respect to ground. Since Is = ID and VG=0V, then VS= IDRS. The gate-to-source voltage is then
given by

Figure.5.5. Self Bias circuit of JFET

VGS= VG -VS=0- IDRS

=- IDRS
the drain-to-source voltage is
VDS= VD -VS=VDD- ID(RD+ RS)
Thus dc conditions of JFET amplifier are fully specified. Self biasing of a JFET stabilizes its quiescent
operating point against any change in its parameters like transconductance. Let the given JFET be

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replaced by another JFET having the double conductance then drain current will also try to be double
but since any increase in voltage drop across Rs, therefore, gate-source voltage, VGS becomes more
negative and thus increase in drain current is reduced.

5.4.2. Voltage Divider Bias:

The JFET gate voltage Vg is biased through the potential divider network set up by resistors R1 and R2and is
biased to operate within its saturation region which is equivalent to the active region of the bipolar junction
transistor. Since the N-Channel JFET is a depletion mode device and is normally “ON”, a negative gate voltage
with respect to the source is required to modulate or control the drain current. This negative voltage can be
provided by biasing from a separate power supply voltage or by a self biasing arrangement as long as a steady
current flows through the JFET even when there is no input signal present and Vg maintains a reverse bias of
the gate-source PN junction.

Figure.5.6. Voltage Divider Bias

VGS= VG -VS= VG - IDRS

The circuit is so designed that IDRs is greater than VG so that VGS is negative. This provides correct bias
voltage.

The operating point can be determined as

ID = (VG – VGS)/ RS

VDS = VDD – ID (RD + RS)

When the JFET is s itched fully ON a oltage d op e ual to Rs*Id is developed across this resistor raising
the potential of the source terminal above 0v or ground level. This voltage drop across Rs due to the drain
current provides the necessary reverse biasing condition across the gate resistor, R2 effectively generating
negative feedback.
So in order to keep the gate-source junction reverse biased, the source voltage, Vs needs to be higher than
the gate voltage, Vg. This source voltage is therefore given as:

Then the Drain current, Id is also equal to the Source current, Is as No Cu ent enters the Gate terminal
and this can be given as:

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5.4.3. Fixed Bias:

DC bias of a FET device needs setting of gate-source voltage VGS to give desired drain current ID . For a
JFET drain current is limited by the saturation current I DS. Since the FET has such a high input
impedance that no gate current flows and the dc voltage of the gate set by a voltage divider or a fixed
battery voltage is not affected or loaded by the FET.
Fixed dc bias is obtained using a battery VQG. This battery ensures that the gate is always
negative with respect to source and no current flows through resistor RG and gate terminal that
is IG =0. The battery provides a voltage VGS to bias the N-channel JFET, but no resulting current is
drawn from the battery VGG. Resistor RG is included to allow any ac signal applied through capacitor C
to develop across RG. While any ac signal will develop across RG, the dc voltage drop across RG is equal
to IG RG i.e. 0 volt.

Figure.5.7.Fixed Bias Circuit

The gate-source voltage VGS is then

VGS = – VG – Vs = – VGG – 0 = – VGG
The drain -source current ID is then fixed by the gate-source voltage as determined by equation.
This current then causes a voltage drop across the drain resistor RD and is given as VRD = ID RD and
output voltage, Vout = VDD – IDRD
5.5. Metal-oxide semiconductor field effect transistor (MOSFET):

In the MOSFET the gate-channel contact is a metal electrode separated from the channel by a thin
layer of insulating oxide. MOSFETs have very good isolation between the gate and the channel, but
the thin oxide is easily damaged (punctured!) by static discharge through careless handling A
depletion-type device is a device that uses an input voltage to reduce the size of the channel to control
the amount of current. An enhancement-type device is a device that uses an input voltage to increase
the size of the channel to control the amount of current. JFETs can operate only in depletion mode.
There are two types of MOSFETS: depletion-type MOSFETs or D-MOSFETs, and enhancement-type
MOSFETs, or E-MOSFETs. There are two types of channel: n-channel and p-channel.

In the MOSFET, the current is controlled by an electric field applied perpendicular to both the
semiconductor surface and to the direction of current. The phenomenon used to modulate the
conductance of a semiconductor, or control the current in a semiconductor, by applying an electric
field perpendicular to the surface is called the field effect. Again, the basic transistor principle is that
the voltage between two terminals controls the current through the third terminal.

5.5.1. Types of MOSFETs: There are two basic types of MOSFETs viz.

 Depletion-type MOSFET or D-MOSFET. The D-MOSFET can be operated in both

the depletion mode and the enhancement-mode. For this reason, a D-MOSFET is


sometimes called depletion/enhancement MOSFET.
Enhancement-type MOSFET or E-MOSFET. The E-MOSFET can be operated only
in enhancement-mode.
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5.5.2. N-Channel Enhancement mode MOSFET:

When the gate voltage is negative with respect to source, the depletion type MOSFET (metal oxide
semiconductor field effect transistor) operates with an enhancement mode. Figure 5.3 shows a
simplified cross section of a MOS field-effect transistor. The gate, oxide, and p-type substrate
regions are the same as those of a MOS capacitor. In addition, we now have two n-regions, called
the source terminal and drain terminal. The current in a MOSFET is the result of the flow of charge
in the inversion layer, also called the channel region, adjacent to the oxide− semiconductor
interface.

The channel length L and channel width E are defined on the figure. The channel length of a typical
integrated circuit MOSFET is less than 1 µm (10—6 m), which means that MOSFETs are small
devices. The oxide thickness t ox is typically on the order of 400 angstroms, or less. The diagram in
Figure1.27 is a simplified sketch of the basic structure of the transistor.

5.5.4. N-Channel MOSFET

 The n-channel D-MOSFET is a piece of n-type material with a p-type region (called
substrate) on the right and an insulated gate on the left as shown in Fig.5.9. The free electrons
(Q it is n-channel) flowing from source to drain must pass through the narrow channel


between the gate and the p-type region.
Note carefully the gate construction of D-MOSFET. A thin layer of metal oxide (usually
silicon dioxide, SiO2) is deposited over a small portion of the channel. A metallic gate is
deposited over the oxide layer. As SiO2 is an insulator, therefore, gate is insulated from the
channel. Note that the arrangement forms a capacitor. One plate of this capacitor is the gate


and the other plate is the channel with SiO2 as the dielectric.
It is a usual practice to connect the substrate to the source (S) internally so that a MOSFET
has three terminals that is source (S), gate (G) and drain (D).Since the gate is insulated from
the channel; we can apply either negative or positive voltage to the gate. Therefore, D-
MOSFET can be operated in both depletion-mode and enhancement-mode. However, JFET
can be operated only in depletion-mode.

Source VGS VDS

Metal electrode
Oxide

W
Gate

Source Drain
tox
n n+
Channel L
p-type

(Substrate bias)
Figure.5.8. Schematic diagram of an n-channel enhancement mode MOSFET

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Drain (D) Drain (D)

Si02 Layer N Si02 Layer N

P P
Gate (G) Gate (G)

N-channel No-channel

Source (S) Source (S)

(a) N-channel D-
MOSFET (b) N-channel E-
MOSFET

Figure.5.9. MOSFET construction

5.5.5. D-MOSFET

Fig.5.4 (a) shows the circuit of n-channel D-MOSFET. The gate forms a small capacitor. One plate of
this capacitor is the gate and the other plate is the channel with metal oxide layer as the dielectric. When
gate voltage is changed, the electric field of the capacitor changes, which in turn changes the resistance
of the n-channel. Since the gate is insulated from the channel, we can apply either negative or positive
voltage to the gate. The negative-gate operation is called depletion mode whereas positive gate
operation is known as enhancement mode.

5.5.6. E-MOSFET

Fig. 5.4(b) shows the constructional details of n-channel E-MOSFET. Its gate construction is similar to
that of D-MOSFET. The E-MOSFET has no channel between source and drain unlike the D-MOSFET.
Note that the substrate extends completely to the SiO2 layer so that no channel exists. The E-MOSFET
requires a proper gate voltage to form a channel (called induced channel). It is reminded that E-
MOSFET can be operated only in enhancement mode. In short, the construction of E-MOSFET is quite
similar to that of the D-MOSFET except for the absence of a channel between the drain and source
terminals.

5.5.7. Depletion mode

Fig. 5.10 shows depletion-mode operation of n-channel D-MOSFET. Since gate is negative, it means
electrons are on the gate as shown is Fig.1.26. These electrons repel the free electrons in the n-channel,
leaving a layer of positive ions in a part of the channel. In other words, we have depleted (i.e. emptied)
the n-channel of some of its free electrons. Therefore, lesser number of free electrons is made available
for current conduction through the n-channel. This is the same thing as if the resistance of the channel is
increased. The greater the negative voltage on the gate, the lesser is the current from source to drain.

Thus by changing the negative voltage on the gate, we can vary the resistance of the n-channel and
hence the current from source to drain. Note that with negative voltage to the gate, the action of D-
MOSFET is similar to JFET. Because the action with negative gate depends upon depleting (i.e.
emptying) the channel of free electrons, the negative-gate operation is called depletion mode.

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Drain (D)

P
Gate (G) VDD
Substrate

VGG

Source (S)

Figure.5.10. Depletion mode MOSFET

5.5.7. Enhancement mode:

Fig. 5.11 shows enhancement-mode operation of n-channel D- MOSFET. Again, the gate acts
like a capacitor. Since the gate is positive, it induces negative charges in the n-channel. These
negative charges are the free electrons drawn into the channel. Because these free electrons
are added to those already in the channel, the total number of free electrons in the channel is
increased. Thus a positive gate voltage enhances or increases the conductivity of the channel.
Greater the positive voltage on the gate, greater the conduction from source to drain. Thus by
changing the positive voltage on the gate, we can change the conductivity of the channel. The
main difference between D-MOSFET and JFET is that we can apply positive gate voltage to
D-MOSFET and still have essentially zero current. Because the action with a positive gate
depends upon enhancing the conductivity of the channel, the positive gate operation is called
enhancement mode.

Drain (D)

P
Gate (G) VDD
Substrate

VGG

Source (S)

Figure.5.11. Enhancement mode MOSFET

The following points may be noted about D-MOSFET operation:

 In a D-MOSFET, the source to drain current is controlled by the electric field of capacitor


formed at the gate.
The gate of JFET behaves as a reverse-biased diode whereas the gate of a D-MOSFET acts
like a capacitor. For this reason, it is possible to operate D-MOSFET with positive or
negative gate voltage.

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 As the gate of D-MOSFET forms a capacitor, therefore, negligible gate current flows
whether positive or negative voltage is applied to the gate. For this reason, the input
impedance of D-MOSFET is very high, ranging from 10,000 MΩ to 10,000,00 MΩ.
 The extremely small dimensions of the oxide layer under the gate terminal result in a very
low capacitance and the D-MOSFET has, therefore, a very low input capacitance. This
characteristic makes the D-MOSFET useful in high-frequency applications.

5.6. Drain and Transfer Characteristics of MOSFET:

DE-MOSFETs are classified as the depletion-mode devices because their conductivity

depends on the action of depletion layers. E-MOSFET is classified as an enhancement-
mode device because its conductivity depends on the action of the inversion layer.
Depletion-mode devices are normally ON when the gate-source voltage VGS = 0, whereas
the enhancement-mode devices are normally OFF when VGS = 0. In general, any MOSFET
characteristics is seen to exhibit three operating regions viz.,

1. Cut-Off Region: Cut-off region is a region in which the MOSFET will be OFF as there will
be no current flow through it. In this region, MOSFET behaves like an open switch and is
thus used when they are required to function as electronic switches.
2. Ohmic or Linear Region Ohmic or linear region is a region where in the current I DS
increases with an increase in the value of VDS. When MOSFETs are made to operate in this
region, they can be used as amplifiers.
3. Saturation Region In saturation region, the MOSFETs have their I DS constant inspite of an
increase in VDS and occur once VDS exceeds the value of pinch-off voltage VP. Under this
condition, the device will act like a closed switch through which a saturated value of I DS
flows. As a result, this operating region is chosen whenever MOSFETs are required to
perform switching operations.

5.6.1. N-Channel EMOSFET characteristics: Drain characteristics of an N-channel E-

MOSFET are shown in figure. The lowest curve is the VGST curve. When VGS is lesser than
VGST, ID is approximately zero. When VGS is greater than VGST, the device turns- on and the
drain current ID is controlled by the gate voltage and the current through the device
increases with an increase in IDS initially (Ohmic region) and then saturates to a value as
determined by the VGS (saturation region of operation) i.e. as VGS increases, even the
saturation current flowing through the device also increases. The characteristic curves have
almost vertical and almost horizontal parts. The almost vertical components of the curves
correspond to the ohmic region, and the horizontal components correspond to the constant
current region. Thus E-MOSFET can be operated in either of these regions i.e. it can be
used as a variable-voltage resistor (VVR) or as a constant current source.

Figure.5.12. Drain and transfer Characteristics of EMOSFET

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Transfer characteristics: The transconductance curve is shown in figure 5.12. The current
IDSS at VGS <=0 is very small, being of the order of a few nano-amperes. When the VGS is
made positive, the drain current ID increases slowly at first, and then much more rapidly
with an increase in VGS.

The equation for the transfer characteristic of E-MOSFETs is given as:

ID=K(VGS-VGST)2

5.6.2. N-Channel DMOSFET characteristics:

The transfer characteristics of n-channel depletion MOSFET shown by Figure 5.13 indicate that the device
has a current flowing through it even when VGS is 0V. This indicates that these devices conduct even when
the gate terminal is left unbiased, which is further emphasized by the V GS0 curve of Figure 5.13(b). Under
this condition, the current through the MOSFET is seen to increase with an increase in the value of VDS
(Ohmic region) until VDS becomes equal to pinch-off voltage VP. After this, IDS will get saturated to a
particular level IDSS (saturation region of operation) which increases with an increase in V GS i.e. IDSS3 >
IDSS2 > IDSS1, as VGS3 > VGS2 > VGS1. Further, the locus of the pinch-off voltage also shows that VP
increases with an increase in V GS. However it is to be noted that, if one needs to operate these devices in
cut-off state, then it is required to make VGS negative and once it becomes equal to -VT, the conduction
through the device stops (IDS = 0) as it gets deprived of its n-type channel (Figure 5.13(a)).

Figure.5.13.N-Channel D-MOSFET characteristics

5.7. Unijunction Transistor (UJT):

The Unijunction transistor (UJT) is a three terminal device having one emitter and two base contacts. It is
also known as double-base diode because it is a 2-layered, 3-terminal solid-state switching device. It has
only one junction so it is called as a uni-junction device. This device has a unique characteristics that when it
is triggered, the emitter current increases regeneratively until it is limited by emitter power supply. Due to
this characteristics, the uni-junction transistor can be employed in a variety of applications e.g., switching,
pulse generator, saw-tooth generator etc.
5.7.1. Construction of UJT
Fig.5.14 shows the basic structure of a uni-junction transistor. It consists of an n-type silicon bar with an
electrical connection on each end. The leads to those connections are called base leads base-one B1 and base
two B2. Part way along the bar between the two bases, nearer to B2 than B1.a PN junction is formed between
a p-type emitter and the bar. The lead to this junction is called the emitter lead E. The emitter is heavily
doped having many holes. The n-region, however, is lightly doped. For this reason, the resistance between
the base terminals is very high when emitter lead is open.

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Figure.5.14. UJT construction

5.7.2. Equivalent circuit of UJT:
The voltage applied at the emitter is indicated as VE and the internal resistances are indicated as RB1 and
RB2 at bases 1 and 2 respectively. Both resistances present internally are together called as intrinsic
resistance, indicated as RBB. The voltage across RB1 can be denoted as V1. The dc voltage applied for the
circuit to function is VBB. The UJT equivalent circuit is as given below in figure 5.15.

Figure.5.15. Equivalent Circuit of UJT

(i) With no voltage applied to the UJT, the inter-base resistance is given by ;
RBB = RB1 + RB2
(ii) If a voltage VBB is applied between the bases with emitter open, the voltage will divide up across
RB1 and RB2.

Voltage across RB1,

The ratio V1/ VBB is called intrinsic stand-off ratio and is represented by η.
Hence,

The value of η lies between 0.51 and 0.82.

So voltage across RB1 = ηVBB

The voltage ηVBB appearing across RB1 reverse biases the diode. Therefore, the emitter current is
zero.
(iii) If now a progressively rising voltage is applied to the emitter, the diode will become forward
biased when input voltage exceeds ηV BB by VD, the forward voltage drop across the silicon diode

i.e.

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5.7.2. Principle of operation and characteristics:

The device has normally B2 positive with respect to B1.
(i) If voltage VBB is applied between B2 and B1with emitter open, a voltage gradient is established
along the n-type bar. Since the emitter is located nearer to B2, more than half of VBB appears
between the emitter and B1. The voltage V1 between emitter and B1 establishes a reverse bias on the
PN junction and the emitter current is cut off. A small leakage current flows from B2 to emitter due
to minority carriers.
(ii) This transistor operation starts by making the emitter supply voltage to zero, and its emitter
diode is reverse biased with the intrinsic stand-off voltage. If VB is the voltage of the emitter diode,
then the total reverse bias voltage is V1 + VB = Ƞ VBB + VD. For silicon VD = 0.7 V.
(iii) If a positive voltage is applied at the emitter, the PN junction will remain reverse biased so
long as the input voltage is less than V1.If the input voltage to the emitter exceeds V1, the PN
junction becomes forward biased. Under these conditions, holes are injected from p-type material
into the n-type bar. These holes are repelled by positive B2 terminal and they are attracted towards
B1 terminal of the bar. This accumulation of the holes in the emitter to B1 region results in the
decrease of resistance in this section of the bar. The result is that internal voltage drop from emitter
to B1 is decreased and hence the emitter current I E increases.

(iv)As more holes are injected, a condition of saturation will eventually be reached. At this point,
the emitter current is limited by emitter power supply only. The device is now in the ON sate.

Figure.5.16 (a) Characteristics of UJT;(b)UJT model for Vp

(v) The Unijunction emitter current vs voltage characteristic curve (Figure.5.16) shows that as VE
increases, current IE increases up IP at the peak point. Beyond the peak point, current increases as
voltage decreases in the negative resistance region. The voltage reaches a minimum at the valley
point. The resistance of RB1, the saturation resistance is lowest at the valley point.

5.8. UJT relaxation oscillator:

The relaxation oscillator in Figure 5.17 is an application of the UJT oscillator.

Operation of UJT Oscillator:

(i) When a voltage (Vs) is firstly applied, the UJT is “OFF” and the capacitor C1 is fully discharged
but begins to charge up exponentially through resistor R3.

(ii) As the Emitter of the UJT is connected to the capacitor, when the charging voltage Vc across
the capacitor becomes greater than the diode volt drop value, the p-n junction behaves as a normal
diode and becomes forward biased triggering the UJT into conduction. The UJT is “ON”. At this
point the Emitter to B1 impedance collapses as the Emitter goes into a low impedance saturated
state with the flow of Emitter current through R1 taking place.
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(iii) As the ohmic value of resistor R1 is very low, the capacitor discharges rapidly through the UJT
and a fast rising voltage pulse appears across R1. Also, because the capacitor discharges more
quickly through the UJT than it does charging up through resistor R3, the discharging time is a lot
less than the charging time as the capacitor discharges through the low resistance UJT.

(iv) When the voltage across the capacitor decreases below the holding point of the p-n junction
( VOFF ), the UJT turns “OFF” and no current flows into the Emitter junction so once again the
capacitor charges up through resistor R3 and this charging and discharging process
between VON and VOFF is constantly repeated while there is a supply voltage, Vs applied.

Figure.5.17. UJT relaxation Oscillator and waveforms

5.9. Thyristor:
It is a multi-layer semiconductor device, requires a gate signal to turn it “ON”, and once “ON” it behaves
like a rectifying diode. The Thyristor is a four layer (P-N-P-N) semiconductor device that contains three PN
junctions in series, and is represented by the symbol as shown. It is a unidirectional device that is it will only
conduct current in one direction and only in the switching mode and cannot be used for amplification. The
thyristor is a three-terminal device labeled as “Anode”, “Cathode” and “Gate” and consisting of three PN
junctions which can be switched “ON” and “OFF” at an extremely fast rate.

Figure.5.18.Thyristor and its symbol

5.9.1. V-I Characteristics of Thyristor or SCR:

The basic circuit for obtaining Thyristor V-I characteristics is given below, the anode and cathode
of the Thyristor are connected to main supply through the load. The gate and cathode of the
Thyristor are fed from a source Es, used to provide gate current from gate to cathode.

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Figure.5.19.VI characteristics of Thyristor

As per the characteristic diagram, there are three basic modes of SCR: reverse blocking mode, forward blocking
mode, and forward conduction mode.

Reverse Blocking Mode: In this mode the cathode is made positive with respect to anode with switch S open.
Junction J1 and J3 are reversed biased and J2 is forward biased. When reverse voltage applied across Thyristor
(should be less than VBR), the device offers a high impedance in the reverse direction. Therefore, Thyristor
treated as open switch in the reverse blocking mode. VBR is the reverse breakdown voltage where the avalanche
occurs, if voltage exceeds VBR may cause to Thyristor damage.

Forward Blocking Mode: When anode is made positive with respect to cathode, with gate switch open.
Thyristor is said to be forward biased, junction J1 and J3 are forward biased and J2 is reversed biased as you can
see in figure. In this mode, small current flows called forward leakage current, as the forward leakage current is
small and not enough to trigger the SCR. Therefore, SCR is treated as open switch even in forward blocking
mode.

Forward Conduction Mode: As the forward voltage is increased with gate circuit remain open, an avalanche
occurs at junction J2 and SCR comes into conduction mode. We can turn ON the SCR at any moment by giving
a positive gate pulse between gate and cathode or by a forward break over voltage across anode and cathode of
the Thyristor.

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