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ELECTRONIC DEVICES

4 FIELD EFFECT TRANSISTOR

1. INTRODUCTION

There are two types of field-effect transistors, the Junction Field-Effect Transistor (JFET) and
the "Metal-Oxide Semiconductor" Field-Effect Transistor (MOSFET), or Insulated-Gate Field-
Effect Transistor (IGFET). The principles on which these devices operate (current controlled by
an electric field) are very similar, the primary difference being in the methods by which the
control element is made. This difference, however, results in a considerable difference in device
characteristics and necessitates variances in circuit design, which are discussed in this chapter.

Figure 1
1.1. Junction Field-Effect Transistor (JFET)
In its simplest form the junction field-effect transistor starts with nothing more than a
bar of doped silicon that behaves as a resistor. By convention, the terminal into which
current is injected is called the source terminal, since, as far as the FET is concerned,
current originates from this terminal. The other terminal is called the drain terminal.
Current flow between source and drain is related to the drain-source voltage by the
resistance of the intervening material. In Figure, p-type regions have been diffused into
the n-type substrate of Figure 1.1(a) leaving an n-type channel between the source and
drain. (A complementary p-type device is made by reversing all of the material types.)
These p-type regions will be used to control the current flow between the source and the
drain and are thus called gate regions.
As with any p-n junction, a depletion region surrounds the p-n junctions when the
junctions are reverse biased (Figure 1.1(c)). As the reverse voltage is increased, the
depletion regions spread into the channel until they meet, creating an almost infinite
resistance between the source and the drain.

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If an external voltage is applied between source and drain (Figure 1.1(d)) with zero gate
voltage, drain current flow in the channel sets up a reverse bias along the surface of the
gate, parallel to the channel. As the drain-source voltage increases, the depletion regions
again spread into the channel because of the voltage drop in the channel which reverse
biases the junctions. As VDS is increased, the depletion regions grow until they meet,
whereby any further increase in voltage is counterbalanced by an increase in the depletion
region toward the drain. There is an effective increase in channel resistance that prevents
any further increase in drain current. The drain-source voltage that causes this current
limiting condition is called the "pinch off" voltage (V p). A further increase in drain-source
voltage produces only a slight increase in drain current. The variation in drain current (I D)
with drain-source voltage (VDS) at zero gate-source voltage (VGS) is shown in Figure 2a.
In the low-current region, the drain current is linearly related to V DS. As ID increases, the
"channel" begins to deplete and the slope of the ID curve decreases. When the VDs is
equal to Vp, ID "saturates" and stays relatively constant until drain-to-gate avalanche,
VBR(DSS) is reached. If a reverse voltage is applied to the gates, channel pinch-off occurs
at a lower ID level (Figure 2b) because the depletion region spread caused by the reverse-
biased gates adds to that produced by VDS. Thus, reducing the maximum current for any
value of VDS.

Figure 1.1. Development of junction field-effect transistors

Basic Structure
Figure 1.2(a) shows the basic structure of an n-channel JFET (junction field-effect
transistor). Wire leads are connected to each end of the n-channel; the drain is at the
upper end, and the source is at the lower end. Two p-type regions are diffused in the n-
type material to form a channel, and both p-type regions are connected to the gate lead.
For simplicity, the gate lead is shown connected to only one of the p regions. A p-channel
JFET is shown in Figure 1.2(b).

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Figure 1.2 A representation of the basic structure of the two types of JFET.

2. BASIC OPERATION

To illustrate the operation of a JFET, Figure 2 shows dc bias voltages applied to an n-channel

device. VDD provides a drain-to-source voltage and supplies current from

Figure 2 A biased n-channel JFET.

drain to source. VGG sets the reverse-bias voltage between the gate and the source, as shown.

The JFET is always operated with the gate-source pn junction reverse-biased. Reverse-biasing

of the gate-source junction with a negative gate voltage produces a depletion region along the

pn junction, which extends into the n channel and thus increases its resistance by restricting

the channel width.

The channel width and thus the channel resistance can be controlled by varying the gate

voltage, thereby controlling the amount of drain current, ID.

2.1. JFET Symbols

The schematic symbols for both n-channel and p-channel JFETs are shown in Figure 2.1.

Notice that the arrow on the gate points "in" for n channel and "out" for p channel.

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Figure 2.1 JFET schematic symbols.

2.2. Drain Characteristic Curve
Consider the case when the gate-to-source voltage is zero (VGS = 0 V). This is produced
by shorting the gate to the source, as in Figure 2.2(a) where both are grounded. As V DD
(and thus VDS) is increased from 0 V, ID will increase proportionally, as shown in the graph
of Figure 2.2(b) between points A and B. In this area, the channel resistance is essentially
constant because the depletion region is not large enough to have significant effect. This
is called the ohmic region because VDS and ID are related by Ohm's law.
At point B in Figure 2.2(b), the curve levels off and enters the active region where I D
becomes essentially constant. As VDS increases from point B to point C, the reverse-bias

Figure 2.2: The drain characteristic curve of a JFET for VGS = 0 showing pinch-
off voltage.

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voltage from gate to drain (VGD) produces a depletion region large enough to offset the
in-crease in VDS, thus keeping ID relatively constant
Pinch-Off Voltage:
For VGS = 0 V, the value of VDS at which ID becomes essentially constant (point B on the
curve in Figure 2.2(b)) is the pinch-off voltage, Vp. For a given, Vp has a fixed value. As
you can see, a continued increase in VDS above the pinch-off voltage produces an almost
constant drain current. This value of drain current is I DSS (Drain to Source current with
gate Shorted) and is always specified on JFET datasheets. I DSS is the maximum drain
current that a specific JFET can produce regardless of the external circuit, and it is always
specified for the condition, VGS = 0 V.
Breakdown:
As shown in the graph in Figure 2.2(b), breakdown occurs at point C when I D begins to
increase very rapidly with any further increase in VDS. Breakdown can result in irreversible
damage to the device, so JFETs are always operated below breakdown and within the
active region (constant current) (between points B and C on the graph). The JFET action
that produces the drain characteristic curve to the point of breakdown for VGS = 0V.
VGS Controls ID:
Let's connect a bias voltage, VGG, from gate to source as shown in Figure 2.3(a). As V GS
is set to increasingly more negative values by adjusting V GG, a family of drain
characteristic curves is produced, as shown in Figure 2.3(b). Notice that I D decreases as
the magnitude of VGS is increased to larger negative values because of the narrowing of
the channel. Also notice that, for each increase in V GS, the JFET reaches pinch-off (where
constant current begins) at values of VDS less than Vp. The term pinch-off is not the same
as pinch-off voltage, VP. Therefore, the amount of drain current is controlled by VGS, as
illustrated.
Cutoff Voltage:
The value of VGs that makes ID approximately zero is the cutoff voltage, V GS(off), as shown
in below figure. The JFET must be operated between V GS = 0 V and VGS(off). For this range
of gate-to-source voltages, ID will vary from a maximum of IDSS to a minimum of almost
zero.

Figure. 2.3: Pinch off occurs at a lower VDS as VGS is increased to

more negative values.

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Comparison of Pinch-Off Voltage and Cutoff Voltage:

As you have seen, there is a difference between pinch-off and cutoff voltages. There is
also a connection. The pinch-off voltage Vp is the value of VDS at which the drain current
becomes constant and equal to IDSS and is always measured at VGS = 0 V. However,

Figure 2.3: A biased p-channel JFET.

pinch-off occurs for VDS values less than Vp when VGS is nonzero. So, although Vp is a
constant, the minimum value of VDS at which ID becomes constant varies with VGS.
VGS (off) and Vp are always equal in magnitude but opposite in sign. A datasheet usually
will give either VGS(off) or Vp, but not both. However, when you know one, you have the
other. For example, if VGS(off) = –5 V, then Vp = +5 V, as shown in Figure 2.3(b).
EXAMPLE 1
For the JFET in Figure 2.4, VGS(off) = –4 V and IDSS= 12 mA. Determine the minimum value
of VDD required to put the device in the constant-current region of operation when VGS =
0 V.

Figure 2.4
Solution:
Since VGS(off) = –4 V, Vp = 4 V. The minimum value of VDS for the JFET to be in its constant-
current region is
VDS = Vp = 4 V
In the constant-current region with VGS = 0 V,
ID = IDSS = 12 mA

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The drop across the drain resistor is

VRD = IDRD = (12 mA)(560 Ω) = 6.72 V
Apply Kirchhoff's law around the drain circuit.
VDD = VDS + VRD = 4 V + 6.72 V = 10.7 V
This is the value of VDD to make VDS = Vp and put the device in the constant-current
region.

3. JFET UNIVERSAL TRANSFER CHARACTERISTIC

You have learned that a range of VGS values from zero to VGS(off) controls the amount of drain
current. For an n-channel VGS(off) is negative, and for a p-channel JFET, VGS(off) is positive.
Because VGS does control ID, the relationship between these two quantities is very important.
Figure 2.5 is a general transfer characteristic curve that illustrates graphically the relationship
between VGS and ID. This curve is also known as a transconductance curve.

Figure 2.5
Notice that the bottom end of the curve is at a point on the VGS axis equal to VGS(off), and the
top end of the curve is at a point on the ID axis equal to IDSS. This curve shows that
ID=0 when VGS = 4 VGS(off)
IDSS
ID = When VGS = 0.5VGS(off )
4
IDSS
ID = When VGS = 0.3VGS(off )
2
And
ID = IDSS when VGS = 0
The transfer characteristic curve can also be developed from the drain characteristic curves by
plotting values of ID for the values of VGS taken from the family of drain curves at pinch-off, as
illustrated in Figure 2.6 for a specific set of curves. Each point on the transfer characteristic
curve corresponds to specific values of VGS and ID on the drain curves. For example, when VGS
= –2 V, ID = 4.32 mA. Also, for this specific JFET, VGS(off) = –5 V and IDSS = 12 mA.

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Figure 2.6 Example of the development of an n-channel J FET transfer characteristic

curve from the JFET drain characteristic curves
A JFET transfer characteristic curve is expressed approximately as
2
 VGS 
I D  I DSS 1 − 
 VGS(off )
 
ID can be determined for any VGS if VGS(off) and IDSS are known. These quantities are usually
available from the datasheet for a given JFET. Notice the squared term in the equation. Because
of its form, a parabolic relationship is known as a square law, and therefore, JFETs and
MOSFETs are often referred to as square-law devices.
Example 2:
The partial datasheet for a 2N5459 JFET indicates that typically IDSS = 9 mA and VGS(off) = –8 V
(maximum). Using these values, determine the drain current for VGS = 0 V, – 1 V, and –4 V.
Solution:
For VGS = 0 V,
ID = IDSS = 9mA
For VGS = –1V
2
 VGS   −1V 
2

ID  IDSS 1 −  = (9mA) 1 − 
 VGS(off )   −8V 
 
= (9mA) (1 – 0.125)2 = (9 mA) (0.766) = 6.89 mA
For VGS = –4 V,

 −4V 
2

I D  (9mA) 1 − 
 −8V 
= (9mA)(1 − 0.5) 2 = (9mA)(0.25) = 2.25mA

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Example 3:
Calculate ID and VDS(sat) in an n-channel pn JFET. Assume the saturation current is IDSS = 2 mA
and the pinch off voltage is VP = -3.5 V. Calculate iD and vDS(sat) for vGS = 0, VP/4, and VP/2.
Solution:
2
 v   vGS 
ID = IDSS 1 − GS  = (2 ) 1 − 
 VP   ( −3.5) 
Therefore, for vGS = 0, VP/4, and VP/2, we obtain
ID = 2, 1.13, and 0.5 mA
we have,
vDS(sat) = vGS – VP = vGS – (–3.5)
Therefore, for vGS = 0, VP/4, and VP/2 we obtain
vDS(sat) = 3.5, 2.63, and 1.75V
[Note:
The current capability of a JFET can be increased by increasing the value of I DSS, which is a
function of the transistor width.]

CONVENTIONAL PRACTICE PROBLEM

1. Define the pinch off voltage. In the saturation region, how does the drain current vary with gate
voltage? And sketch the basic structure of an n- channel JFET transistor.
2. The parameters of an n-channel JFET are IDSS = 12 mA, VP = –4.5 V, and λ = 0. Determine
VDS(sat) for VGS = –1.2 V, and calculate ID for VDS > VDS(sat).
[Ans. VDS(sat) = 3.3 V, ID = 6.45 mA]
3. For an n-channel JFET, the parameters are: IDSS = 2 mA, VP = –2.5V, and λ = 0. What is the
value of VGS when ID = 1.2 mA and the transistor is biased in the saturation region?
[Ans. VGS = –0.564 V]
4. A p-channel JFET has a pinch off voltage of VP = 3.8 V. The drain current in the saturation region
is ID = 3 mA when VGS = 0.8 V. Determine IDSS and VSD(sat).
[Ans. IDSS = 4.81 mA, VSD(sat) = 3.0 V]

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