EE213 Topic00 Intro

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EE213

Digital Integrated Circuits II

Topic 0: Introduction

Prof. Pingqiang Zhou


Associate Professor
ShanghaiTech University
School of Information Science and Technology

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Outline of Topic 0
 Course logistics
 Introduction to IC
• The history of IC
• The current trends in IC
• The future of IC

 The status of IC in China

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Course Logistics
 Time: Mon./Wed., 1PM – 2:40PM
 Venue: SIST Rm 1D-107
 Instructor: Pingqiang Zhou (周平强)
[email protected]
Office Hour: TBD
 TAs: Wanzheng Weng (翁万正, wengwzh2022@)
Zi’ang Ge (葛梓昂, geza2022@)
Xin Xiong (熊欣, xiongxin2022@)
Office Hours: TBD

 We use Blackboard (互动教学平台)

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Grading Information
 Homework/lab assignments 25%
 Midterm exam (week 8) 20%
• Closed-book, closed-notes
 Final exam (week 17?) 10%
• Open book/notes

 Project (4 weeks, 1 credit) 25%


 Literature review (week 9 -) 15%
- Review report (w/ >= 6 pages, double column)
- Presentation video

 Class participation 5%

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Project Sample: A Simple CPU with SRAM

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Project Sample: A Simple CPU with SRAM

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Sample Topics for Literature Review
 AI for IC design
 AI chips
 Design for testability
 Design for manufacturing
 Emerging memories
 Emerging technologies, such as
• Quantum computing
• Superconducting computer
• Optical computing
• Neuromorphic computing

 2.5D/3D Integration

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Academic Integrity

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Course Spectrum: From Device to System

SYSTEM

MODULE
+
GATE

CIRCUIT
Vin Vout

DEVICE
G
S D
n+ n+

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Example of IC Systems: An MIPS Processor

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Course Topics (Tentative)
 Basic module (device to circuit), ~7 weeks
• Transistor and wires
• Inverter (delay, power, …)
• CMOS logic (combinational, sequential)

 Advanced module (system), ~5 weeks


• Data path (adder, multiplier, …)
• Memory (SRAM, DRAM, peripheral circuitry)
• Timing, clock/power distribution

 Selective module (the state-of-art), ~2 weeks


• From architecture to layout
• Low power design
• Technology variability (source, model, impact, …)

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Class Materials
 UC Berkeley
• EE141: Digital Integrated Circuits
• EE241: Advanced Digital Integrated Circuits
 J. M. Rabaey, A. Chandrakasan, B. Nikolić, Digital
Integrated Circuits - A Design Perspective, 2nd ed., 2003.
 N. H. E. Weste and D. Harris, CMOS VLSI Design, 4th
ed., Addison Wesley, Reading, MA, 2011.
 J. Rabaey, Low Power Design Essentials, Springer 2009.

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Class Materials - Other References
 VLSI Conferences
• International Solid-State Circuits Conference (ISSCC)
• Symposium on VLSI Circuits (VLSI)
• Custom Integrated Circuits Conference (CICC)
• Design Automation Conference (DAC)

 VLSI Journals
• IEEE Journal of Solid-State Circuits (JSSC)
• IEEE Trans. on VLSI Systems (TVLSI)
• IEEE Transactions on Circuits and Systems I/II

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Tools, PDK and Models
 Tools
• HSPICE
• Schematic/layout tools (from Cadence/Synopsys)

 PDK
• NanGate open cell library http://www.nangate.com/?page_id=22

 Models
• Predictive sub-100nm models http://ptm.asu.edu/
• BSIM models http://bsim.berkeley.edu/models/

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Course Goals
 This course aims to convey a knowledge of advanced
concepts of digital circuit and system design in state-of-art
MOS technologies
 Course goals
• Ability to design and implement CMOS digital circuits and optimize
them with respect to different constraints on PPA: performance
(speed), power and area (cost)
• Study the most significant challenges facing digital circuit designers in
the coming years and promising solutions

 Course prerequisites (optional)


• EE 113. Digital Integrated Circuits (CMOS devices and manufacturing
technology, logic gates and layout, delay, power, combinational circuit
design)
• EE 123. Microelectronic Devices (basic knowledge on CMOS device
operation)

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EE113 vs. EE213
 EE113 (undergraduate level)
• Basic transistor and circuit models
• Basic circuit design styles
• First experiences with design – creating a solution given a set of
specifications
– At 90nm CMOS or even older
• Well defined design project

 EE213 (graduate level)


• Transistor model of varying accuracy
• Design under constraints: power, robust, reliability, …
• Learning more advanced techniques
– 45nm, 15nm, …
• Study the challenges facing designers in the coming years

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Challenge Example – Low Power

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Challenge Example – Variation

Layout 0.25µ 0.18µ

0.13µ 90-nm

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Outline of Topic 0
 Course introduction
 Introduction to IC
• What is IC?
• The history of IC
• The current trends in IC
• The future of IC

 The status of IC in China

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被“卡脖子”的中国芯片

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IPhone Generations (2007 - 2017)

EE213 Topic0-Intro.22 [Google Image] ShanghaiTech University


The Teardown of IPhone 3G (2008)

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Making of a Chip

EE213 Topic0-Intro.24 [GlobalFoundaries] ShanghaiTech University


IC Products
 Processors
• CPU, DSP, Controllers

 Memory chips
• RAM, ROM, EEPROM

 System-on-chip (SoC)
 In smartphones

 Analog
• Mobile communication,
audio/video processing

 Embedded systems
• In cars, factories
• Network cards

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IC vs. Semiconductor

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Semiconductor

Osborne executive portable computer (1982) v.s iPhone (2007)

Weight 100x
Size 500x
Performance 1/100

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A Snapshot of Future Computing Applications
 “Computing everywhere”

 Future systems
• Cloud computing Mobile Users

• Clients
• Embedded systems Sea of Sensors

• Ambient intelligence

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Outline of Topic 0
 Course introduction
 Introduction to IC
• What is IC?
• The history of IC
• The current trends in IC
• The future of IC

 The status of IC in China

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The Evolution of ICs

EE213 Topic0-Intro.30 [YouTube] ShanghaiTech University


Two Related Nobel Prizes (1956, 2000)

Early IC, 1958, TI

er/2000/kilby.html
http://www.nobel.se/physics/educational/post
Vacuum tube Modern IC

1947, bipolar
transistor, Bell

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Function of a Transistor - Switch

EE213 Topic0-Intro.32 [Google Image] ShanghaiTech University


The Number of Transistors on IC Chips

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Transistor Numbers in iPhone XS/Mate 20?

A12 Bionic

4-core GPU

6.9
Billions!
2 performance cores

8-core 4 performance cores


Neural Engine

A12 Bionic multicore chip


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Moore’s Law – the Driving Force
Transistor count

Power

Frequency

EE213 Topic0-Intro.35 [Intel] ShanghaiTech University


Cost Incentive – What’s behind Moore’s Law

The compound annual reduction in processing cost of


one transistor is [14% - 22%] from 130nm to 14nm.
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Outline of Topic 00
 Course introduction
 Introduction to IC
• What is IC?
• The history of IC
• The current trends in IC
• The future of IC

 The status of IC in China

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IC Design Trends

speed/area speed
security
speed/power variation
speed/
area power

thermal
power low power ultra-low power variation

1970’s 1980’s 1990’s 2000’s 2010’s

[©Xie]
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The International Technology Roadmap
for Semiconductors (ITRS)
Tech Num of Num Freq Vdd Power
Year Node Transistors Wire
Level (GHz) (V) (W)
(nm) (Billion)

2011 22 1.5 12 3.7 0.9 161


2013 18 3.1 13 4.0 0.85 149
2015 15 3.1 13 4.3 0.80 143
2017 13 6.2 14 4.7 0.75 130
2019 11 12.4 14 5.1 0.71 133
2021 9 12.4 15 5.7 0.66 130
2023 8 24.7 15 6.0 0.62 -

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Tech. Node of Representative Foundries

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#1: Thermal Issue
Sun’s
10000
Surface
…chips become too hot…
Rocket
1000
Power Density (W/cm2)

Nozzle
Nuclear
Reactor
100

8086 Hot Plate


10 4004 P6
8008 8085 386 Pentium®
286 486
1 8080

1970 1980 1990 2000 2010 Source: pconline


Year

EE213 Topic0-Intro.41 Source: Borkar, De Intel ShanghaiTech University


#2: Variations
Spatial variation
110

100

90

Temperature (C)
80

70

60

50

40

[©Xie]
On-Die temperature [©Mohanty]
Process variation
Temporal variation

Circuit aging effect


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#3: 3D Integration

Detailed view Generalized view

Layer 5

Layer 4

Interlayer Via Layer 3


(TSVs)
Layer 2
Metal wires
of layer 1
[www.tourtx.cn]

Layer 1
Device on
layer 1 Bulk Substrate

3D chip

• Higher packing density, faster on-chip communication


 But higher power density -> hotter chip
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Chiplets – 2.5D

Chiplet-based design

EE213 Topic0-Intro.44 https://en.wikichip.org/wiki/chiplet ShanghaiTech University


3D Carbon Nanotube Chips?

$61million !!!

The Electronics Max Shulaker Subhasish Mitra Philip Wong


MIT Stanford
Resurgence Initiative
EE213 Topic0-Intro.45 http://www.eri-summit.com/ ShanghaiTech University
#4: Security

Trojans

U
U D
D F

U
T

D: Design, F: Fabrication
T: Test, U: User

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#5: AI Chips

AlphaGo vs. Lee Sedol

Source: googleblog.com

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AI Chip – Google TPU

“Google一直坚信伟大的软件将在伟大的硬件的帮助下更加大放异彩,所以
Google便在想,我们可不可以做出一款专用机机器学习算法的专用芯片,TPU
便诞生了。”

[New York Times]


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Google TPU

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Big AI Placers

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#6: Open Source RISC-V

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Outline of Topic 0
 Course introduction
 Introduction to IC
• What is IC?
• The history of IC
• The current trends of IC
• The future of IC

 The status of IC in China

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CMOS Device Scaling Continues (ITRS)
But facing challenges and limiting!
90nm Node
2003 65nm Node
2005
45nm Node
2007
32nm Node
2009
22nm Node
50nm Length 2011
(IEDM2002) 16 nm node
30nm 25 nm
Prototype 2013
15nm
(IEDM2000) 20nm Prototype 11nm node
(VLSI2001) 2015
15nm Prototype 8 nm node
(IEDM2001) 2017
10nm Prototype 7nm
(DRC 2003)
5nm

3nm

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FinFET and GAA

Watch Prof. Chenming Hu’s Recorded Talk at SWEDCS’2016


Gate Fin
Why FinFET and What Next?
http://swedcs2016.shanghaitech.edu.cn/register.html

EE213 Topic0-Intro.56 https://www.eet-china.com/news/40a11532.html ShanghaiTech University


Technology Strategy/Roadmap

T. C. Chen, Where Si-CMOS is going: Trendy Hype vs. Real Technology, ISSCC’06

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Outline of Topic 0
 Course introduction
 Introduction to IC
• What is IC?
• The history of IC
• The current trends in IC
• The future of IC

 The status of IC in China

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IC Design/Fabrication/Test/Assembly Flow

EE213 Topic0-Intro.59 [Ozgur, NYU] ShanghaiTech University


Example of Globalized IC Value Chain
 Design – Europe, India and China
 Fabrication – Taiwan/South Korea
 Test, package – Taiwan/China Mainland
 Assembly – China Mainland

EE213 Topic0-Intro.60 [Digitimes and the Economist] ShanghaiTech University


Global/China’s IC Industry

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[Shaojun Wei, DAC 2017] ShanghaiTech University
Values of ICs Consumed in China
 Largest consumer in the world

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Electronic Device Production in China

Large portions are “Made in China”

EE213 Topic0-Intro.63 [Shaojun Wei, DAC 2017] ShanghaiTech University


Few IC Products from Indigenous Suppliers

EE213 Topic0-Intro.64 [Shaojun Wei, DAC 2017] ShanghaiTech University


2021: $432.6 Billion!
 Since 2013, China’s import of ICs > $200 billion.

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Top Semiconductor Players

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Future IC in China

《中国制造 2025》提出:2020年中国芯片自给率要达到40%,
2025年要达到70%,但目前国内的自给率仍为10%左右,
因此接下来几年中国半导体将迎来跨越式大发展。
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Investment Funds in China

EE213 Topic0-Intro.72 [Shaojun Wei, DAC 2017] ShanghaiTech University


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“中国IC设计现在不缺市场、不缺资本、最缺的是人才”

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“中美之争,其实是人才之争”

 我国芯片自给率目前不到30%,尤其是高端芯片方面,对外依赖严重,
而“缺芯”的一个重要原因,就是缺乏芯片的设计和制造人才。
 《中国集成电路产业人才白皮书(2019—2020年版)》指出,我国集
成电路人才在供给总量上仍显不足,到2022年,芯片专业人才缺口仍
将近25万。
 2020年,华为创始人任正非造访东南大学、南京大学等高校时表示:“
点燃未来灯塔的责任无疑是要落在高校上,而高校就是为社会输出人才
的地方,中国芯片的崛起必然需要人才的努力。”
 2020年7月30日,国务院学位委员会会议投票通过提案:集成电路专业
成为一级学科,从电子科学与技术一级学科中独立出来,将为我国培养
更多的芯片人才。
 目前在芯片相关人才学历方面,本科生占比73.76%,硕士及以上学历
仅占6.53%。
EE213 Topic0-Intro.78 ShanghaiTech University
Major Institutions Conducting IC Research in China

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National Lab/IC Industry around ShanghaiTech
张江集成电 上海超级 张江人工
路产业区 计算中心 智能岛
上海中医药大学 复旦张江校区 张江药谷
上海同
步 交大张江校区 新药研发 张江中区
辐射光 国家蛋白质 平台 文创空间
中科院微小卫星
源 科学中心· 张江中区
创新研究院 众创空间
上海 中科路站

中国科学院
上海高等研究院 上海市三大先导产业
(张江实验室)
人工智能

集成电路

生物医药

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IC Industry around ShanghaiTech
 上海集成电路从业人员占全国40%,人才缺口超过10万。
华为
 上海电子/集成电路一级博士点不足10个,人才供应严重不足。 海思
集成电路设计产业园(紫光集团、
阿里巴巴、威尔股份、兆易创新等
复旦 )
微电子 上海韦
凯世通 中芯国 尔上海微电
际 子装备
技 创 兆芯
紫光
集成电路企业
博通 600余家
展锐
科 华大
新 大疆 华虹宏力
日月光
从业人数 20万人
产值 1450亿 上海
合 性国家 中
高通 盛美 、华力
人工智能岛
海 科 美光 (上海平头哥)
综 学 超威
张江
江 中
上海科技大学
AMD
上 实验室 张江实验室 心
张 心
15公里

1. 集成电路产业最集中
2. 综合技术水平最高
3. 产业链最完整

华力二期

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Clean Room@ShanghaiTech

1500m2 下一代量子器件加工平台
梯队完备的科研工程团队

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Questions?

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