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17.5 GPIO Registers

NOTE: The GPIO registers in this chapter are duplicated in each GPIO block; however, depending
on the block, all eight bits may not be connected to a GPIO pad. In those cases, writing to
unconnected bits has no effect, and reading unconnected bits returns no meaningful data.
See the device-specific data sheet for the GPIOs included on any given device.

The offset is a hexadecimal increment to the register's address, relative to the base address of that GPIO
port:
• GPIO Port A (AHB): 0x40058000 (ending address of 0x40058FFF)
• GPIO Port B (AHB): 0x40059000 (ending address of 0x40059FFF)
• GPIO Port C (AHB): 0x4005A000 (ending address of 0x4005AFFF)
• GPIO Port D (AHB): 0x4005B000 (ending address of 0x4005BFFF)
• GPIO Port E (AHB): 0x4005C000 (ending address of 0x4005CFFF)
• GPIO Port F (AHB): 0x4005D000 (ending address of 0x4005DFFF)
• GPIO Port G (AHB): 0x4005E000 (ending address of 0x4005EFFF)
• GPIO Port H (AHB): 0x4005F000 (ending address of 0x4005FFFF)
• GPIO Port J (AHB): 0x40060000 (ending address of 0x40060FFF)
• GPIO Port K (AHB): 0x40061000 (ending address of 0x40061FFF)
• GPIO Port L (AHB): 0x40062000 (ending address of 0x40062FFF)
• GPIO Port M (AHB): 0x40063000 (ending address of 0x40063FFF)
• GPIO Port N (AHB): 0x40064000 (ending address of 0x40064FFF)
• GPIO Port P (AHB): 0x40065000 (ending address of 0x40065FFF)
• GPIO Port Q (AHB): 0x40066000 (ending address of 0x40066FFF)
• GPIO Port R (AHB): 0x40067000 (ending address of 0x40067FFF)
• GPIO Port S (AHB): 0x40068000 (ending address of 0x40068FFF)
• GPIO Port T (AHB): 0x40069000 (ending address of 0x40069FFF)
Note that each GPIO module clock must be enabled before the registers can be programmed (see
Section 4.2.87). There must be a delay of 3 system clocks after the GPIO module clock is enabled before
any GPIO module registers are accessed.
The table below shows special consideration GPIO pins. Most GPIO pins are configured as GPIOs and
high-impedance by default (GPIOAFSEL = 0, GPIODEN = 0, GPIOPDR = 0, GPIOPUR = 0, and
GPIOPCTL = 0). Special consideration pins may be programed to a nonGPIO function or may have
special commit controls out of reset. In addition, a Power-On-Reset (POR) returns these GPIO to their
original special consideration state.

Table 17-4. GPIO Pins With Special Considerations

GPIO Pins Default Reset GPIOAFSEL GPIODEN GPIOPDR GPIOPUR GPIOPCTL GPIOCR
State
PC[3:0] JTAG/SWD 1 1 0 1 0x1 0
PD[7] GPIO (1) 0 0 0 0 0x0 0
(1)
PE[7] GPIO 0 0 0 0 0x0 0
(1)
This pin is configured as a GPIO by default but is locked and can only be reprogrammed by unlocking the pin in the GPIOLOCK
register and uncommitting it by setting the GPIOCR register.

The GPIO commit control registers provide a layer of protection against accidental programming of critical
hardware signals including the GPIO pins that can function as JTAG/SWD signals and the NMI signal. The
commit control process must be followed for these pins, even if they are programmed as alternate
functions other than JTAG/SWD or NMI; see Section 17.3.4.

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NOTE: If the device fails initialization during reset, the hardware toggles the TDO output as an
indication of failure. Thus, during board layout, designers should not designate the TDO pin
as a GPIO in sensitive applications where the possibility of toggling could affect the design.

The default register type for the GPIOCR register is read-only for all GPIO pins with the exception of the
NMI pin and the four JTAG/SWD pins (see the device-specific data sheet for pin numbers). These six pins
are the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for the
corresponding GPIO Ports is RW.
The default reset value for the GPIOCR register is 0x000000FF for all GPIO pins, with the exception of the
NMI and JTAG/SWD pins (see the device-specific data sheet for pin numbers). To ensure that the JTAG
and NMI pins are not accidentally programmed as GPIO pins, these pins default to noncommittable.
Because of this, the default reset value of GPIOCR changes for the corresponding ports.
Table 17-5 lists the memory-mapped registers for the GPIO. All register offset addresses not listed in
Table 17-5 should be considered as reserved locations and the register contents should not be modified.

Table 17-5. GPIO Registers

Offset Acronym Register Name Section
0x0 GPIODATA GPIO Data Section 17.5.1
0x400 GPIODIR GPIO Direction Section 17.5.2
0x404 GPIOIS GPIO Interrupt Sense Section 17.5.3
0x408 GPIOIBE GPIO Interrupt Both Edges Section 17.5.4
0x40C GPIOIEV GPIO Interrupt Event Section 17.5.5
0x410 GPIOIM GPIO Interrupt Mask Section 17.5.6
0x414 GPIORIS GPIO Raw Interrupt Status Section 17.5.7
0x418 GPIOMIS GPIO Masked Interrupt Status Section 17.5.8
0x41C GPIOICR GPIO Interrupt Clear Section 17.5.9
0x420 GPIOAFSEL GPIO Alternate Function Select Section 17.5.10
0x500 GPIODR2R GPIO 2-mA Drive Select Section 17.5.11
0x504 GPIODR4R GPIO 4-mA Drive Select Section 17.5.12
0x508 GPIODR8R GPIO 8-mA Drive Select Section 17.5.13
0x50C GPIOODR GPIO Open Drain Select Section 17.5.14
0x510 GPIOPUR GPIO Pullup Select Section 17.5.15
0x514 GPIOPDR GPIO Pulldown Select Section 17.5.16
0x518 GPIOSLR GPIO Slew Rate Control Select Section 17.5.17
0x51C GPIODEN GPIO Digital Enable Section 17.5.18
0x520 GPIOLOCK GPIO Lock Section 17.5.19
0x524 GPIOCR GPIO Commit Section 17.5.20
0x528 GPIOAMSEL GPIO Analog Mode Select Section 17.5.21
0x52C GPIOPCTL GPIO Port Control Section 17.5.22
0x530 GPIOADCCTL GPIO ADC Control Section 17.5.23
0x534 GPIODMACTL GPIO DMA Control Section 17.5.24
0x538 GPIOSI GPIO Select Interrupt Section 17.5.25
0x53C GPIODR12R GPIO 12-mA Drive Select Section 17.5.26
0x540 GPIOWAKEPEN GPIO Wake Pin Enable Section 17.5.27
0x544 GPIOWAKELVL GPIO Wake Level Section 17.5.28
0x548 GPIOWAKESTAT GPIO Wake Status Section 17.5.29
0xFC0 GPIOPP GPIO Peripheral Property Section 17.5.30
0xFC4 GPIOPC GPIO Peripheral Configuration Section 17.5.31
0xFD0 GPIOPeriphID4 GPIO Peripheral Identification 4 Section 17.5.32
0xFD4 GPIOPeriphID5 GPIO Peripheral Identification 5 Section 17.5.33
0xFD8 GPIOPeriphID6 GPIO Peripheral Identification 6 Section 17.5.34

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Table 17-5. GPIO Registers (continued)

Offset Acronym Register Name Section
0xFDC GPIOPeriphID7 GPIO Peripheral Identification 7 Section 17.5.35
0xFE0 GPIOPeriphID0 GPIO Peripheral Identification 0 Section 17.5.36
0xFE4 GPIOPeriphID1 GPIO Peripheral Identification 1 Section 17.5.37
0xFE8 GPIOPeriphID2 GPIO Peripheral Identification 2 Section 17.5.38
0xFEC GPIOPeriphID3 GPIO Peripheral Identification 3 Section 17.5.39
0xFF0 GPIOPCellID0 GPIO PrimeCell Identification 0 Section 17.5.40
0xFF4 GPIOPCellID1 GPIO PrimeCell Identification 1 Section 17.5.41
0xFF8 GPIOPCellID2 GPIO PrimeCell Identification 2 Section 17.5.42
0xFFC GPIOPCellID3 GPIO PrimeCell Identification 3 Section 17.5.43

Complex bit access types are encoded to fit into small table cells. Table 17-6 shows the codes that are
used for access types in this section.

Table 17-6. GPIO Access Type Codes

Access Type Code Description
Read Type
R R Read
Write Type
W W Write
W1C 1C 1 to clear
W Write
Reset or Default Value
-n Value after reset or the default
value

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