An 11106
An 11106
An 11106
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Abstract This application note provides a Failure Modes and Effects Analysis (FMEA) for Nexperia's AHC/
AHCT family under typical failure situations
Nexperia AN11106
Pin FMEA for AHC/AHCT family
1. Introduction
The Advanced High-Speed CMOS (AHC and AHCT) family of logic devices from Nexperia
Semiconductors, offers many of the same functions found in the High-Speed CMOS (HC and HCT)
family. However, it has higher performance and lower power consumption than the HC/HCT while
maintaining competitive prices. In addition, Nexperia Semiconductors guarantees AHC/AHCT
products to operate over an extended temperature range of -40 °C to +125 °C. The increase in
product specification is at no extra cost to the customer..
The AHC/AHCT family of products is ideally suited for notebooks, telecom infrastructure, and
portable applications. The capability to operate at both 5 V and 3.3 V, further extends its integration
into new designs. The dual voltage facilitates the migration of existing designs to low-voltage
systems and establishes it as a truly mixed-voltage product.
The AHC/AHCT family includes gates, octals, MSI, and 16 bit-wide devices. It is both functionally
and pin-for-pin compatible with the HC/HCT family of products.
2. Pin FMEA
This chapter provides a Failure Modes and Effects Analysis (FMEA) for the device pins of
Nexperia’s AHC/AHCT family under typical failure situations such as a short-circuit to VCC or GND
or to a neighboring pin, or if a pin is left open.
A failure is classified according to its effect on the AHC/AHCT device and the functionality of the
application; see Table 1.
AN11106 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
AN11106 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
3. Abbreviations
Table 6. Abbreviations
Acronym Description
AHCT Advanced High-Speed CMOS TTL
CMOS Complementary Metal-Oxide Semiconductor
FMEA Failure Modes and Effects Analysis
LSTTL Low power Schottky TTL
TTL Transistor-Transistor Logic
4. Revision history
Table 7. Revision history
Rev Date Description
v.2 20190109 AN11106, updated to latest Nexperia documentation standard
v.1 20111104 AN11106 initial version
AN11106 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
5. Legal information
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for the products described herein shall be limited in accordance with the
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specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
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Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
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suppliers accept no liability for inclusion and/or use of Nexperia products in
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Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
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for the planned application and use of customer’s third party customer(s).
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Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
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AN11106 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
List of Tables
Table 1. Classification of failure effects................................2
Table 2. FMEA matrix for pin short-circuit to VCC............... 2
Table 3. FMEA matrix for pin short-circuit to GND............... 3
Table 4. FMEA matrix for pin left open................................ 3
Table 5. FMEA matrix for pin short-circuits between
neighbor pins........................................................................3
Table 6. Abbreviations..........................................................4
Table 7. Revision history......................................................4
AN11106 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Contents
1. Introduction................................................................... 2
2. Pin FMEA.......................................................................2
3. Abbreviations................................................................ 4
4. Revision history............................................................4
5. Legal information......................................................... 5
AN11106 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved