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Published in IET Power Electronics
Received on 6th June 2011
Revised on 20th March 2012
doi: 10.1049/iet-pel.2011.0215

ISSN 1755-4535

Diode – capacitor voltage multipliers combined with

boost-converters: topologies and characteristics
B. Axelrod Y. Berkovich A. Shenkman G. Golan
Holon Institute of Technology, 52 Golomb Street, Holon 58102, Israel
E-mail: [email protected]

Abstract: Various topological modifications of diode – capacitor voltage multipliers are considered. All the topologies are based
on two known schemes: Cockcroft – Walton and Dickson. These topologies are built combined with a boost-converter, operating
at a high switching frequency. Such a solution allows reducing the values of the capacitors. The proposed topologies can also be
used by feeding them directly from a three-phase network through the regular rectifier; in this case the influence of such circuits on
a supply network is reduced. A number of novel modifications of multipliers, having their specific features, are obtained. The
procedure of calculating the output voltage, depending on the capacitor values and load parameters is proposed and the
design formulas for the output voltage of some of the schemes are developed. It is shown that a decrease in the output
voltage is caused by some sort of internal resistance. The essentially similar operating modes of different topologies are
characterised by a different value of such a resistance, and accordingly by a different internal voltage drop. Dynamic models
for some of the proposed topologies are also developed. The computer simulation and the experimental results proved the
theoretical expectations.

1 Introduction high-voltage transformer. A discrete dynamic model of a

Dickson voltage multiplier is presented in [10, 11]. In
Diode – capacitor voltage multipliers, having a long and [12, 13] an analysis of the on-chip high-voltage generator
interesting history, are widely used as transformer-less high- circuits is performed.
voltage DC sources [1 – 3]. The field of application of such In [14, 15] the diode – capacitor voltage multiplier is applied
multipliers is rather wide. For instance, they are used in in combination with an intermediate high-frequency link, so
telecom standard equipment providing Internet services, that the multiplier is fed not directly from an industrial
where the 48 V of the DC battery plant has to be boosted to network, but through an additional rectifier– inverter of
a 380-V intermediate DC bus [4]. They can also be used in high frequency. As a result the values of the multiplier
X-ray systems, electrostatic systems and lasers. The recently capacitors can be considerably reduced. It has also been
growing interest in renewable sources, such as photovoltaic proposed to interpret the decrease of the underload output
(PV) systems, fuel cells, etc. will greatly increase the voltage as a result of some internal resistance, despite
demand on such DC voltage multipliers. There are many the fact that none of the resistors is actually connected in the
configurations of DC voltage multipliers, based on circuit. This idea is proven and further developed in the
Cockcroft – Walton and Dickson cells, which have been present study. In [16] a high-frequency link as a boost
proposed and analysed in numerous technical publications. converter, rather than a high-frequency inverter is performed,
Thus, a DC – DC converter topology based on a boost and the multiplier cells are connected to its output. In this
converter connected to the Cockcroft– Walton multiplier is case the high frequency is obtained in a simpler way. In [17]
presented in [5, 6]. A boost converter with a coupled the description and simplified analysis of two new types
inductor and Cockcroft – Walton voltage multiplier is of voltage multipliers, based on some different type of
presented in [7]. The secondary voltage of the coupled connections of diode – capacitor cells, are given. Such
inductor is rectified using a voltage multiplier. A multiplier new topologies result in a little higher value of output
built on a boost-converter and Dickson cell with a resonant voltage, when the values of the duty cycle, D, of the boost
inductor is presented in [8]. The main advantages of the converters’ operation are raised. In the present study
proposed structure are high static gain without the use of a these schemes are presented as a result of topological
transformer, low-voltage stress and zero-current switching transformations of two basic circuits.
(ZCS) turn-on commutation. A bipolar Cockcroft–Walton The study contains the following sections. In Section 2,
voltage multiplier is proposed in [9]. It is formed by the different topological transformations, performed on
combining positive and negative voltage multipliers the basis of two elementary schemes of diode – capacitor
consisting of an equal number of stages and driving in multipliers, namely Cockcroft – Walton and Dickson, and
parallel by an AC voltage source. Since it requires only some general features of the proposed new multipliers are
one AC power source, there is no need for a centre taped given. In Section 3, the detailed analysis of an operating

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mode of the Dickson scheme in combination with the constructed by connecting two A cells accordingly in
boost-converter is presented. The analysis of the external positive and negative poles of the boost-converter and is
characteristic, the expressions for internal voltage drop, the designated as A + A. The topology (7), B + B, is obtained
maximum value of efficiency and the simplified dynamic in the same way. Topology (3) is designated as A × A. As
model of such a multiplier are also given in this section. can be seen, this topology is made by a cross connection of
Section 4 is devoted to the similar analysis of a more the capacitors of two A schemes, connected between two
complicated topology based on the Dickson scheme. The poles of a boost converter, and separated by diodes, which
experimental results are presented in Section 5. now are connected in cascade. Topology (8) is obtained in
the same way as topology (3) by interchanging the
capacitors and diodes. Since the capacitors now are
2 Basic schemes and their topological connected in cascade and the diodes are connected in
transformations parallel branches, this topology, somehow, looks as if it is
In this section the possibility of the construction of new based on scheme B and is designated as B × B.
topologies, based on two well-known schemes, Dickson It is also possible to connect in the two poles of the boost-
(Fig. 1a) and Cockcroft – Walton (Fig. 1b) will be converter identical types of schemes with a different number
introduced. These two schemes became widespread so that of cells. In such a way the topologies (4) mA + A and (9)
obtaining new topologies, based on them, is of scientific mB + B are obtained. Finally by combining in one voltage
and practical interest. In power electronic applications multiplier two different types of cells, two more topologies
feeding the voltage multiplier directly from the industrial (5), A + B, and (10), A × B, are made. In the schemes
frequency network is problematic and not useful. First of A × A and B × B one cell will be understood as a
all, because of the large size of the capacitors because of combination of two capacitors and two diodes and the
the low operating frequency (50 – 60 Hz) and second of all, number of cells will be designated as N.
because the pulsating current, which is consumed by the Each of the new topologies has its own ripple level, which
multiplier, is polluting the network. Therefore, to avoid does not exceed the approximate value of (2/n)Vo , where Vo
these shortcomings topologies, which combine the boost is the output voltage (see further on item (5) of the
converter and the diode –capacitor multiplier, are proposed. topologies’ features and Table 1), so that for a large n, the
In this case such topologies can be fed from industrial ripple level will be acceptable. However, for better
networks, and particularly from the three-phase network, operation, all the topologies have an additional output LC
through regular rectifiers. filter (see further discussion).
In the following study the Dickson cell will be designated
as A, and Cockcroft– Walton cell will be designated as 2.1 Some general features of the specified
B. Note that both schemes have the same number of diode – topologies can be indicated
capacitor cells with the only difference being that if scheme
A has n cells (to be specific, we consider n as an odd 1. In schemes A + A and B + B the potentials of the positive
number), then scheme B has (n + 1) cells. The topologies and negative poles of the load, relative to the ground, which in
created by a bigger or smaller number of cells are not the all topologies is the negative input pole, is twice as low as
considered as separate topologies. However, to show the in each of basic schemes A or B, with a double number of cells
differences, they will be designated as mA or mB (The as in each pole of A + A or B + B. This happens because in
symbol ‘m’ indicates that the number of cells in one of the such schemes each multiplier, which is connected to the
A schemes is different from the other by ‘m,’ whereby ‘m ’ input poles, multiplies their potentials: one the positive and
can be fractional. For example, if the number of cells in the other the negative, so that the potential difference, that
scheme A is 5 and the number of the cells in mA is 7, then is the output voltage, will be equal to the voltage of basic
the value of m will be 7/5. schemes, without enlarging the potential relative to the
All the created topologies are shown in Fig. 2, where ground. (Note that input voltage, Vin , is very small relative
topologies 1 – 5 are based on scheme A and topologies to the output voltage so that it will not, practically,
(6) – (10) are based on scheme B. A new topology (2) is influence the output positive potential.)
2. Although in each of the basic schemes A and B, the
number of cells are odd (scheme A) or even (scheme B),
the total number of cells in the newly formed A + A, B + B,
mA + A and mB + B schemes will always be even (except
scheme 5, A + B, where the number of cells is odd).
Indeed, since the number of cells in A is odd and in B it is
even, then the number of cells in A + B will be odd). In the
schemes A × A, B × B and A × B, in which each cell is
considered as consisting of two diodes and two capacitors,
the number of such cells will also be odd. Note that the
number of cells in such schemes is designated by N.
3. In all the schemes there is a mode of capacitor recharge
through the switch, through the diodes, and also through the
parasitic elements of the scheme (resistances and
inductances), so that power losses in the parasitic resistances
take place. Below, these power losses will be determined and
it will be shown that, by increasing the capacity of the
Fig. 1 Two basic AC-DC voltage multipliers capacitors, they can be reduced to a pretty small value.
a Dickson 4. More topologies can be made depending on how the load
b Cockcroft–Walton in scheme (6) is connected: either (1) between points ‘a ’ and

874 IET Power Electron., 2012, Vol. 5, Iss. 6, pp. 873 –884
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Fig. 2 Basic and some created topologies

Table 1 Ideal voltage ratios for some topologies

0 or (2) between points ‘b ’ and 0, herewith also on the
Type A B A×A B×B direction of the diodes. In particular, in the scheme (6) the
n+1 1 n 1 1 1 load is connected between points ‘a ’ and 0, and the scheme
V (N + D) (N + D) (7), that is B + B topology, is made by using two such
M= o 2 (1 − D) 2 (1 − D) 1−D 1−D
Vin schemes. However, combination (7) can also be performed
(n − odd) (n − even) (N − odd) (N − odd)
by using two schemes of choice (2).

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5. Since the source of the ripples in all the topologies is the
square form of voltage of the boost converter, the ripple
value of the basic schemes, is Vin/(1 2 D). In the n-cell
multipliers, having the output voltage Vo ¼ Vin(n + 1)/
2(1 2 D) or Vo ¼ Vinn/2(1 2 D). The ripple level,
normalised to output voltage, Vo , will be inversely smaller,
that is 2/(n + 1) or 2/n, or with a large n, approximately
just 2/n (see Table 1). The ripple level in the formed
topologies will be even lower; so that we can define it is as
acceptable. However, all the topologies have an additional
output LC filter.
6. Each of the topologies has its own value of inner
resistance, which means a different voltage drop, and each
one has its own dynamic model.
7. Topologies A × A and B × B give a somewhat larger
output voltage for the same number of cells. Note also, that
topologies A × A and B × B are more appropriate to use
with an odd number of cells, since an additional even cell
does not provide any significant increase in the output
voltage [17]. Schemes A + A and B + B are preferable
because of the lower output poles potentials (as has been
explained above) with the same output voltage and the
same number of cells.

Two of the above topologies (Fig. 2) are further analysed in

detail, namely scheme A, as a basic scheme, and scheme
A × A, as having a distinctive structure with crossconnected
capacitances. For the reader’s convenience the ideal voltage
ratios for the schemes, having ideal elements and output Fig. 3 Switching topologies for the multiplier of type A for
load, Ro , for the main topologies, are given in Table 1 a First
[16, 17]. b Second
c Third time intervals

3 Output characteristics of the A-type

voltage multiplier, taking into consideration
the inner voltage drops
3.1 Output voltage

An analysis of the three-cell circuit will be made, as an

example, of scheme A (Fig. 2). The switching topologies of
the above circuit are shown in Fig. 3 and the corresponding
timing diagram is shown in Fig. 4. It should also be
mentioned that all the diodes are assumed to be ideal and
the effects of parasitic capacitances are neglected here and
throughout the whole study.
The operation period can be divided into three time
intervals:

1. t0 2 t1: At t0 switch S is turned-off. The current iL , which

is also input current, Iin , flows through two parallel branches.
Since the capacitances are ideal, current iC2 arises instantly
when the switch turns off at the moment t ¼ t0 . Current iC1
charges capacitor C1, while the current iC2 discharges partly
capacitor C2 and recharges capacitor C3 .
2. t1 2 t2: At t1 switch S turns on and diode D1 stops
conducting, while diode D2 turns into a conducting mode.
As a result, two capacitors C1 and C2 are short-circuited via
diode D2 and switch S. The short negative current pulse
aligns the voltages of the capacitors C1 and C2 , which
become equal, since the capacitances become connected in
parallel. Capacitor C3 discharges through the load.
3. t2 2 t3: After the voltages across capacitances C1 and C2
become equal, currents iC1 and iC2 stop flowing and the
voltages on capacitors C1 and C2 remain constant and
equal. Capacitor C3 continues discharging through the load. Fig. 4 Time diagrams of the multiplier of type A

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For a small load and big capacitors, and neglecting the according to (1) we may write
voltage drop in the elements of the scheme, see Table 1 and
[16], the output voltage of the circuit is defined by its ideal Vo2 4Vin2
voltage ratio. For three capacitors it gives Vin Iin = Vo Io = =
Ro (1 − D)2 Ro
Vo 2
M3 = = (1) Therefore
Vin 1 − D
4Vin
Now, we will consider the inner voltage drops and losses of Iin = IL = (8)
(1 − D)2 Ro
the scheme. In the first interval the capacitance C1 is
connected in parallel with two capacitances C2 and C3
(Fig. 3a) so that, averaging through the interval the voltages And substituting this into (7), we obtain the expression for the
across the capacitances, we can write voltage drop

2Vin toff
VC1,av = VC3,av − VC2,av (2) DV = (9)
(1 − D)2 Ro C
On the other hand, since the voltage across capacitance C1 is
equal to the average, on period T, of the switch voltage, that is or since toff ¼ (1 2 D)T ¼ (1 2 D)/f, we finally have
of the voltage across the switch.
2Vin
DV = (10)
Vin (1 − D)Ro Cf
VC1,av = (3)
1−D
Substituting (10), into (6) and with VC3,av ¼ Vo we obtain the
we may write for the voltage across C3 output voltage, Vo,DV, by taking into consideration the inner
voltage drops
Vin  
VC3,av = VC2,av + (4) 2Vin 1
1−D Vo,DV = 1− (11)
1−D Ro Cf
From the time diagram in Fig. 4 it follows that
In the general case, for the n capacitor circuit, on the interval
t0 2 t1 , there are (n + 1)/2 parallel branches, therefore the
VC2,av = VC1,av − DV (5) ideal output voltage will be ((n + 1)/2)Vin/(1 2 D).
However, since the voltage drop, DV, takes place in the
where DV is the change of the capacitor voltage during the second interval, that is in the second scheme (Fig. 3b),
first time interval. where the number of branches is equal to (n 2 1)/2, the
Substituting (5) into (4) and again considering (3), we have total voltage drop will have the coefficient (n 2 1)/2 and
the output voltage becomes
2Vin  
VC3,av = − DV (6) n+1 n−1 1
1−D Vo,DV =
V
× in 1− (12)
2 1−D 2 Ro Cf
Next we will take into consideration the process of charging/
discharging the capacitors. For the infinitesimal differences Taking into account the voltage drops on n diodes, we may
and neglecting the load current, which is much smaller than finally write
the input current, Iin , (because it is in reverse proportion to
the output voltage), we may use for the current through the  
n+1 V n−1 1
capacitance the expression IC ¼ C(DVC/Dt), where in the Vo,DV = × in 1 − × − nDVD (13)
first time interval Dt ¼ toff , and write specifically for the 2 1−D 2 Ro Cf
charging currents
The normalised output voltage will be
DVC1 C2,3 DVC2 + DVC3  
IC1 = C1 and IC2,3 = Vo,DV n−1 1
toff 2 toff vo,DV = = 1− × − nDvD
V 2 Ro Cf
 B 
Now, considering that during the interval t0 2 t1 ¼ toff the n−1
= 1− − nDvD (14)
capacitor currents iC1 ≃ iC2 , we obtain 2ro

IL toff where
DV = (7)
2C  
DVD n+1 1
DvD = ; VB = Vo,ideal = × V ;
where IL is the input inductor current (we assume VB 2 1 − D in
IL ≃ constant).
1 V V I R
Considering first that the input and output powers are RB = ; I o = B I B = B ; i o = o ; ro = o
equal, Pin ¼ Pout , which means that VinIin ¼ VoIo and Cf Ro RB IB RB

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The output curves, vo ¼ f (io) ¼ 1 2 (n 2 1)io /2, for n ¼ 3; Since the power losses during the other time intervals
n ¼ 5; n ¼ 7; n ¼ 9 DvD ¼ 0 are shown in Fig. 5. are negligibly small, and since (8) Pin = 4Vin2 /((1 − D)2 Ro ),
we may determine the ideal efficiency of the scheme as
3.2 Inner resistance and ideal efficiency follows

Considering first the three diode – capacitor cells, we may Po Pin − DP 1

recognise that h= = =1− (21)
Pin Pin Ro Cf
1. at t ¼ t2 the capacitor voltages VC1 ¼ VC2 ¼ V, that the
total energy, accumulated in these two capacitors will be For the n diode – capacitor scheme the change of the capacitor
voltage during the interval t0 2 t1 is
CV 2 n+1
WC1,C2 (t2 ) = 2 = CV 2 (15) DVi,n =
V
× in ×
1
(22)
2 2 1 − D Ro Cf
2. at t ¼ t1 , however, the total energy of these two capacitors
was greater, that is and the energy change during the interval t1 2 t2 on one pair
of capacitors will be DWi = CDVi2 . Therefore, for (n 2 1)/2
pairs of capacitors the total energy change becomes
C(V + DV )2 C(V − DV )2
WC1,C2 (t1 ) = +
2 2
n−1 (n + 1)2 (n − 1) Vin2
= C(V + DV )
2 2
(16) DWtot,n = DWi,n = ×
2 2×4 (1 − D)2 R2o Cf 2
(23)
Thus, the change of energy during this short-circuited interval
of operation is and the total power losses will be

DW = CDV 2 (17) DWtot,n (n + 1)2 (n − 1) Vin2

DPtot,n = = × (24)
T 2×4 (1 − D)2 R2o Cf
This difference of energy has been released in the form of
power losses in the circuit elements. With (10), it becomes
which gives the ideal efficiency as
4Vin2
DW = (18) Pin,n − DPtot,n n−1 1
(1 − D)2 R2o f 2 C hn = =1− × (25)
Pin,n 2 Ro Cf
and the average power losses are
Here Pin,n is found as
DW 4Vin2
DP = = (19) 2
T (1 − D)2 R2o Cf Vo,n (n + 1)2 Vin2
Pin,n = = ×
Ro 4 (1 − D)2 Ro
Now we can estimate the inner resistance, which corresponds
to these losses. With the input current (8) we have where for Vo see Table 1.

DP (1 − D)2 3.3 Dynamic model

Rin = = (20)
Iin2 4Cf
The dynamic model of the multiplier under consideration (an
equivalent circuit) is built by using two basic principles: (1)
All the parameters are referred to the output voltage, like in
a conventional transformer (note that the diode –capacitor
voltage multiplier changes DC voltage just like the classical
transformer changes AC voltage) and (2) The equivalent
parameters of the model, shown in Fig. 6, a primarily
equivalent capacitor, are estimated on the principal of
energy consumption. Following the first principle, the

Fig. 5 Output voltage vo,DV of A-type multiplier against output

current io for a various number of cells: (1) n ¼ 3; (2) n ¼ 5; (3)
n ¼ 7 and (4) n ¼ 9; DvD ¼ 0 Fig. 6 Equivalent circuit of an A-type multiplier

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parameters Lin , Rin are referred to the output of the multiplier where S1(n) (see the appendix) is the sum of the numbers
of a natural sequence in the form of S1(n) ¼ 12 + 22 + . . . +
Leq = Mn2 Lin ; Req = Mn2 Rin (26) ((n + 1)/2 2 1)2 + (1/2)((n + 1)/2)2.
With (28) for n cells, in the ideal case (DV ¼ 0 and
where Mn is the ideal voltage ratio (1) and Rin is the inner VC1,t2  (VC1,t2)av) we can write
resistance (20).
The input voltage of the equivalent circuit is the same as  
the input voltage of the multiplier referred to the output, 1 n+1 2
W2 = Co,eq (VC1,t2 )2av = S2 (n)Co,eq (VC1,t2 )2av (31)
that is Vin,eq ¼ MnVin and the output equivalent resistance is 2 2
just the load resistance: Ro,eq ¼ Ro .
Following the second principle, let us first estimate the
equivalent capacitor of a three capacitor circuit (Fig. 2, A). Assuming that W1 ¼ W2 , we finally have
Since VC3(t2)  2VC1(t2), which follows from (3) and (6) by
neglecting DV, and since VC2(t2) ¼ VC1(t2), the total energy
accumulated in three capacitors at t ¼ t2 , (Fig. 4), is S1 (n)
Co,eq = C (32)
S2 (n)
1
W1 = [CVC1
2
(t2 ) + CVC2
2
(t2 ) + 4CVC1
2
(t2 )] = 3CVC1
2
(t2 ) (27)
2
As an example, an equivalent circuit as shown in Fig. 6, of
At the same time t = t2 the energy, stored in the equivalent basic multiplier A (Fig. 2), has been analysed. The
capacitance, is W2 = (1/2)Co,eq Vo2 and since at this time parameters of the given circuit are taken as: Vin ¼ 24 V;
Vo ¼ 2VC1 , we may write L ¼ 0.8 mH; C ¼ 1 mF; Ro ¼ 300 V; D ¼ 0.5; n ¼ 3;
f ¼ 50 kHz and the voltage ratio is calculated as follows:
W2 = 2Co,eq VC1
2
(28) M3 ¼ ((n + 1)/2) × (1/(1 2 D)) ¼ 4. Therefore, the parameters
of the equivalent scheme are: Co,eq ¼ 1.5C ¼ 1.5 mF;
Equating (27) and (28), gives Ro,eq ¼ Ro ¼ 300 V; Vin,eq ¼ M3Vin ¼ 96 V; Lin,eq = M32
Lin = 12.8 mH and Rin,eq = M32 Rin = 20 V, where Rin is
3 calculated in accordance with (20): Rin ¼ ((1 2 D)2/
Co,eq = C (29) 4Cf) ¼ 1.25 V. The transient behaviour of the above
2
dynamic model performed by the SPICE simulation is
For an n cell multiplier the equivalent Co,eq can be defined as shown in Fig. 7. In this figure Vo,DV and Iin are the
follows. simulation results for the multiplier given in the example,
First we calculate the energy and Vo,eq and MIin,eq are the computed results for its
equivalent circuit. As can be seen, the transient curve of the
W1 = C(VC1,t2 )2 + 4C(VC1,t2 )2 + 9C(VC1,t2 )2 + · · · multiplier is a decremented periodic function, having a
 2   period of approximately 1 ms and the whole process takes
n+1 1 n+1 2 place in approximately 2.5 ms. Such fast damping of the
+ − 1 C(VC1,t2 ) +2
C(VC1,t2 )2 transient process also indicates the presence of inner losses.
2 2 2
As also can be seen, both the simulation and computing
= S1 (n)C(VC1,t2 )2 (30) results are in good agreement.

Fig. 7 Simulated output voltage and current for the original and equivalent circuits of an A-type multiplier for n ¼ 3 during the transient
switching-on process

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4 Output characteristics of the A 3 A-type through the parallel connected capacitors of the third cell
voltage multiplier, taking into consideration C5 and C6 and partly through the output inductor. Capacitor
the inner voltage drops Co discharges to the load.
2. t1 2 t2 (Fig. 8b): Switch S is still turned-off, however now
4.1 Output voltage the conditions for the current flow through diodes D1 and D2
instead of diodes D5 and D6 were created. As a result,
It is also worthwhile to analyse some other configuration, for capacitors C3 , C4 , C5 and C6 are connected in series while
example, type A × A (Fig. 2), which is also based on the capacitors C1 and C2 are connected in parallel. From the
Dickson topology. The corresponding switching topologies computer simulation it also follows that the first two
and their time diagrams, which are the simplified results of the intervals are approximately equal in time.
computer simulation, are shown in Figs. 8 and 9. Here it is 3. t2 2 t3 (Fig. 8s): At t ¼ t2 switch S is turned-on. As a result
also assumed that all the diodes are ideal. The operation period a short negative current pulse flows via switch S. Capacitors
of this configuration can be divided into four time intervals C1 , C2 , C5 and C6 are connected in series, while capacitors
1. t0 2 t1 (Fig. 8a): At t ¼ t0 switch S is turned-off. The C3 and C4 are connected in parallel.
current Iin flows via all series connected capacitors of the 4. t3 2 t4 (Fig. 8d): The input current continues to flow
first and second cells (C1 , C2 , C3 and C4) and further on through the input inductor and closed switch S. All six

Fig. 8 Steady-state switching topologies of an A × A multiplier for the time intervals

a [t0 2 t1]
b [t1 2 t2]
c [t2 2 t3]
d [t3 2 t4]

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where n is the number of diode –capacitor cells (each of them
consists of two diodes and two capacitors).
For an arbitrary load and the selected value of the
capacitors we may write the following formulas. The total
energy of four capacitors C1 , C2 , C3 and C4 in a steady-
state regime at t ¼ t3 (Fig. 9) (note, that VC3 ¼ VC4 ¼ 2VC1) is

C
WC1,C2,C3,C4 (t3 ) = 2
(2VC1 + 2VC3
2
) = 5VC1
2
(33)
2

However at t ¼ t2 the total energy of these capacitors was

greater

C
WC1,C2,C3,C4 (t2 ) = (2(VC1 + DVC1 )2 + 2(VC3 − DVC3 )2 )
2
(34)

Since in interval t2 2 t3 the same current flows through

capacitors C1 and C2 , which are connected in series, and
through C3 and C4 , which are connected in parallel, their
voltage change becomes
 
1 
|DVC3 | =  DVC1  (35)
2

Note that capacitors C5 and C6 (during the time interval

(t2 – t3), are also connected in series with the inductor, Lo ,
and resistor, Ro , and not directly to the rest of the
Fig. 9 Time diagrams of A × A multiplier capacitors, so that their energy discharges through the
output inductor and the load, that is this energy partly
converts to the magnetic energy of the inductor and partly
capacitors are connected in series and the load current flows dissipates in the load. Therefore, this energy, practically,
through them. does not participate in the inner losses and does not
influence the inner voltage drop.
The analysis of the above switching topologies, is based Substituting (35) into (34), gives
on three principles: (1) there are two main situations in
which the switch is first open and then closed; (2) the  
C 1
diodes of the odd and even cells in such topologies WC1,C2,C3,C4 (t0 ) = 2(VC1 + DVC1 ) + 2(VC3 − DVC1 )
2 2

conductive alternatively, so that in schemes (a) and (b) the 2 2

diodes of the odd cells are in the conductive mode, and in 5
scheme (c) the diodes of the even cells. Note that in basic = 5CVC1
2
+ CDVC1
2
(36)
4
schemes the odd diodes conduct in the same time interval.
However, here, in accordance with the computer simulation, Thus, the change of energy of two capacitor groups during the
the diodes of the third and the first cells conduct in two third interval is
different intervals, as shown in Fig. 8, although the time
difference between these two intervals is very short. Finally,
5
the third principle says that after discharging capacitors C1 DWC1,C2,C3,C4 = CDVC1
2
(37)
and C2 on capacitors C3 and C4 the voltages across all of 4
them even out so that all the diodes turn-off and the fourth
time topology comes into being. This energy happens to be released in the form of power
Being inversely proportional to the output voltage, in losses on the parasitic resistive elements of the circuit. The
accordance with the expression Iin/Io ¼ Vo/Vin ¼ M, where voltage change of the capacitor C1 , (DVC1), during this time
M is large, the output current in scheme (d) is small, interval t2 2 t3 in the steady-state mode is equal and
relative to the input current. Because of that, as can be seen opposite to its change during three other intervals:
from the time diagram, Fig. 9, the voltages across the t0 2 t1 ,t1 2 t2 and t3 2 t4 (Fig. 9).
capacitances practically do not change. Note also, that since
the diodes are ideal, the ripple of the currents are absent DVC1 = DVC1,t0−t1 + DVC1,t1−t2 + DVC1,t3−t4
and they look, on the time diagram, as straight lines.  
Capacitor Co continues to be discharged through the load. 1 I − Io
= Iin (t1 − t0 ) + in (t2 − t1 ) − Io (t4 − t3 )
The ideal voltage ratio, in this case, will be as given in Table 1 C 2
and [17], that is (38)

N +D With the obvious relationship VinIin ¼ VoIo we may write

Mn =
1−D M3 ¼ Vo/Vin ¼ Iin/Io and for the ideal output voltage and for

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N ¼ 3 we have been found for the output current Io ¼ Vo/Ro (where Vo is
the maximal output voltage in the ideal case). For the
Vo Iin 3 + D Vo M3 Vin actual output voltage, which is lower than an ideal, the
M3 = = = ; Io = = ; inner voltage drop also decreases, so that factor ‘5’ in
Vin Io 1 − D Ro Ro
(47) should be reduced to 3 –4 (especially for bigger
M32 Vin loads). The value of the output voltage can be calculated
Iin = M3 Io = (39) more precisely by the step-by-step approach according to
Ro
(38). (The real output voltage calculation for the scheme
and also the time intervals A × A in the general case of N cells is the subject of
special research.)
D
t4 − t2 = ton = DT = ;
f 4.2 Ideal efficiency
1−D
t2 − t0 = toff = (1 − D)T = (40) The ideal efficiency of the circuit can be obtained as follows
f

Now, by assumption that (t0 2 t1) ¼ (t1 2 t2) and by Po Pin − DP 5

h= = =1− (48)
neglecting the very short time interval (t2 2 t3), with (39) Pin Pin Ro Cf
and (40) the voltage drop across capacitor C1 becomes
4.3 Dynamic model
2M3 Vin
DVC1 = (41) By analogy to a dynamic model of an A multiplier, a dynamic
Ro Cf
model of the A × A multiplier can be developed as the
Now, substituting (41) into (37), we obtain equivalent scheme, shown in Fig. 10.
The input voltage of this scheme should be the same as
  an ideal value of the output voltage of the given multiplier:
5C 2M3 Vin 2 (M V )2
DWC1,C2,C3,C4 = = 5 23 2in (42) Vin,eq ¼ M3Vin . Then, Lin,eq = M32 Lin ; Rin,eq = M32 Rin and
4 Ro Cf Ro f C in this case we will assign Ro,eq ¼ Ro; Co,eq ¼ Co; Lo,eq ¼ Lo .
The value of an equivalent capacity Co1,eq is defined,
and the power losses will be as previously, on the basis of the law of conservation of
energy.
DWC1,C2,C3,C4 (M V )2 Considering the voltage balance in the closed loop (see the
DP = = 5 32 in (43) first scheme, Fig. 8): open switch, the series capacitances C1
T Ro fC
and C4 , two parallel capacitances C5 and C6 , and the last two
The output voltage can be obtained as follows series capacitances C3 and C2 , we may write

DP DP −Vsw + VC1 − VC4 + VC5 − VC3 + VC2 = 0

DVo = =
Io (M3 Vin )/Ro
Taking into consideration, as previously, the average, through
Considering (43), we have the whole period, voltages across the capacitances, as
Vsw ¼ VC1 ¼ VC2 , VC3 ¼ 2VC1 and VC5 ¼ VC6 we may
M3 Vin obtain: VC5 ¼ 3VC1 .
DVo = 5 (44) Therefore, the total energy of these six capacitors will be
Ro fC

Thus, for N ¼ 3 the real output voltage is 1

W1 = [2CVC12
+ 2CVC3
2
+ 2CVC5
2
] = 14CVC1
2
  2
5  
Vo = M3 Vin − DVo = M3 Vin 1− (45) Vin 2
Ro fC = 14C (49)
1−D
As it was previously done, we can write this formula by
taking into account a voltage drop for N ¼ 3 diode cells and the energy of Co1,eq is
   
Vo = M3 Vin 1 −
5
− 2N DVD 1 1 Vin 2
(46) W2 = Co1,eq Vo = Co1,eq (N + D)
2
(50)
Ro fC 2 2 1−D

Now, we can find the expression for the inner resistance,

which corresponds to the above losses: Rin = (DP/Iin2 ), or,
since the input current is Iin = (Vo Io /Vin ) = Vo2 /(Ro Vin ) =
(M3 Vin )2 /(Ro Vin ) = (M32 Vin /Ro ) it gives

5
Rin = (47)
M32 Cf

It should be noted that the value of the inner resistance has Fig. 10 Equivalent circuit of A × A multiplier

882 IET Power Electron., 2012, Vol. 5, Iss. 6, pp. 873 –884
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Fig. 11 Simulated output voltage for the original and equivalent circuits of A × A-type multiplier during the transient switching-on process

Equating (48) and (49) for N ¼ 3; D ¼ 0.5, gives 5 Experimental results

Along with the computer simulation, two laboratory
28 prototypes in accordance with scheme A and scheme A × A
Co1,eq = C ≃ 2.28 C (51) were implemented and tested. The parameters of scheme A
(N + D)2
are as follows:
Vin ¼ 24 V; D ¼ 0.5; f ¼ 50 kHz; L ¼ 0.8 mHand
M3 ¼ (n + 1)/2(1 2 D) ¼ 4, where n ¼ 3; C ¼ 1 mF and
The scheme of a three cell multiplier of type A × A, having Ro ¼ 300 V [as in a computer simulation model (see
the parameters: Section 3.3)]. The experimental results are shown in Fig. 12.
D ¼ 0.5; M ¼ (N + D)/(1 2 D) ¼ 7; Vin ¼ 24 V; As can be seen, the actual value of the output voltage
f ¼ 50 kHz; Lin ¼ 0.8 mH; Lo ¼ 0.3 mH; C ¼ 1 mF and is about Vo ¼ 24 V, which is very close to its theoretical
Ro ¼ 500 V was simulated by the equivalent scheme, Fig. 10, value, calculated according to (13).
with the parameters, calculated by the above developed The scheme of a three-cell multiplier of type A × A has
formulas: Vin,eq ¼ 168 V; Lin,eq ¼ 39.2 mH; Co,eq ¼ 1 mF; been checked for the following parameters:
Ro,eq ¼ 500 V; Co1,eq ¼ 2.28 mF and Rin,eq ¼ 100 V [where Vin ¼ 12 V; D ¼ 0.61; M3 ¼ (N + D)/(1 2 D) ¼ 9.26;
Rin is calculated in accordance with (47)]. The results of the f ¼ 75 kHz; Lin ¼ 0.3 mH; C ¼ Co ¼ 10 mF; Lo ¼ 0.1 mH
transient behaviour of an A × A scheme and the equivalent and Ro ¼ 1000 V. The experimental results are shown in
scheme, performed by the SPICE program are shown in Fig. 11. Fig. 13.
As can also be seen here there is a good agreement between As can be seen, for the input voltage Vin ¼ 12 V the output
the simulation results and the transient behaviour of the voltage is about Vo ¼ 107 V, which is close enough to
equivalent circuit. the value calculated in accordance with (45), which is

Fig. 12 Experimental waveforms of the laboratory model of Fig. 13 Experimental waveforms of the laboratory model of the
scheme A; Vin , input voltage; Vo output voltage and VS , voltage scheme A × A: Vin , input voltage; Vo , output voltage and VS ,
across the switch voltage across the switch

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Vo ¼ 110.3 V. (Note that this value is obtained without 3 Cockroft, J.D., Walton, E.T.: ‘Production of high velocity positive ions’,
consideration of the voltage drops on the diodes, that is by Proc. R. Soc. A, 1932, 136, pp. 619 –630
4 Huber, L., Jovanovich, M.M.: ‘A design approach for server power
considering these drops, the output voltage becomes even supplies for networking applications’. Proc. IEEE Applied Power
closer to the experimental one.) The maximum voltage Electronics Conf., Darussalam, Brunei, November 2000,
across the switch is VS ¼ 32 V (calculated voltage in pp. 1163– 1169
accordance with (3) is VS ¼ 30.8 V). 5 Rosas-Caro, J.C., Ramirez, J.M., Garcia-Vite, P.M.: ‘Novel DC-DC
multilevel boost converter’. Proc. IEEE Power Electronics Specialists
Conf., Rhodes, Greece, June 2008, pp. 2146–2151
6 Conclusions 6 Rosas-Caro, J.C., Ramirez, J.M., Peng, F.Z., Valderrabano, A.: ‘A DC–
DC multilevel boost converter’, IET Power Electron., 2010, 3, (1),
1. On the basis of two well-known schemes of voltage pp. 129–137
multipliers, namely Dickson and Cockcroft – Walton, new 7 Baek, J.W., Ryoo, M.H., Kim, T.J., Yoo, D.W., Kim, J.S.: ‘High boost
converter using voltage multiplier’. Proc. IEEE Industrial Electronics
schemes, having their own features and their specific values Conf., Raleigh, USA, November 2005, pp. 6– 10
of the maximum output voltage, have been developed 8 Prudente, M., Pfitscher, L.L., Gules, R.: ‘A boost converter with voltage
and analysed. These new schemes were implemented multiplier cells’. Proc. IEEE Power Electronics Specialists Conf., Recife,
by topological transformations, that is, by connecting the Brasil, June 2005, pp. 2716– 2721
9 Iqbal, S., Besar, R.: ‘A bipolar Cockcroft-Walton voltage multiplier for
corresponding elements in the positive and negative lines of gas lasers’, Am. J. Appl. Sci., 2007, 4, (10), pp. 795– 801
the converter. 10 Di Cataldo, G., Palumbo, G.: ‘Design of Nth order Dickson
2. It was shown that both, the base schemes and the newly voltage multiplier’, IEEE Trans. Circuits Syst. 1, 1996, 43, (5),
formed topologies are characterised by the presence of the pp. 414–418
internal voltage drop, causing a decrease in the output 11 Tanzawa, T., Tanaka, T.: ‘A dynamic analysis of the Dickson charge
pump circuit’, IEEE J. Solid-State Circuits, 1997, 32, (8),
voltage, when the load of the multipliers increases. The pp. 1231– 1240
reason for this effect is the periodic recharge of the 12 Moisiadis, Y., Bouras, I., Arapoyanni, A.: ‘Charge pump circuits for
capacitors, having different voltage levels. This process is low- voltage applications’, VLSI Des., 2002, 15, (1), pp. 477– 483
accompanied by the loss of energy. 13 Baderna, D., Cabrini, A., Pasotti, M., Torelli, G.: ‘Power efficiency
evaluation in Dickson and voltage doubler charge pump topologies’,
3. The above phenomena take place despite the visible Microelectron. J., 2006, 37, pp. 1128– 1135
absence of resistive elements. In spite of this, the equivalent 14 Shenkman, A., Berkovich, Y., Axelrod, B.: ‘The transformerless
internal resistance, which influences the output voltage and AC-DC and DC-DC converters with a diode-capacitor voltage
the efficiency of the circuit, can be brought into consideration. multiplier’. Proc. IEEE Power Tech. Conf., Bologna, Italy, June 2003,
4. The method and the formulas for calculating the values of pp. 3– 26
15 Shenkman, A., Berkovich, Y., Axelrod, B.: ‘Novel AC-DC and DC-DC
the specified internal voltage drop and power losses are given, converters with a diode-capacitor multiplier’, IEEE Trans. Aerosp.
and their dependence on the values of the capacitors and Electron. Syst., 2004, 40, (4), pp. 1286– 1293
frequency is shown. As a result, the expressions for the 16 Berkovich, Y., Axelrod, B., Shenkman, A., Golan, G.: ‘Structures of
external characteristics of the multipliers are given. transformerless step-up and step-down controlled rectifiers’, IET
5. The method for forming a simple equivalent dynamic Power Electron., 2008, 1, (2), pp. 245 –254
17 Berkovich, Y., Axelrod, B., Shenkman, A.: ‘A novel diode-capacitor
scheme of the voltage multipliers, based on the use of an voltage multiplier for increasing the voltage of photovoltaic cells’.
internal resistance is proposed. Proc. 11th Workshop on Control and Modeling for Power Electronics,
6. Being close to each other by their values of the output Zurich, Switzerland, August 2008, pp. 1 –5
voltage, for the same number of cells, each type of
topology has its specific expression of the ideal output 8 Appendix
voltage of the equivalent inner resistance and the value of
the internal voltage drop at loading and its specific dynamic Let us consider the Dickson voltage multiplier as shown in
model. All this allows choosing the optimal solution in Fig. 14.
each specific case. Here all the capacitances are equal. Then we have
7. The computer simulation and laboratory test of the VC1 ¼ VC2 ¼ VC; VC3 ¼ VC4 ¼ 2VC; VC5 ¼ VC6 ¼ 3VC;
proposed multipliers of A and A × A types have been VCn22 ¼ VCn21 ¼ ((n 2 1)/2)VC and VCn ¼ ((n + 1)/2)VC ,
performed. In both cases the simulation and the laboratory where the last term is the output voltage of the boost-
test gave results fairly close to the theoretical ones. converter in the ideal operation (12).
The energy of two equally charged capacitors C1 and C2
7 References is (for the second time interval) WC1,C2 ¼ C(VC1,t2)2 and
of two equally charged capacitors C3 and C4 is
1 Feng, P., Tapan, S.: ‘Charge pump circuit design’ (McGraw-Hill, 2006)
2 Dickson, J.F.: ‘On-chip high-voltage generation in MNOS integrated
WC3,C4 ¼ 4C(VC1,t2)2 etc., except for the last term, which
circuits using an improved voltage multiplier technique’, IEEE is not a pair, WCn ¼ (1/2)[(n + 1)/2]2C(VC1,t2)2. Thus, we
J. Solid-State Circuits, 1976, 11, (3), pp. 374– 378 obtain (30).

Fig. 14 Dickson voltage multiplier consisting of n cells (n is odd)

884 IET Power Electron., 2012, Vol. 5, Iss. 6, pp. 873 –884
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