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TPS630250
TPS630251, TPS630252
SLVSBJ9B – MAY 2014 – REVISED MARCH 2015

TPS63025x High Current, High Efficiency Single Inductor Buck-Boost Converter

1 Features 3 Description
1• Real Buck or Boost Operation with Automatic and The TPS63025x are high efficiency, low quiescent
Seamless Transition Between Buck and Boost current buck-boost converters suitable for application
where the input voltage is higher or lower than the
Operation
output. Output currents can go as high as 2 A in
• 2.3 V to 5.5 V input voltage range boost mode and as high as 4 A in buck mode. The
• 2 A Continuous Output Current : VIN≥ 2.5 V, maximum average current in the switches is limited to
VOUT= 3.3 V a typical value of 4 A. The TPS63025x regulates the
• Adjustable and Fixed Output Voltage output voltage over the complete input voltage range
by automatically switching between buck or boost
• Efficiency up to 95% in Buck or Boost Mode and mode depending on the input voltage ensuring a
up to 97% when VIN=VOUT seamless transition between modes. The buck-boost
• 2.5MHz Typical Switching Frequency converter is based on a fixed frequency, pulse-width-
• 35-μA Operating Quiescent Current modulation (PWM) controller using synchronous
rectification to obtain highest efficiency. At low load
• Integrated Soft Start currents, the converter enters Power Save Mode to
• Power Save Mode maintain high efficiency over the complete load
• True Shutdown Function current range. There is a PFM/PWM pin that allows
the user to choose between automatic PFM/PWM
• Output Capacitor Discharge Function mode operation and forced PWM operation. During
• Over-Temperature Protection and Over-Current PWM mode a fixed-frequency of typically 2.5 MHz is
Protection used. The output voltage is programmable using an
• Wide Capacitance Selection external resistor divider, or is fixed internally on the
chip. The converter can be disabled to minimize
• Small 1.766 mm x 2.086 mm, 20-pin WCSP and
battery drain. During shutdown, the load is
2.5 mm x 3 mm, 14-pin Hot Rod disconnected from the battery. The device is
packaged in a 20-pin WCSP package measuring
2 Applications 1.766 mm x 2.086mm and 14-pin HotRod package
• Cellular Phones, Smart Phones measuring 2.5 mm x 3mm.
• Tablets PC Device Information(1)
• PC and Smart Phone accessories PART NUMBER PACKAGE BODY SIZE (NOM)
• Point of load regulation DSBGA (20) 1.766 mm × 2.086 mm
TPS63025x
• Battery Powered Applications VQFN (14)(2) 2.5 mm x 3 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
(2) Product Preview

4 Typical Application
sp Efficiency vs Output Current
L1 1µH

TPS63025
VIN VOUT
L1 L2
2.7 V to 5.5 V 3.3 V up to 2A
VIN VOUT
Efficiency (%)

C1 C2
EN FB
10µF 2X22µF
VINA PFM/
PWM
VIN = 2.8V, V OUT = 3.3V
VIN = 3.3V, V OUT = 3.3V
GND PGND
VIN = 3.6V, V OUT = 3.3V
VIN = 4.2V, V OUT = 3.3V

TPS63025, Power Save Enabled

0.1
Output Current (mA)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TPS630250
TPS630251, TPS630252
SLVSBJ9B – MAY 2014 – REVISED MARCH 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 9.3 Feature Description................................................... 8
2 Applications ........................................................... 1 9.4 Device Functional Modes........................................ 10
3 Description ............................................................. 1 10 Application and Implementation........................ 13
4 Typical Application ................................................ 1 10.1 Application Information.......................................... 13
10.2 Typical Application ............................................... 13
5 Revision History..................................................... 2
6 Device Comparison Table..................................... 3 11 Power Supply Recommendations ..................... 20
7 Pin Configuration and Functions ......................... 3 12 Layout................................................................... 20
12.1 Layout Guidelines ................................................. 20
8 Specifications......................................................... 4
12.2 Layout Example .................................................... 20
8.1 Absolute Maximum Ratings ...................................... 4
8.2 ESD Ratings ............................................................ 4 13 Device and Documentation Support ................. 21
13.1 Device Support .................................................... 21
8.3 Recommended Operating Conditions....................... 4
13.2 Documentation Support ....................................... 21
8.4 Thermal Information .................................................. 5
13.3 Related Links ........................................................ 21
8.5 Electrical Characteristics........................................... 5
13.4 Trademarks ........................................................... 21
8.6 Timing Requirements ................................................ 6
13.5 Electrostatic Discharge Caution ............................ 21
8.7 Typical Characteristics .............................................. 6
13.6 Glossary ................................................................ 21
9 Detailed Description .............................................. 7
9.1 Overview ................................................................... 7 14 Mechanical, Packaging, and Orderable
Information ........................................................... 21
9.2 Functional Block Diagram ......................................... 7

5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (May 2014) to Revision B Page

• Added VQFN (RNC) package option .................................................................................................................................... 3

• Changed UVLO in the Electrical Characteristics From: MAX = 1.9 V To: 2 V ...................................................................... 5

Changes from Original (May 2014) to Revision A Page

• Added devices TPS630250, TPS630251, and TPS630252 voltage options ......................................................................... 1

• Added Specifications, Detailed Description section, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section; and, changed status to
Production Data. .................................................................................................................................................................... 4
• Changed Load Regulation Typ spec from "125 mV/A" to "2.5 mV/A" ................................................................................... 6

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6 Device Comparison Table

PART NUMBER VOUT

TPS630250 Adjustable
TPS630251 2.9 V
TPS630252 3.3 V

7 Pin Configuration and Functions

VQFN 14-Pin
DSBGA 20-Pin RNC Package
YFF Package Top View
Top View

E1 D1 C1 B1 A1 4 3 2 1 14

E2 D2 C2 B2 A2 5 13

E3 D3 C3 B3 A3 6 12

E4 D4 C4 B4 A4 7 8 9 10 11

Product Preview

Pin Functions
PIN
I/O DESCRIPTION
NAME DSBGA RNC
VOUT A1,A2,A3 12, 13, 14 PWR Buck-Boost converter output
FB A4 11 IN Voltage feedback of adjustable version, must be connected to VOUT on fixed output voltage
versions
L2 B1,B2,B3 1 PWR Connection for Inductor
PFM/PWM B4 10 IN set low for PFM mode, set high for forced PWM mode. It must not be left floating
PGND C1,C2,C3 2 PWR Power Ground
GND C4 9 PWR Analog Ground
L1 D1,D2,D3 3 PWR Connection for Inductor
EN D4 8 IN Enable input. Set high to enable and low to disable. It must not be left floating.
VIN E1,E2,E3 4, 5, 6 PWR Supply voltage for power stage
VINA E4 7 PWR Supply voltage for control stage.

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8 Specifications
8.1 Absolute Maximum Ratings (1)
over junction temperature range (unless otherwise noted)
VALUE
MIN MAX UNIT
(2)
Voltage VIN, L1, EN, VINA, PFM/PWM –0.3 7 V
VOUT, FB –0.3 4 V
L2 (3) –0.3 4 V
(4)
L2 -0.3 5.5 V
Input current Continuos average current into L1 (5) 2.7 A
TJ Operating junction temperature –40 125
°C
Tstg Storage temperature range –65 150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground pin.
(3) DC voltage rating.
(4) AC voltage rating.
(5) Maximum continuos average input current 3.5A, under those condition do not exceed 105°C for more than 25% operating time.

8.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±700
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions (1)

MIN TYP MAX UNIT
VIN Input Voltage Range 2.3 5.5 V
VOUT Output Voltage 2.5 3.6 V
(2)
L Inductance 0.5 1 1.3 µH
Cout Output Capacitance (3) 20 µF
TA Operating ambient temperature –40 85 °C
TJ Operating virtual junction temperature –40 125 °C

(1) Refer to the Application Information section for further information

(2) Effective inductance value at operating condition. The nominal value given matches a typical inductor to be chosen to meet the
inductance required.
(3) Due to the dc bias effect of ceramic capacitors, the effective capacitance is lower then the nominal value when a voltage is applied. This
is why the capacitance is specified to allow the selection of the nominal capacitor required with the dc bias effect for this type of
capacitor. The nominal value given matches a typical capacitor to be chosen to meet the minimum capacitance required.

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8.4 Thermal Information

TPS63025x
THERMAL METRIC (1) YFF (DSBGA) RNC (VQFN) (2) UNIT
20 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 71.1 69.2
RθJC(top) Junction-to-case (top) thermal resistance 0.5 38.2
RθJB Junction-to-board thermal resistance 11.4 12.7
°C/W
ψJT Junction-to-top characterization parameter 2 1.9
ψJB Junction-to-board characterization parameter 11.3 12.7
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Product Preview

8.5 Electrical Characteristics

VIN= 2.3V to 5.5V, TJ= –40°C to 125°C, typical values are at TA= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VIN Input voltage range 2.3 5.5 V
VIN_Min Minimum input voltage to turn on into full load IOUT = 2A 2.8 V
(1)
IOUT Continuos Output Current VIN >=2.5V, VOUT=3.3V 2 A
VIN IOUT = 0mA, EN = VIN = 3.6V, 35 70 μA
IQ Quiescent current VOUT = 3.3V TJ = -40°C to 85°C,
VOUT not switching 12 μA
Isd Shutdown current EN = low, TJ = -40°C to 85°C 0.1 2 μA
Under voltage lockout threshold VIN falling 1.6 1.7 2 V
UVLO
Under voltage lockout hysteresis 180 mV
Thermal shutdown Temperature rising 140 °C
Thermal Shutdown hysteresis 20 °C
LOGIC SIGNALS EN, PFM/PWM
VIH High level input voltage VIN = 2.3V to 5.5V 1.2 V
VIL Low level input voltage VIN = 2.3V to 5.5V 0.4 V
Ilkg Input leakage current EN = GND or VIN 0.01 0.2 μA
OUTPUT
VOUT Output Voltage range 2.3 3.6 V
VFB Feedback regulation voltage 0.8 V
VFB Feedback voltage accuracy PWM mode, TPS630250 -1% 1%
(2)
VFB Feedback voltage accuracy PFM mode, TPS630250 -1% 1.3% +3%
VOUT Output voltage accuracy PWM mode, TPS630251 2.871 2.9 2.929 V
VOUT Output voltage accuracy (2) PFM mode, TPS630251 2.871 2.938 2.987 V
VOUT Output voltage accuracy PWM mode, TPS630252 3.267 3.3 3.333 V
VOUT Output voltage accuracy (2) PFM mode, TPS630252 3.267 3.343 3.399 V
IPWM/PFM Output current to enter PFM mode VIN = 3V; VOUT = 3.3V 350 mA
IFB Feedback input bias current VFB = 0.8V 10 100 nA
High side FET on-resistance VIN = 3.0V, VOUT = 3.3V 35 mΩ
RDS_Buck(on)
Low side FET on-resistance VIN = 3.0V, VOUT = 3.3V 50 mΩ
High side FET on-resistance VIN = 3.0V, VOUT = 3.3V 25 mΩ
RDS_Boost(on)
Low side FET on-resistance VIN = 3.0V, VOUT = 3.3V 50 mΩ

(1) For minimum output current in a specific working point see Figure 5 and Equation 1 trough Equation 4.
(2) Conditions: L = 1 µH, COUT = 2 × 22 µF.
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Electrical Characteristics (continued)

VIN= 2.3V to 5.5V, TJ= –40°C to 125°C, typical values are at TA= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(3) VIN = 3.0V, VOUT = 3.3V TJ =
IIN Average input current limit 3.5 4.5 5 A
65°C to 125°C
fs Switching Frequency 2.5 MHz
RON_DISC Discharge ON-Resistance EN = low 120 Ω
mV/
Line regulation VIN = 2.8V to 5.5V, IOUT = 2A 7.4
V
mV/
Load regulation VIN= 3.6V, IOUT = 0A to 2A 5
A

(3) For variation of this parameter with Input voltage and temperature see Figure 5.

8.6 Timing Requirements

VIN= 2.3 V to 5.5 V, TJ= –40°C to 125°C, typical values are at TA= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT
VOUT=EN=low to high, Buck
mode VIN=3.6V, VOUT=3.3V, 450 µs
IOUT=2A
tSS Soft-start time
VOUT=EN=low to high, Boost
mode VIN=2.8V, VOUT=3.3V, 700 µs
IOUT=2A
Time from when EN=high to
td Start up delay 100 µs
when device starts switching

8.7 Typical Characteristics

60 0.016
TA = -40 ºC
TA = 25 ºC
50 TA = 85 ºC
Quiescent Current (mA)
Resistance (mS)

40 0.012

30

20 0.008

10 TA = -40 ºC
TA = 25 ºC
TA = 85 ºC TPS630252
0 0.004
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
Input Voltage (V) Input Voltage (V)

Figure 1. High Side FET On-Resistance vs Input Voltage Figure 2. Quiescent Current vs Input Voltage

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9 Detailed Description

9.1 Overview
The TPS63025x use 4 internal N-channel MOSFETs to maintain synchronous power conversion at all possible
operating conditions. This enables the device to keep high efficiency over the complete input voltage and output
power range. To regulate the output voltage at all possible input voltage conditions, the device automatically
switches from buck operation to boost operation and back as required by the configuration. It always uses one
active switch, one rectifying switch, one switch is held on, and one switch held off. Therefore, it operates as a
buck converter when the input voltage is higher than the output voltage, and as a boost converter when the input
voltage is lower than the output voltage. There is no mode of operation in which all 4 switches are switching at
the same time. Keeping one switch on and one switch off eliminates their switching losses. The RMS current
through the switches and the inductor is kept at a minimum, to minimize switching and conduction losses.
Controlling the switches this way allows the converter to always keep higher efficiency.
The device provides a seamless transition from buck to boost or from boost to buck operation.

9.2 Functional Block Diagram

L1 L2

VIN VOUT

Current
Sensor
EN

PGND PGND PGND

VIN
Gate
VOUT
Control

_
_
VINA Modulator FB
+
+
Oscillator + VREF
-
Device
PFM/PWM Control

EN Temperature
Control PGND
GND
PGND

Functional Block Diagram (Adjustable Output Voltage)

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Functional Block Diagram (continued)

L1 L2

VIN VOUT

Current
Sensor
EN

PGND PGND PGND

VIN
Gate
VOUT FB
Control

_
_
VINA Modulator
+
+
Oscillator + VREF
-
Device
PFM/PWM Control

EN Temperature
Control PGND
GND
PGND

Functional Block Diagram (Fixed Output Voltage)

9.3 Feature Description

9.3.1 Undervoltage Lockout (UVLO)
To avoid mis-operation of the device at low input voltages, an undervoltage lockout is included. UVLO shuts
down the device at input voltages lower than typically 1.7 V with a 180 mV hysteresis.

9.3.2 Output Discharge Function

When the device is disabled by pulling enable low and the supply voltage is still applied, the internal transistor
use to discharge the output capacitor is turned on, and the output capacitor is discharged until UVLO is reached.
This means, if there is no supply voltage applied the output discharge function is also disabled. The transistor
which is responsible of the discharge function, when turned on, operates like an equivalent 120-Ω resistor,
ensuring typically less than 10ms discharge time for 20-µF output capacitance and a 3.3 V output.

9.3.3 Thermal Shutdown

The device goes into thermal shutdown once the junction temperature exceeds typically 140°C with a 20°C
hysteresis.

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Feature Description (continued)

9.3.4 Softstart
To minimize inrush current and output voltage overshoot during start up, the device has a Softstart. At turn on,
the input current raises monotonic until the output voltage reaches regulation. During Softstart, the input current
follows the current ramp charging the internal Softstart capacitor. The device smoothly ramps up the input current
bringing the output voltage to its regulated value even if a large capacitor is connected at the output.
The Softstart time is measured as the time from when the EN pin is asserted to when the output voltage has
reached 90% of its nominal value. There is typically a 100µs delay time from when the EN pin is asserted to
when the device starts the switching activity. The Softstart time depends on the load current, the input voltage,
and the output capacitor. The Softstart time in boost mode is longer then the time in buck mode. The total typical
Softstart time is 1ms.
The inductor current is able to increase and always assure a soft start unless a real short circuit is applied at the
output.

9.3.5 Short Circuit Protection

The TPS63025x provides short circuit protection to protect itself and the application. When the output voltage
does not increase above 1.2V, the device assumes a short circuit at the output and limits the input current to 4 A.

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9.4 Device Functional Modes

9.4.1 Control Loop Description

Ramp and Clock 0.8V

Generator

Figure 3. Average Current Mode Control

The controller circuit of the device is based on an average current mode topology. The average inductor current
is regulated by a fast current regulator loop which is controlled by a voltage control loop. Figure 3 shows the
control loop.
The non inverting input of the transconductance amplifier, gmv, is assumed to be constant. The output of gmv
defines the average inductor current. The inductor current is reconstructed by measuring the current through the
high side buck MOSFET. This current corresponds exactly to the inductor current in boost mode. In buck mode
the current is measured during the on time of the same MOSFET. During the off time, the current is
reconstructed internally starting from the peak value at the end of the on time cycle. The average current and the
feedback from the error amplifier gmv forms the correction signal gmc. This correction signal is compared to the
buck and the boost sawtooth ramp giving the PWM signal. Depending on which of the two ramps the gmc output
crosses either the Buck or the Boost stage is initiated. When the input voltage is close to the output voltage, one
buck cycle is always followed by a boost cycle. In this condition, no more than three cycles in a row of the same
mode are allowed. This control method in the buck-boost region ensures a robust control and the highest
efficiency.

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Device Functional Modes (continued)

9.4.2 Power Save Mode Operation

Heavy Load transient step

PFM mode at light load
current
Comparator High
Vo+1.3%*Vo 30mV ripple
Comparator low
Vo
PWM mode

Absolute Voltage drop

with positioning

Figure 4. Power Save Mode Operation

Depending on the load current, in order to provide the best efficiency over the complete load range, the device
works in PWM mode at load currents of approximately 350mA or higher. At lighter loads, the device switches
automatically into Power Save Mode to reduce power consumption and extend battery life. The PFM/PWM pin is
used to select between the two different operation modes. To enable Power Save Mode, the PFM/PWM pin must
be set low.
During Power Save Mode, the part operates with a reduced switching frequency and lowest supply current to
maintain high efficiency. The output voltage is monitored with a comparator at every clock cycle by the thresholds
comp low and comp high. When the device enters Power Save Mode, the converter stops operating and the
output voltage drops. The slope of the output voltage depends on the load and the output capacitance. When the
output voltage reaches the comp low threshold, at the next clock cycle the device ramps up the output voltage
again, by starting operation. Operation can last for one or several pulses until the comp high threshold is
reached. At the next clock cycle, if the load is still lower than about 350mA, the device switches off again and the
same operation is repeated. Instead, if at the next clock cycle, the load is above 350mA, the device automatically
switches to PWM mode.
In order to keep high efficiency in PFM mode, there is only one comparator active to keep the output voltage
regulated. The AC ripple in this condition is increased, compared to the PWM mode. The amplitude of this
voltage ripple in the worst case scenario is 50mV pk-pk, (typically 30 mV pk-pk), with 2-µF effective output
capacitance. In order to avoid a critical voltage drop when switching from 0A to full load, the output voltage in
PFM mode is typically 1.3% above the nominal value in PWM mode. This is called Dynamic Voltage Positioning
and allows the converter to operate with a small output capacitor and still have a low absolute voltage drop
during heavy load transients.
Power Save Mode is disabled by setting the PFM/PWM pin high.

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Device Functional Modes (continued)

9.4.3 Current Limit
The current limit variation depends on the difference between the input and output voltage. The maximum current
limit value is at the highest difference.
Given the curves provided in Figure 5, it is possible to calculate the output current reached in boost mode, using
Equation 1 and Equation 2 and in buck mode using Equation 3 and Equation 4.

V -V
Duty Cycle Boost D= OUT IN
V
OUT (1)

Output Current Boost IOUT = 0 x IIN (1-D) (2)

V
Duty Cycle Buck D= OUT
V
IN (3)

Output Current Buck IOUT = ( 0 x IIN ) / D (4)

With,
η = Estimated converter efficiency (use the number from the efficiency curves or 0.90 as an assumption)
IIN= Minimum average input current (Figure 5)

9.4.4 Supply and Ground

The TPS63025x provides two input pins (VIN and VINA) and two ground pins (PGND and GND).
The VIN pin supplies the input power, while the VINA pin provides voltage for the control circuits. A similar
approach is used for the ground pins. GND and PGND are used to avoid ground shift problems due to the high
currents in the switches. The reference for all control functions is the GND pin. The power switches are
connected to PGND. Both grounds must be connected on the PCB at only one point, ideally, close to the GND
pin.

9.4.5 Device Enable

The device starts operation when the EN pin is set high. The device enters shutdown mode when the EN pin is
set low. In shutdown mode, the regulator stops switching, all internal control circuitry is switched off, and the load
is disconnected from the input.

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10 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information

The TPS63025x are high efficiency, low quiescent current buck-boost converters suitable for application where
the input voltage is higher, lower or equal to the output. Output currents can go as high as 2A in boost mode and
as high as 4A in buck mode. The maximum average current in the switches is limited to a typical value of 4 A.

10.2 Typical Application

L1 1µH

TPS630250
VIN VOUT
L1 L2
2.5 V to 5.5 V 3.3 V up to 2A
VIN VOUT
C1 R1 C2
EN FB
10µF 560k
47µF
VINA PFM/ R2
PWM VIN or GND 180k
GND PGND

3.3V Adjustable Version

10.2.1 Design Requirements

The design guideline provides a component selection to operate the device within the recommended operating
conditions.
Table 1 shows the list of components for the Application Characteristic Curves.

Table 1. Components for Application Characteristic Curves (1)

REFERENCE DESCRIPTION MANUFACTURER
TPS630250 Texas Instruments
L1 1 μH, 8.75A, 13mΩ, SMD XAL4020-102MEB, Coilcraft
C1 10 μF 6.3V, 0603, X5R ceramic Standard
C2 47 μF 6.3V, 0603, X5R ceramic Standard
R1 560kΩ Standard
R2 180kΩ Standard

(1) See Third-Party Products Discalimer

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10.2.2 Detailed Design Procedure

The first step is the selection of the output filter components. To simplify this process Table 2 outlines possible
inductor and capacitor value combinations.

10.2.2.1 Output Filter Design

Table 2. Matrix of Output Capacitor and Inductor Combinations

NOMINAL NOMINAL OUTPUT CAPACITOR VALUE [µF] (2)
INDUCTOR
VALUE [µH] (1) 44 47 66 88 100
0.680 + + + + +
1.0 + (3) + + + +
1.5 + + +

(1) Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by 20% and –30%.
(2) Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by 20% and –50%.
(3) Typical application. Other check mark indicates recommended filter combinations

10.2.2.2 Inductor Selection

The inductor selection is affected by several parameter like inductor ripple current, output voltage ripple,
transition point into Power Save Mode, and efficiency. See Table 3 for typical inductors.

Table 3. List of Recommended Inductors (1)

INDUCTOR VALUE COMPONENT SUPPLIER SIZE (LxWxH mm) Isat/DCR
1 µH Coilcraft XAL4020-102ME 4 X 4 X 2.10 4.5A/10mΩ
1 µH Toko, DFE322512C 3.2 X 2.5 X 1.2 4.7A/34mΩ
1 µH TDK, SPM4012 4.4 X 4.1 X 1.2 4.1A/38mΩ
1 µH Wuerth, 74438334010 3 X 3 X 1.2 6.6A/42.10mΩ
0.6 µH Coilcraft XFL4012-601ME 4 X 4 X 1.2 5A/17.40mΩ
0.68µH Wuerth,744383340068 3 X 3 X 1.2 7.7A/36mΩ

(1) See Third-Party Products Desclaimer

For high efficiencies, the inductor should have a low dc resistance to minimize conduction losses. Especially at
high-switching frequencies, the core material has a high impact on efficiency. When using small chip inductors,
the efficiency is reduced mainly due to higher inductor core losses. This needs to be considered when selecting
the appropriate inductor. The inductor value determines the inductor ripple current. The larger the inductor value,
the smaller the inductor ripple current and the lower the conduction losses of the converter. Conversely, larger
inductor values cause a slower load transient response. To avoid saturation of the inductor, the peak current for
the inductor in steady state operation is calculated using Equation 6. Only the equation which defines the switch
current in boost mode is shown, because this provides the highest value of current and represents the critical
current value for selecting the right inductor.
V -V
Duty Cycle Boost D= OUT IN
V
OUT (5)
Iout Vin ´ D
IPEAK = +
η ´ (1 - D) 2 ´ f ´ L (6)
Where,
D =Duty Cycle in Boost mode
f = Converter switching frequency (typical 2.5MHz)
L = Inductor value
η = Estimated converter efficiency (use the number from the efficiency curves or 0.90 as an assumption)
Note: The calculation must be done for the minimum input voltage which is possible to have in boost mode
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. It's recommended to choose an inductor with a saturation current 20% higher
than the value calculated using Equation 6. Possible inductors are listed in Table 3.
14 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated

Product Folder Links: TPS630251 TPS630252

 TPS630250
TPS630251, TPS630252
www.ti.com SLVSBJ9B – MAY 2014 – REVISED MARCH 2015

10.2.2.3 Capacitor Selection

10.2.2.3.1 Input Capacitor

At least a 10μF input capacitor is recommended to improve line transient behavior of the regulator and EMI
behavior of the total power supply circuit. An X5R or X7R ceramic capacitor placed as close as possible to the
VIN and PGND pins of the IC is recommended. This capacitance can be increased without limit. If the input
supply is located more than a few inches from the TPS63025x converter additional bulk capacitance may be
required in addition to the ceramic bypass capacitors. An electrolytic or tantalum capacitor with a value of 47 μF
is a typical choice.

10.2.2.3.2 Output Capacitor

For the output capacitor, use of a small ceramic capacitors placed as close as possible to the VOUT and PGND
pins of the IC is recommended. The recommended nominal output capacitance value is 20 µF with a variance as
outlined in Table 2.
There is also no upper limit for the output capacitance value. Larger capacitors causes lower output voltage
ripple as well as lower output voltage drop during load transients.

10.2.2.4 Setting The Output Voltage

When the adjustable output voltage version TPS63025x is used, the output voltage is set by an external resistor
divider. The resistor divider must be connected between VOUT, FB and GND. When the output voltage is
regulated properly, the typical value of the voltage at the FB pin is 800 mV. The current through the resistive
divider should be about 10 times greater than the current into the FB pin. The typical current into the FB pin is
0.1 μA, and the voltage across the resistor between FB and GND, R2, is typically 800 mV. Based on these two
values, the recommended value for R2 should be lower than 180 kΩ, in order to set the divider current at 4μA or
higher. It is recommended to keep the value for this resistor in the range of 180kΩ. From that, the value of the
resistor connected between VOUT and FB, R1, depending on the needed output voltage (VOUT), can be
calculated using Equation 7:
æV ö
R1 = R2 × ç OUT - 1÷
V
è FB ø (7)

10.2.3 Application Curves

5
Minimum Average Input Current (A)

4.5

3.5
Efficiency (%)

2.5 VIN = 2.8V, V OUT = 3.3V

VIN = 3.3V, V OUT = 3.3V
2 TPS63025, VOUT = 3.3V VIN = 3.6V, V OUT = 3.3V
VIN = 4.2V, V OUT = 3.3V
1.5 TA = 25 °C
TA = 85 °C TPS63025, Power Save Enabled
1
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 0.1
Input Voltage (V) Output Current (mA)

Figure 5. Minimum Average Input Current vs Input Voltage Figure 6. Efficiency vs Output Current

Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: TPS630251 TPS630252
TPS630250
TPS630251, TPS630252
SLVSBJ9B – MAY 2014 – REVISED MARCH 2015 www.ti.com
Efficiency (%)

Efficiency (%)
VIN = 2.8V, V OUT = 3.3V VIN = 2.8V, V OUT = 2.9V
VIN = 3.3V, V OUT = 3.3V VIN = 2.9V, V OUT = 2.9V
VIN = 3.6V, V OUT = 3.3V VIN = 3.6V, V OUT = 2.9V
VIN = 4.2V, V OUT = 3.3V VIN = 4.2V, V OUT = 2.9V

TPS63025, Power Save Disabled TPS63025, Power Save Enabled

0.1 1 10 100 1k 2k 0.1 1 10 100 1k 2k
Output Current (mA) Output Current (mA)

Figure 7. Efficiency vs Output Current Figure 8. Efficiency vs Output Current

Efficiency (%)
Efficiency (%)

VIN = 2.8V, V OUT = 2.9V IOUT = 10mA

VIN = 2.9V, V OUT = 2.9V IOUT = 200mA
VIN = 3.6V, V OUT = 2.9V IOUT = 1A
VIN = 4.2V, V OUT = 2.9V IOUT = 2A

TPS63025, Power Save Disabled TPS63025, VOUT = 3.3V, Power Save enabled

0.1 1 10 100 1k 2k
Output Current (mA) Input Voltage (V)

Figure 9. Efficiency vs Output Current Figure 10. Efficiency vs Input Voltage

Efficiency (%)

Efficiency (%)

IOUT = 10mA IOUT = 10mA

IOUT = 200mA IOUT = 200mA
IOUT = 1A IOUT = 1A
IOUT = 2A IOUT = 2A

TPS63025, VOUT = 3.3V, Power Save Disabled TPS63025, VOUT = 2.9V, Power Save enabled

Input Voltage (V) Input Voltage (V)

Figure 11. Efficiency vs Input Voltage Figure 12. Efficiency vs Input Voltage

16 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated

Product Folder Links: TPS630251 TPS630252

 TPS630250
TPS630251, TPS630252
www.ti.com SLVSBJ9B – MAY 2014 – REVISED MARCH 2015

VIN = 2.8V
VIN = 3.3V
VIN = 3.6V

Output Voltage (V)

VIN = 4.2V
Efficiency (%)

TPS63025, VOUT = 2.9V, Power Save Disabled

IOUT = 10mA
IOUT = 200mA
IOUT = 1A
IOUT = 2A

TPS63025, Power Save Enabled

Output Current (mA)

Input Voltage (V)

Figure 14. Output Voltage vs Output Current

Figure 13. Efficiency vs Input Voltage

TPS63025
VIN = 2.8V
VIN = 3.3V
VIN = 3.6V L2
Output Voltage (V)

VIN = 4.2V

L1

VOUT_Ripple 50mV/div

Time 2µs/div VIN = 3.3 V, IOUT = 200mA

Output Current (mA)

Figure 16. Output Voltage Ripple in Buck-Boost Mode

Figure 15. Output Voltage vs Output Current
and PFM to PWM Transition

TPS63025 TPS63025

L2 L2

L1 L1

VOUT_Ripple 50mV/div VOUT_Ripple 50mV/div

Time 2µs/div VIN = 2.8 V, VOUT =3.3V, IOUT =16mA Time 2µs/div VIN = 4.2 V, VOUT =3.3V, IOUT =16mA

VIN = 2.8 V IOUT = 16 mA

Figure 17. Output Voltage Ripple in Boost Mode and PFM Figure 18. Output Voltage Ripple in Buck Mode
Operation and PFM Operation

Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: TPS630251 TPS630252
TPS630250
TPS630251, TPS630252
SLVSBJ9B – MAY 2014 – REVISED MARCH 2015 www.ti.com

TPS63025 TPS63025
L2
L2

L1

L1

VOUT_Ripple 50mV/div
VOUT_Ripple 50mV/div

Time 1µs/div VIN = 2.5 V, VOUT =3.3V, IOUT =1A Time 1µs/div VIN = 4.5V, VOUT =3.3V, IOUT =1A

Figure 19. Switching Waveforms in Boost Mode Figure 20. Switching Waveforms in Buck Mode
and PWM Operation and PWM Operation

TPS63025 TPS63025

Output Current
1A/div, DC
L2

L1 Output Voltage
100 mV/div, AC

VOUT_Ripple 50mV/div

Time 1µs/div VIN = 3.3V, VOUT =3.3V, IOUT =1A Time 1 ms/div VIN = 2.8 V, VOUT = 3.3 V, IOUT = 0A to 1.5A

Figure 21. Switching Waveforms in Buck-Boost Mode Figure 22. Load Transient Response Boost Mode
and PWM Operation

TPS63025 VIN = from 3V to 3.6V, IOUT = 1.5A TPS63025

Output Current
1A/div, DC

Input Voltage
200 mV/div,
Offset 3V
Output Voltage
100 mV/div, AC
Output Voltage
50 mV/div

Time 1 ms/div VIN = 4.2 V, VOUT = 3.3 V, IOUT = 0A to 1.5A Time 1 ms/div

Figure 23. Load Transient Response Buck Mode Figure 24. Line Transient Response

18 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated

Product Folder Links: TPS630251 TPS630252

 TPS630250
TPS630251, TPS630252
www.ti.com SLVSBJ9B – MAY 2014 – REVISED MARCH 2015

TPS63025 VOUT = 3.3 V TPS63025, VOUT = 3.3V

Enable Enable
2 V/div, DC 2 V/div, DC

Output Voltage
Output Voltage 1V/div, DC
1V/div, DC

Inductor Current
500 mA/div, DC Inductor Current
500 mA/div, DC

Time 100 ms/div VIN = 2.5 V, IL = 0A Time 100 ms/div VIN = 4.5 V, IL = 0A

Figure 25. Start Up After Enable Figure 26. Start Up After Enable

Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: TPS630251 TPS630252
TPS630250
TPS630251, TPS630252
SLVSBJ9B – MAY 2014 – REVISED MARCH 2015 www.ti.com

11 Power Supply Recommendations

The TPS63025x device family has no special requirements for its input power supply. The input power supply’s
output current needs to be rated according to the supply voltage, output voltage and output current of the
TPS63025x.

12 Layout

12.1 Layout Guidelines

The PCB layout is an important step to maintain the high performance of the TPS63025x devices.
• Place input and output capacitors as close as possible to the IC. Traces need to be kept short. Routing wide
and direct traces to the input and output capacitor results in low trace resistance and low parasitic inductance.
• Use a common-power GND
• Use separate traces for the supply voltage of the power stage; and, the supply voltage of the analog stage.
• The sense trace connected to FB is signal trace. Keep these traces away from L1 and L2 nodes.

12.2 Layout Example

GND GND
L

CIN COUT
CIN COUT

VIN VOUT
AVIN FB

R1
R2
EN PFM/PWM
Figure 27. TPS63025x RNC Package Layout

20 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated

Product Folder Links: TPS630251 TPS630252

 TPS630250
TPS630251, TPS630252
www.ti.com SLVSBJ9B – MAY 2014 – REVISED MARCH 2015

13 Device and Documentation Support

13.1 Device Support

13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

13.2 Documentation Support

13.2.1 Related Documentation
For related documentation see the following:
TPS63025EVM-553 User's Guide, TPS63025 High Current, High Efficiency Single Inductor Buck-Boost
Converter, SLVUA24

13.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 4. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
TPS630250 Click here Click here Click here Click here Click here
TPS630251 Click here Click here Click here Click here Click here
TPS630252 Click here Click here Click here Click here Click here

13.4 Trademarks
All trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 21

Product Folder Links: TPS630251 TPS630252
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS630250RNCR ACTIVE VQFN-HR RNC 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 63025P

TPS630250RNCT ACTIVE VQFN-HR RNC 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 63025P

TPS630250YFFR ACTIVE DSBGA YFF 20 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 TPS
630250
TPS630250YFFT ACTIVE DSBGA YFF 20 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 TPS
630250
TPS630251YFFR ACTIVE DSBGA YFF 20 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 TPS
630251
TPS630251YFFT ACTIVE DSBGA YFF 20 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 TPS
630251
TPS630252YFFR ACTIVE DSBGA YFF 20 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 TPS
630252
TPS630252YFFT ACTIVE DSBGA YFF 20 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 TPS
630252

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS630250RNCR VQFN- RNC 14 3000 330.0 12.4 2.8 3.3 1.2 8.0 12.0 Q1
HR
TPS630250RNCT VQFN- RNC 14 250 180.0 12.4 2.8 3.3 1.2 8.0 12.0 Q1
HR
TPS630250YFFR DSBGA YFF 20 3000 180.0 8.4 1.89 2.2 0.69 4.0 8.0 Q1
TPS630250YFFT DSBGA YFF 20 250 180.0 8.4 1.89 2.2 0.69 4.0 8.0 Q1
TPS630251YFFR DSBGA YFF 20 3000 180.0 8.4 1.89 2.2 0.69 4.0 8.0 Q1
TPS630251YFFT DSBGA YFF 20 250 180.0 8.4 1.89 2.2 0.69 4.0 8.0 Q1
TPS630252YFFR DSBGA YFF 20 3000 180.0 8.4 1.89 2.2 0.69 4.0 8.0 Q1
TPS630252YFFT DSBGA YFF 20 250 180.0 8.4 1.89 2.2 0.69 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS630250RNCR VQFN-HR RNC 14 3000 346.0 346.0 33.0
TPS630250RNCT VQFN-HR RNC 14 250 182.0 182.0 20.0
TPS630250YFFR DSBGA YFF 20 3000 182.0 182.0 20.0
TPS630250YFFT DSBGA YFF 20 250 182.0 182.0 20.0
TPS630251YFFR DSBGA YFF 20 3000 182.0 182.0 20.0
TPS630251YFFT DSBGA YFF 20 250 182.0 182.0 20.0
TPS630252YFFR DSBGA YFF 20 3000 182.0 182.0 20.0
TPS630252YFFT DSBGA YFF 20 250 182.0 182.0 20.0

Pack Materials-Page 2
 PACKAGE OUTLINE
RNC0014A SCALE 4.000
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

2.6 B
A
2.4

PIN 1 INDEX AREA

3.1
2.9

0.9 0.1 C

SEATING PLANE

0.08 C

2X
1.5 (0.2) TYP
0.05
6X 0.5 0.00
4 7

2X 0.49 2X 0.5
3 8

SYMM
1

0.29
0.19
1 10
0.29
0.27 11X
0.19
0.17
PINS 1 & 3 0.1 C A B
14 11 0.05 C
PKG
0.5
11X
0.3
1.69
1.49
4221630/C 04/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
RNC0014A VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

PKG
11X (0.24)
SEE SOLDER MASK
14 11 DETAIL

11X (0.6)

8X (0.5)
1 10
2X
(0.49) SYMM

(2.8)

(0.24) 8
3
(0.22)
PADS 1 & 3

4 7
(0.555) (1.15)

3X (1.79)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:20X

0.05 MAX 0.05 MIN

ALL AROUND
METAL UNDER
METAL EDGE SOLDER MASK

EXPOSED
EXPOSED SOLDER MASK SOLDER MASK
METAL
METAL OPENING OPENING

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4221630/C 04/2018

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
RNC0014A VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

11X (0.24) PKG

14 11

11X (0.6)

3X
6X (0.795) EXPOSED METAL
4X (0.22)
1
10

(0.24) 8X
(0.5)
SYMM

(2.8)
2X (0.49)

8
3

3X (0.06)

4 7
3X (1.05) (1.15)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

FOR EXPOSED PADS 1-3

89% PRINTED SOLDER COVERAGE BY AREA
SCALE:30X

4221630/C 04/2018
NOTES: (continued)

5. For alternate stencil design recommendations, see IPC-7525 or board assembly site preference.

www.ti.com
D: Max = 2.116 mm, Min =2.056 mm

E: Max = 1.796 mm, Min =1.736 mm

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