A 12b-ENOB 61f-LW Noise-Shaping SAR ADC

with a Passive Integrator

Wenj uan Guo and Nan Sun
Department of Electrical and Computer Engineering
The University of Texas at Austin, Austin, TX 78712, USA
Email: wj [email protected], [email protected]

Abstract-This paper presents a novel noise shaping SAR power for the same SNR. In addition, it requires 2-time more
architecture that is simple, robust and low power. It is fully capacitance, increasing chip area.
passive and only needs minor modification to a conventional
SAR ADC . Through a passive integrator, quantization noise,
comparator noise and DAC noise are shaped with a noise transfer
function of (1 - 0.75z-1). Unlike conventional multi-bit delta­
sigma ADCs, both the noise transfer function and the error
transfer function of DAC mismatches are immune to process­
voltage-temperature variations. A prototype chip is fabricated in
a O.13J.lm CMOS process. At 1.2V and 2MS/s, the chip consumes
61J.lW power. SNDR increases by 6dB and the Schreier FoM
increases by 3dB with OSR doubled. At an OSR of 8, SNDR is
74dB and the Schreier FoM is 167dB.

I. INTRODUCTION

For medium-resolution applications, successive approxima­

tion register (SAR) ADC is of great popularity due to its
high power efficiency in nanometer technology. However, as Fig. 1. NTF magnitude comparisons with zeros from [4] . [5] and this work.
the target resolution goes beyond 10-bit, its efficiency quickly
diminishes due to its tight requirement on comparator noise. This paper proposes a novel NS SAR architecture that is
Moreover, the exponentially increasing capacitor DAC array simple, robust, and low power. It gets rid of the OTA-based
not only costs large chip area and power, but also makes active integrators and realizes a NTF zero at 0.75 with a pas­
it difficult to drive. For high-resolution application, delta­ sive integrator. The passive integrator only requires one switch
sigma (��) ADC is a more widely-used architecture. Taking and two capacitors. The zero location is fully determined by
advantage of oversampling and noise shaping, it can use a low­ the capacitor ratio, which is insensitive to PVT variations
resolution quantizer to reach high resolution. Nevertheless, and ensures the robustness of the architecture. Compared to
its realization usually requires OTA-based active integrators [4] (z = 0.64) and [5] (z = 0.5), the proposed NS SAR
which are power hungry and scaling unfriendly. This has ADC achieves the best noise shaping performance with a zero
motivated the development of voltage-controlled oscillators closest to 1. Fig. 1 compares the NTF magnitude with zeros
(VCO)-based �� ADCs that use VCO as integrators [1]-[3]. from [4], [5] and this work. As can be seen, this work achieves
However, VCO performs a voltage-to-phase/frequency con­ around 3dB more in-band attenuation than [4] and 6dB more
version, which is nonlinear and sensitive to process-voltage­ in-band attenuation than [5]. Furthermore, the proposed ar­
temperature (PVT) variations. chitecture does not cause any signal attenuation, and requires
Recently, there have been emerging efforts in the research less capacitance than [5]. With minimum modification to the
community trying to develop hybrid ADC architectures that original SAR ADC architecture, the proposed NS SAR ADC
combine the merits of SAR and �� ADCs [4], [5]. The first altogether shapes the quantization noise, comparator noise,
noise-shaping (NS) SAR ADC is published in [4], but it still and DAC noise with a NTF of ( 1 - 0 .7 5z - 1 ) .1t allows the
s
needs an OTA to realize a 1 t-order noise transfer function use of a low-resolution DAC and relaxes the requirement on
(NTF) zero at 0.64. It also requires a FIR DAC that introduces comparator noise, making it possible to reach high-resolution
s
extra noise and increases chip area. Later, a fully-passive 1 t_ and high-power efficiency simultaneously.
order NS SAR ADC is published in [5]. It obviates the need To demonstrate the proposed NS SAR ADC, the paper is
for any OTA, but its noise-shaping performance is very limited, organized as follows. Section II introduces the circuit architec­
as its NTF zero is located at 0.5 rather than 1. Moreover, its ture. Section III analyzes the detailed signal flow diagram and
input signal is attenuated by 2 times during normal conversion, its non-ideal effects. Section IV presents the chip measurement
leading to the 6-dB penalty in SNR or quadrupled analog results. Finally, Section V draws the conclusion.

978-1-5090-2972-3/15/$3l.00 ©2016 IEEE 405

 Fig. 2. Proposed NS SAR ADC architecture.

II. CIRCUIT ARCHITECTURE OTAs are still required to provide a gain to compensate the
attenuation of Vres. Fortunately, as the comparators result is a
s
Fig. 2 shows the architecture of the proposed 1 t-order NS I-bit sign, what is required here is only a relative gain between
SAR ADC. Compared to conventional SAR operations, two Vint and Vres, which can be realized by simply sizing the
more clock cycles, ¢nso and ¢nsl are added. Before ¢nso comparator input transistors correspondingly. As shown in Fig.
cycle, the SAR ADC does the normal conversion. Different 2, to provide a gain of 4 on Vint path for a proper NTF, we
from [5], there is no capacitor connected to Vres node during size its corresponding input transistors 4 times larger than the
normal conversion, and thus, the signal attenuation problem Vres path. After ¢nsl cycle, the charge on C2 is cleared in next
s
is avoided. To realize 1 t-order noise shaping, the key is to ¢s cycle to be ready for getting the new residual voltage. In
integrate the residual voltage Vres and feed it back to the real implementation, amode signal is used to pull down Vint
comparator input. to ground so that the SAR ADC can be easily reconfigured
During ¢nso cycle, a small capacitor, C2 = C/3 is merged to the conventional mode in case of Nyquist-rate applications.
with the DAC capacitor, C1 C , to get the residue voltage,
=
Additionally, foreground calibration on DAC mismatch can
Vres. At the end of ¢nso cycle, C2 will carry O.75Vres. In also be conducted in the Nyquist mode.
the following ¢nsl cycle, C2 dumps its charge onto another
III. ANALY SIS
capacitor, C3 C , effectively realizing a passive integration.
=

The voltage integrated on C3 is labelled as Vint, which is To provide a better understanding of the proposed NS SAR
fed back to the comparator input. Now the comparator has architecture, Fig. 3 shows the general signal flow diagram
2-path inputs, one of which is connected to Vres while the assuming C1 = C3 = C , C2 = a/(l-a)C , and the integration
other is connected to Vint. However, there is a limitation with path gain of g. As can be seen from the derived NTF in Dout
passive integration that only a fraction of Vres is integrated, equation, there is a zero located at (1 - a) and a pole located
which degrades the noise shaping performance. It seems that at (1 - a)(l - ga). When 9 = l/a , the pole is gone and only

Fig. 3. General signal flow diagram of the proposed NS SAR ADC assuming Cl = C3 = C, C2 = al(l - a)C, and the integration path gain of g.

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 Fig. 4. Non-ideal effects in the proposed NS SAR ADC with the integration path gain 9 = l/a.

left is the zero. In this design, we choose a = 1/4 and 9 4, =

realizing a NTF of (1 - 0.75z-1 ). With a = 1/4, C2 value

is C/3 and consequently only 4 /3 times more capacitors are
required for the 1 st-order NS. Note that the NTF is completely
set by component ratios a and g, and thus, is insensitive to
PVT variations. To ensure stability, the pole needs to be within
the unit circle. The stability condition is shown in Fig. 3. Given
that the current stability condition is 4/3 < 9 < 28/3, 9 = 4
determined by the comparator input transistor ratio is very far
from the unstable boundary. Therefore, the proposed NS SAR
architecture is highly robust.
Fig. 5. Chip die photo and layout.
With 9 = l/ a, Fig. 4 further investigates the non-ideal
effects including thermal noises and DAC mismatch errors in
the flow. nl is the kT/C sampling noise which directly adds that c2(Z) = -c1 (Z). As a result, the ETF is 1 regardless of
to the input signal. n2 is the noise voltage on C2 at the end the values of a and 9 (see the eqn. in Fig. 4. Even though
of 1YnsQ while n3 is the noise voltage on C3 at the end of there exist capacitor mismatches, it is equivalent to a NS SAR
1Ynsl . Fig. 4 also shows the noise power for n2 and n3. With that uses a non-binary DAC array. As long as the capacitor
a = 1/4, n§ = 9kT/4C and n§ = kT/4C. As shown in the mismatches are estimated, we can fully remove them in the
Dout equation, nl, n2, and n3 directly pass through without digital domain. In this design, we reconfigure the NS ADC
being shaped while the comparator noise n4, the DAC noise in the conventional Nyquist SAR mode at first and apply
n5, and the quantization noise Q added at the same location classic foreground calibration techniques [7] to estimate the
are altogether shaped to the pt-order. DAC mismatch errors.

Another interesting merit of the proposed NS SAR ADC

I V. CHIP MEASUREMENT RESULTS
is its simplified digital DAC mismatch calibration. For con­
ventional multi-bit �� ADCs, in order to completely remove As a proof of concept, a prototype 1 st-order NS SAR ADC
the DAC mismatch error in the digital domain, we need to is fabricated in a O.13p,m CMOS process. Fig. 5 shows its die
2
accurately extract not only the DAC mismatch percentage but photo and layout. The core area is O.13mm . The DAC array
also the DAC mismatch error transfer function (ETF), as the capacitor C 1 is lO-bit with a total capacitance of 2.1pFx2
ETF may not be exactly 1 due to PVT variations. As a result, and a unit MOM capacitor of 2tF. The passive integrator
special techniques such as inserting a binary pseudo-random capacitors C2 and C3 are implemented using high-density
test signal [6] are required to measure the ETF. By contrast, MIM capacitors so that they consume much less area than
the ETF in the NS SAR ADC is always 1 for any NTF under C 1 (see Fig. 5). The sampling frequency is 2MS/s. At 1.2V
any PVT variation. The key reason is that the quantizer and supply, the chip consumes 60p,W power. 63% of the total
the feedback DAC use the same capacitor array in a NS SAR power comes from the clock generation and the SAR logic,
ADC. It is different from conventional multi-bit �� ADCs which are fully digital and can be greatly reduced with the
whose DAC and quantizer are unrelated. As shown in Fig. 4, CMOS scaling. With a 95.37KHz, -2dBFS sinusoidal input,
Cl represents the quantizer error due to capacitor mismatch, the measured output spectrum is shown in Fig. 6. At an OSR
and C2 represents the feedback mismatch error. Since they are of 8, SNDR and SFDR are 74dB and 95dB, respectively.
from the same origin in the NS SAR, it is easy to derive Fig. 7 shows the measured SNRlSNDR with different input

407
amplitudes. Fig. 8 shows the measured SNDRISchreier FoM
(FoMs) trend with different OSRs. As shown in Fig. 8(a),
with OSR doubled, SNDR increases by 6dB which matches
(1 - 0.75z-1 ). Therefore, according to FoMs
the NTF of =

SNDR+lOloglO ( BW/Power ) , the FoMs increases by 3dB

with OSR doubled. As shown in Fig. 8(b), when OSR is 8,
the chip achieves a FoMs of 167 dB.

Fig. 8. With different OSRs: (a) Measured SNDR and (b) Schreier FoM.

PVT variations and highly robust. Compared to prior NS SAR

ADC works, it gives the best noise shaping performance with
a zero closet to 1. A O.13f.Lm CMOS prototype chip achieves
the highest ENOB and the best Schreier FoM.

TABLE I
COMPARISON WITH PREVIOUS NS SAR ADC WORKS

Design ISSCC12 [4] YLSIlS [5] This work

Architecture
Need OTA Yes No No
Need FIR filter Yes No No
Fig. 6. Measured output spectrum with a 95.37KHz, -2dBFS sinusoidal input. Signal attenuation No Yes No
NTF zero location 0.64 0.5 0.75
Chip performance
Table I summarizes the architecture and chip performance
Technology (nm) 65 65 130
comparisons between the proposed work and previous NS Supply (Y) 1.2 0.8 1.2
SAR ADC works. As can be seen, with a simple and power­ Bandwidth (MHz) 11 6.25 0.125
Power (/-lW) 806 120.7 61
efficient architecture, this work reaches the highest ENOB and
SNDR (dB) 62 58 74
the best Schreier FoM in an older process. Since the power is ENOB (bit) 10 9.35 12
dominated by the digital portion, its power efficiency can be FoMs (dB) 163 165 167
further improved with the CMOS scaling. FoMs = SNDR+ 1OIoglO(BW/Power)

ACKNOW LEDGMENT

We thank MOSIS MEP program for chip fabrication.

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