2478 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 55, NO.

9, SEPTEMBER 2020

A 0.07-mm2 162-mW DAC Achieving >65 dBc

SFDR and < −70 dBc IM3 at 10 GS/s With Output
Impedance Compensation and Concentric
Parallelogram Routing
Hung-Yi Huang , Student Member, IEEE, and Tai-Haur Kuo , Senior Member, IEEE

Abstract— A digital-to-analog converter (DAC) with small- cascoded transistors [6], [7]. However, these transistors require
size non-cascoded current cells is proposed to achieve small additional voltage headroom. As a result, the power supply of
area, low-power consumption, and high linearity over a wide the DAC must be increased and, hence, the power consumption
bandwidth. An output impedance compensation (OIC) technique
using a compensation resistor, implemented by a PMOS with of the device is also inevitably increased. The prior arts in [1]
code-dependent gate voltage control, is proposed to remedy the and [6] showed that the increase in the power consumption
nonlinearity induced by the insufficient output impedance of the can be reduced by using a high-voltage supply for the current
non-cascoded current cells. In addition, a proposed concentric cells with cascoded transistors and a low-voltage supply for
parallelogram routing (CPR) technique, in which the subcells of the remaining DAC circuits. In this work, an output impedance
each current cell are arranged such that they form a parallel-
ogram shape with a common centroid, is used to reduce both compensation (OIC) technique [8] is proposed instead to
the mismatch error and the routing-induced timing skew among remedy the finite output impedance effect. Notably, the OIC
the current cells. The DAC, implemented in a 28-nm CMOS technique enables the use of non-cascoded current cells. In
process, achieves >65-dBc spurious-free dynamic range (SFDR) addition, a compact layout and placement of the unit non-
and < −70-dBc third-order intermodulation distortion (IM3) cascoded current cell for the more significant bits [4] are used
over the entire Nyquist bandwidth at 10 GS/s while consuming
162 mW from a single 1.1 V supply. to reduce the area and routing parasitic capacitance of the cur-
rent cell array and, therefore, widen the bandwidth, relax the
Index Terms— Compensation, current steering, digital-to- requirement of switch driver’s driving ability, and reduce the
analog converter (DAC), layout arrangement, output impedance,
timing skew. power consumption. Furthermore, by removing the cascoded
transistors, the DAC can be operated from a single low-voltage
I. I NTRODUCTION supply. Compared with the use of multiple supplies, the single

D IGITAL-TO-ANALOG converters (DACs) designed to

directly synthesize the signals of advanced communica-
tion systems have gained increasing attention in recent years
low-voltage supply further reduces the power consumption;
simplifies the signal grounding, wire routing on the PCB, and
supply generation circuits; and eliminates the need for high-
[1]–[3] due to the ability they provide to greatly simplify voltage components.
the system by removing the intermediate frequency stage. Current cells suffer from two types of mismatch errors,
To maximize their operational advantage, such DACs should namely gradient mismatch error and random mismatch error
provide a high linearity over a wide bandwidth, while simulta- [10]–[17]. Prior arts [10]–[13] have shown that the gradient
neously consuming low power and small area. However, it is a mismatch error can be reduced by a careful arrangement of
critical challenge to realize such DACs due to the finite output the current cells in the current cell array. However, the routing
impedance, mismatch error of the current cell, and transient- wires in [10]–[13] are complex and non-uniform and, there-
induced nonlinearity [4], which are described in the following. fore, induce a timing skew among the different current cells.
The finite output impedance of the current cell induces dis- The timing skew can be mitigated by increasing the switch
tortion [5]–[7]. To reduce this distortion, the output impedance driver’s driving ability. However, this increases the switching
of the current cell is commonly enhanced by means of current and power consumption. Therefore, in this work, a
layout arrangement, referred to as concentric parallelogram
Manuscript received November 15, 2019; revised February 8, 2020 and
March 29, 2020; accepted April 27, 2020. Date of publication May 21, routing (CPR) [8], is proposed to simultaneously reduce both
2020; date of current version August 26, 2020. This article was approved by the gradient mismatch error and the large-quantity-cell routing-
Associate Editor Hui Pan. This work was supported by the Ministry of Science induced timing skew. The other mismatch error of current
and Technology (MOST) of Taiwan. (Corresponding author: Tai-Haur Kuo.)
The authors are with the Department of Electrical Engineering, cells, namely random mismatch error, can be suppressed by
National Cheng Kung University (NCKU), Tainan 70101, Taiwan (e-mail: either dynamic element matching (DEM) [14] or calibration
[email protected]). circuits [15]–[17]. Of these two methods, DEM has a lower
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org. circuit overhead and complexity and is hence chosen in this
Digital Object Identifier 10.1109/JSSC.2020.2993672 work. The gradient mismatch error is already substantially
0018-9200 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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HUANG AND KUO: 0.07-mm2 162-mW DAC ACHIEVING >65 dBc SFDR AND < −70 dBc IM3 AT 10 GS/s WITH OIC AND CPR 2479

Fig. 1. Analysis of finite output impedance. (a) Simplified current cell array of 14-bit DAC. (b) Equivalent model of 14-bit DAC. (c) First-order function
modeling of Ru .

reduced by the proposed CPR technique. Hence, in the pro- DAC and the current sources (Mcs ) are switched to either Vop
posed DAC, DEM is used only to randomize the random or Von depending on the digital input code. To illustrate the
mismatch error. Consequently, the elevated noise floor caused finite output impedance effect and the concept of the proposed
by DEM is mitigated. OIC technique, Fig. 1(b) shows the equivalent model of the
DACs suffer from transient-induced nonlinearity due to the DAC with a digital input code Din (0 ≤ Din ≤ 16383).
previous-signal-dependent DAC output transition [4], [17]. Note that Iu and Z u are the current and output impedance of
Compared with current cells with cascoded transistors, non- the unit current cell, respectively. As shown, Z u is modeled
cascoded current cells are more susceptible to transient- by the parallel connection of a resistor Ru and capacitor
induced nonlinearity due to the larger drain voltage change of Cu . Using this equivalent model of the DAC, Section II-A
the current source during DAC output transition. Accordingly, analyzes the finite output impedance of the current cell at low
in this work, the digital return-to-zero (DRZ) method [4], [17], frequencies. Section II-B then elaborates the Din -dependent
which inserts a zero differential output between two adjacent compensation resistor, Rcp (Din ), used in the proposed OIC
signals, is used to prevent the DAC output transition from the architecture. Section II-C examines the effect of the finite
influence of the previous signal, thereby reducing the transient- output impedance at higher frequencies on Rcp (Din ). Finally,
induced nonlinearity. Although the use of the DRZ method Section II-D illustrates the approximation and process-voltage-
causes up to 6-dB output power loss in the first Nyquist zone, temperature (PVT) variation of Rcp (Din ).
it results in both a flat signal amplitude over a wide bandwidth
and an improved in-band spurious-free dynamic range (SFDR)
performance [4]. A. Finite Output Impedance at Low Frequencies
As described above, the DAC proposed in this work utilizes At low frequencies, the effect of Cu is negligible and, hence
the OIC technique to relax the requirement on the DAC output in examining the finite output impedance, only Ru needs be
impedance and the CPR technique to reduce the gradient considered. According to prior arts [6], [17], Ru (Vo ) can be
mismatch error and routing-induced timing skew. In addition, treated as a constant regardless of the output voltage Vo , where
DEMDRZ [4] is used to further suppress the mismatch error of Vo is either Vop or Von depending on whether Mcs is connected
the current cell and reduce the transient-induced nonlinearity. to Vop or Von , respectively. However, due to the channel-length
Through the use of these techniques, together with small-size modulation effect of Mcs in saturation region, Ru actually
non-cascoded current cells, the DAC achieves high linearity reduces as Vo decreases. According to the data of foundry,
over wide bandwidth, low-power consumption, small area, and the relationship between Ru and Vo can be approximated by
the ability to use a single low-voltage supply. The remainder of the first-order function Ru (Vo ) = α · Vo + β, where α is the
this article is organized as follows. Section II presents a more slope of Ru (Vo ), in which Ru reaches its maximum value,
accurate analysis of the relationship between the DAC linearity Ru_max , and minimum value, Ru_min , at Vo equal to VDD and
and the finite output impedance compared with the prior analy- VDD − (214 − 1) · Iu · R L , respectively, as shown in Fig. 1(c).
sis. The basic concepts of the proposed OIC technique and its Fig. 2 shows the ideal and nonideal transfer curves of
design tradeoffs are then introduced. Section III describes the the DAC output, VDAC , versus Din based on the equivalent
circuit implementation of the proposed 14-bit DAC using the DAC model presented in Fig. 1(b) and the first-order function
OIC and CPR techniques. Section IV presents and discusses modeling of Ru shown in Fig. 1(c). For an infinite value of
the measurement results and comparisons. Finally, Section V Ru , the transfer curve of VDAC versus Din is linear, as shown
presents brief concluding remarks. by the solid line in Fig. 2. However, for a finite and output-
voltage-dependent value of Ru , VDAC varies nonlinearly with
II. OIC A RCHITECTURE Din and causes distortion, as shown by the dashed line in
Fig. 1(a) shows the simplified current cell array of a DAC Fig. 2. According to the derivation in [5] and the first-order
with k unit current cells, where k = 214 − 1 for a 14-bit function modeling of Ru , for a full output voltage swing of

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2480 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 55, NO. 9, SEPTEMBER 2020

Fig. 2. Transfer curves of DAC output, VDAC , versus digital input code, Din ,
where VPP is the peak-to-peak voltage swing of DAC.

the DAC, the third-order distortion can be expressed as

 
 R 2L ·k 2 · (1 − α·Iu ) 
HD3 ≈ 20 · log10  
2
{4 · [α·(VDD − k·Iu · R L ) + β]}
 
 R 2 ·k 2 · (1 − α·I ) 
 L u 
= 20 · log10   2 . (1) Fig. 3. SFDR versus Ru_min with different α.
 4·Ru_min 
Compared with the analysis of prior arts based on constant
Ru [5], [6], [17], the first-order function modeling of Ru
described above leads to a more accurate expression for the
third-order distortion, HD3. Besides HD3, other distortion
components can also be derived according to the modeling of
the finite output impedance in Fig. 1; however, HD3 dominates
the SFDR for a differential DAC [5]. Fig. 3 compares the
results obtained from (1) for the SFDR with different α and
Ru_min with the equivalent results obtained from behavioral
simulations. As can be seen, the SFDR is degraded when
Ru_min decreases or α increases.

B. Operation Principle of the Proposed OIC

As shown in Fig. 4(a), the proposed OIC technique uses
a Din -dependent compensation resistor Rcp (Din ), connected
between nodes Vop and Von , to remedy the SFDR degradation
caused by finite output impedance. The current induced by
Rcp (Din ) changes the current through the load resistors, R L ,
and hence compensates the transfer curve of the nonideal
VDAC . With α = 80 M/V, Fig. 4(b) shows the transfer
curves of the nonideal VDAC for Ru_min = 20 M, and
Ru_min = 35 M, respectively. The required compensation
amount, VDAC, is equal to the difference between the non-
ideal VDAC and the compensated VDAC . Compared with the
nonideal VDAC with a large Ru , the nonideal VDAC with a small
Ru is more nonlinear, and hence a larger VDAC is required.
The resistance of the ideal Rcp (Din ) required to achieve the
compensated VDAC can be approximated as follows:
Fig. 4. Proposed OIC technique. (a) Din -dependent compensation resistor,
Nonideal VDAC (Din ) Rcp (Din ). (b) Transfer curves of ideal VDAC , and nonideal VDAC versus Din .
Rcp (Din ) ≈ · 2 · RL . (2) (c) Resistance curves of ideal Rcp (Din ) for Ru_min = 20 M and Ru_min =
V DAC (Din )
35 M.
Fig. 4(c) shows the calculated ideal Rcp (Din ) versus Din , which
are U-shaped, for Ru_min = 20 M, and 35 M, respectively.
presented in Sections II-A and II-B above assume that Z u
The resistance of the ideal Rcp (Din ) for Ru_min = 20 M is
is equal to Ru . However, at higher frequencies, the magnitude
less than that for Ru_min = 35 M to get more VDAC .
of Z u is decreased by Cu . To illustrate the effect of Cu on
VDAC in the time domain, Fig. 5(b) shows the VDAC transition
C. Finite Output Impedance at High Frequencies over a single sampling period for three different cases, namely,
Fig. 5(a) shows the frequency response of Z u , which is infinite Ru with zero Cu , finite Ru with zero Cu , and finite
modeled by the parallel connection of Ru and Cu . Since the Ru with non-zero Cu . Note that the sampling period, Ts , is
effect of Cu at low frequencies is negligible, the analyses divided into two phases, namely the DRZ phase and the signal

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HUANG AND KUO: 0.07-mm2 162-mW DAC ACHIEVING >65 dBc SFDR AND < −70 dBc IM3 AT 10 GS/s WITH OIC AND CPR 2481

Fig. 6. Simulated SFDR versus f out for 14-bit DAC with and without OIC.

D. Approximation of Rcp (Din )

The ideal U-shaped Rcp (Din ) can be approximated by a
PMOS biased with a code-dependent gate voltage VG (Din ),
as shown in Fig. 7(a). Fig. 7(b) shows two illustrative
VG (Din ) voltage plots, namely, two-level VG (Din ) and three-
level VG (Din ). For two-level VG (Din ), the PMOS operates
in the cutoff region with a large resistance to reduce the
approximation error when Din is less than 512 or greater
than 15871. By contrast, when Din is greater than 512 and
less than 15871, the PMOS operates in the triode region to
approximate the ideal Rcp (Din ). Based on Fig. 4(a) and (2), the
thresholds of Din and the PMOS resistance in the triode region
can be chosen in such a way to minimize the approximation
error, namely the difference between VDAC compensated by
PMOS with two-level VG (Din ) and VDAC compensated by
Fig. 5. (a) Frequency response of finite output impedance of unit current cell, ideal Rcp . Fig. 7(c) shows the simulated maximum absolute
Z u . (b) VDAC transition waveforms for infinite Ru with zero Cu , finite Ru with value of the approximation error versus the PMOS resistance
zero Cu , and finite Ru with non-zero Cu . (c) Normalized VDAC of illustrative with different thresholds of Din for the PMOS with two-level
a 3-bit DAC example with different output signal frequencies, f out = 0.125 fs
and f out = 0.375 fs . VG (Din ). It was found that the maximum absolute value of the
approximation error is minimized when the PMOS resistance
is equal to 30 k and thresholds of Din are set as 512 and
15871. Fig. 7(d) shows the resistance of the ideal Rcp (Din )
phase. As can be seen, the finite Ru causes a steady-state error, and the approximated resistance of the PMOS with two-level
while the non-zero Cu causes a transient-state error. Since the VG (Din ) in this work. Although VG (Din ) is constant for Din
transient state contains high-frequency components, and the between 512 and 15871, the PMOS resistance still changes
magnitude of Z u reduces at high frequencies, VDAC is more slightly with Vop and Von , thus better fitting the ideal resistance
nonlinear during the transient state than during the steady state. Rcp (Din ) and reducing the approximation error, which leads
In this work, to reduce the effect of Cu on the resistance of in turn to an additional improvement of around 2 dB in the
the ideal Rcp (Din ), a small-size unit non-cascoded current cell SFDR in this work. In addition, the PMOS is designed as small
is used and placed at the 5th bit from the least significant bit. as possible. Therefore, the additional parasitic capacitance
Therefore, when using OIC, the SFDR is greater than 70 dBc introduced by the PMOS at the output node is only 0.15 fF.
according to circuit-level simulations, while the equivalent This value is much smaller than that of the current cell
Cu of the small-size unit non-cascoded current cell is less array. Consequently, the additional parasitic capacitance of
than 0.1 fF. Fig. 5(c) shows the VDAC transitions of a 3-bit the PMOS at the output node has only a negligible impact
DAC example with different output signal frequencies (i.e., on the SFDR. Fig. 7(e) shows the approximation error versus
f out = 0.125 f s and f out = 0.375 f s ). The DRZ phase prevents Din with the approximated Rcp (Din ) obtained using the PMOS
the VDAC transition of the present sampling period from the with two-level VG (Din ) and PMOS with three-level VG (Din ),
influence of the previous period. In other words, the VDAC respectively. It is seen that the approximation error obtained
transition of the present sampling period is dependent only on using the approximated Rcp (Din ) is smaller than that obtained
the present Din regardless of f out . As a result, the required without the approximated Rcp (Din ). According to the results
resistance of the ideal Rcp (Din ) is nearly independent of f out . presented for three-level VG (Din ) in Fig. 7(b), (d), and (e), a
Fig. 6 shows the simulated SFDR versus f out for a 14-bit DAC better Rcp (Din )-fit PMOS resistor for an improved linearity
with and without the proposed OIC technique, respectively. can be obtained when VG (Din ) has more levels. However,
In the simulation, DEMDRZ is enabled and the resistance of two-level VG (Din ) is sufficient to achieve SFDR better than
Rcp (Din ) is not changed for different f out . The results confirm 70 dBc. Hence, for reasons of simplicity, two-level VG (Din )
that the SFDR improvement yielded by the OIC technique was chosen for implementation in this work. Fig. 8 shows the
is nearly independent of f out over the entire Nyquist band at simulated SFDR improvement versus the variation of Rcp /Z u
10 GS/s. caused by PVT variation. It is seen that even with ±40%

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2482 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 55, NO. 9, SEPTEMBER 2020

Fig. 8. Simulated SFDR improvement versus variation of Rcp /Z u caused by

PVT variation.

input code, Din , is segmented into three unary MSB bits, three
unary upper LSB (ULSB) bits, three unary LSB bits, and five
binary lower LSB (LLSB) bits. The upper 9 bits and lower 5
bits pass through the DEM and delay equalizer, respectively,
and enter the DRZ circuit. Depending on the DRZ outputs, the
switch drivers control the switch pairs of the current cells in
such a way as to generate the DAC output. In addition, during
the DRZ phase, the DRZ turns ON all of the switch pairs of
the current cells to produce a zero differential DAC output,
i.e., VDAC = Vop − Von = 0.
Section III-A introduces the sizing and placement of the unit
current cell in the proposed DAC. Section III-B describes the
proposed CPR technique used to reduce the gradient mismatch
error. Finally, Section III-C introduces the two-level VG (Din )
generator used in the proposed OIC technique.

A. Compact Layout of Unit Current Cell

Fig. 10 shows the circuit diagram of the current cell array,
where the unit current cell is used for the most significant
bit of the LLSB, i.e., LL5 , rather than the least significant
bit of the LLSB, i.e., LL1 , in order to reduce the total layout
area of the current cell array. Conventional unit current
cell comprises switch pair transistors MSW , a cascoded
transistor MCAS , a current-source transistor MCS , and a long
metal interconnect [4]. However, the present non-cascoded
current cells omit MCAS . Furthermore, to shorten the metal
interconnect and reduce the parasitic capacitance between
MSW and MCS , MCS is placed together with its own MSW
in a small area. To make the layout of the unit current cell
compact, the width of MCS is designed as the minimum
layout width of two minimum-size MSW plus the distance
between them, as shown in the bottom-right of Fig. 10. The
Fig. 7. (a) PMOS biased with code-dependent gate voltage, VG (Din ).
(b) Illustrative two-level VG (Din ) and three-level VG (Din ). (c) Simulated
length of MCS is obtained from the device mismatch data
maximum absolute value of approximation error versus PMOS resistance and the required full-scale DAC output current. The LSB
with different thresholds of Din for the PMOS with two-level VG (Din ). (d) (L 1 –L 7 ), ULSB (UL1 –UL7 ) and MSB (M1 –M7 ) current cells
Approximated resistances of PMOS with two-level VG (Din ) and three-level
VG (Din ). (e) Approximation error versus Din with approximated Rcp (Din ) by
are formed by the parallel connection of 2, 16, and 128
PMOS with two-level VG (Din ) and PMOS with three-level VG (Din ). unit current cells, respectively. In addition, the LL4 and LL3
current sources are formed via the series connection of 2 and 4
variation of Rcp /Z u , the simulated SFDR improvement is still MCS , respectively. For the LL2 and LL1 bits, the width of the
larger than 5 dB by using the simple PMOS-based Rcp (Din ) series-connected four MCS is divided by 2 and 4, respectively.
with two-level VG (Din ). Fig. 11 shows the simulated SFDR of the proposed DAC
versus the random mismatch of the current source with and
III. DAC W ITH OIC AND CPR T ECHNIQUES without DEM, respectively, where the random mismatch of
Fig. 9 shows a block diagram of the proposed 14-bit DAC the current source is modeled as a Gaussian distribution with
architecture. A higher partition level of segmentation results in standard deviation (σ ). It is noted that each SFDR is the worst
lower implementation area, including the current cells, switch case in the 3σ range (i.e., 99.7% yield) over 10 000 Monte-
drivers, and DEM [14]. Therefore, in this work, the digital Carlo simulation runs. As can be seen, for an SFDR larger than

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HUANG AND KUO: 0.07-mm2 162-mW DAC ACHIEVING >65 dBc SFDR AND < −70 dBc IM3 AT 10 GS/s WITH OIC AND CPR 2483

Fig. 9. Architecture of the proposed DAC with CPR and OIC techniques.

Fig. 10. Circuit diagram of current cells with 3 + 3 + 3 + 5 segmentation.

problem, this work reduces the gradient mismatch through a

careful design of the layout arrangement of the current cells.
The proposed DAC incorporates seven MSB (M1 –M7 ) current
cells, where each cell is divided into 32 identical subcells
as shown in Fig. 12(a) and each subcell contains four unit
current cells. Fig. 12(b) shows a simple layout arrangement of
the seven current cells. The routing for the interconnection of
the subcells within each MSB current cell is uniform. Hence,
Fig. 11. Behavior simulation of DEM in the proposed DAC. (Note that no timing skew occurs between the different MSB current
current source mismatch of 1.6% (σ ) is chosen for unit current cell).
cells. However, the reduction of the gradient mismatch error
produced by this arrangement of the current cells is insufficient
70 dBc, the allowable σ of the random mismatch of current-
for high-resolution DACs. Fig. 12(c) thus shows an alternative
source for the unit current cell without DEM is around 0.45%.
layout arrangement based on the well-known Q 2 random
However, when DEM is applied, the permissible value of σ
walk method [10]. Compared with the simple arrangement
increases to 1.6%. As described above, the MCS length can
in Fig. 12(b), the random walk arrangement has a common
be calculated from the device mismatch data. For 1.6% (σ )
centroid and, therefore, achieves a lower gradient mismatch
random mismatch, MCS for the LL5 bit is sized as follows:
error. However, the total routing lengths used to connect the
width = 0.44 μm and length = 0.85 μm, while MSW is sized
subcells of each MSB cell are different. Furthermore, the
as width = 0.1 μm and length = 0.05 μm. As a result, the
lengths of the routings used to connect any two adjacent
layout area of the unit current cell is around 0.8 μm2 .
subcells of the same MSB current cell are not the same. Hence,
a timing skew is induced between the current cells.
B. Concentric Parallelogram Routing To reduce the gradient mismatch error, while simultaneously
The DEM reduces the distortion induced by the mis- equalizing the routing-induced delay, this article proposes the
match, including both the random mismatch and the gradient CPR arrangement shown in Fig. 13, in which the 32 subcells
mismatch. However, it raises the noise floor. To mitigate this of each MSB current cell are arranged in the form of a

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2484 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 55, NO. 9, SEPTEMBER 2020

Fig. 13. Proposed CPR technique for seven MSB current cells and seven
ULSB current cells.

Fig. 14. (a) Gradient mismatch error profile with joint error distribution
(rotation angle of profile is zero degree). (b) Simulated SFDR versus rotation
angle for different current cell array layouts.

from the output of the switch driver to the 32 subcells of each

MSB current cell, the routing wires used to interconnect the
Fig. 12. Layout arrangements of seven current cells (note each cell has 32 32 subcells are arranged in the form, as shown in Fig. 13.
subcells). (a) Illustration of a subcell, (b) simple layout (no common centroid),
and (c) Q 2 random walk layout (common centroid). As shown, each MSB current cell has two routing paths from
the vertex (i.e., the output of the switch driver) to the diagonal
vertex of the parallelogram. The number of connected subcells
parallelogram evenly distributed over the x- and y-axes. Since in each routing path of every MSB current cell is, therefore,
the parallelograms of the seven MSB current cells are concen- always equal to 16. Moreover, the length of the routing for
tric, the gradient mismatch error among the cells is reduced. connecting any two adjacent subcells of the same MSB current
Furthermore, to mitigate the mismatch between the MSB and cell is always equal to the length of the diagonal of the subcell.
ULSB segments, each ULSB current cell, which is divided into Given the routing path arrangement shown in Fig. 13, the delay
four identical subcells, is allocated within the layout array of of the switch control signal from the output of the switch
the MSB current cells. To deliver the switch control signal driver to the subcells in the same column of each MSB current

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HUANG AND KUO: 0.07-mm2 162-mW DAC ACHIEVING >65 dBc SFDR AND < −70 dBc IM3 AT 10 GS/s WITH OIC AND CPR 2485

of Q 2 random walk are comparable. When the routing-induced

timing skew at 10 GS/s is introduced, the simulated SFDR of
the Q 2 random walk layout degrades to less than 50 dBc. How-
ever, that of the proposed CPR remains higher than 70 dBc.

C. Two-Level VG (Din ) Generator

Fig. 15(a) shows the circuit implementation of the L-level
VG (Din ) generator, where L = 2 is chosen in this work since
two-level VG (Din ) is sufficient to achieve SFDR better than
70 dBc. As shown, the L-level VG (Din ) generator with L = 2
is composed of a digital comparator with a threshold of
Dth1 = 512, a retiming DFF, a switch driver, and a current
cell. The assistant clock Clkast, for the VG (Din ) generator is
used to determine the timing of the VG transition through the
retiming DFF. To prevent VDAC from VG transition-induced
non-linearity, the VG transition point is located at the middle
of the DRZ phase, as shown in Fig. 15(b). With this timing
arrangement, the variation tolerance of the rising edge of Clkast
is as much as ±25% of sampling period.

IV. M EASUREMENTS AND C OMPARISONS

The DAC, which was fabricated in a 28-nm CMOS process,
has an active area of 285 × 246 μm2 , as shown in Fig. 16.
The DAC output current was converted to a voltage through an
off-chip 50- resistive differential load and coupled to a spec-
Fig. 15. (a) Circuit implementation of L-level VG (Din ) generator for OIC. trum analyzer through a balun [4], [17], [18]. Unless otherwise
(b) Time-domain waveform of L-level VG (Din ) generator with L = 2. specified, all of the following measurements were performed
with DEM ON and a full-scale output current of 16 mA, which
corresponds to a 400-mV peak-to-peak output voltage swing
and generates a sine wave of −10 dBm due to the intrinsic
DRZ effect. In addition, in this work, the output power of the
DAC with finite output impedance is about 0.09 dB smaller
than that of a DAC with infinite output impedance. Although
the proposed OIC technique cannot recover the degradation of
the output power caused by the finite output impedance, it can
linearize the resultant nonlinearity.
Fig. 17(a) shows the measured spectra with a 117 MHz
Fig. 16. Chip photograph.
signal clocked at 10 GS/s. When DEM is OFF, the measured
SFDR is 62.2 dBc, which is limited mainly by the random
cell is equal since the switch control signal passes through mismatch error of the current cell. When DEM is ON but OIC
the same routing length and the same number of subcells. is not applied, the measured SFDR improves to 65.2 dBc and
Consequently, the routing-induced timing skew error among is limited by the finite output impedance effect. When the OIC
the different MSB cells is greatly reduced. is enabled, the measured SFDR further improves to 75.2 dBc.
In accordance with [4], [11], and [13], the gradient mis- Fig. 17(b) shows the measured spectra for a 4570 MHz signal
match quantity of the proposed CPR design was verified by clocked at 10 GS/s. When DEM is OFF, the measured SFDR
MATLAB simulations using a joint error distribution (50% is 51.0 dBc, which is mainly limited by the random skew
linear +50% quadratic). The maximum gradient mismatch was variation from the switch drivers. When DEM is ON but OIC
equal to 2% and provided sufficient tolerance to maintain a is not applied, the measured SFDR improves to 57.8 dBc and
high yield, as shown in Fig. 14(a). A rotation angle parameter is limited by the finite output impedance effect. When OIC is
was used to simultaneously rotate the x- and y-axes of the enabled, the measured SFDR further improves to 65.5 dBc.
gradient mismatch profile in the clockwise direction in order The power attenuation of the 4570 MHz signal is caused
to model the error distribution under various chip allocations by the pad and PCB parasitics, and the balun insertion loss.
within a silicon wafer. Fig. 14(b) shows the simulated SFDR Fig. 18 shows the measured output power versus output signal
versus the rotation angle for the three current cell array frequency, f out , with and without the de-embedded power
arrangements described above (i.e., simple, random walk and attenuation, respectively. As shown in Fig. 19(a) and (b),
CPR). When the routing-induced timing skew is ignored in the measured third-order inter-modulation distortion (IM3),
every case, the simulated SFDR of the proposed CPR and that which was tested at signal frequencies of 4570 and 4648 MHz

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2486 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 55, NO. 9, SEPTEMBER 2020

Fig. 17. Measured spectra for (a) SFDR with 117 MHz signal clocked at 10 GS/s and (b) SFDR with 4570 MHz signal clocked at 10 GS/s.

Fig. 18. Measured output power versus output signal frequency, f out .

clocked at 10 GS/s, improved from −60 to −70.8 dBc when

the OIC technique was enabled. In other words, the OIC
technique effectively remedies the finite output impedance
effect. Fig. 20(a) and (b) summarizes the measured SFDR and
IM3 versus output signal frequency, f out , clocked at 10 GS/s,
respectively. The results show that the measured SFDR and
IM3 improved by at least 7.7 and 10 dB, respectively, at
10 GS/s when the OIC technique is enabled. For the 4570 MHz
signal clocked at 10 GS/s, Fig. 17(b) shows that the measured Fig. 19. Measured spectra for IM3 with signal frequencies of 4570 and
HD3 improvement with OIC is around 10 dB. Since both 4648 MHz clocked at 10 GS/s. (a) Without OIC. (b) With OIC.
the power of HD3 and the power of the output signal are
attenuated, another spur at low frequency becomes larger than conditions unchanged). When the temperature is increased
HD3, as shown in the bottom-right corner of Fig. 17(b). from 10 ◦ C to 40 ◦ C with a supply voltage of 1.1 V and
As a result, the measured SFDR improvement with OIC is a full-scale output current of 16 mA, the measured SFDR
actually only 7.7 dB rather than 10 dB. In addition, Fig. 20(c) improvement with OIC is larger than 7.9 dB. In addition,
shows the measured noise spectral density (NSD) of signals when the supply voltage is increased from 1.07 to 1.13 V at a
clocked at 10 GS/s. As shown, the NSD varies from −161 to temperature of 25 ◦ C and a full-scale output current of 16 mA,
−158 dBm/Hz over the 5-GHz Nyquist bandwidth range. the measured SFDR improvement with OIC is greater than
Fig. 21 shows the measured SFDR versus the temperature, 6.6 dB. Finally, when the full-scale output current is increased
supply voltage, and full-scaled output current (with the other from 14.5 to 17.5 mA with a constant temperature of 25 ◦ C and

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HUANG AND KUO: 0.07-mm2 162-mW DAC ACHIEVING >65 dBc SFDR AND < −70 dBc IM3 AT 10 GS/s WITH OIC AND CPR 2487

TABLE I
C OMPARISON OF THE DAC W ITH O THER S TATE - OF - THE -A RT CMOS
N YQUIST DAC S W ITH f s ≥ 6 GHz AND R ESOLUTION ≥ 10 Bits

Fig. 20. (a) SFDR, (b) IM3, and (c) NSD versus output signal frequency,
f out , clocked at 10 GS/s.

Fig. 22. Common FoM versus f s for proposed DAC and other state-of-the-art
CMOS Nyquist DACs with f s ≥ 1 GHz and resolution ≥ 10 bits.

[3], [16], [18]. Using the OIC and CPR, the proposed DAC
achieves a high linearity over a wide bandwidth and operates
from a single 1.1-V supply. The power consumption from the
single 1.1 V supply clocked at 10 GS/s is only 162 mW, which
is much smaller than in [1], [3], [16], and [18]; even with a
lower f s . Furthermore, the active area of the IC is less than one
seventh of that of the others. Fig. 22 plots a common figure-
of-merit (FoM) [4], [14], [19] versus f s for the proposed DAC
and the compared state-of-the-art CMOS Nyquist DACs with
f s ≥ 1 GHz and resolution ≥ 10 bits. The envelope is curve-fit
by the two best prior state of the arts. It is seen that, compared
with the envelope, this work achieves a 9× better FoM with
f s equal to 10 GS/s and a 1.6× higher f s with the same FoM.

V. C ONCLUSION
Fig. 21. Measured SFDR versus (a) temperature, (b) supply voltage, and This article has proposed a DAC with OIC and CPR
(c) full-scaled output current with other conditions unchanged.
techniques to improve the SFDR and IM3 performance. The
two techniques additionally enable the use of small-size non-
a supply voltage of 1.1 V, the measured SFDR improvement cascoded current cells, which reduce the area and routing
with OIC exceeds 9.5 dB. parasitic capacitance of the current cell array, and hence widen
For a smaller output swing, the nonlinearity caused by the the bandwidth, relax the requirement of switch driver’s driving
finite output impedance is also smaller. In addition, if Din is ability, and reduce the power consumption. The measurement
limited to the region between 512 and 15871, for which the results have shown that the implemented DAC achieves a high
output swing is 0.9375 of the full-scale range, the PMOS will linearity over a wide bandwidth, a low-power consumption, a
always operate in the triode region with a fixed gate voltage in small area, and the ability to use a single low-voltage supply.
this work. However, the PMOS resistance still changes slightly Consequently, the proposed OIC and CPR techniques provide
with Vop and Von . As a result, the measured SFDR with OIC an effective means of resolving the low output impedance and
at a small output swing still shows some improvement, e.g., a critical strict timing skew issues of DAC when more advanced
2-dB measured SFDR improvement when output swing is −6 processes are used and wider bandwidths are targeted.
or −12 dBFS. Notably, if VG (Din ) has more levels, the SFDR
at small output swings will show further improvement. ACKNOWLEDGMENT
Table I compares the measured performance of the DAC The authors would like to acknowledge the chip fabrication
with that of other state-of-the-art CMOS Nyquist DACs with support provided by Taiwan Semiconductor Research Institute
sampling frequency f s ≥ 6 GHz and resolution ≥10 bits [1], (TSRI), Taiwan.

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2488 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 55, NO. 9, SEPTEMBER 2020

R EFERENCES [19] M. Clara, W. Klatzer, B. Seger, A. D. Giandomenico, and L. Gori, “A

1.5 V 200 MS/s 13b 25 mW DAC with randomized nested background
[1] V. Ravinuthula et al., “A 14-bit 8.9 GS/s RF DAC in 40 nm CMOS calibration in 0.13 μm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb.
achieving >71dBc LTE ACPR at 2.9 GHz,” in Proc. IEEE Symp. VLSI 2007, pp. 250–251.
Circuits (VLSIC), Jun. 2016, pp. 1–2.
[2] L. Duncan et al., “A 10-bit DC-20-GHz multiple-return-to-zero DAC
with >48-dB SFDR,” IEEE J. Solid-State Circuits, vol. 52, no. 12,
pp. 3262–3275, Dec. 2017.
[3] C. Erdmann et al., “16.3 A 330 mW 14b 6.8 GS/s dual-mode RF DAC
in 16 nm FinFET achieving −70.8 dBc ACPR in a 20 MHz channel at Hung-Yi Huang (Student Member, IEEE) was
5.2 GHz,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. born in Tainan, Taiwan, in 1987. He received the
Papers, Feb. 2017, pp. 280–281. B.S. degree (Hons.) in electrical engineering from
[4] W.-T. Lin, H.-Y. Huang, and T.-H. Kuo, “A 12-bit 40 nm DAC achieving National Cheng Kung University, Tainan, in 2010,
SFDR >70 dB at 1.6 GS/s and IMD <61 dB at 2.8 GS/s with DEMDRZ where he is currently pursuing the Ph.D. degree.
technique,” IEEE J.Solid-State Circuits, vol. 49, no. 3, pp. 708–717, His research interests include Nyquist and over-
Mar. 2014. sampling ADCs and DACs.
[5] S. Luschas and H.-S. Lee, “Output impedance requirements for Mr. Huang received the Annual Best Analog
DACs,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2003, IC-Design Award from the Taiwan Semiconductor
pp. I-861–I-864. Research Institute (TSRI) of Taiwan in 2015. He is
[6] C.-H. Lin et al., “A 12 bit 2.9 GS/s DAC with IM3 <−60 dBc beyond an Honorary Member of the Phi Tau Phi Scholastic
1 GHz in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 12, Honor Society, Taiwan.
pp. 3285–3293, Dec. 2009.
[7] P. Palmers and M. J. Steyaert, “A 10-Bit 1.6-GS/s 27-mW current-
steering D/A converter with 550-MHz 54-dB SFDR bandwidth in
130-nm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57,
no. 11, pp. 2870–2879, Nov. 2010.
[8] H.-Y. Huang and T.-H. Kuo, “A 0.07 mm2 210 mW single-1.1 V-supply
14-bit 10 GS/s DAC with concentric parallelogram routing and output Tai-Haur Kuo (Senior Member, IEEE) was born in
impedance compensation,” in Proc. IEEE Symp. VLSI Circuits (VLSIC), Tainan, Taiwan, in 1960. He received the B.S. degree
Jun. 2019, pp. C136–C137. in electrical engineering from National Cheng Kung
[9] A. Nazemi et al., “3.4 A 36 Gb/s PAM4 transmitter using an 8b 18 GS/S University (NCKU), Tainan, in 1982, and the M.S.
DAC in 28 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) and Ph.D. degrees in electrical engineering from the
Dig. Tech. Papers, Feb. 2015, pp. 58–59. University of Maryland, College Park, MD, USA, in
[10] G. A. M. Van der Plas, J. Vandenbussche, W. Sansen, M. S. J. Steyaert, 1988 and 1990, respectively.
and G. G. E. Gielen, “A 14-bit intrinsic accuracy Q2 random walk CMOS In 1982, he joined Military Police, Taipei, Tai-
DAC,” IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1708–1718, wan, as a Reserve Officer, where he was elevated
Dec. 1999. to Second Lieutenant and finally promoted to the
[11] Y. Cong and R. L. Geiger, “Switching sequence optimization for Military Police Captain of the Taipei Train Station.
gradient error compensation in thermometer-decoded DAC arrays,” IEEE From 1984 to 1986, he was an Analog Integrated Circuit (IC) Designer with
Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 7, the Industrial Technology and Research Institute (ITRI), Hsinchu, Taiwan.
pp. 585–595, Jul. 2000. In 1989, he joined the Aerospace Technology Center of Allied-Signal,
[12] J. Deveugele, G. Van der Plas, M. Steyaert, G. Gielen, and W. Sansen, Columbia, MD, USA, where he was involved in the research on the design
“A gradient-error and edge-effect tolerant switching scheme for a high- of monolithic ultrahigh-speed RTD-HEMT ICs. From 1990 to 1992, he was
accuracy DAC,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, initially a Design Engineer with Integrated Device Technology, Santa Clara,
pp. 191–195, Jan. 2004. CA, USA, and then a Project Manager with ITRI. In 2004, he joined Advanic
[13] D.-H. Lee, Y.-H. Lin, and T.-H. Kuo, “Nyquist-rate current-steering Technologies, Tainan, as the President. In 2005, he joined Elite Semiconductor
digital-to-analog converters with random multiple data-weighted aver- Memory Technology, Hsinchu, as the Vice President. He joined the Board of
aging technique and Q N rotated walk switching scheme,” IEEE Trans. Directors with ChipMOS Technology, Hsinchu, in 2012, Holtek Semiconduc-
Circuits Syst. II, Exp. Briefs, vol. 53, no. 11, pp. 1264–1268, Nov. 2006. tor, Hsinchu, in 2016, Zilltek Technology, Hsinchu, in 2016, and Taiwan IC
[14] W.-T. Lin and T.-H. Kuo, “A compact dynamic-performance-improved Industry and Academia Research Alliance, Hsinchu, in 2016. Since 1992, he
current-steering DAC with random rotation-based binary-weighted selec- has been with the Department of Electrical Engineering, NCKU, where he
tion,” IEEE J. Solid-State Circuits, vol. 47, no. 2, pp. 444–453, became a Professor in 1997 and is currently a Distinguished Professor. He
Feb. 2012. holds 43 patents. His current research interests include data converters, delta–
[15] Y. Tang et al., “A 14 bit 200 MS/s DAC with SFDR >78 dBc, IM3 sigma modulators, class-D audio amplifiers, energy harvesting, and power
< −83 dBc and NSD < −163 dBm/Hz across the whole nyquist band management ICs.
enabled by dynamic-mismatch mapping,” IEEE J. Solid-State Circuits, Dr. Kuo received the Annual Personal Special Contribution Award from
vol. 46, no. 6, pp. 1371–1381, Jun. 2011. ITRI in 1986, the Outstanding Teaching Excellence Award from NCKU in
[16] C.-H. Lin et al., “A 16 b 6 GS/s Nyquist DAC with IMD < −90dBc up 2012, the Outstanding Industry-Academy Cooperation Achievement Award
to 1.9 GHz in 16 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. from NCKU in 2012, the Technical Achievement Award and the Himax Award
(ISSCC) Dig. Tech. Papers, Feb. 2018, pp. 360–361. from the IEEE Tainan Section in 2015 and 2016, the Outstanding Technology
[17] W.-H. Tseng, C.-W. Fan, and J.-T. Wu, “A 12-bit 1.25-GS/s DAC in Transfer Award and the Outstanding Research Award from the Ministry of
90 nm CMOS with >70 dB SFDR up to 500 MHz,” IEEE J. Solid- Science and Technology of Taiwan in 2016 and 2018, and the Takuo Sugano
State Circuits, vol. 46, no. 12, pp. 2845–2856, Dec. 2011. Award of the IEEE International Solid-State Circuits Conference (ISSCC) in
[18] S. Su and M. S.-W. Chen, “A 16-bit 12-GS/s single-/dual-rate DAC with 2020. He was a co-recipient of five Annual Best Analog IC-Design Awards
a successive bandpass delta-sigma modulator achieving < −67-dBc IM3 from the Taiwan Semiconductor Research Institute (TSRI), Taiwan. He served
within DC to 6-GHz tunable passbands,” IEEE J. Solid-State Circuits, on the Technical Program Committee of the IEEE ISSCC. He served as a
vol. 53, no. 12, pp. 3517–3527, Dec. 2018. Guest Editor for the IEEE J OURNAL OF S OLID -S TATE C IRCUITS .

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