A 2GS/s 9-bit 8-12x Time-Interleaved Pipeline-SAR

ADC for a PMCW Radar in 28nm CMOS

Oscar E. Mattia∗ , Davide Guermandi, Guerric de Streel, Mark Ingels, Andy Dewilde, Piet Wambacq∗ , Jan Craninckx
IoT Sensing, imec, Leuven, Belgium
∗ also with ETRO Department, Vrije Universiteit Brussel, Brussels, Belgium
Email: [email protected]

Abstract—This paper describes a 2 GS/s 9-bit 8-12x time- a few mW. Instead, programmability, simplicity of calibration
interleaved analog to digital converter for a millimeter-wave and silicon area are given priority.
phase-modulated continuous-wave radar in 28 nm CMOS. The
lane samples are quantized by a 2-stage pipelined-successive- Shown in Fig. 1 is the PMCW radar receiver (RX) block
approximation-register algorithm, where a novel dynamic am- diagram. It is part of a larger SoC that comprises two iden-
plifier with output common-mode control performs the residue tical transmitter and receiver chains, enabling multiple-input,
amplification with high linearity. Characterization of the con- multiple-output (MIMO) radar like in [1]. The chip contains
verter including the radar analog baseband is presented, as well complete millimeter-wave functionality (PA, LNA, injection-
as reconstructed radar waveforms with TX leakage and a static locked oscillators, mixers), complete mixed-signal functional-
target. ity (ADCs, shared PLL for LO and CK frequency synthesis)
Keywords—analog to digital converter, PMCW radar, pipeline, and the first stage of digital functionality (code generator, cor-
successive approximation, time interleaved, CMOS relators, accumulators, memory storage and output interface).
The baseband variable gain amplifiers (VGA) are implemented
as fully-differential Miller OTAs with programmable resistive
I. I NTRODUCTION feedback and 1 GHz bandwidth.
Phase modulated continuous wave (PMCW) radars are
based on binary sequences with good periodic autocorrelation
properties, such as M-sequences [1]. The sequence is used
to binary phase modulate the RF or mm-wave carrier, that is
radiated over the air, reflected by the targets to the receiver
and down-converted by the same carrier. Delayed versions of
the sequence are then correlated with the digitized received
data, where non-zero correlation values indicate the location
of the targets in so called range bins. If a target is moving
in the direction of the radar, the reflected frequency will be
slightly shifted (Doppler shift) from the transmitted one. An
accumulation of coherently sampled sequences increases the
signal-to-noise ratio (SNR), and a further FFT of accumulated Fig. 1. Top-level block diagram of one 79 GHz PMCW radar RX.
complex values (I and Q) is used to compute the target’s
velocity, producing a range-Doppler mesh. Non-linearity in the The ADC architecture and its main building blocks are
signal path increases the noise floor and creates ghost targets, discussed in Section II. Section III presents experimental
reducing the detection accuracy [2]. results for the ADC characterization and a reconstructed radar
waveform based on a static target. Section IV concludes the
For a range resolution of 7.5 cm a 2 Gbps chirp rate
paper.
is needed, and therefore a 2 GS/s converter, which is im-
plemented in a time-interleaved (TI) fashion. Thanks to the
II. ADC A RCHITECTURE
correlation and accumulation of multiple ADC samples, it is
convenient to have a non-integer ratio of the number of ADC A block diagram of the implemented ADC is shown in Fig.
lanes and the modulated sequence length (e.g. 10 or 11 for 2. The number of active lanes can be programmed between
a 504 symbol APS-sequence, or 8-12 for a 511 symbols M- 8 and 12, to accommodate a variety of sequence lengths and
sequence), such that the same symbol of subsequent sequences accumulation factors, with a fixed clock of 1.975 GHz provided
is converted by different lanes. If the number of averaged by the on-chip PLL (see Fig. 1). To overcome the limitation
sequences is a multiple (or much larger) of the number of of the ADC in [1], each lane is designed for 9-bit quantization
lanes, each symbol experiences the non-idealities of all lanes, and 8-bit spurious free dynamic range (SFDR). As discussed
resulting in desensitization of the TI non-idealities. Differing in [1] noise is less of a concern due to the integration nature
from recent trends in data-converter research, power consump- of the signal processing. Some extra noise can be beneficial,
tion of the ADC is not so relevant for this application, where an since it results in quantization level dithering for small target
antenna path consumes around 500 mW for an ADC power of reflections in presence of large clutters or TX-leakage.
Fig. 2. Programmable Time-Interleaved ADC block diagram.

A common input buffer drives the bootstrapped samplers,

that are activated by non-overlapping clock phases. Quanti-
zation is performed by 2 pipelined-SAR stages: 5 bits are Fig. 3. ADC input buffer schematic for single-ended input. Implementation
asynchronously resolved in the first stage by a low-power is pseudo-differential.
double tail comparator S1, followed by a novel dynamic
residue amplifier with a gain of 4, and a second stage that also
asynchronously resolves 4+2 bits with increasingly lower noise
comparators S2 and LN [3]. There is 1-bit redundancy between
the 1st and 2nd stage, and 1-bit in the second stage last
conversion, totaling 9 quantization bits [3]. One of the main
challenges in such a design is to maintain more than 50 dB
SFDR for the whole signal path across 1 GHz of bandwidth
and under a 0.9 V supply. Key contributors to achieve this
Fig. 4. Sampling network simplified schematics for single-ended input.
specification are the ADC input buffer and residue amplifier.

A. ADC Input Buffer and Sampling Network capacitances being split) are connected to VDD. During the
For the required bandwidth a source-follower type of buffer sampling phase R2 is open, S closed (bootstrapped) and the
is preferred over an op-amp based one. The main drawback of input voltage is sampled on CP + CS . After sampling, reset
the source-follower is the common-mode voltage drop from is released, and the DAC is connected to the comparator input
input to output. In order to achieve the desired linearity with nodes by means of the series capacitor divider. At release of
a 0.9 V supply, the full-scale has been set at 440 mVP P,dif f . reset the bottom plate of half DAC is connected to ground to
The buffer is designed for more than 70 dB SFDR, not to operate in split mode – if the DAC would have been in this
affect the overall receiver performance. Shown in Fig. 3, it is position during reset, its output could go above VDD during
an improvement of the one in [1] and partially inspired by [4]. conversion.

Transistors M1 to M7 realize a flipped source follower, B. Dynamic Residue Amplifier with Common-Mode Control
with the feedback implemented by the common-gate M6 and
current mirror M3-4 (ratio 4:1). R1 provides enough VDS for The proposed residue dynamic amplifier is shown in Fig.
M7, shorted by C1 for the AC signal. Transistor M7 improves 5. During the reset phase (reset = 1) nodes VOP and VOM are
the buffer linearity when the output voltage is close to its discharged to ground. When the integration phase starts, and
minimum range by copying the VDS of M3 onto M4, so that clock goes high, charge is injected from VDD to capacitances
the current of M4 is better mirrored by M3. Without M7, CDAC and CP on nodes VOP and VOM . CP is used to scale
the current of M3 will decrease with respect to M4 while the DAC contribution, implemented mostly as metal finger
reducing the output voltage due to channel length modulation. capacitors.
To achieve 9-bit matching a 300 fF DAC array is required,
while only 125 fF are needed for sampled kT/C noise. The Common-mode and differential-mode voltages are decou-
series sampling network of Fig. 4 was adopted, scaling the pled in this amplifier by pre-charging the bottom plate of part
DAC contribution to the residue voltage by CS /(CP + CS ) of the parasitic capacitance CP to VDD during the reset phase
[3]. The sampling capacitance CS and (part of) the parasitics and discharging it to VSS during the integration phase. The
CP are laid out together with the DAC and using the same discharging current on the bottom plate is a scaled replica of
unit capacitor, guaranteeing good matching between the lanes the common-mode charging current of the top plate, reducing
and reducing interleaving gain errors. the common-mode gain of the amplifier. Controlling the output
common-mode voltage at the end of integration phase is thus
At the reset phase (end of conversion) switches R and R2 possible, by selecting how much of the CP capacitance bottom
are closed. The inputs VIN P and VIN M are shorted and both plate is pre-charged to VDD. The common mode voltage
the bottom and the top plate of the DAC (represented as two is kept reasonably low, to maintain M1-3 in saturation and
significantly improve the linearity. common-mode for the 1st stage comparator, and by shorting
the amplifier’s output for the 2nd stage comparators. The
output bits of the inactive stages are masked, and an average
code is sought with a binary search algorithm. The amplifier
gain and offset calibration is done in a two-step procedure. The
first round compensates coarsely for the gain, and coarsely
for the offset on the 1st stage auxiliary DAC. During the
second run, only the gain is calibrated finely with half the
resolution of the first run. Finally, the small residual offset is
compensated by re-calibrating the 2nd stage comparators, now
without shorting the amplifier’s output.

III. M EASUREMENT R ESULTS

The SoC is fabricated in 28 nm CMOS and powered by
0.9/1.8 V supplies for the core and I/Os, respectively. A die
micrograph of the baseband and 12-lane ADC is shown in Fig.
6. The ADC lanes are geographically interleaved as [11, 9, 7,
...1, 10, 8, 6...0] to reduce the impact of gradients.

Fig. 6. SoC micrograph in 28 nm CMOS (left). Two mirrored ADCs for I

and Q signal paths (right), with an area of 2*12*18 µm x 500 µm each.

Fig. 5. Proposed dynamic residue amplifier with output common-mode

control simplified schematics and simulated waveforms with α = 0 (dotted) A. ADC Characterization
and α = 0.26 (solid).
In addition to the ADC blocks described previously, the
Shown in Fig. 5 are simulated waveforms for the bottom following results are affected by the preceding two stages
plate control α = 0 (dotted lines) and α = 0.26 (solid lines). of variable gain amplifier (VGA) and bypass input buffer,
The output common-mode has been reduced from 345 mV to as well as the clock generation and buffering of a LC-based
170 mV without affecting the differential gain of 4, improving 16 GHz PLL and divider by 8 and DSP engine (Fig. 1). An
the amplifier’s linearity. Since the 2nd stage comparator’s have integrated memory captures the data and is offloaded through
PMOS inputs, the lower common mode also improves their an SPI interface, which also allows the evaluation of each lane
decision time. separately. The following measurements are taken for 12 lanes
active, but no significant difference has been measured for any
Under typical conditions the amplifier achieves more lane combination between 8 and 12, and for 2 ADCs. In Fig. 7
than 70 dB SFDR with 2nd SAR stage full-scale output of the calibrated TI ADC FFT is shown for a low input frequency
110 mVP P,dif f including over-range. The input referred noise around 16 MHz. The interleaved ADC achieves more than
is less than 110 µVRM S and the input referred offset sigma 58 dB SFDR and 44 dB of SNDR. At high frequency, shown
is less than 4 mV. To compensate for the amplifier offset in Fig. 8, the SFDR is severely impacted by a single time-
an extra 5-bit step-down DAC is used at the 1st SAR stage interleaving spur at FS /2–FIN .
and activated together with the DAC LSB; it produces a
programmable unbalance between the positive and the negative This TI spur is caused by interference from the DSP, that
residue voltage before amplification, cancelling the amplifier couples to the ADC clock buffers through the common power
offset. supply. The ADC clock has been measured off-chip with a
spectrum analyzer, using an internal buffer bypass, not shown
C. Foreground calibration in Fig. 1. Spurs at 3/2 and 5/2 of the clock frequency corrupt
the ADC clock when the DSP is turned ON, skewing one
Calibration is performed offline, independently for each out of two rising edges, independent of the number of active
lane and only for the three comparators’ offsets, the residue lanes. Significant broadband switching noise is also picked up
amplifier gain and offset. The comparators’ offsets are straight- from the DSP, introducing excessive sampling aperture jitter
forward to calibrate, one at a time, by sampling the input and creating the side-lobe around 60 MHz of the input signal.
 normalized peak at 0 dB corresponds to the TX leakage, while
there is one target at -30 dB 20 range bins after that. The
expected noise floor of -54 dB (20 log10 (511)) is seen despite
some decay due to the input AC coupling. Most importantly
there are no visible ghosts caused by signal harmonic distortion
[2], and the range profile is not affected by the clock skew due
to the nature of the PMCW radar system.

Fig. 7. Measured calibrated ADC at low frequency (16.745 MHz).

Fig. 10. Reconstructed range profile for a static target at range bin 20. Averge
of 43 repetitions of the 511 M-seq at 1.975 GS/s.

IV. C ONCLUSION
Fig. 8. Measured calibrated ADC at close to Nyquist (950 MHz). This paper presented a high linearity PMCW radar receiver
baseband including a 9-bit 2 GS/s 8-12x time-interleaved
pipelined-SAR ADC. An improved input buffer and a novel
Harmonic distortion of the input signal, shown in Fig. 9, is
dynamic residue amplifier with output voltage common mode
measured to be better than 50 dB across all the Nyquist band.
control have been introduced. Foreground calibration was
Disregarding the clock issues, overall the total SNDR should
performed individually for each lane, where conservative siz-
be limited by thermal noise, which does not affect the radar
ing, careful layout implementation and the rotation of the
detection due to the averaging operation.
modulation sequence across the multiple lanes further atten-
uates the time-interleaving non-idealities. This was confirmed
by characterizing the baseband with a sine wave input, and
through a reconstructed range profile of an M-sequence input
including TX leakage and one static target.

ACKNOWLEDGMENT
The authors thank the imec radar team Marc Bauduin, Luc
Pauwels, Matthias Hartmann, Michael Libois, Veerle Derudder.

R EFERENCES
Fig. 9. Measured calibrated ADC signal harmonic distortion. [1] D. Guermandi, Q. Shi, A. Dewilde, V. Derudder, U. Ahmad, A. Spagnolo,
I. Ocket, A. Bourdoux, P. Wambacq, J. Craninckx, and W. Van Thillo, “A
79-GHz 2x2 MIMO PMCW Radar SoC in 28-nm CMOS,” IEEE Journal
Offline correction of residual offset and gain mismatch of Solid-State Circuits, vol. 52, no. 10, pp. 2613–2626, oct 2017.
between lanes was performed showing less than 0.1 ENOB [2] U. Ahmad, D. Guermandi, A. Medra, W. Van Thillo, and A. Bourdoux,
improvement over the on-chip foreground calibration. The “Impact of even and odd order non-linearity on PMCW radars,” 2016
ADC consumes 17 mW from a 0.9 V supply, resulting in IEEE Radar Conference, RadarConf 2016, no. 6, 2016.
a Waldem FOM of 59 fJ/conversion step at low frequency, [3] B. Verbruggen, M. Iriguchi, and J. Craninckx, “A 1.7mW 11b 250MS/s
including the input buffer but excluding the 2 GHz input clock 2× interleaved fully dynamic pipelined SAR ADC in 40nm dig-
generation. ital CMOS,” in 2012 IEEE International Solid-State Circuits Conference,
vol. 55. IEEE, feb 2012, pp. 466–468.
[4] B. Vaz, A. Lynam, B. Verbruggen, A. Laraba, C. Mesadri, A. Boumaalif,
B. Radar waveform measurements J. Mcgrath, U. Kamath, R. De Le Torre, A. Manlapat, D. Breathnach,
C. Erdmann, and B. Farley, “16.1 A 13b 4GS/s digitally assisted dynamic
The use of an arbitrary waveform generator (AWG) allows 3-stage asynchronous pipelined-SAR ADC,” in 2017 IEEE International
the characterization of the baseband impact on the radar Solid-State Circuits Conference (ISSCC), vol. 60. IEEE, feb 2017, pp.
performance separately from the RF front-end. It was used to 276–277.
emulate the radar waveform for an M-511 sequence, including
TX leakage, one static target at range bin 20, and noise. The
reconstructed range profile for an average of 43 repetitions
of the 511 M-seq at 1.975 GS/s is presented in Fig. 10. The