Silicon

https://doi.org/10.1007/s12633-023-02364-z

ORIGINAL PAPER

Design and Performance Projection of Virtually Doped Dual Gate

Junctionless IMOS
Dasari Srikanya1 · Nawaz Shafi2 · Chitrakant Sahu1

Received: 9 September 2022 / Accepted: 19 February 2023

© The Author(s), under exclusive licence to Springer Nature B.V. 2023

Abstract
This research investigates the virtually doped dual gate junctionless impact ionization MOS (DG-JL-IMOS). Virtually doped
source and drain regions are realized through the genesis of charge plasma using different work-functions for their electrodes,
easing the process complexity with simultaneous reduction of process-induced variations to implant uniform doping. The
proposed DG-JL-IMOS device exhibits two order increase in I O N /I O F F ratio at a lower source bias of −4.5 V with respect
to −5 V required for a single gate JIMOS device. This work further examines the breakdown behavior of the proposed
DG-JL-IMOS by analyzing carrier density distribution, impact ionization, and electric field profile through extensive TCAD
simulations. The proposed device exhibits a super steep sub-threshold swing (SS) of 0.6 mV /dec over several orders of drain
current, which is not achieved by any other counterpart steep-slope technologies. The effect of interface traps on the proposed
DG-JL-IMOS is studied and investigated for hysteresis in the transfer characteristics. Furthermore, analog parameters such as
transconductance (gm ), unity gain cutoff-frequency ( f T ), and current gain of the proposed device are evaluated and compared
with conventional DG-IMOS. It is observed that the proposed device shows a 2.6× increase in I O N , 1.7× higher gm , 1.6×
higher f T , and a 5 d B improvement in current gain compared to conventional DG-IMOS. The proposed DG-JL-IMOS device
breakdowns at a voltage, (VB D ) of −4.21 V , whereas DG-IMOS breakdowns at −4.75 V . The enhanced performance metrics
of DG-JL-IMOS elucidate its suitability for high-speed and high-performance analog applications.

Keywords Dual gate · Junctionless · Charge plasma · IMOS · Breakdown · Sub-threshold swing

1 Introduction to deliver low-cost integrated circuits [14]. However, the

rapid scaling of conventional MOSFETs is confronting sev-
Over the last four decades, the aggressive scaling of con- eral short channel effects [15]. Hence to continue the scaling
ventional metal oxide semiconductor field effect transistors of emerging semiconductor devices; numerous innovations
(MOSFETs) has been witnessing the enhancement of inte- and structural modifications in CMOS technologies have
grated circuits (ICs) functionality, packaging density and been proposed and implemented, such as ultra-thin body sil-
performance [11–13]. It is allowing semiconductor industries icon on insulator FETs, multi-gate FETs, band-engineered
transistors, FinFETs, vertical FETs, etc. [16,17]. But the
B Dasari Srikanya sub-threshold swing (SS) of these devices is limited to
[email protected] 60 mV /dec due to its inherent thermionic emission, so the
Nawaz Shafi possibility of a steep sub-threshold slope is not mitigated.
[email protected] The novel non-classical device structures such as tunnel field
Chitrakant Sahu effect transistors (TFETs), impact ionization MOS (IMOS),
[email protected] feedback FETs, and negative capacitance FETs (NC-FET),
etc. have been proposed by researchers for steeper sub-
1 Department of Electronics and Communication Engineering, threshold slopes [18–20].
Malaviya National Institiute of Technology Jaipur, 302017
Rajasthan, India The search for the optimal CMOS electronics successor
2 resulted in a wide range of novel device designs. The fol-
School of Electronics Engineering (SENSE), Vellore Institute
of Technology, 632014 Vellore, Tamilnadu, India lowing Table 1 represents the critical performance metrics

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Table 1 Important performance metrics of few state-of-art devices reported in the literature
Device Year L ch IO N IO F F I O N /I O F F SS Reference
Configuration (nm) (A/μm) (A/μm) ratio (mV /dec)

Vertical TFET 2016 100 10 μ 1n 104 48 Experimental [1]

NC-FET 2016 100 1.9 m 0.1 n 1.9X 107 57-59 Simulation [2]
NC-FinFET 2017 70 (L g ) 0.5 m 5n 107 18 Experimental [3]
III-V H-TFET 2011 100 5μ 0.05 n 105 60 Experimental [4]
Asymmetric gate bias JLT 2014 50 − − 107 19 Simulation [5]
NT-FET-HALO 2020 40 5.1 μ 16.8 p 3.03 × 107 42 Simulation [6]
NC-FinFET 2015 30 (L g ) 67 μ 0.01 n 6.7 × 105 55 Experimental [7]
CP-BML-FET 2021 28 0.71 m 2.97 n 2.4 × 105 65 Simulation [8]
Ge/Si SPE-V-HTFETs 2020 25 0.26 m 0.15 f 1.7 × 1010 20 Simulation [9]
FinFET 2021 5 0.95 m 10 n 0.9 × 105 78 IRDS [10]
LGAA 2021 3 0.91 m 10 n 0.9 × 105 82 IRDS [10]
Bold entries signify subthreshold swings

of the few advanced emerging devices over the recent high fabrication cost (high thermal budget process) due
years. Among these devices, negative capacitance (NC) to increased photolithography steps [26,27].
FinFET and asymmetric gate bias junctionless transistor
(JLT) achieved sub-threshold swings around 20 mV /dec. The abovementioned issues can be mitigated by introduc-
Beyond 2022 a switch to lateral gate all around (LGAA) ing the virtual doping (charge plasma) technique [28,29] in
finFET devices are expected to start with technology nodes the source and drain regions called junctionless impact ion-
less than 5 nm showing sub-threshold swings greater than ization MOS (JIMOS) reported in ref. [30,31].
80 mV /dec as projected by the international roadmap for
devices and systems (IRDS 2021). Hence the improvisation 1.1 Deliverables and Organization of this Work
of sub-threshold swing is still challenging. Impact-ionization
MOSFET (IMOS) is a gate modulated reverse biased p-i-n This paper reports a junctionless impact ionization MOSFET
diode that tends to exhibit lower OFF currents, and it can with dual gate technology delivering ideal transfer charac-
produce steep transfer characteristics with SS ≤ 5 mV /dec. teristics with nearly zero sub-threshold swing. This paper
IMOS was proposed and demonstrated experimentally by investigates proposed device’s contour study and DC per-
Gopalakrishnan et al. in 2002 for the first time [21,22]. The formance and compares it with the conventional dual gate
gate electrode of an IMOS does not cover the complete intrin- IMOS (DG-IMOS). The proposed DG-JL-IMOS induces
sic region. Unlike MOS, the conduction mechanism of IMOS heavy doping in S/D regions by charge plasma technique
is entirely different. IMOS uses avalanche impact ionization and delivers the following superior advantages that
mechanism as a carrier conduction phenomenon; therefore,
it can facilitate the abrupt transition from OFF-state to ON-
1. Fabrication with a low thermal budget.
state with a ratio I O N /I O F F greater than 107 . The reverse
2. Exhibition of ultra-steep transfer characteristics (SS ≤ 1
leakage current of the p-i-n diode is responsible for the OFF-
mV /dec).
state current of IMOS, which is very low. Thus an IMOS
3. Reduction in the operating supply voltage.
is more resistant to short channel effects (SCEs) than con-
4. Enhancement of I O N /I O F F ratio.
ventional MOS, and it has the capability to replace CMOS
for high-speed and high-performance applications [23–25].
Conventional IMOS, on the other hand, has two significant In addition, this work also focuses on studying various analog
drawbacks: performance parameters of the proposed device and com-
pares it with the conventional DG-IMOS.
The rest of this paper is organized as follows: The device
1. To commence the avalanche multiplication process, a structure, simulation setup, and physical models used for
high supply voltage is required for the device to break- TCAD simulation are described in Section 2, followed by
down. device characterization and simulation findings in Section 3,
2. Conventionally, the source, gate, and drain regions of which comprise a carrier concentration contour investigation,
an IMOS are patterned using distinct masks resulting in DC characteristics, and analog performance analysis. Finally,

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Fig. 1 Cross-sectional views of

(a) conventional n-type
DG-IMOS and (b) proposed
n-type DG-JL-IMOS

Section 4 presents some key findings and conclusions from simulations. The schockly read hall model (SRH) used for
the study. recombination with fixed carrier lifetimes; the fermidirac
model (FERMI) considered for carrier statistics to reduce
the carrier concentration in heavily doped regions; as IMOS
2 Device Structure & Simulation Framework deals with high electric fields, standard band to band tun-
neling model (BBT.STD) with direct transitions used for
Figure 1(a-b) shows the cross-sectional view of the conven- OFF state leakage current; Lombardi CVT mobility model
tional n-type DG-IMOS and proposed n-type DG-JL-IMOS. used for to include the effect of doping, temperature, par-
In the proposed DG-JL-IMOS, the source, channel and drain allel electric field and transverse electric field. Selberherr’s
are lightly p-type doped Si material with a doping concen- impact ionization model is used to account for the impact
tration of 1015 /cm 3 without any metallurgical junctions. The ionized avalanche multiplication of the carriers of the device
values of all the physical parameters of the proposed device, in the ON state. Selberherr’s impact model includes all
and conventional DG-IMOS are listed in Table 2. The length the temperature dependent parameters. When impact ion-
of the source/drain is considered identical, and spacer oxide 
ization integral, (α) approaches 1, multiplication factor
length (L G A P ) is assumed as 10 nm. The heavily doped M = 1−1 α becomes infinity and leads to avalanche break-
source and drain regions are created by charge plasma instead
down; where α denotes the impact ionization coefficient. The
of chemical doping. Heavily doped p + source and n + drain
multiplication factor for both electrons and holes is given as
regions with concentration of 5 × 1019 /cm 3 are induced by
selecting platinum (work function of 5.93 eV ) and hafnium
(work function of 3.9 eV ) for source and drain contact metal 1
Mn, p = w x (1)
electrodes, respectively [32]. Induced carrier concentration 1− 0 αn, p ex p(− 0 (αn, p − α p,n )d x  )d x
in the source and drain regions of the proposed DG-JL-IMOS
is in good agreement with the doping of conventional DG- where w is the avalanche region width. The impact ionization
IMOS. generation rate(G) for electron-hole pairs expressed as
The behavior of the structures shown in Fig. 1 are simu-
lated and verified by using TCAD Silvaco Atlas V5.32.1.R
[34]. The following physical models are invoked to sim- αn |Jn | + α p |J p |
G= (2)
ulate the behavior of the proposed device during the 2-D q

Table 2 Physical parameters

Device/Parameter Symbol DG-IMOS DG-JL-IMOS
used for the 2D simulation
Silicon thickness TSi 10 nm 10 nm
Gate oxide thickness TO X 1 nm 1 nm
Gate length LG 60 nm 60 nm
Open body length LOB 40 nm 40 nm
Gate work function φm 4.6 eV 4.6 eV
Drain doping ND 5 × 1019 /cm 3 −
Source doping NA 5 × 1019 /cm 3 −
Channel Doping NA 1015 /cm 3 1015 /cm 3
Source electrode work function φS − 5.93 eV
Drain electrode work function φD − 3.9 eV

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where |Jn | & |J p | are current densities αn & α p are the impact induces hole plasma in the source region and electron plasma
ionization coefficients for electrons and holes, respectively in the drain regions, which leads to uniform charge car-
given as rier concentration in the source and drain regions under
the thermal equilibrium state. During the OFF-state, both
   
BN B E T AN electron and hole concentrations in the channel region
αn = A N exp − (3) are less due to a lack of inversion under the gate. In
E
    contrast, in ON-state, the inversion layer under the gate
BP B E T AP is created with an increment of the gate voltage, which
α p = A P exp − (4)
E leads to an increase in electron concentration under the
gate. Consequently, the new electron-hole pairs genera-
Where as E is the position dependent electric field in the tion takes place in the open body region due to avalanche
direction of current flow and other ionization parameters breakdown, which leads to an increase in total carrier con-
are considered as default values, A N = 7.03 × 105 cm −1 , centration in the intrinsic region of the device. Figure 4(a)
A P = 6.71 × 105 cm −1 , B N = 1.231 × 106 V /cm, B P = describes the electron and hole concentration along the hor-
1.693 × 106 V /cm, B E T A N = 1, B E T A P = 1 from the izontal cutline 1 nm below Si/Si O2 interface. The electron
ATLAS simulator. The models and methods used for TCAD and hole carrier concentrations during the ON state are very
simulation are calibrated in accordance with a fabricated dou- high due to avalanche multiplication-induced breakdown of
ble spacer conventional p-i-n I-MOS by keeping the exact the carriers in the open body region of the device. It can also
dimensions [33]. Figure 2 illustrates a good match of sim- be observed that the carrier concentration during the ON state
ulation results, which implies background physics is well of the device is very high in the channel region, including the
accounted for. open body, compared to the OFF state of the device. The
cause for this change can be understood from the impact
generation rate contour profile of DG-JL-IMOS during ON
and OFF state conditions.
3 Device Characterization and Simulation Figure 4(b) shows the energy band diagram of the
Results proposed DG-JL-IMOS across a horizontal cutline drawn
approximately 1 nm below the interface of Si/Si O2 dur-
3.1 Carrier Concentration Contour Study ing ON and OFF state conditions. It is observed that the
surface accumulation of electrons in the channel region
Negative biasing at the source region instead of positive
causes energy bands to bend downwards as the gate voltage
drain biasing is considered for better electrical character-
increases. This band bending makes it easy for the electrons
ization [35]. The charge-carrier concentration contours of
in the source to spill over the channel though diffusion, which
the proposed DG-JL-IMOS under thermal equilibrium state,
leads to an increase in the electric field.
OFF state and, ON-state are shown in the Fig. 3(a-f).
Figure 5(a) depicts the electric field profile of the proposed
The work-function difference between the metal electrodes DG-JL-IMOS across a horizontal cutline drawn approxi-
mately 1 nm below the interface of Si/Si O2 for different
operating states. The electric field under the channel region is
significantly less during the thermal equilibrium state. When
VG is low or zero and VS is less than zero, the inversion layer
under the gate is underdeveloped due to which effective chan-
nel length is the entire intrinsic region (gate length + open
body length). Hence, only a fraction of the applied source
voltage is shared with the open body region [36–38]. Conse-
quently, the generated electric field in the channel region is
less to induce breakdown. Additionally, it decreases the peak
electric field at the gate-source junction, thus reducing the
risk of gate oxide breakdown. As the gate voltage increases,
the inversion layer under the gate develops. Now most of
the applied source voltage is shared with open body region.
Therefore, the lateral and transverse electric field in the chan-
nel region increases, which increases the total electric field.
Fig. 2 Model calibration of the proposed device with the fabricated Figure 5(b) shows the electric field profile of DG-JL-IMOS
results [33] operating at VDS , (VD − VS ) = 4.5 V , compared with DG-

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Fig. 3 Carrie concentration contour plots of proposed DG-JL-IMOS 0 V , VD = 0 V , VS = −4.5 V (e) hole and (f) electron under ON-state
for (a) hole and (b) electron under thermal equilibrium state (VG = 0 V , (VG = 1 V , VD = 0 V , VS = −5 V ) conditions of DG-JL-IMOS
VD = 0 V , VS = 0 V (c) hole and (d) electron under OFF-state (VG =

Fig. 4 Proposed DG-JL-IMOS

(a) electron and hole carrier
concentration and (b) energy
band diagram, along a horizontal
cutline 1nm below the Si/Si O2
interface during OFF-state and
ON-state conditions

Fig. 5 Electric field profile of

(a) proposed DG-JL-IMOS in
different operating states and (b)
proposed DG-JL-IMOS
comparison with conventional
DG-IMOS under different
biasing conditions, across a
horizontal cutline drawn
approximately 1 nm below the
interface of Si/Si O2

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IMOS operating at different supply voltages where the gate the impact generation rate of the conventional DG-IMOS at
voltage is kept fixed at 1 V . Electric field profile of DG-JL- VS = −5 V is very high, and it is comparable with the pro-
IMOS comparable with the DG-IMOS operating at VS = −5 posed operating DG-JL-IMOS at supply voltage VS = −4.5
V . The non-zero electric field at the source and drain sides V as shown in Fig. 6(c-f). The proposed DG-JL-IMOS break-
in DG-JL-IMOS is due to charge plasma. downs at −4.21 V hence it has a high impact generation rate
Further, Fig. 6(a-f) shows a detailed examination of the at VS = −4.5 V , and VG = 1 V is able to induce an impact
impact ionization process initiated in the open body region ionization process. Figure 6(g-h) depicts the impact gener-
of both conventional DG-IMOS and proposed DG-JL-IMOS, ation rate profile of conventional DG-IMOS and proposed
along with their impact ionization generation rate shown DG-JL-IMOS across a horizontal cutline drawn approxi-
in Fig. 6(g-h). The impact generation rate of conventional mately 1 nm below the interface of Si/Si O2 , respectively.
DG-IMOS during OFF-state and ON-states, respectively, at The conventional DG-IMOS has an impact generation rate of
VS = −4.5 V is depicted in Fig. 6(a-b). The impact genera- 2.88×1021 /cm 3 s and 5.8×1022 /cm 3 s, during OFF and ON-
tion rate of the conventional DG-IMOS at VS = −4.5 V is state, respectively, at VS = −4.5 V , which are significantly
very less even for VG of 1 V . The operating voltage of DG- less to induce avalanche breakdown in the open body region.
IMOS is less than its breakdown voltage (−4.75 V ) thus; At VS = −5 V , the impact generation rate of DG-IMOS
it does not induce avalanche multiplication of carriers. But during ON and OFF states are 1.1 × 1024 /cm 3 s, and 1.84 ×

Fig. 6 Impact generation rate contour plots for (a) OFF-state (b) ON- horizontal cutline drawn approximately 1 nm below the interface of
state of DG-IMOS at VS = −4.5 V , (c) OFF-state (d) ON-state of Si/Si O2 for (g) conventional DG-IMOS operating at different supply
DG-IMOS at VS = −5 V , (e) OFF-state (f) ON-state of proposed voltages, (h) proposed DG-JL-IMOS operating at VS = −4.5 V
DG-JL-IMOS VS = −4.5 V . Impact generation rate profile across a

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VS = −4.21 V . The breakdown voltage (VB D ) of the device

is extracted from the standard method, which is commonly
used in the literature [31,39,40]. The breakdown voltage was
defined as the source voltage at which the drain current sud-
denly increases. The early breakdown in DG-JL-IMOS is due
to the surface accumulation of charge carriers at the source
and drain regions.
Figure 8(a) compares the transfer characteristics (I DS
versus VG ) of proposed DG-JL-IMOS with conventional
DG-IMOS and conventional DG-MOS. The proposed DG-
JL-IMOS, DG-IMOS operated at supply voltage VS = −4.5
V , whereas conventional DG-MOS operated at supply volt-
age VDS = 1.5 V was also simulated only for the comparison
purposes. Except for supply voltage, other physical param-
eters required for the 2D simulation of the abovementioned
structures considered as same. The sub-threshold swing (SS)
Fig. 7 Breakdown characteristics (I D - VS ) of proposed DG-JL-IMOS of conventional DG-MOS and proposed DG-JL-IMOS are
and conventional DG-IMOS where VG =1 V and VD =0 V
observed as 60.9 mV /dec and 0.6 mV /dec, respectively
whereas DG-IMOS is not completely ON at this supply volt-
1031 /cm 3 s, respectively, compared with the corresponding age. However, DG-JL-IMOS can produce ultra steep transfer
values of the proposed DG-JL-IMOS is 9 × 1024 /cm 3 s and characteristics which lead to abrupt switching from OFF-
9.8 × 1030 /cm 3 s, respectively, at VS = −4.5 V . state to ON-state compared with conventional DG-MOS and
can find application in high-speed switching. The I O N /I O F F
3.2 DC Characteristics ratio of the proposed device is 108 , which is 24× more than
DG-MOS.
In contrast to conventional MOS transistors, the output char- Figure 8(b) depicts the transfer characteristics of DG-JL-
acteristics of an IMOS do not saturate. For a fixed gate IMOS and DG-IMOS for different supply voltages VS =
voltage, when VDS increases, some of the applied voltage −4.5 V and VS = −5 V . The proposed DG-JL-IMOS gen-
falls across the open body region, pushing it farther into the erates nearly ideal switching characteristics at VS = −5 V ,
breakdown. As a result, the ON current of the device fur- whereas DG-IMOS fails at this voltage. At VS = −5 V ,
ther increases with an increasing number of carriers injected the induced carrier concentration in the open body region
into the channel region, despite the fact that all carriers of proposed DG-JL-IMOS is very high. This sweeps the
flow with saturation velocity. Figure 7 shows the breakdown threshold voltage to negative, resulting in high leakage cur-
characteristics (I DS − VS ) of the proposed DG-JL-IMOS and rent even at zero gate bias. Hence, for the proper functioning
conventional DG-IMOS are performed under specific bias- of the device, the optimal source bias should be selected just
ing conditions such as a fixed gate voltage (VG ) of 1 V and above the breakdown voltage. Therefore, the source bias for
a variable source voltage with a grounded drain terminal. the proposed device is optimized to −4.5 V. Similarly, the
We observed conventional DG-IMOS breakdowns at VS = conventional DG-IMOS breakdowns at a source voltage of
−4.75 V , whereas proposed DG-JL-IMOS breakdowns at −4.71 V ; hence its source bias is optimized to −5 V . The ON

Fig. 8 (a) Comparison of

transfer characteristics of
proposed DG-JL-IMOS,
conventional DG-IMOS and
conventional DG-MOS, (b)
Comparison of transfer
characteristics of the proposed
DG-JL-IMOS and conventional
DG-IMOS at VS =−4.5 V and
−5 V where VD fixed at 0 V

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Fig. 9 (a) Comparison of

transfer characteristics of the
proposed DG-JL-IMOS with
and without the presence of
interface traps, (b) Hysteresis in
I DS − VG characteristics of the
proposed DG-JL-IMOS in the
presence of acceptor-type
interface traps (1012 /cm 2 )

current (I O N ) and OFF current (I O F F ) of the DG-JL-IMOS threshold voltage because the traps act as additional sources
are 9.23 × 10−4 A/μm and 9.18 × 10−12 A/μm at VS = of electrons. When the gate voltage is applied, it creates
−4.5 V whereas the corresponding values for conventional an electric field that attracts electrons from a source to a
DG-IMOS are 3.55 × 10−4 A/μm and 1.9 × 10−12 A/μm, channel region, which can cause electrons to be trapped in
respectively, at VS = −5 V . Hence, the proposed DG- the acceptor-type traps. This reduces the number of elec-
JL-IMOS configuration enhances the DC characteristics’ trons available for conduction, resulting in an increase in the
performance at reduced supply voltage compared to conven- threshold voltage. This further decreases the current flow-
tional DG-IMOS. ing through the device and increases the subthreshold swing.
Table 3 compares the electrical performance of the device
3.3 Impact of Interface Traps on the Electrical with and without presence of interface traps. The thresh-
Performance of the DG-JL-IMOS old voltage of the proposed DG-JL-IMOS device increases
by 0.04 V , and the subthreshold swing is increased to 1.22
The effect of interface traps on the performance of the pro- mV /dec under the presence of trap charges. Furthermore,
posed DG-JL-IMOS in terms of I O N , I O F F , Vth , SS, and the ON current (I O N ) is observed to decrease from 0.92 m A
I O N /I O F F ratio are investigated through the incorporation of to 0.87 m A, while the I O N /I O F F remains relatively con-
the Heimen trap model in the device simulations. Generally, stant. It is important to note that the effect of interface-traps
acceptor-type traps usually occur near the conduction band, on the device performance is relatively minimal compared to
while donor-type traps typically occur near the valence band. other devices that incorporate high-K oxides.
The donor-type traps require more energy than acceptor- Figure 9(b) investigates the presence of hysteresis in
type traps for conduction, showing a negligible impact on I DS − VG characteristics of the proposed DG-JL-IMOS
the device’s performance [41,42]. Hence, the acceptor-type device. Hysteresis in I DS − VG characteristics can be caused
traps are only taken into account for the simulations. In this by the presence of interface traps in the device structure.
study, we have assumed uniformly distributed acceptor-type These traps can act as charge storage elements, leading to
trap charges with a density of 1012 /cm 2 and defined them at the accumulation or depletion of charges depending on the
both the interfaces of the gate oxide and the silicon channel applied bias, which can result in different I DS −VG character-
layer [43]. istics for the forward and reverse sweep biasing conditions.
The Fig. 9(a) depicts the transfer characteristics of the The simulations were conducted by sweeping the gate volt-
device with and without the presence of interface traps. age from 0 to 2 V in the forward direction and 2 to 0 V in the
The inclusion of acceptor-type traps increases the device’s reverse direction at a fixed source voltage of −4.5 V with a
grounded drain terminal. The hysteresis width, defined as the
difference between the forward and reverse threshold voltage
Table 3 Comparison of the electrical performance of the proposed DG- at a constant current, was found to be negligible, in the order
JL-IMOS device with and without the presence of interface traps
8 mV . Furthermore, the device performance was found to be
Parameter Without traps With traps stable under reverse biasing conditions, with minimal varia-
tions in the I O N , I O F F , Vth , SS, and I O N /I O F F ratio. These
I O N (A/μm) 9.23 × 10−4 8.68 × 10−4
results of the simulations indicate that the proposed device
I O F F (A/μm) 9.18 × 10−12 7.92 × 10−11
does not exhibit any significant hysteresis in its I DS − VG
I O N /I O F F ≈ 108 ≈ 108
characteristics for the applied biasing conditions. These find-
VT H (V ) 0.5 0.54
ings suggest that the proposed device has promising potential
SS(mV /dec) 0.6 1.22
for future applications.

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Fig. 10 Comparison of intrinsic

capacitances of proposed
DG-JL-IMOS with conventional
DG-IMOS (a) gate to source
capacitance (C gs ) (b) gate to
drain capacitance (C gd ) as a
function of gate voltage (VG )

3.4 Analog Performance Metrics 2.71 f F/μm, respectively, compared with the correspond-
ing capacitance values of conventional DG-IMOS are 1.48
This section describes analog performance metrics such as f F/μm and 2.53 f F/μm, respectively.
transconductance (gm ), unity gain cut-off frequency ( f T ), Figure 11 compares the transconductance (gm ) of the
and current gain of proposed DG-JL-IMOS which are com- proposed DG-JL-IMOS with conventional DG-IMOS. The
pared with conventional DG-IMOS at a frequency of 1M H z. device’s ability to convert gate voltage (VG ) into drain cur-
The analog performance metrics of the device is limited rent (I DS ) is defined by its transconductance given as
by parasitic or intrinsic capacitances such as gate to source
capacitance (C gs ), and the gate to drain capacitance (C gd ). ∂ Ids
The parasitic capacitances associated with the device are the gm = (5)
∂ Vg
first crucial parameters to be studied for analog performance
analysis because both C gs and C gd are accountable for par- gm depends on the slope of the I DS −VG curve. The gm can be
asitic oscillation at high frequencies. used to calculate the device’s switching speed. A higher (gm )
The capacitive behaviour of proposed DG-JL-IMOS and value is desired for better device performance, which leads to
conventional DG-IMOS were evaluated and the comparison faster circuit performance. It is observed that the maximum
was established as shown in Fig. 10(a-b). The gate-to-gate
gm of the proposed DG-JIMOS has 1.47 m S/μm, which
intrinsic capacitance greatly influences the analog perfor-
is 1.7× the maximum gm of DG-IMOS has 0.87 m S/μm.
mance of the device. The gate-to-gate intrinsic capacitance
Another vital performance metric of analog performance
(C gg ) is sum of the C gs and C gd . It is observed that C gs
and C gd of the proposed device are 1.38 f F/μm and analysis is unity gain cut-offfrequency ( f T ), also called as

Fig. 11 Comparison of transconductance (gm ) as a function of gate Fig. 12 Comparison of cut-off frequency ( f T ) vs gate voltage (VG ) of
voltage (VG ) of proposed DG-JL-IMOS with conventional DG-IMOS the proposed DG-JL-IMOS with the conventional DG-IMOS

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At higher VG , f T falls down once C gg becomes dominating

parameter. The proposed DG-JL-IMOS exhibits f T of 60.81
G H z, whereas conventional DG-IMOS offers f T of 37.9
G H z.
Figure 13 compares one more important analog perfor-
mance parameter as current gain versus frequency charac-
teristics of the DG-JL-IMOS and DG-IMOS were obtained
under optimal biasing conditions. The proposed DG-JL-
IMOS has a higher current gain compared to the conventional
DG-IMOS. Maximum cutoff frequency ( f T ) extracted by
extrapolating the current gain of the device above 100 M H z
with −20 d B/decade slope. The transit frequency, f T of
DG-JL-IMOS noted as 61 G H z; similarly f T of the DG-
IMOS was noted as 38 G H z.
Table 4 compares the DC and analog performance metrics
of the proposed DG-JL-IMOS with conventional DG-IMOS,
Fig. 13 Comparison of current gain as a function of the frequency of conventional DG-MOS, and earlier reported single-gate
the proposed DG-JL-IMOS and conventional DG-IMOS junctionless IMOS (JIMOS) devices [31]. The impact of
dual gate on JIMOS improves the gate controllability over
transit frequency of DG-JL-IMOS and DG-IMOS studied the channel, which leads to an improvement in the DC
and compared, as shown in Fig. 12 performance of the proposed device. The conventional DG-
IMOS configuration offers two orders lower I O F F and
gm consequently two orders increase in I O N /I O F F compared
fT = (6)
2π(C gs + C gd ) to single-gate JIMOS. Further, it is perceived that the pro-
posed DG-JL-IMOS achieves breakdown 0.544 V earlier
The cut-off frequency ( f T ) represnts the frequency of the than the conventional DG-IMOS. A comparison between
device at which gain falls to unity. As mentioned in the all the results of the proposed DG-JL-IMOS operating at
equation f T is directly proportional to gm but inversely pro- VS = −4.5 V and conventional DG-IMOS operating at
portional to total gate intrinsic capacitance (C gg ). For lower VS = −5 V is done. The proposed DG-JL-IMOS config-
VG , the effect of gm is more, hence f T increases with gm . uration further improves the DC and analog performance

Table 4 Comparison of different Figure of Merits (FOM) of the proposed DG-JL-IMOS with conventional DG-IMOS, conventional DG-MOS,
and single gate junctionless IMOS devices
Device/FOM JIMOS DG-MOS DG-IMOS DG-JL-IMOS

ON current, I O N (A/μm) 7 × 10−4 2.61 × 10−4 3.55 × 10−4 9.23 × 10−4

OFF current, I O F F (A/μm) 5.65 × 10−10 26.59 × 10−11 1.9 × 10−12 9.18 × 10−12
I O N /I O F F ratio 1.23 × 106 4.2 × 106 1.65 × 108 108
Threshold voltage, Vth (V ) 0.45 0.19 0.51 0.50
Breakdown voltage, V B D (V ) −4.5 − −4.75 −4.21
Supply voltage, (V ) −5 1.5 −5 −4.5
Sub-threshold swing, SS(mV /dec) 1.8 60.9 1 0.6
OFF-state impact gen. rate, G(/cm 3 s) − − 1.1 × 1024 9 × 1024
ON-state impact gen. rate, G(/cm 3 s) − − 1.84 × 1031 9.8 × 1030
Gate-to-source capacitance, C gs ( f F/μm) − 3.51 1.48 1.38
Gate-to-drain capacitance, C gd ( f F/μm) − 3.54 2.53 2.71
C gg ( f F/μm) − 7.05 4.01 4.09
Trans-conductance, gm (m S/μm) − 0.77 0.87 1.47
Transit frequency, f T (G H z) − 46.6 37.94 60.81
Max. current gain, (d B) − 67 71 76
Reference [31] Conventional Conventional Proposed work

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parameters with very steep sub-threshold swing at reduced be a potential candidate for high-speed and high-performance
supply voltage. With nearly zero SS of 0.6 mV /dec, evi- analog applications with ease of fabrication complexities.
dence that the proposed DG-JL-IMOS exhibits almost ideal
Acknowledgements We are grateful for the support provided by “The
switching characteristics and makes it a potential candidate
Department of Electronics and Communication Engineering, Malaviya
for fast switching applications. Compared with conven- National Institute of Technology, Jaipur.”
tional DG-IMOS and conventional DG-MOS, the proposed
DG-JL-IMOS shows improved analog performance metrics Author Contributions Dasari Srikanya (first author) proposed and per-
formed this work. Regarding simulations and data accomplishment,
exhibiting gm , f T and current gain values of 1.47 m S/μm, Nawaz Shafi supported the needed assistance. Dr. Chitrakant Sahu
61 G H z, and 76 d B, respectively. Hence this analysis shows supervised this research and significantly improved the final paper
that the proposed DG-JL-IMOS exhibits enhanced DC and through discussions and suggestions.
analog performance metrics with respect to the conventional
Data Availability For this submission, there are no related research data
DG-IMOS and DG-MOS. sets.

Declarations
4 Conclusions
Competing Interests It is declared that none of the authors have any
In summary, we demonstrated DG-JL-IMOS without metal-
competing financial interests or relationships that might have influenced
lurgical junctions yielding steep subthreshold slope embark- their work.
ing superior switching characteristics. This work provides a
strong understanding of the breakdown behavior of the pro- Conflicts of interest Authors declare that they do not have any conflicts
of interest.
posed DG-JL-IMOS through extensive simulations, devel-
oping insights into its functioning by studying its carrier
concentration and electric field contour profile along with
the impact generation rate. Additionally, the effect of inter- References
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