‫ن ا ْلعِْلِم إِاَّل قَلِ ًيل‬ِ ‫وما أُوتِيتم‬

‫م‬
26 March 2018 1439 ‫ رجب‬9

َ ُْ ََ

IC Layout

Lecture 01
CMOS Fabrication

Dr. Hesham A. Omran

Integrated Circuits Lab (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Ain Shams University
This lecture is mainly based on “CMOS VLSI Design”, 4th edition, by N. Weste and D. Harris and
its accompanying lecture notes
 MOSFET
 MOSFET: Metal Oxide Semiconductor Field Effect Transistor
 Since 1970s: The gate has been formed from polycrystalline silicon
(polysilicon)
 Metal gates reemerged in 2007 (45 nm technology) to solve
materials problems in advanced manufacturing processes

Source Gate Drain Source Gate Drain

Polysilicon
SiO2

n+ n+ p+ p+
Body
p bulk Si n bulk Si

01: CMOS Fabrication 2

 CMOS Fabrication
 CMOS: NMOS and PMOS transistors are fabricated on the same
silicon wafer
 On each step, different materials are deposited or etched
 Lithography process similar to printing press
 Easiest to understand by viewing both top and cross-section of
wafer in a simplified manufacturing process

01: CMOS Fabrication 3

 Photolithography
 Photolithography: Carving features using light
 For deep sub-micron (DSM) technologies it is much more complex
than the schematic below
– Many resolution enhancement techniques (RETs) are required
(see Section 3.2.2)

01: CMOS Fabrication 4

 Inverter Cross-section
 Typically use p-type substrate for NMOS transistors
 Requires n-well for body of PMOS transistors

A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

01: CMOS Fabrication 5

 Well and Substrate Taps
 Substrate must be tied to GND and n-well to VDD
 Metal to lightly-doped semiconductor forms a Schottky Diode
– Use heavily doped well and substrate contacts / taps to create a
low resistance ohmic contact

A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

well
substrate tap
tap

01: CMOS Fabrication 6

 Inverter Layout
 Transistors and wires are defined by masks
 Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

01: CMOS Fabrication 7

 Layout vs Cross-Section

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

well
01: CMOS Fabricationsubstrate tap tap 8
 Inverter Mask Set
 Six masks n well
1. N-well
2. Polysilicon
Polysilicon
3. n+ diffusion
4. p+ diffusion n+ Diffusion

5. Contact p+ Diffusion

6. Metal Contact

 The transistor is formed

by the intersection of
polysilicon and diffusion Metal

GND VDD
01: CMOS Fabrication substrate tap
nMOS transistor pMOS transistor
well tap
9
 Fabrication
 Chips are built in huge factories called fabs (fabrication plants)
 Fabs contain “clean rooms” as large as football fields
 A fab processing 300 mm wafers in a 45 nm process costs about $3
billion (that’s why many semiconductor companies are fabless)
 Big players: Intel, Global Foundries, TSMC, UMC, IBM, …

01: CMOS Fabrication 10

 Fabrication Steps
 Two phases:
– FEOL (front-end-of-line): Fabricating transistors
– BEOL (back-end-of-line): Metallization (> 10 layers in modern
technologies)
 Start with blank wafer
 Build inverter from the bottom up

p substrate

01: CMOS Fabrication 11

 Silicon Wafer
 Silicon is the second most common
element in the earth’s crust
 Sand is mostly silica (silicon dioxide, or
SiO2)
 Wafer is a disk of silicon, roughly
75mm to 300mm in diameter and less
than 1mm thick
 Wafers are cut from cylindrical ingots
of high-purity single-crystal silicon

01: CMOS Fabrication 12

 N-Well (Oxidation)
 Oxidation
– Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O (wet oxidation) or O2 (dry oxidation) in
oxidation furnace

SiO2

p substrate

01: CMOS Fabrication 13

 N-Well cont. (Apply Photoresist)
 Spin on photoresist
– Photoresist (PR) is a light-sensitive organic polymer
– Positive PR: Exposed is soluble
– Negative PR: Exposed is insoluble

Photoresist
SiO2

p substrate

01: CMOS Fabrication 14

 N-Well cont. (Photolithography)
 Photolithography
– Expose photoresist through n-well mask
– Strip off exposed photoresist

Photoresist
SiO2

p substrate

01: CMOS Fabrication 15

 N-Well cont. (Oxide Etch)
 Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone;
nasty stuff!!!
– Needs special personal protective
equipment (PPE)
 Only attacks oxide where resist has been
exposed

Photoresist
SiO2

p substrate

01: CMOS Fabrication 16

 N-Well cont. (Strip Photoresist)
 Strip off remaining photoresist
– Use mixture of acids called piranha etch
 Necessary so resist doesn’t melt in next step

SiO2

p substrate

01: CMOS Fabrication 17

 N-Well cont. (Well Formation)
 Diffusion (for old technologies)
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
 Ion Implantation (for modern technologies)
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
– Better control on dopant concentration and profile
– Less lateral diffusion

SiO2

n well

01: CMOS Fabrication 18

 Diffusion vs Ion Implantation
 Ion implantation is currently the technology of choice
– Better control on dopant concentration and profile
– Less lateral diffusion

http://www.intechopen.com/books/crystalline-silicon-
01: CMOS Fabrication properties-and-uses/high-mass-molecular-ion-implantation 19
 N-Well cont. (Strip Oxide)
 Strip off the remaining oxide using HF
 Back to bare wafer with n-well
 Subsequent steps involve similar series of steps

n well
p substrate

01: CMOS Fabrication 20

 Polysilicon
 Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers) for modern technologies
 Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor
 Metal gates reemerged in 2007 (45 nm technology) to solve
materials problems in advanced manufacturing processes

Polysilicon
Thin gate oxide

n well
p substrate

01: CMOS Fabrication 21

 Polysilicon cont. (Patterning)
 Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

01: CMOS Fabrication 22

 N-diffusion (Oxidation)
 Use oxide and masking to expose where n+ dopants should be
diffused or implanted
 N-diffusion forms NMOS source, drain, and n-well contact

n well
p substrate

01: CMOS Fabrication 23

 N-diffusion cont. (Oxide Patterning)
 Pattern oxide and form n+ regions
 Self-aligned process where gate blocks diffusion

n+ Diffusion

n well
p substrate

01: CMOS Fabrication 24

 N-diffusion cont. (Doping)
 Self-aligned process
– The polysilicon gate blocks the diffusion
– Source and drain are automatically formed adjacent to the gate
– No need to precisely align the masks
 Historically dopants were diffused
 Usually ion implantation today
 But regions are still called diffusion

n+ n+ n+

n well
p substrate

01: CMOS Fabrication 25

 N-diffusion cont. (Strip Oxide)
 Strip off oxide to complete patterning step

n+ n+ n+

n well
p substrate

01: CMOS Fabrication 26

 P-Diffusion
 Similar set of steps form p+ diffusion regions for PMOS source and
drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate

01: CMOS Fabrication 27

 Contacts
 Now we need to wire together the devices
 Cover chip with thick field oxide
– Provides isolation and prevents parasitic MOS channels
– Now trench isolation is used (more about this later)
 Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate

01: CMOS Fabrication 28

 Metalization
 Sputter on aluminum over whole wafer
 Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

01: CMOS Fabrication 29

 Metallization cont.
 Old processes used Aluminum (Al)
 New technologies use Copper (Cu) for its lower resistivity
 Top metal layers are usually thicker for global interconnects

01: CMOS Fabrication 30

 More on CMOS Technology
 Twin- and triple-well technologies
 Shallow trench isolation (STI)
 Lightly doped drain (LDD)
 High-k and low-k dielectrics
 Transistor flavors
 Parasitic PNP transistors
 Strained Silicon
 FinFET
 Silicon on insulator (SOI)
 Micro-electro-mechanical systems (MEMS)
 3D ICs and through-silicon vias (TSVs)
 TFTs and Plastic transistors

01: CMOS Fabrication 31

 Twin and Triple Well Technologies
 The previous flow described an n-well process
– The bulk node is common for all NMOS transistors
 Modern processes use twin well and triple well technologies
– Twin well process helps reduce noise injected from the
substrate
– Triple well process provides more isolation between analog and
digital blocks

01: CMOS Fabrication 32

 Well Formation
 Well-Edge Proximity Effect
– Ions scatter near the well edge increasing doping level
– Transistors near the edge may have different threshold voltage

01: CMOS Fabrication 33

 Shallow Trench Isolation (STI)
 Old processes used LOCOS (local oxidation of silicon)
 Starting from 0.35µm, shallow trench isolation (STI) is used
 Chemical Mechanical Polishing (CMP) planarizes the structure

01: CMOS Fabrication 34

 Lightly Doped Drain (LDD)
 LDD is used at the junction  reduces electric fields
– Reduces hot carrier damage and short channel effects
 Deeper heavily doped S/D implants are used  lower resistance
 Refractory metal is used to form a silicide layer  lower resistance

01: CMOS Fabrication 35

 High-k and Low-k Dielectrics
 Old technologies used SiO2 (k = 3.9) as gate oxide and inter-layer
dielectric
 For modern technologies
– high-k dielectric for gate oxide (k > 20)
• Thicker dielectric layer can be used
– Mitigates leakage
• But it has higher capacitance
– Smaller equivalent oxide thickness (EOT = T * kSiO2 / khigh)
– More gate control on channel (less short channel effects)
– Low-k dielectric for interlayer isolation (k < 3)
• Decreases the parasitic capacitances
• Reduces delay, noise, and power consumption

01: CMOS Fabrication 36

 Transistor Flavors
 Modern technologies offer multiple flavors of transistors
– Low-threshold (VT) devices:
• Higher current, faster, but more leakage
• Use in critical paths
– High-threshold (VT) devices:
• Lower leakage
– Thick oxide devices
• Higher breakdown voltages
• Use in I/O circuits

01: CMOS Fabrication 37

 Parasitic PNP Transistors
 A PNP BJT can be fabricated in a standard n-well CMOS process
 Called “parasitic” or “vertical” PNP
 This parasitic PNP may cause latchup (more about this later)
 Needed for the design of bandgap reference circuits (essential
block in any analog/mixed-signal chip)

01: CMOS Fabrication 38

 Strained Silicon
 Mechanical strain in the channel improves mobility
– Higher current and speed
 Strained Si in Intel 65nm
– NMOS: tensile stress by SiN capping the gate  40% boost
– PMOS: compressive stress by SiGe layer  100% boost

01: CMOS Fabrication 39

 FinFET
 Planar CMOS cannot be scaled below 20nm due
to excess leakage current and severe short
channel effects
 FinFET: gate has better control the channel
– Intel’s version is called trigate FET
– Generally: multigate transistor
 In the future: Gate-all-around

01: CMOS Fabrication 40

 Silicon on Insulator (SOI)
 Transistors fabricated on insulator
instead of semiconductor substrate
 Two main insulators are used: sapphire
and SiO2
 Parasitic capacitances between S/D
and body are eliminated
– Allows higher speed
 Lower leakage currents
 But higher fabrication costs
 Available, but not mainstream

01: CMOS Fabrication 41

 Micro-Electro-Mechanical Systems (MEMS)
 Use IC technology to build tiny mechanical systems monolithically
 Can be integrated with electronics in special CMOS-MEMS
technologies
 Example: MEMS accelerometer, now in every smart phone and air
bag system

www.memsjournal.com/2010/05/baolab-emerges-as-a-cmos-mems-player.html
01: CMOS Fabrication memsblog.wordpress.com/2011/01/05/chipworks-2/ 42
 3D ICs and Through-Silicon Vias (TSVs)
 Stacking multiple wafers vertically on top of each other
– More packing density, more speed, less power
– Combining heterogeneous technologies, e.g., memory and RF
 Top wafers are ground down (thinning) to decrease their thickness
 Through-silicon vias (TSVs) are used to connect wafers vertically

01: CMOS Fabrication http://semimd.com/insights-from-leading-edge/2014/01/ 43

 TFTs and Plastic Transistors
 Thin-film transistors (TFT): The
active layer is a thin film of a
semiconductor material
 Transistor is built upside down
 Poor density (L > 5µm)
 Poor performance (low mobility)
 But has key advantages
– Flexible
– Transparent
– Inexpensive
 Applications: active matrix displays,
flexible electronics, RF ID tags

01: CMOS Fabrication http://www.eetimes.com/document.asp?doc_id=1258532 44

 Thank you!

01: CMOS Fabrication 45

 Extra Material

01: CMOS Fabrication 46

 Silicon Lattice
 Transistors are built on a silicon substrate
 Silicon is a Group IV material
 Forms crystal lattice with bonds to four neighbors

Si Si Si

Si Si Si

Si Si Si

01: CMOS Fabrication 47

 Dopants
 Silicon is a semiconductor
 Pure silicon has no free carriers and conducts poorly
 Adding dopants increases the conductivity
 Group V: extra electron (n-type)
 Group III: missing electron, called hole (p-type)

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si

01: CMOS Fabrication 48

 p-n Junctions
 A junction between p-type and n-type semiconductor forms a
diode
 Current flows only in one direction

p-type n-type

anode cathode

01: CMOS Fabrication 49

 Diffusion vs Ion Implantation
 Ion implantation is currently the technology of choice
– Better control on dopant concentration and profile
– Less lateral diffusion

01: CMOS Fabrication [N. Cheung, Berkeley] 50

 Isolation
 Old processes used LOCOS (local oxidation of silicon)
– Bird’s peak limits transistor packing density

01: CMOS Fabrication http://www.iue.tuwien.ac.at/phd/filipovic 51

 Copper Dual Damascene Process
 Cu metallization is formed using a process called “dual damascene”

01: CMOS Fabrication 52

 Examples of CMOS Technologies

01: CMOS Fabrication 53