Sequential Circuit

In sequential circuits, the present output depends on the present input as well as past
output/outputs.

Block Diagram –

1. Elementary building blocks: Flip-flops

2. In this output depends upon present as well as past input.
3. Speed is slow.
4. Design is not easy as compared to combinational circuits.
5. There exists a feedback path between input and output.
6. This is time dependent.
7. Mainly used for storing data.
8. Sequential circuits have capability to store any state or to retain earlier state.
9. As sequential circuits are clock dependent they need triggering.
10. These circuits have memory element.

Examples – Flip-flops, Counters

 Flip-Flops

Flip flops are actually an application of logic gates. A flip flop is an electronic circuit with two
stable states that can be used to store binary data. The stored data can be changed by applying
varying inputs. Flip flops can also be considered as the most basic idea of a Random Access
Memory [RAM]. When a certain input value is given to them, they will be remembered and
executed, if the logic gates are designed correctly. A higher application of flip flops is helpful in
designing better electronic circuits.
The most commonly used application of flip flops is in the implementation of a feedback circuit.
As a memory relies on the feedback concept, flip flops can be used to design it.

There are mainly four types of flip flops that are used in electronic circuits. They are
1. Set-Reset Flip Flop [SR Flip Flop]
2. Delay Flip Flop [D Flip Flop]
3. J-K Flip Flop
4. T Flip Flop

 S-R Flip Flop

The SET-RESET flip flop is designed with the help of two NOR gates and also two NAND
gates. These flip flops are also called S-R Latch.

 S-R Latch using NAND Gate

The circuit of the S-R flip flop using NAND Gate and its truth table is shown below.

S-R flip flop with NAND gate has four states. They are

 S=1, R=0—Q=0, Q’=1 This state is also called the SET state.

 S=0, R=1—Q=1, Q’=0 This state is known as the RESET state.

In both the states you can see that the outputs are just compliments of each other and that the
value of Q follows the compliment value of S.

 S=0, R=0—Q=1, & Q’ =1 [Invalid]

If both the values of S and R are switched to 0 it is an invalid state because the values of both
Q and Q’ are 1. They are supposed to be compliments of each other. Normally, this state must be
avoided.

 S=1, R=1—Q & Q’= Remember/Memory

If both the values of S and R are switched to 1, then the circuit remembers the value of S and
R in their previous state.
 Clocked S-R Flip Flop

It is also called a Gated S-R flip flop. The problems with S-R flip flops using NOR and NAND
gates is the invalid state. This problem can be overcome by using a bi-stable SR flip-flop that can
change outputs when certain invalid states are met, regardless of the condition of either the Set or
the Reset inputs. For this, a clocked S-R flip flop is designed by adding two NAND gates to a
basic NAND Gate flip flop. The circuit diagram and truth table is shown below.

In this circuit, the output is changed (i.e. the stored data is changed) only when you give an
active clock signal. Otherwise, even if the S or R is active the data will not change.

Timing diagram:
 D Flip Flop

D flip flop is actually a slight modification of the clocked SR flip-flop. From the figure you can
see that the D input is connected to the S input and the complement of the D input is connected
to the R input. The D input is passed on to the flip flop when the value of CP is ‘1’.

The circuit diagram and truth table is given below.

In a D flip flop, the output can be only changed at the clock edge, and if the input changes at
other times, the output will be unaffected.

The change of state of the output is dependent on the rising edge of the clock. The output (Q) is
same as the input and can only change at the rising edge of the clock.

Timing Diagram:
 J-K Flip-flop

A J-K flip flop can also be defined as a modification of the S-R flip flop. The only difference is
that the intermediate state is more refined and precise than that of a S-R flip flop.

The behavior of inputs J and K is same as the S and R inputs of the S-R flip flop. The letter J
stands for SET and the letter K stands for RESET.

When both the inputs J and K have a HIGH state, the flip-flop switch to the complement state.
So, for a value of Q = 1, it switches to Q=0 and for a value of Q = 0, it switches to Q=1.

The input condition of J=K=1, gives an output inverting the output state. However, the outputs
are same when one tests the circuit practically.

Timing diagram:
 T Flip Flop

A T flip flops is like JK flip-flop. These are basically single input version of JK flip flops. This
modified form of JK flip-flop is obtained by connecting both inputs J and K together. This flip-
flop has only one input along with the clock input.

These flip-flops are called T flip-flops because of their ability to complement its state (i.e.)
Toggle, hence the name Toggle flip-flop.

Truth Table

Timing diagram:
 Counters

Counter is a device which stores (and sometimes displays) the number of times a particular
event or process has occurred, often in relationship to a clock signal. Counters are used in digital
electronics for counting purpose, they can count specific event happening in the circuit. For
example, in UP counter a counter increases count for every rising edge of clock. Not only
counting, a counter can follow the certain sequence based on design. They are designed with the
help of flip flops.

Counter Classification: Counters are broadly divided into two categories

1. Asynchronous counter
2. Synchronous counter

1. Asynchronous Counter

In asynchronous counter universal clock is not used, only first flip flop is driven by main clock
and the clock input of rest of the counters is driven by output of previous flip flops. This can be
understood by following diagram-
It is evident from timing diagram that Q0 is changing as soon as the falling edge of clock pulse is
encountered, Q1 is changing when falling edge of Q0 is encountered (because Q0 is clock pulse
for second flip flop), Q2 is changing when falling edge of Q1 is encountered (because Q1 is
clock pulse for third flip flop) Q3 is changing when falling edge of Q2 is encountered (because
Q2 is clock pulse for fourth flip flop). In this way ripples are generated through Q0, Q1, Q2, Q3
hence it is also called RIPPLE counter.

2. Synchronous Counter

Synchronous counter has one global clock which drives each flip flop so output changes in
parallel. The one advantage of synchronous counter over asynchronous counter is, it can operate
on higher frequency than asynchronous counter as it does not have cumulative delay because of
same clock is given to each flip flop.
 From circuit diagram we see that
1. Q0 bit gives response to each falling edge of clock
2. Q1 is dependent on Q0,
3. Q2 is dependent on Q1 and Q0,
4. Q3 is dependent on Q2, Q1 and Q0.

 Shift Registers

Shift Registers are sequential logic circuits, capable of storage and transfer of data. They are
made up of Flip Flops which are connected in such a way that the output of one flip flop could
serve as the input of the other flip-flop, depending on the type of shift registers being created.

 Types of Shift Registers:

Shift registers are categorized into types majorly by their mode of operation, either serial or
parallel. There are four (4) basic types of shift registers:
1. Serial in – Serial out Shift Register (SISO)
2. Serial in – Parallel out shift Register (SIPO)
3. Parallel in – Parallel out Shift Register (PIPO)
4. Parallel in – Serial out Shift Register (PISO)

1. Serial in - Serial out Shift Registers

Serial in – Serial out shift registers are shift registers that streams in data serially (one bit per
clock cycle) and streams out data too in the same way, one after the other.

1. At the first clock pulse, the data at “data in” will be present at the Stage A output.
2. After the second pulse stage A data is transferred to stage B output, and data at “data in” is
transferred to stage A output.
3. After the third clock pulse, stage C is replaced by stage B output; stage B is replaced by stage
A output; and stage A is replaced by data present at “data in”.
4. After the fourth clock, the data which was first present at “data in” is at stage D output.
5. The “first in” data is “first out” as it is shifted from “data in” to “data out”.
 2. Serial in – Parallel out Shift Register

These types of shift registers are used for the conversion of data from serial to parallel. The data
comes in one after the other per clock cycle and can either be shifted or replaced or be read off
at each output. This means when the data is read in, each read in bit becomes available
simultaneously on their respective output line (QA to QD for the 4-bit shift register shown below).

3. Parallel in – Serial out Shift Register

For this type of shift register, the data is supplied in parallel, for example consider the 4-bit shift
register shown below.

This register can be used to store and shift a 4-bit word, with the write/shift (WS) control input
controlling the mode of operation of the shift register. When the WS control line is low (Write
Mode), data can be written and clocked in via D A to DD. To shift the data out serially, the WS
control line is brought HIGH (Shift mode), the register then shifts the data out on clock input.

4. Parallel in – Parallel out shift register

For parallel in – parallel out shift register, the output data across the parallel outputs appear
simultaneously as the input data is fed in.
The input data at each of the input pins from DA to DD are read in at the same time when the
device is clocked and at the same time, the data read in from each of the inputs is passed out at
the corresponding output (from Q A to QD).