24AA64/24LC64/24FC64: 64K I C Serial EEPROM

24AA64/24LC64/24FC64
64K I2C™ Serial EEPROM

Device Selection Table Description:
Part VCC Max. Clock Temp. The Microchip Technology Inc. 24AA64/24LC64/
Number Range Frequency Ranges 24FC64 (24XX64*) is a 64 Kbit Electrically Erasable
PROM. The device is organized as a single block of 8K
24AA64 1.7-5.5 400 kHz(1) I
x 8-bit memory with a 2-wire serial interface. Low-volt-
24LC64 2.5-5.5 400 kHz I, E age design permits operation down to 1.7V, with
24FC64 1.7-5.5 1 MHz(2) I standby and active currents of only 1 μA and 1 mA,
Note 1: 100 kHz for VCC<2.5V respectively. It has been developed for advanced, low-
power applications such as personal communications
2: 400 kHz for VCC <2.5V
or data acquisition. The 24XX64 also has a page write
capability for up to 32 bytes of data. Functional address
Features: lines allow up to eight devices on the same bus, for up
• Single-supply with operation down to 1.7V for to 512 Kbits address space. The 24XX64 is available in
24AA64/24FC64 devices, 2.5V for 24LC64 the standard 8-pin PDIP, surface mount SOIC, TSSOP,
devices DFN and MSOP packages.
• Low-power CMOS technology: Package Types
- Active current 1 mA, typical PDIP, MSOP SOIC, TSSOP
- Standby current 1 μA, typical
A0 1 8 VCC
• 2-wire serial interface, I2C™ compatible A0 1 8 VCC
• Schmitt Trigger inputs for noise suppression A1 2 7 WP A1 2 7 WP

• Output slope control to eliminate ground bounce A2 3 6 SCL A2 3 6 SCL
• 100 kHz and 400 kHz clock compatibility VSS 4 5 SDA VSS 4 5 SDA
• 1 MHz clock for FC versions
• Page write time 5 ms, typical DFN
• Self-timed erase/write cycle
A0 1 8 VCC
• 32-byte page write buffer 7 WP
A1 2
• Hardware write-protect A2 3 6 SCL
• ESD protection > 4,000V VSS 4 5 SDA
• More than 1 million erase/write cycles
• Data retention > 200 years
• Factory programming available Block Diagram
• Packages include 8-lead PDIP, SOIC, TSSOP, HV
MSOP and DFN WP Generator
• Pb-free and RoHS compliant
• Temperature ranges:
- Industrial (I): -40°C to +85°C I/O Memory EEPROM
Control Control XDEC Array
- Automotive (E): -40°C to +125°C Logic Logic
Page
Latches
I/O
SCL
YDEC
SDA
VCC
* 24XX64 is used in this document as a generic part VSS Sense Amp.
number for the 24AA64/24LC64/24FC64 devices. R/W Control
© 2007 Microchip Technology Inc. DS21189L-page 1

24AA64/24LC64/24FC64
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1: DC CHARACTERISTICS

Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V
DC CHARACTERISTICS
Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V
Param.
Sym. Characteristic Min. Typ. Max. Units Conditions
No.
— A0, A1, A2, WP, SCL — — — — —
and SDA pins
D1 VIH High-level input voltage 0.7 VCC — — V —
D2 VIL Low-level input voltage — — 0.3 VCC V VCC ≥ 2.5V
0.2 VCC V VCC < 2.5V
D3 VHYS Hysteresis of Schmitt 0.05 VCC — — V VCC ≥ 2.5V (Note 1)
Trigger inputs (SDA,
SCL pins)
D4 VOL Low-level output voltage — — 0.40 V IOL = 3.0 mA @ VCC = 4.5V
IOL = 2.1 mA @ VCC = 2.5V
D5 ILI Input leakage current — — ±1 μA VIN = VSS or VCC, WP = VSS
VIN = VSS or VCC, WP = VCC
D6 ILO Output leakage current — — ±1 μA VOUT = VSS or VCC
D7 CIN, Pin capacitance — — 10 pF VCC = 5.0V (Note 1)
COUT (all inputs/outputs) TA = 25°C, FCLK = 1 MHz
D8 ICC write Operating current — 0.1 3 mA VCC = 5.5V, SCL = 400 kHz
D9 ICC read — 0.05 400 μA
D10 ICCS Standby current — .01 1 μA Industrial
— — 5 μA Automotive
SDA = SCL = VCC
A0, A1, A2, WP = VSS
Note 1: This parameter is periodically sampled and not 100% tested.
2: Typical measurements taken at room temperature.
DS21189L-page 2 © 2007 Microchip Technology Inc.

24AA64/24LC64/24FC64
TABLE 1-2: AC CHARACTERISTICS
Electrical Characteristics:
AC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C
Param.
Sym. Characteristic Min. Max. Units Conditions
No.
1 FCLK Clock frequency — 100 kHz 1.7V ≤ VCC < 2.5V
— 400 2.5V ≤ VCC ≤ 5.5V
— 400 1.7V ≤ VCC < 2.5V 24FC64
— 1000 2.5V ≤ VCC ≤ 5.5V 24FC64
2 THIGH Clock high time 4000 — ns 1.7V ≤ VCC < 2.5V
600 — 2.5V ≤ VCC ≤ 5.5V
600 — 1.7V ≤ VCC < 2.5V 24FC64
500 — 2.5V ≤ VCC ≤ 5.5V 24FC64
3 TLOW Clock low time 4700 — ns 1.7V ≤ VCC < 2.5V
1300 — 2.5V ≤ VCC ≤ 5.5V
1300 — 1.7V ≤ VCC < 2.5V 24FC64
500 — 2.5V ≤ VCC ≤ 5.5V 24FC64
4 TR SDA and SCL rise time — 1000 ns 1.7V ≤ VCC < 2.5V
(Note 1) — 300 2.5V ≤ VCC ≤ 5.5V
— 300 1.7V ≤ VCC ≤ 5.5V 24FC64
5 TF SDA and SCL fall time — 300 ns All except, 24FC64
(Note 1) — 100 1.7V ≤ VCC ≤ 5.5V 24FC64
6 THD:STA Start condition hold time 4000 — ns 1.7V ≤ VCC < 2.5V
600 — 2.5V ≤ VCC ≤ 5.5V
600 — 1.7V ≤ VCC < 2.5V 24FC64
250 — 2.5V ≤ VCC ≤ 5.5V 24FC64
7 TSU:STA Start condition setup time 4700 — ns 1.7V ≤ VCC < 2.5V
600 — 2.5V ≤ VCC ≤ 5.5V
600 — 1.7V ≤ VCC < 2.5V 24FC64
250 — 2.5V ≤ VCC ≤ 5.5V 24FC64
8 THD:DAT Data input hold time 0 — ns (Note 2)
9 TSU:DAT Data input setup time 250 — ns 1.7V ≤ VCC < 2.5V
100 — 2.5V ≤ VCC ≤ 5.5V
100 — 1.7V ≤ VCC ≤ 5.5V 24FC64
10 TSU:STO Stop condition setup time 4000 — ns 1.7 V ≤ VCC < 2.5V
600 — 2.5 V ≤ VCC ≤ 5.5V
600 — 1.7V ≤ VCC < 2.5V 24FC64
250 — 2.5 V ≤ VCC ≤ 5.5V 24FC64
11 TSU:WP WP setup time 4000 — ns 1.7V ≤ VCC < 2.5V
600 — 2.5V ≤ VCC ≤ 5.5V
600 — 1.7V ≤ VCC ≤ 5.5V 24FC64
12 THD:WP WP hold time 4700 — ns 1.7V ≤ VCC < 2.5V
1300 — 2.5V ≤ VCC ≤ 5.5V
1300 — 1.7V ≤ VCC ≤ 5.5V 24FC64
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.

24AA64/24LC64/24FC64
Electrical Characteristics:
AC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C
Param.
Sym. Characteristic Min. Max. Units Conditions
No.
13 TAA Output valid from clock — 3500 ns 1.7V ≤ VCC < 2.5V
(Note 2) — 900 2.5V ≤ VCC ≤ 5.5V
— 900 1.7V ≤ VCC < 2.5V 24FC64
— 400 2.5V ≤ VCC ≤ 5.5V 24FC64
14 TBUF Bus free time: Time the bus 4700 — ns 1.7V ≤ VCC < 2.5V
must be free before a new 1300 — 2.5V ≤ VCC ≤ 5.5V
transmission can start 1300 — 1.7V ≤ VCC < 2.5V 24FC64
500 — 2.5V ≤ VCC ≤ 5.5V 24FC64
15 TOF Output fall time from VIH 10 + 0.1CB 250 ns All except, 24FC64 (Note 1)
minimum to VIL maximum 250 24FC64 (Note 1)
CB ≤ 100 pF
16 TSP Input filter spike suppression — 50 ns All except, 24FC64 (Notes 1
(SDA and SCL pins) and 3)
17 TWC Write cycle time (byte or — 5 ms —
page)
18 — Endurance 1,000,000 — cycles 25°C (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.
FIGURE 1-1: BUS TIMING DATA
5 4
2 D4
SCL 7
3 8 9 10
SDA 6
IN
16
13 14
SDA
OUT
(protected)
WP 11 12
(unprotected)

24AA64/24LC64/24FC64
2.0 FUNCTIONAL DESCRIPTION 3.4 Data Valid (D)
The 24XX64 supports a bidirectional, 2-wire bus and The state of the data line represents valid data when,
data transmission protocol. A device that sends data after a Start condition, the data line is stable for the
onto the bus is defined as transmitter, while a device duration of the high period of the clock signal.
receiving data is defined as a receiver. The bus has to The data on the line must be changed during the low
be controlled by a master device which generates the period of the clock signal. There is one clock pulse per
Serial Clock (SCL), controls the bus access and bit of data.
generates the Start and Stop conditions, while the
24XX64 works as slave. Both master and slave can Each data transfer is initiated with a Start condition and
operate as transmitter or receiver, but the master terminated with a Stop condition. The number of data
device determines which mode is activated. bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically,
unlimited (although only the last thirty two will be stored
3.0 BUS CHARACTERISTICS when doing a write operation). When an overwrite does
occur, it will replace data in a first-in first-out (FIFO)
The following bus protocol has been defined:
fashion.
• Data transfer may be initiated only when the bus
is not busy 3.5 Acknowledge
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in Each receiving device, when addressed, is obliged to
the data line while the clock line is high will be generate an acknowledge after the reception of each
interpreted as a Start or Stop condition byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Accordingly, the following bus conditions have been
defined (Figure 3-1). Note: The 24XX64 does not generate any
Acknowledge bits if an internal
3.1 Bus Not Busy (A) programming cycle is in progress.
The device that acknowledges has to pull down the
Both data and clock lines remain high.
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
3.2 Start Data Transfer (B) period of the acknowledge related clock pulse. Of
A high-to-low transition of the SDA line while the clock course, setup and hold times must be taken into
(SCL) is high determines a Start condition. All account. During reads, a master must signal an end of
commands must be preceded by a Start condition. data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX64) will leave the data line
3.3 Stop Data Transfer (C)
high to enable the master to generate the Stop
A low-to-high transition of the SDA line while the clock condition.
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A) (B) (D) (D) (C) (A)

SCL
SDA
Start Address or Data Stop

Condition Acknowledge Allowed Condition
Valid to Change

24AA64/24LC64/24FC64
3.6 Device Addressing FIGURE 3-2: CONTROL BYTE FORMAT
A control byte is the first byte received following the Read/Write Bit
Start condition from the master device (Figure 3-2).
The control byte consists of a four-bit control code. For Chip Select
the 24XX64, this is set as ‘1010’ binary for read and Control Code Bits
write operations. The next three bits of the control byte
are the Chip Select bits (A2, A1, A0). The Chip Select S 1 0 1 0 A2 A1 A0 R/W ACK
bits allow the use of up to eight 24XX64 devices on the
same bus and are used to select which device is Slave Address
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2, Start Bit Acknowledge Bit
A1 and A0 pins for the device to respond. These bits
are, in effect, the three Most Significant bits of the word
address.
3.7 Contiguous Addressing Across
The last bit of the control byte defines the operation to Multiple Devices
be performed. When set to a ‘1’, a read operation is
selected. When set to a ‘0’, a write operation is The Chip Select bits A2, A1 and A0 can be used to
selected. The next two bytes received define the expand the contiguous address space for up to 512K
address of the first data byte (Figure 3-3). Because bits by adding up to eight 24XX64 devices on the same
only A12...A0 are used, the upper-three address bits bus. In this case, software can use A0 of the control
are “don’t care” bits. The upper-address bits are byte as address bit A13; A1 as address bit A14; and A2
transferred first, followed by the Less Significant bits. as address bit A15. It is not possible to sequentially
read across device boundaries.
Following the Start condition, the 24XX64 monitors the
SDA bus, checking the device-type identifier being
transmitted. Upon receiving a ‘1010’ code and appro-
priate device-select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24XX64 will select a read or
write operation.
FIGURE 3-3: ADDRESS SEQUENCE BIT ASSIGNMENTS
Control Byte Address High Byte Address Low Byte
A A A A A A A A A A
1 0 1 0 2 1 0 R/W x x x 12 11 10 9 8 7 • • • • • • 0
Control Chip
Code Select x = “don’t care” bit
bits

24AA64/24LC64/24FC64
4.0 WRITE OPERATIONS 4.2 Page Write
The write control byte, word address and the first data
4.1 Byte Write byte are transmitted to the 24XX64 in the same way as
Following the Start condition from the master, the in a byte write. However, instead of generating a Stop
control code (four bits), the Chip Select (three bits) and condition, the master transmits up to 31 additional
the R/W bit (which is a logic low) are clocked onto the bytes which are temporarily stored in the on-chip page
bus by the master transmitter. This indicates to the buffer and will be written into memory once the master
addressed slave receiver that the address high byte will has transmitted a Stop condition. Upon receipt of each
follow once it has generated an Acknowledge bit during word, the five lower Address Pointer bits are internally
the ninth clock cycle. Therefore, the next byte transmit- incremented by one. If the master should transmit more
ted by the master is the high-order byte of the word than 32 bytes prior to generating the Stop condition, the
address and will be written into the Address Pointer of address counter will roll over and the previously
the 24XX64. The next byte is the Least Significant received data will be overwritten. As with the byte write
Address Byte. After receiving another Acknowledge operation, once the Stop condition is received, an inter-
signal from the 24XX64, the master device will transmit nal write cycle will begin (Figure 4-2). If an attempt is
the data word to be written into the addressed memory made to write to the array with the WP pin held high, the
location. The 24XX64 acknowledges again and the device will acknowledge the command, but no write
master generates a Stop condition. This initiates the cycle will occur, no data will be written, and the device
internal write cycle and, during this time, the 24XX64 will immediately accept a new command.
will not generate Acknowledge signals (Figure 4-1). If
Note: Page write operations are limited to writing
an attempt is made to write to the array with the WP pin
bytes within a single physical page,
held high, the device will acknowledge the command,
regardless of the number of bytes
but no write cycle will occur, no data will be written and
actually being written. Physical page
the device will immediately accept a new command.
boundaries start at addresses that are
After a byte Write command, the internal address
integer multiples of the page buffer size (or
counter will point to the address location following the
‘page size’) and end at addresses that are
one that was just written.
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
4.3 Write Protection

The WP pin allows the user to write-protect the entire
array (0000-1FFF) when the pin is tied to VCC. If tied to
VSS the write protection is disabled. The WP pin is
sampled at the Stop bit for every Write command
(Figure 3-1). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.

24AA64/24LC64/24FC64
FIGURE 4-1: BYTE WRITE
S
Bus Activity T S
Master A Control Address Address T
R Byte High Byte Low Byte Data O
T P
SDA Line S1 01 0A AA
2 10 0
xxx P
A A A A
Bus Activity C C C C
K K K K
x = “don’t care” bit
FIGURE 4-2: PAGE WRITE
S
T S
Bus Activity A Control Address Address T
Master R Byte High Byte Low Byte Data Byte 0 Data Byte 31 O
T P
SDA Line S 10 10A AA
2 1 0 0 xxx P
A A A A A
Bus Activity C C C C C
K K K K K
x = “don’t care” bit

24AA64/24LC64/24FC64
5.0 ACKNOWLEDGE POLLING FIGURE 5-1: ACKNOWLEDGE POLLING
FLOW
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device Send
initiates the internally-timed write cycle and ACK polling Write Command
can then be initiated immediately. This involves the
master sending a Start condition followed by the control
byte for a Write command (R/W = 0). If the device is still Send Stop
busy with the write cycle, then no ACK will be returned. Condition to
Initiate Write Cycle
If no ACK is returned, the Start bit and control byte must
be re-sent. If the cycle is complete, the device will
return the ACK and the master can then proceed with
the next Read or Write command. See Figure 5-1 for a Send Start
flow diagram of this operation.
Send Control Byte

with R/W = 0
Did Device No
Acknowledge
(ACK = 0)?
Yes
Next
Operation

24AA64/24LC64/24FC64
6.0 READ OPERATION This terminates the write operation, but not before
the internal Address Pointer is set. The master then
Read operations are initiated in the same way as write issues the control byte again, but with the R/W bit set
operations, with the exception that the R/W bit of the to a one. The 24XX64 will then issue an acknowl-
control byte is set to one. There are three basic types edge and transmit the 8-bit data word. The master
of read operations: current address read, random read will not acknowledge the transfer, but does generate
and sequential read. a Stop condition, which causes the 24XX64 to
discontinue transmission (Figure 6-2). After a
6.1 Current Address Read random Read command, the internal address
counter will point to the address location following
The 24XX64 contains an address counter that main- the one that was just read.
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address ‘n’ (n is any legal address), the
6.3 Sequential Read
next current address read operation would access data Sequential reads are initiated in the same way as
from address n + 1. random reads, except that once the 24XX64 transmits
Upon receipt of the control byte with R/W bit set to one, the first data byte, the master issues an acknowledge as
the 24XX64 issues an acknowledge and transmits the opposed to the Stop condition used in a random read.
eight-bit data word. The master will not acknowledge This acknowledge directs the 24XX64 to transmit the
the transfer, but does generate a Stop condition and the next sequentially-addressed 8-bit word (Figure 6-3).
24XX64 discontinues transmission (Figure 6-1). Following the final byte being transmitted to the master,
the master will NOT generate an acknowledge, but will
6.2 Random Read generate a Stop condition. To provide sequential reads,
the 24XX64 contains an internal Address Pointer which
Random read operations allow the master to access is incremented by one at the completion of each
any memory location in a random manner. To operation. This Address Pointer allows the entire
perform this type of read operation, the word address memory contents to be serially read during one opera-
must first be set. This is accomplished by sending tion. The internal Address Pointer will automatically roll
the word address to the 24XX64 as part of a write over from address 1FFF to address 0000 if the master
operation (R/W bit set to ‘0’). Once the word address acknowledges the byte received from the array address
is sent, the master generates a Start condition 1FFF.
following the acknowledge.
FIGURE 6-1: CURRENT ADDRESS READ
S
Bus Activity T Control S
Master A Byte Data (n) T
R O
T P
SDA Line S P
A N
Bus Activity C O
K
A
C
K

24AA64/24LC64/24FC64
FIGURE 6-2: RANDOM READ
S S
Bus Activity T T S
Master A Control Address Address A Control Data T
R Byte High Byte Low Byte R Byte Byte O
T T P
SDA Line S1 01 0AAA0 xxx S 1 0 1 0 A AA1 P
2 1 0 2 10
A A A A N
Bus Activity C C C C O
K K K K A
x = “don’t care” bit C
K
FIGURE 6-3: SEQUENTIAL READ

S
Bus Activity Control T
Master Byte Data n Data n + 1 Data n + 2 Data n + x O
P
SDA Line P
A A A A N
C C C C O
Bus Activity K K K K A
C
K

24AA64/24LC64/24FC64
7.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 7-1.
TABLE 7-1: PIN FUNCTION TABLE

Name PDIP SOIC TSSOP DFN MSOP Description
A0 1 1 1 1 1 Chip Address Input
VSS 4 4 4 4 4 Ground
SDA 5 5 5 5 5 Serial Address/Data I/O
SCL 6 6 6 6 6 Serial Clock
WP 7 7 7 7 7 Write-Protect Input
VCC 8 8 8 8 8 +1.7V to 5.5V Power Supply
7.1 A0, A1, A2 Chip Address Inputs 7.3 Serial Clock (SCL)
The A0, A1 and A2 inputs are used by the 24XX64 for The SCL input is used to synchronize the data transfer
multiple device operation. The levels on these inputs from and to the device.
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true. 7.4 Write-Protect (WP)
Up to eight devices may be connected to the same bus
This pin must be connected to either VSS or VCC. If tied
by using different Chip Select bit combinations. These
to VSS, write operations are enabled. If tied to VCC,
inputs must be connected to either VCC or VSS.
write operations are inhibited but read operations are
In Most applications, the chip address inputs A0, A1 not affected.
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
7.2 Serial Data (SDA)

SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an open-
drain terminal, the SDA bus requires a pull-up resistor
to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.

24AA64/24LC64/24FC64
8.0 PACKAGING INFORMATION
8.1 Package Marking Information

8-Lead PDIP (300 mil) Example:
XXXXXXXX 24LC64
T/XXXNNN I/P e3 13F
YYWW 0527
8-Lead SOIC (3.90 mm) Example:
XXXXXXXT 24LC64I
XXXXYYWW SN e3 0527
NNN 13F
8-Lead SOIC (5.28 mm) Example:
XXXXXXXX 24LC64
T/XXXXXX I/SM e3
YYWWNNN 052713F
8-Lead TSSOP Example:
XXXX 4LB
TYWW I527
NNN 13F
8-Lead MSOP Example:
XXXXXT 4L64I
YWWNNN 52713F
8-Lead 2x3 DFN Example:
XXX 274
YWW 527
NN I3

24AA64/24LC64/24FC64
1st Line Marking Codes

Part Number TSSOP MSOP DFN
I Temp. E Temp.
24AA64 4AB 4A64T 271 —
24LC64 4LB 4L64T 274 275
24FC64 4FB 4F64T 27A 27B
Note: T = Temperature grade (I, E)
Legend: XX...X Part number or part number code

T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
e3 Pb-free JEDEC designator for Matte Tin (Sn)
Note: For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

24AA64/24LC64/24FC64
8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
NOTE 1
E1
1 2 3
D
E
A A2
A1 L
c
e
b1 eB
b
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A – – .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 – –
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB – – .430
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-018B

24AA64/24LC64/24FC64
8-Lead Plastic Small Outline (SN or OA) – Narrow, 3.90 mm Body [SOIC]
e
N
E1
NOTE 1
1 2 3
h α
b
h
c
A A2 φ
A1 L
L1 β
Units MILLIMETERS
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A – – 1.75
Molded Package Thickness A2 1.25 – –
Standoff § A1 0.10 – 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 4.90 BSC
Chamfer (optional) h 0.25 – 0.50
Foot Length L 0.40 – 1.27
Footprint L1 1.04 REF
Foot Angle φ 0° – 8°
Lead Thickness c 0.17 – 0.25
Lead Width b 0.31 – 0.51
Mold Draft Angle Top α 5° – 15°
Mold Draft Angle Bottom β 5° – 15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
REF: Reference Dimension, usually without tolerance, for information purposes only.

24AA64/24LC64/24FC64
8-Lead Plastic Small Outline (SM) – Medium, 5.28 mm Body [SOIJ]

D
N
E1
1 2
e
b
c
A2 φ
A
β
A1 L
Units MILLIMETERS
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A 1.77 – 2.03
Molded Package Thickness A2 1.75 – 1.98
Standoff § A1 0.05 – 0.25
Overall Width E 7.62 – 8.26
Molded Package Width E1 5.11 – 5.38
Overall Length D 5.13 – 5.33
Foot Length L 0.51 – 0.76
Mold Draft Angle Top α – – 15°
Mold Draft Angle Bottom β – – 15°
Notes:
1. SOIJ, JEITA/EIAJ Standard, formerly called SOIC.

24AA64/24LC64/24FC64
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]
E1
NOTE 1
1 2
b
e
c
A A2 φ
A1 L1 L
Units MILLIMETERS
Number of Pins N 8
Pitch e 0.65 BSC
Molded Package Thickness A2 0.80 1.00 1.05
Standoff A1 0.05 – 0.15
Molded Package Width E1 4.30 4.40 4.50
Molded Package Length D 2.90 3.00 3.10
Foot Length L 0.45 0.60 0.75
Notes:

24AA64/24LC64/24FC64
8-Lead Plastic Micro Small Outline Package (MS or UA) [MSOP]

D
N
E
E1
NOTE 1
1 2
e
c φ
A A2
A1 L1 L
Units MILLIMETERS
Number of Pins N 8
Pitch e 0.65 BSC
Molded Package Thickness A2 0.75 0.85 0.95
Standoff A1 0.00 – 0.15
Molded Package Width E1 3.00 BSC
Foot Length L 0.40 0.60 0.80
Notes:

24AA64/24LC64/24FC64
8-Lead Plastic Dual Flat, No Lead Package (MC) – 2x3x0.9 mm Body [DFN]
D e
b
N N
L
E E2
EXPOSED PAD
NOTE 1
NOTE 1
1 2 2 1
D2
TOP VIEW BOTTOM VIEW
A3 A1 NOTE 2
Units MILLIMETERS
Number of Pins N 8
Pitch e 0.50 BSC
Overall Height A 0.80 0.90 1.00
Standoff A1 0.00 0.02 0.05
Contact Thickness A3 0.20 REF
Exposed Pad Length D2 1.30 – 1.75
Exposed Pad Width E2 1.50 – 1.90
Contact Width b 0.18 0.25 0.30
Contact Length L 0.30 0.40 0.50
Contact-to-Exposed Pad K 0.20 – –
Notes:
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated.

24AA64/24LC64/24FC64
APPENDIX A: REVISION HISTORY
Revision H
Corrections to Section 1.0, Electrical Characteristics.
Revision J
Added DFN package.
Revision K
Revised Sections 7.1 and 7.4.
Revision L
Added 24FC64 Part; Revised Device Selection Table;
Revised Features Section; Deleted Rotated TSSOP
Package; Revised Table 1-2; Revised Table 7-1;
Revised Package Information; Replaced Package
Drawings; Revised Product ID Section.

24AA64/24LC64/24FC64
NOTES:

24AA64/24LC64/24FC64
THE MICROCHIP WEB SITE CUSTOMER SUPPORT
Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following
information: • Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design • Development Systems Information Line
resources, user’s guides and hardware support Customers should contact their distributor,
documents, latest software releases and archived representative or field application engineer (FAE) for
software support. Local sales offices are also available to help
• General Technical Support – Frequently Asked customers. A listing of sales offices and locations is
Questions (FAQ), technical support requests, included in the back of this document.
online discussion groups, Microchip consultant Technical support is available through the web site
program member listing at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.

24AA64/24LC64/24FC64
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To: Technical Publications Manager Total Pages Sent ________

RE: Reader Response
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: 24AA64/24LC64/24FC64 Literature Number: DS21189L
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?

24AA64/24LC64/24FC64
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX
Examples:
Device Temperature Package a) 24AA64-I/P: Industrial Temperature,
Range 1.7V, PDIP package
b) 24AA64-I/SN: Industrial Temperature,
Device: 24AA64: 1.7V, 64 Kbit I2C Serial EEPROM 1.7V, SOIC package
24AA64T: 1.7V, 64 Kbit I2C Serial EEPROM c) 24AA64-I/SM: Industrial Temperature,
(Tape and Reel) 1.7V, SOIC (5.28 mm) package
24LC64: 2.5V, 64 Kbit I2C Serial EEPROM d) 24AA64T-I/ST: Industrial Temperature,
24LC64T: 2.5V, 64 Kbit I2C Serial EEPROM 1.7V, TSSOP package, tape and reel
(Tape and Reel) e) 24LC64-I/P: Industrial Temperature,
2.5V, PDIP package
Temperature I = -40°C to +85°C f) 24LC64-E/SN: Extended Temperature,
Range: E = -40°C to +125°C 2.5V, SOIC package
g) 24LC64-E/SM: Extended Temperature,
2.5V, SOIC (5.28 mm) package
Package: P = Plastic DIP (300 mil body), 8-lead h) 24LC64-I/ST: Industrial Temperature,
SN = Plastic SOIC (3.90 mm body), 8-lead 2.5V, TSSOP package
SM = Plastic SOIC (5.28 mm body), 8-lead
ST = Plastic TSSOP (4.4 mm), 8-lead
MS = Plastic Micro Small Outline (MSOP), 8-lead
MC = 2x3 DFN, 8-lead
© 2007 Microchip Technology Inc. DS21189L-page25

24AA64/24LC64/24FC64
NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
ensure that your application meets with your specifications.
PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and
MICROCHIP MAKES NO REPRESENTATIONS OR
SmartShunt are registered trademarks of Microchip
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
Technology Incorporated in the U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Linear Active Thermistor, Migratable
INCLUDING BUT NOT LIMITED TO ITS CONDITION, Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor
QUALITY, PERFORMANCE, MERCHANTABILITY OR and The Embedded Control Solutions Company are
FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated
arising from this information and its use. Use of Microchip in the U.S.A.
devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, Application Maestro, CodeGuard,
the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
hold harmless Microchip from any and all damages, claims, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
suits, or expenses resulting from such use. No licenses are In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
conveyed, implicitly or otherwise, under any Microchip MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
intellectual property rights. PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.

WORLDWIDE SALES AND SERVICE
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Asia Pacific Office India - Bangalore Austria - Wels
2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-4182-8400 Tel: 43-7242-2244-39
Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-4182-8422 Fax: 43-7242-2244-393
Tel: 480-792-7200 Habour City, Kowloon Denmark - Copenhagen
India - New Delhi
Fax: 480-792-7277 Hong Kong Tel: 45-4450-2828
Tel: 91-11-4160-8631
Technical Support: Tel: 852-2401-1200 Fax: 45-4485-2829
Fax: 91-11-4160-8632
http://support.microchip.com Fax: 852-2401-3431
India - Pune France - Paris
Web Address:
Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20
www.microchip.com
Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79
Atlanta Fax: 61-2-9868-6755
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Tel: 678-957-9614 Tel: 81-45-471- 6166
Tel: 86-10-8528-2100 Fax: 49-89-627-144-44
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Kokomo, IN Tel: 86-24-2334-2829 Tel: 886-3-572-9526
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Fax: 765-864-8387
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Los Angeles Tel: 86-755-8203-2660 Tel: 886-7-536-4818
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Tel: 949-462-9523
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Tel: 408-961-6444
Tel: 86-27-5980-5300 Tel: 66-2-694-1351
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Fax: 86-27-5980-5118 Fax: 66-2-694-1350
Toronto
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Mississauga, Ontario,
Tel: 86-29-8833-7250
Canada
Fax: 86-29-8833-7256
Tel: 905-673-0699
Fax: 905-673-6509
12/08/06

24AA64/24LC64/24FC64: 64K I C Serial EEPROM

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24AA64/24LC64/24FC64

64K I2C™ Serial EEPROM

• Schmitt Trigger inputs for noise suppression A1 2 7 WP A1 2 7 WP

© 2007 Microchip Technology Inc. DS21189L-page 1

TABLE 1-1: DC CHARACTERISTICS

DS21189L-page 2 © 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc. DS21189L-page 3

FIGURE 1-1: BUS TIMING DATA

DS21189L-page 4 © 2007 Microchip Technology Inc.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (D) (D) (C) (A)

Start Address or Data Stop

© 2007 Microchip Technology Inc. DS21189L-page 5

FIGURE 3-3: ADDRESS SEQUENCE BIT ASSIGNMENTS

Control Byte Address High Byte Address Low Byte

DS21189L-page 6 © 2007 Microchip Technology Inc.

4.3 Write Protection

© 2007 Microchip Technology Inc. DS21189L-page 7

FIGURE 4-2: PAGE WRITE

DS21189L-page 8 © 2007 Microchip Technology Inc.

Send Control Byte

© 2007 Microchip Technology Inc. DS21189L-page 9

FIGURE 6-1: CURRENT ADDRESS READ

DS21189L-page 10 © 2007 Microchip Technology Inc.

FIGURE 6-3: SEQUENTIAL READ

© 2007 Microchip Technology Inc. DS21189L-page 11

TABLE 7-1: PIN FUNCTION TABLE

7.2 Serial Data (SDA)

DS21189L-page 12 © 2007 Microchip Technology Inc.

8.1 Package Marking Information

8-Lead SOIC (3.90 mm) Example:

8-Lead SOIC (5.28 mm) Example:

8-Lead TSSOP Example:

8-Lead MSOP Example:

8-Lead 2x3 DFN Example:

© 2007 Microchip Technology Inc. DS21189L-page 13

1st Line Marking Codes

Legend: XX...X Part number or part number code

DS21189L-page 14 © 2007 Microchip Technology Inc.

8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP]

Microchip Technology Drawing C04-018B

© 2007 Microchip Technology Inc. DS21189L-page 15

DS21189L-page 16 © 2007 Microchip Technology Inc.

8-Lead Plastic Small Outline (SM) – Medium, 5.28 mm Body [SOIJ]

© 2007 Microchip Technology Inc. DS21189L-page 17

Microchip Technology Drawing C04-086B

DS21189L-page 18 © 2007 Microchip Technology Inc.

8-Lead Plastic Micro Small Outline Package (MS or UA) [MSOP]

© 2007 Microchip Technology Inc. DS21189L-page 19

DS21189L-page 20 © 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc. DS21189L-page 21

DS21189L-page 22 © 2007 Microchip Technology Inc.

CUSTOMER CHANGE NOTIFICATION

© 2007 Microchip Technology Inc. DS21189L-page 23

To: Technical Publications Manager Total Pages Sent ________

Device: 24AA64/24LC64/24FC64 Literature Number: DS21189L

1. What are the best features of this document?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?