25LC320

32K 2.5V SPI Bus Serial EEPROM

FEATURES PACKAGE TYPES
SPI modes 0,0 and 1,1 DIP/SOIC
3.0 MHz Clock Rate
Single supply with Programming Operation down CS 1 8 VCC
to 2.5V

25LC320
SO 2 7 HOLD
Low Power CMOS Technology
- Max Write Current: 5.0 mA WP 3 6 SCK
- Read Current: 1 mA at 5.5V, 3 Mhz
- Standby Current: 1 A typical VSS 4 5 SI
4096 x 8 Organization
32-Byte Page TSSOP
Sequential Read
CS 1 14 VCC
Self-timed ERASE and WRITE Cycles

25LC320
SO 2 13 HOLD
Block Write Protection NC 3 12 NC
NC 4 11 NC
- Protect none, 1/4, 1/2, or all of Array NC 5 10 NC
Built-in Write Protection WP 6 9 SCK
VSS 7 8 SI
- Power On/Off Data Protection Circuitry
- Write Enable Latch
- Write Protect Pin BLOCK DIAGRAM
High Reliability
- Endurance: 1M cycles (guaranteed) Status
HV Generator
- Data Retention: >200 years Register
- ESD protection: >4000V
8-pin PDIP/SOIC, 14-pin TSSOP
Temperature ranges supported
- Commercial (C): 0C to +70C EEPROM
- Industrial (I): -40C to +85C Memory X
I/O Control
Control Array
Logic
DESCRIPTION Logic Dec

The Microchip Technology Inc. 25LC320 is a 32K-bit

Page Latches
serial Electrically Erasable PROM (EEPROM). The
memory is accessed via a simple Serial Peripheral WP
Interface (SPI) compatible serial bus. The bus signals SI
required are a clock input (SCK) plus separate data in SO Y Decoder
(SI) and data out (SO) lines. Access to the device is
CS
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus. SCK
Sense Amp.
HOLD
There are two other inputs that provide the end user R/W Control
with additional flexibility. Communication to the device Vcc
can be paused via the hold pin (HOLD). While the Vss
device is paused, transitions on its inputs will be
ignored, with exception of chip select, allowing the host
to service higher priority interrupts. Also write opera-
tions to the Status Register can be disabled via the
write protect pin (WP).

SPI is a trademark of Motorola.

1996 Microchip Technology Inc. Preliminary DS21158B-page 1

This document was created with FrameMaker 4 0 4

25LC320
1.0 ELECTRICAL FIGURE 1-1: AC TEST CIRCUIT
CHARACTERISTICS Vcc

1.1 Maximum Ratings*

2.25 K
VCC ........................................................................ 7.0V
All inputs and outputs w.r.t. VSS ....... -0.6V to VCC+1.0V SO
Storage temperature ............................ -65C to 150C
Ambient temperature under bias.......... -65C to 125C 1.8 K 100 pF
Soldering temperature of leads
(10 seconds) .................................................... +300C
ESD protection on all pins..................................... 4 kV
*Notice: Stresses above those listed under Maximum ratings 1.2 AC Test Conditions
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any AC Waveform:
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
VLO = 0.2V
conditions for extended period of time may affect device reliability VHI = Vcc - 0.2V (Note 1)
VHI = 4.0V (Note 2)
TABLE 1-1: PIN FUNCTION TABLE
Timing Measurement Reference Level
Name Function
Input 0.5 VCC
CS Chip Select Input Output 0.5 VCC
SO Serial Data Output Note 1: For VCC 4.0V
SI Serial Data Input 2: For VCC > 4.0V
SCK Serial Clock Input
WP Write Protect Pin
VSS Ground
VCC Supply Voltage
HOLD Hold Input
NC No Connect

TABLE 1-2: DC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted:
VCC = 2.5V to 5.5V
Commercial (C): Tamb = 0C to +70C
Industrial (I): Tamb = -40C to +85C
Parameter Symbol Min Max Units Test Conditions
High level input voltage VIH1 2.0 VCC+1 V VCC 2.7V
VIH2 0.7 VCC VCC+1 V VCC< 2.7V
Low level input voltage VIL1 -0.3 0.8 V VCC 2.7V
VIL2 -0.3 0.3 VCC V VCC< 2.7V
Low level output voltage VOL 0.4 V IOL=2.1 mA
High level output voltage VOH VCC-0.5 V IOH=-400 A
Input leakage current ILI -10 10 A CS=VIH, VIN=GND to VCC
Output leakage current ILO -10 10 A CS=VIH, VOUT=GND to VCC
Internal Capacitance CINT 7 pF Tamb=25C, FCLK= 1.0 MHz,
(all inputs and outputs) VCC=5.5V (Note)
Operating Current ICC write 5 mA VCC=5.5V; SO=Open
3 mA VCC=2.5V; SO=Open
ICC read 1 mA VCC=5.5V; SO=Open, FCLK=3.0 MHz
500 A VCC=2.5V; SO=Open, FCLK=2.0 MHz
Standby Current ICCS 5 A CS=VCC=5.5V; VIN=Gnd or VCC
2 A CS=VCC=2.5V; VIN=Gnd or VCC
Note: This parameter is periodically sampled and not 100% tested.

DS21158B-page 2 Preliminary 1996 Microchip Technology Inc.

 25LC320
FIGURE 1-2: SERIAL INPUT TIMING
tCSD

CS
tCSS tR tCLD
tF tCSH

SCK
tSU tHD

SI msb in lsb in

high impedance
SO

FIGURE 1-3: SERIAL OUTPUT TIMING

CS

tCSH
tHI tLO
SCK
tV tDIS
tHO

SO msb out lsb out

dont care
SI

FIGURE 1-4: HOLD TIMING

CS
tHS tHH tHS tHH

SCK
tHZ tHV
high impedance
SO n+2 n+1 n n n-1

tSU
dont care
SI n+2 n+1 n n n-1

HOLD

1996 Microchip Technology Inc. Preliminary DS21158B-page 3

25LC320
TABLE 1-3: AC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted:
VCC = 2.5V to 5.5V
Commercial (C): Tamb = 0C to +70C
Industrial (I): Tamb = -40C to +85C
Symbol Parameter Min Max Units Test Conditions
fSCK Clock Frequency 3 MHz VCC=4.5V to 5.5V
2 MHz VCC=2.5V to 4.5V
tCSS CS Setup Time 100 ns VCC=4.5V to 5.5V
250 ns VCC=2.5V to 4.5V
tCSH CS Hold Time 100 ns VCC=4.5V to 5.5V
250 ns VCC=2.5V to 4.5V
tCSD CS Disable Time 250 ns VCC=4.5V to 5.5V
500 ns VCC=2.5V to 4.5V
tSU Data Setup Time 30 ns VCC=4.5V to 5.5V
50 ns VCC=2.5V to 4.5V
tHD Data Hold Time 50 ns VCC=4.5V to 5.5V
100 ns VCC=2.5V to 4.5V
tR CLK Rise Time 2 s (Note 1)
tF CLK Fall Time 2 s (Note 1)
tHI Clock High Time 150 ns VCC=4.5V to 5.5V
250 ns VCC=2.5V to 4.5V
tLO Clock Low Time 150 ns VCC=4.5V to 5.5V
250 ns VCC=2.5V to 4.5V
tCLD Clock Delay Time 50 ns
tV Output Valid from 150 ns VCC=4.5V to 5.5V
Clock Low 250 ns VCC=2.5V to 4.5V
tHO Output Hold Time 0 ns
tDIS Output Disable Time 200 ns VCC=4.5V to 5.5V (Note 1)
250 ns VCC=2.5V to 4.5V (Note 1)
tHS HOLD Setup Time 100 ns VCC=4.5V to 5.5V
100 ns VCC=2.5V to 4.5V
tHH HOLD Hold Time 100 ns VCC=4.5V to 5.5V
100 ns VCC=2.5V to 4.5V
tHZ HOLD Low to Output High-Z 100 ns VCC=4.5V to 5.5V (Note 1)
150 ns VCC=2.5V to 4.5V (Note 1)
tHV HOLD High to Output Valid 100 ns VCC=4.5V to 5.5V (Note 1)
150 ns VCC=2.5V to 4.5V (Note 1)
tWC Internal Write Cycle Time 5 ms (Note 2)
Endurance 1M E/W Cycles 25C, Vcc = 5.0V, Block Mode
(Note 3)
Note 1: This parameter is periodically sampled and not 100% tested.
2: tWC begins on the rising edge of CS after a valid write sequence and ends when the internal self-timed write
cycle is complete.
3: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

DS21158B-page 4 Preliminary 1996 Microchip Technology Inc.

 25LC320
2.0 PRINCIPLES OF OPERATION 2.2 Read Status Register (RDSR)
The 25LC320 is a 4096 byte EEPROM designed to The RDSR instruction provides access to the status
interface directly with the serial peripheral interface register. The status register may be read at any time,
(SPI) port of many of todays popular microcontroller even during a write cycle. The status register is format-
families, including Microchips midrange PIC16CXX ted as follows:
microcontrollers. It may also interface with microcontrol-
lers that do not have a built-in SPI port by using dis- 7 6 5 4 3 2 1 0
crete I/O lines programmed properly with software. WPEN X X X BP1 BP0 WEL WIP
The 25LC320 contains an 8-bit instruction register. The The Write-In-Process (WIP) bit indicates whether the
part is accessed via the SI pin, with data being clocked 25LC320 is busy with a write operation. When set to a
in on the rising edge of SCK. If the WPEN bit in the Sta- 1 a write is in progress, when set to a 0 no write is in
tus Register is set, the WP pin must be held high to progress. This bit is read only.
allow writing to the non-volatile bits in the status regis- The Write Enable Latch (WEL) bit indicates the status
ter. of the write enable latch. When set to a 1 the latch
Table 2-1 contains a list of the possible instruction bytes allows writes to the array and status register, when set
and format for device operation. All instructions, to a 0 the latch prohibits writes to the array and status
addresses and data are transferred MSB first, LSB last. register. The state of this bit can always be updated via
the WREN or WRDI commands regardless of the state
Data is sampled on the first rising edge of SCK after CS
of write protection on the status register. This bit is read
goes low. If the clock line is shared with other peripheral
only.
devices on the SPI bus, the user can assert the
HOLD input and place the 25LC320 in HOLD mode. The Block Protection (BP0 and BP1) bits indicate
After releasing the HOLD pin, operation will resume which blocks are currently write protected. These bits
from the point when the HOLD was asserted. are set by the user issuing the WRSR instruction.
These bits are non-volatile.
2.1 Write Enable (WREN) and Write
The Write Protect Enable (WPEN) bit is a non-volatile
Disable (WRDI)
bit that is available as an enable bit for the WP pin. The
The 25LC320 contains a write enable latch. This latch Write Protect (WP) pin and the Write Protect Enable
must be set before any write operation will be (WPEN) bit in the status register control the
completed internally. The WREN instruction will set the programmable hardware write protect feature.
latch, and the WRDI will reset the latch. The following is Hardware write protection is enabled when WP pin is
a list of conditions under which the write enable latch low and the WPEN bit is high. Hardware write
will be reset: protection is disabled when either the WP pin is high or
Power-up the WPEN bit is low. When the chip is hardware write
WRDI instruction successfully executed protected, only writes to non-volatile bits in the status
WRSR instruction successfully executed register are disabled. See Table 2-2 for matrix of
WRITE instruction successfully executed functionality on the WPEN bit and Figure 2-1 for a
flowchart of Table 2-2. See Figure 3-5 for RDSR timing
sequence.

TABLE 2-1: INSTRUCTION SET

Instruction Name Instruction Format Description

WREN 0000 0110 Set the write enable latch (enable write operations)
WRDI 0000 0100 Reset the write enable latch (disable write operations)
RDSR 0000 0101 Read status register
WRSR 0000 0001 Write status register (write protect enable and block write protection bits)
READ 0000 0011 Read data from memory array beginning at selected address
WRITE 0000 0010 Write data to memory array beginning at selected address
TABLE 2-2: WRITE PROTECT FUNCTIONALITY MATRIX

WPEN WP WEL Protected Blocks Unprotected Blocks Status Register

0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable

1996 Microchip Technology Inc. Preliminary DS21158B-page 5

25LC320
FIGURE 2-1: WRITE TO STATUS REGISTER AND/OR ARRAY FLOWCHART

CS Returns High

Write No No
to Status Write To other
Reg? to array? Commands

Yes Yes

No No
WEL = 1? WEL = 1?

Yes Yes

No Write to the
WP is low? Unprotected Block

Yes

No Do not write to
WPEN = 1? Array

Yes
Write to
Status Register

Do not write to
Status Register

From other
Commands

Continue

2.3 Write Status Register (WRSR) TABLE 2-3: ARRAY PROTECTION

The WRSR instruction allows the user to select one of Array Addresses
four protection options for the array by writing to the BP1 BP0
Write Protected
appropriate bits in the status register. The array is
0 0 none
divided up into four segments. The user has the ability
to write protect none, one, two, or all four of the seg- 0 1 upper 1/4
ments of the array. The partitioning is controlled as illus- 0C00h - 0FFFh
trated in Table 2-3. 1 0 upper 1/2
0800h - 0FFFh
See Figure 3-6 for WRSR timing sequence.
1 1 all
0000h - 0FFFh

DS21158B-page 6 Preliminary 1996 Microchip Technology Inc.

 25LC320
3.0 DEVICE OPERATION For the data to be actually written to the array, the CS
must be brought high after the least significant bit (D0)
3.1 Clock and Data Timing of the nth data byte has been clocked in. If CS is brought
high at any other time, the write operation will not be
Data input on the SI pin is latched on the rising edge of completed. Refer to Figure 3-3 and Figure 3-4 for more
SCK. Data is output on the SO pin after the falling edge detailed illustrations on the byte write sequence and the
of SCK. page write sequence respectively.
3.2 Read Sequence While the write is in progress, the status register may
be read to check the status of the WPEN, WIP, WEL,
The part is selected by pulling CS low. The 8-bit read BP1, and BP0 bits. A read attempt of a memory array
instruction is transmitted to the 25LC320 followed by location will not be possible during a write cycle. When
the 16-bit address, with the four MSBs of the address a write cycle is completed, the write enable latch is
being dont care bits. After the correct read instruction reset.
and address are sent, the data stored in the memory at
the selected address is shifted out on the SO pin. The 3.4 Data Protection
data stored in the memory at the next address can be
The following protection has been implemented to
read sequentially by continuing to provide clock pulses.
prevent inadvertent writes to the array:
The internal address pointer is automatically incre-
mented to the next higher address after each byte of The write enable latch is reset on power-up.
data is shifted out. When the highest address is A write enable instruction must be issued to set
reached (0FFFh) the address counter rolls over to the write enable latch.
address 0000h allowing the read cycle to be continued After a successful byte write, page write, or status
indefinitely. The read operation is terminated by setting register write, the write enable latch is reset.
CS high (Figure 3-1). CS must be set high after the proper number of
clock cycles to start an internal write cycle.
3.3 Write Sequence Access to the array during an internal write cycle
is ignored and programming is continued.
Prior to any attempt to write data to the 25LC320, the
write enable latch must be set by issuing the WREN 3.5 Power On State
instruction (Figure 3-2). This is done by setting CS low
and then clocking the proper instruction into the The 25LC320 powers on in the following state:
25LC320. After all eight bits of the instruction are trans- The device is in low power standby mode.
mitted, the CS must be brought high to set the write The write enable latch is reset.
enable latch. If the write operation is initiated SO is in high impedance state.
immediately after the WREN instruction without CS A low level on CS is required to enter active state.
being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set.
Once the write enable latch is set, the user may pro-
ceed by setting the CS low, issuing a write instruction,
followed by the 16-bit address, with the four MSBs of
the address being dont care bits, and then the data to
be written. Up to 32 bytes of data can be sent to the
25LC320 before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page. A page address begins with XXXX XXXX
XXX0 0000 and ends with XXXX XXXX XXX1 1111. If
the internal address counter reaches XXXX XXXX
XXX1 1111 and the clock continues, the counter will roll
back to the first address of the page and overwrite any
data in the page that may have been written.

1996 Microchip Technology Inc. Preliminary DS21158B-page 7

25LC320
FIGURE 3-1: READ SEQUENCE
CS

0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK

instruction 16 bit address

SI 0 0 0 0 0 0 1 1 15 14 13 12 2 1 0

data out
high impedance
SO 7 6 5 4 3 2 1 0

FIGURE 3-2: WRITE ENABLE SEQUENCE

CS

0 1 2 3 4 5 6 7
SCK

SI 0 0 0 0 0 1 1 0

high impedance
SO

FIGURE 3-3: WRITE SEQUENCE

CS
Twc
0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
instruction 16 bit address data byte
SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0

high impedance
SO

DS21158B-page 8 Preliminary 1996 Microchip Technology Inc.

 25LC320
FIGURE 3-4: PAGE WRITE SEQUENCE
CS

0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
instruction 16-bit address data byte 1
SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0

CS

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
data byte 2 data byte 3 data byte n (32 max)
SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

FIGURE 3-5: READ STATUS REGISTER SEQUENCE

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
instruction
SI 0 0 0 0 0 1 0 1

data from status register

high impedance
SO 7 6 5 4 3 2 1 0

FIGURE 3-6: WRITE STATUS REGISTER SEQUENCE

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
instruction data to status register
SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0

high impedance
SO

1996 Microchip Technology Inc. Preliminary DS21158B-page 9

25LC320
4.0 PIN DESCRIPTIONS The WP pin function is blocked when the WPEN bit in
the status register is low. This allows the user to install
4.1 Chip Select (CS) the 25LC320 in a system with WP pin grounded and still
be able to write to the status register. The WP pin
A low level on this pin selects the device. A high level functions will be enabled when the WPEN bit is
deselects the device and forces it into standby mode. set high.
However, a programming cycle which is already in
progress will be completed, regardless of the CS input 4.6 Hold (HOLD)
signal. If CS is brought high during a program cycle, the
device will go into standby mode as soon as the pro- The HOLD pin is used to suspend transmission to the
gramming cycle is complete. As soon as the device is 25LC320 while in the middle of a serial sequence with-
deselected, SO goes to the high impedance state, out having to re-transmit entire sequence over at a later
allowing multiple parts to share the same SPI bus. A time. It should be held high any time this function is not
low to high transition on CS after a valid write sequence being used. Once the device is selected and a serial
is what initiates an internal write cycle. After power-up, sequence is underway, the HOLD pin may be pulled low
a low level on CS is required prior to any sequence to pause further serial communication without resetting
being initiated. the serial sequence. The HOLD pin must be brought
low while SCK is low, otherwise the HOLD function will
4.2 Serial Input (SI) not be evoked until the next SCK high to low transition.
The 25LC320 must remain selected during this
The SI pin is used to transfer data into the device. It sequence. The SI, SCK, and SO pins are in a high
receives instructions, addresses, and data to be written impedance state during the time the part is paused and
to the memory. Input is latched on the rising edge of the transitions on these pins will be ignored. To resume
serial clock. serial communication, HOLD must be brought high
It is possible for the SI pin and the SO pin to be tied while the SCK pin is low, otherwise serial communica-
together. With SI and SO tied together, two way tion will not resume.
communication of data can occur using only one
microcontroller I/O line.

4.3 Serial Output (SO)

The SO pin is used to transfer data out of the 25LC320.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
It is possible for the SI pin and the SO pin to be tied
together. With SI and SO tied together, two-way
communication of data can occur using only one
microcontroller I/O line.

4.4 Serial Clock (SCK)

The SCK is used to synchronize the communication
between a master and the 25LC320. Instructions,
addresses, or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.

4.5 Write Protect (WP)

This pin is used in conjunction with the WPEN bit in the
status register to prohibit writes to the non-volatile bits
in the status register. When WP is low and WPEN is
high, writing to the non-volatile bits in the status register
is disabled. All other operations function normally.
When WP is high, all functions, including writes to the
non-volatile bits in the status register operate normally.
WP going low during a status register write sequence
will disable writing to the status register. If an internal
write cycle has already begun, WP going low will have
no effect on the write.

DS21158B-page 10 Preliminary 1996 Microchip Technology Inc.

 25LC320
25LC320 Product Identification System
To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed
sales offices.

25LC320 - /P

Package: P = PDIP (300 mil Body), 8-lead

SN = SOIC (150 mil Body), 8-lead
ST = TSSOP (4.4 mm Body), 14-lead

Temperature Blank = 0C to +70C

Range: I = -40C to +85C

Device: 25LC320 32K SPI Bus Serial EEPROM

25LC320T 32K SPI Bus Serial EEPROM (Tape and Reel)

Sales and Support

Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office (see next page)
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchips Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.

1996 Microchip Technology Inc. Preliminary DS21158B-page 11

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All rights reserved. 1996, Microchip Technology Incorporated, USA. 11/96

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DS21158B-page 12 Preliminary 1996 Microchip Technology Inc.