Addis Ababa Science and Technology University

College of Engineering
Department of Electrical & Computer Engineering

Computer Architecture and Organization

Lecture by: Habtam Atanaw

1. Basic Concepts and Computer Evolution

Organization and Architecture

Structure and Function

Computer Evolution and Performance

 Organization and Architecture

Computer Architecture

• It refers to those attributes of a system visible to a programmer or, those

attributes that have a direct impact on the logical execution of a program.

• Examples of architectural attributes include:

 The instruction set,
 The number of bits used to represent various data types (e.g.,
numbers, characters),
 I/O mechanisms, and techniques for addressing memory.

• Example: Design a house

 Cont.…….
Computer Organization

• It refers to the operational units and their interconnections that realize the
architectural specifications.

• Organizational attributes include those hardware details transparent to the

programmer, such as:
 Control signals; interfaces between the computer and peripherals;

and the memory technology used.

• Example: Building a house by bricks & technology

 Structure and Function
• A computer is a complex system; It contain millions of elementary electronic
components.

Structure: The way in which the components are interrelated.

Function: The operation of each individual component as part of the

structure.
 Function

• There are four basic functions that a computer can perform:

• Data processing
• Data storage
Short-term
Long-term
• Data movement
Input-output (I/O) - when data are received from or delivered to a device
(peripheral) that is directly connected to the computer.
Data communications – when data are moved over longer distances, to or
from a remote device.
• Control
A control unit manages the computer’s resources.
Fig. 1.1: A Functional
View of the Computer

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Fig 1.2a. Data movement: Fig 1.2b Data storage: data
transferring data from one transferred from the external
peripheral or communication environment to computer storage
line to another. (read) and vice versa (write).
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 Fig 1.2d. Data processing, on data en
Fig 1.2c. Data processing,
route between storage and the
on data in Storage.
external environment.
Structure

Figure 1.3 A Top-down view of a computer

There are four
main structural • CPU: Controls the operation of the computer and performs
components of
its data processing functions.
the computer:
• Main Memory: Stores data for the processor.

• I/O: Moves data between the computer and its external

environment.

• System Interconnection: Some mechanism that provides

for communication among CPU, main memory, and I/O.
 The CPU major • Control Unit: Controls the operation of the CPU and
structural components : hence the computer.

• ALU: Performs the computer’s data processing

function

• Registers: Provide storage internal to the CPU

• CPU Interconnection: Some mechanism that

provides for communication among the control unit,
ALU, and registers
Computer Evolution and Performance
Computer Evolution and Performance….
• Evolution: Reading assignment

• The first generation of computers used vacuum tubes for digital logic
elements and memory.

• The most famous first-generation computer, known as the IAS

computer also known as von Neumann machine.
 The Von Neumann machine
• The task of entering and altering programs for the ENIAC was extremely
tedious.

• Suppose a program could be represented in a form suitable for storing in

memory alongside the data.

• Then, a computer could get its instructions by reading them from memory,
and a program could be set or altered by setting the values of a portion of
memory.

• This idea, known as the stored-program concept., is usually attributed to the

ENIAC designers, most notably the mathematician John von Neumann.
Cont.…….

• In 1946, von Neumann and his colleagues began the design of a

new stored program computer, referred to as the IAS computer,
at the Princeton Institute for Advanced Studies.

• The IAS computer, although not completed until 1952, is the

prototype of all subsequent general-purpose computers.
Performance and Evolution

Fig. 1.4. Structure of the IAS Computer

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 Cont.…….
• The IAS computer consists of

• A main memory, which stores both data and instructions.

• An arithmetic and logic unit (ALU) capable of operating on binary data.

• A control unit, which interprets the instructions in memory and causes

them to be executed.
• Input/output (I/O) equipment operated by the control unit.

• With rare exceptions, all of today’s computers have this same general structure
and function and are thus referred to as von Neumann machines.

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 Memory of the IAS
• Consists of 1000 storage locations called words
• Word length - 40 binary digits (bits) each.
• A word may contain:
• A numbers stored as 40 binary digits( bits)- sign bit +39 bit value.
• An instruction pair. Each instruction:
• An opcode (8 bits) specifying the operation to be performed, and
• An address (12 bits) designating one of the words in memory
(numbered from 0 to 999).
Figure 1.5 below illustrates these formats.

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 Cont.…..

Fig. 1.5. IAS Memory Formats

• A word may also contain two 20-bit instructions, with each instruction
consisting of:
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Cont.……
• The control unit operates the IAS by fetching instructions from memory and
executing them one at a time.

• Both the control unit and the ALU contain storage locations, called registers,
defined as follows:

• For example, the result of multiplying two 40-bit numbers is an 80-bit number;
the most significant 40 bits are stored in the AC and the least significant in the
MQ.
 Registers
Memory buffer register • Contains a word to be stored in memory or sent to the I/O unit
(MBR) • Or is used to receive a word from memory or from the I/O unit

Memory address register • Specifies the address in memory of the word to be written
(MAR) from or read into the MBR

Instruction register (IR) • Contains the 8-bit opcode instruction being executed

Instruction buffer register • Employed to temporarily hold the right-hand instruction from
(IBR) a word in memory

• Contains the address of the next instruction pair to be fetched

Program counter (PC) from memory

Accumulator (AC) and • Employed to temporarily hold operands and results of ALU
multiplier quotient (MQ) operations
Fig. 1.6. Expanded
Structure of IAS
Computer

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 Instruction cycle
• Each instruction cycle consists of two subcycles.
• The fetch cycle
• The execute cycle
• During the fetch cycle, the OPcode of the next instruction is loaded into
the IR and the address portion is loaded into the MAR.
• This instruction may be taken from the IBR, or it can be obtained from
memory by loading a word into the MBR, and then down to the IBR, IR,
and MAR.
• Once the opcode is in the IR, the execute cycle is performed.

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 Cont.……..
• Control circuitry interprets the opcode and executes the instruction by
sending out the appropriate control signals to cause data to be moved or an
operation to be performed by the ALU.

• The IAS computer had a total of 21 instructions, which are listed in below.

• These can be grouped as follows:

• Data transfer: Move data between memory and ALU registers or between
two ALU registers.

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Cont.……
• Unconditional branch: Normally, the control unit executes instructions
in sequence from memory. This sequence can be changed by a branch
instruction, which facilitates repetitive operations.
• Conditional branch: The branch can be made dependent on a
condition, thus allowing decision points.
• Arithmetic: Operations performed by the ALU.

• Address modify: Permits addresses to be computed in the ALU and

then inserted into instructions stored in memory. This allows a
program considerable addressing flexibility.
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Fig. 1.7. Expanded
Structure of IAS
Computer

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 The IAS Instruction Set

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Computer System
• A computer system, like any system , consists of an interrelated set
of components.

Program Concept

• A sequence of steps

• For each step, an arithmetic or logical operation is done

• For each operation, a different set of control signals is needed

 Components
• The Control Unit and the Arithmetic and Logic Unit constitute
the Central Processing Unit

• Data and instructions need to get into the system and results out

Input/output

• Temporary storage of code and results is needed

Main memory
Computer Components: Top Level View
 Instruction Cycle
• Two steps:
• Fetch
• Execute
 Fetch Cycle
• Program Counter (PC) holds address of next instruction to fetch.

• Processor fetches instruction from memory location pointed to by PC.

• Increment PC.

• Instruction loaded into Instruction Register (IR).

• Processor interprets instruction and performs required actions.

 Execute Cycle
• Processor-memory
Data transfer between CPU and main memory
• Processor I/O
Data transfer between CPU and I/O module
• Data processing
Some arithmetic or logical operation on data
• Control
Alteration of sequence of operations
• Combination of above
 Example of Program Execution

0001 Load AC from memory

0010 Store AC to memory
0101 Add to AC from memory
 Instruction cycle state diagram
For any given instruction cycle, some states may be null and others may be visited
more than once. The states can be described as follows:

• Instruction address calculation: Determine the address of the next instruction

to be executed.

• Instruction fetch: Read instruction from its memory location into the
processor.

• Instruction operation decoding: Analyze instruction to determine type of

operation to be performed and operand(s) to be used.
• Operand address calculation: If the operation involves reference to an
operand in memory or available via I/O, then determine the address of the
operand.

• Operand fetch: Fetch the operand from memory or read it in from I/O.

• Data operation: Perform the operation indicated in the instruction.

• Operand store: Write the result into memory or out to I/O.

Instruction Cycle State Diagram
 Interrupts
• Mechanism by which other modules (e.g. I/O) may interrupt
normal sequence of processing
• Program
Example: overflow, division by zero
• Timer
Generated by internal processor timer
Used in pre-emptive multi-tasking
• I/O
from I/O controller
• Hardware failure
e.g. memory parity error
Program Flow Control
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
• Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
• Suspend execution of current program
• Save context
• Set PC to start address of interrupt handler routine
• Process interrupt
• Restore context and continue interrupted program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Program Timing: Short I/O Wait
Program Timing: Long I/O Wait
Instruction Cycle (with Interrupts) - State Diagram