Infineon TC1782 DS v01 - 04 - 01 en

32-Bit
Microcontroller
TC1782
32-Bit Single-Chip Microcontroller
Data Sheet
V 1.4.1 2014-05
Microcontrollers
Edition 2014-05
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
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32-Bit
Microcontroller
TC1782
32-Bit Single-Chip Microcontroller
Data Sheet
V 1.4.1 2014-05
Microcontrollers
TC1782
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2 System Overview of the TC1782 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.1 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.1 TC1782 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
4 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42
5 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
5.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
5.1.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
5.1.2 Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . 5-46
5.1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47
5.1.4 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48
5.1.5 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50
5.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59
5.2.1 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59
5.2.2 Analog to Digital Converters (ADCx) . . . . . . . . . . . . . . . . . . . . . . . . . 5-74
5.2.3 Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . . 5-80
5.2.4 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-85
5.2.5 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-86
5.2.6 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-87
5.2.6.1 Calculating the 1.3 V Current Consumption . . . . . . . . . . . . . . . . . 5-91
5.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-92
5.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-92
5.3.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-93
5.3.3 Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-96
5.3.4 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-99
5.3.5 ERAY Phase Locked Loop (ERAY_PLL) . . . . . . . . . . . . . . . . . . . . . 5-101
5.3.6 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-102
5.3.7 DAP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-104
5.3.8 Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-106
5.3.8.1 Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . 5-106
5.3.8.2 Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . 5-108
5.3.8.3 SSC Master/Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . 5-110
5.3.8.4 ERAY Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-112
5.4 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-114
5.4.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-114
5.4.2 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-115
Data Sheet I-1 V 1.4.1, 2014-05

TC1782
5.4.3 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-115

5.4.4 Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-117
6 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-119
Data Sheet I-2 V 1.4.1, 2014-05

TC1782
Data Sheet 3 V 1.4.1, 2014-05

TC1782
Data Sheet 4 V 1.4.1, 2014-05

TC1782
Summary of Features
1 Summary of Features
The SAK-TC1782F-320F180HR / SAK-TC1782F-320F180HL has the following
features:
• High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Single precision Floating Point Unit (FPU)
– 180 MHz operation at full temperature range
• 32-bit Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
– 32 Kbyte Code Memory (CMEM)
• Multiple on-chip memories
– 2.5 Mbyte Program Flash Memory (PFLASH) with ECC
– 128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 128 Kbyte Data Memory (LDRAM)
– Instruction Cache: up to 16 Kbyte (ICACHE, configurable)
– 40 Kbyte Code Scratchpad Memory (SPRAM)
– Data Cache: up to 4 Kbyte (DCACHE, configurable)
– 8 Kbyte Overlay Memory (OVRAM)
– 16 Kbyte BootROM (BROM)
• 16-Channel DMA Controller
• Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
• High performing on-chip bus structure
– 64-bit Local Memory Buses between CPU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridge (LFI Bridge)
• Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Three High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– One serial Micro Second Bus interface (MSC) for serial port expansion to external
power devices
– One High-Speed Micro Link interface (MLI) for serial inter-processor
communication
– One MultiCAN Module with 3 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
– One FlexRayTM module with 2 channels (E-Ray).
Data Sheet 1 V 1.4.1, 2014-05

TC1782
Summary of Features
– One General Purpose Timer Array Module (GPTA) with additional Local Timer Cell
Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
• 32 analog input lines for ADC
– 2 independent kernels (ADC0 and ADC1)
– Analog supply voltage range from 3.3 V to 5 V (single supply)
• 4 different FADC input channels
– channels with impedance control and overlaid with ADC1 inputs
– Extreme fast conversion, 21 cycles of fFADC clock
– 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
• 86 digital general purpose I/O lines (GPIO), 4 input lines
• Digital I/O ports with 3.3 V capability
• On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
• Dedicated Emulation Device chip available (TC1782ED)
– multi-core debugging, real time tracing, and calibration
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
• Power Management System
• Clock Generation Unit with PLL
Data Sheet 2 V 1.4.1, 2014-05

TC1782
Summary of Features
The SAK-TC1782N-320F180HR / SAK-TC1782N-320F180HL has the following

features:
power devices
communication
Data Sheet 3 V 1.4.1, 2014-05

TC1782
Summary of Features
Data Sheet 4 V 1.4.1, 2014-05

TC1782
Summary of Features

features:
– 2 Mbyte Program Flash Memory (PFLASH) with ECC
power devices
communication
Data Sheet 5 V 1.4.1, 2014-05

TC1782
Summary of Features
Data Sheet 6 V 1.4.1, 2014-05

TC1782
Summary of Features
The SAK-TC1782F-320F160HR / SAK-TC1782F-320F160HL has the following

features:
power devices
communication
– One FlexRayTM module with 2 channels (E-Ray).
Data Sheet 7 V 1.4.1, 2014-05

TC1782
Summary of Features
Data Sheet 8 V 1.4.1, 2014-05

TC1782
Summary of Features

features:
power devices
communication
Data Sheet 9 V 1.4.1, 2014-05

TC1782
Summary of Features
Data Sheet 10 V 1.4.1, 2014-05

TC1782
Summary of Features
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
• The derivative itself, i.e. its function set, the temperature range, and the supply
voltage
• The package and the type of delivery.
For the available ordering codes for the TC1782 please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.
This document describes the derivatives of the device.The Table 1 enumerates these
derivatives and summarizes the differences.
Table 1 TC1782 Derivative Synopsis

Derivative Ambient Temperature Range Package
o o
SAK-TC1782F-320F180HR TA = -40 C to +125 C PG-LQFP-176-20
o o
SAK-TC1782F-320F180HL TA = -40 C to +125 C PG-LQFP-176-10
SAK-TC1782N-320F180HR TA = -40oC to +125oC PG-LQFP-176-20
o o
SAK-TC1782N-320F180HL TA = -40 C to +125 C PG-LQFP-176-10
SAK-TC1782N-256F133HR TA = -40oC to +125oC PG-LQFP-176-20
o o
o o
SAK-TC1782F-320F160HR TA = -40 C to +125 C PG-LQFP-176-20
SAK-TC1782F-320F160HL TA = -40oC to +125oC PG-LQFP-176-10
o o
SAK-TC1782N-320F160HR TA = -40 C to +125 C PG-LQFP-176-20
o o
Data Sheet 11 V 1.4.1, 2014-05

TC1782
System Overview of the TC1782
2 System Overview of the TC1782

The TC1782 combines three powerful technologies within one silicon die, achieving new
levels of power, speed, and economy for embedded applications:
• Reduced Instruction Set Computing (RISC) processor architecture
• Digital Signal Processing (DSP) operations and addressing modes
• On-chip memories and peripherals
DSP operations and addressing modes provide the computational power necessary to
efficiently analyze complex real-world signals. The RISC load/store architecture
provides high computational bandwidth with low system cost. On-chip memory and
peripherals are designed to support even the most demanding high-bandwidth real-time
embedded control-systems tasks.
Additional high-level features of the TC1782 include:
• Efficient memory organization: instruction and data scratch memories, caches
• Serial communication interfaces – flexible synchronous and asynchronous modes
• Peripheral Control Processor – standalone data operations and interrupt servicing
• DMA Controller – DMA operations and interrupt servicing
• General-purpose timers
• High-performance on-chip buses
• On-chip debugging and emulation facilities
• Flexible interconnections to external components
• Flexible power-management
The TC1782 is a high-performance microcontroller with TriCore CPU, program and data
memories, buses, bus arbitration, an interrupt controller, a peripheral control processor
and a DMA controller and several on-chip peripherals. The TC1782 is designed to meet
the needs of the most demanding embedded control systems applications where the
competing issues of price/performance, real-time responsiveness, computational power,
data bandwidth, and power consumption are key design elements.
The TC1782 offers several versatile on-chip peripheral units such as serial controllers,
timer units, and Analog-to-Digital converters. Within the TC1782, all these peripheral
units are connected to the TriCore CPU/system via the Flexible Peripheral Interconnect
(FPI) Bus and the Local Memory Bus (LMB). Several I/O lines on the TC1782 ports are
reserved for these peripheral units to communicate with the external world.
Data Sheet 12 V 1.4.1, 2014-05

TC1782
System Overview of the TC1782Block Diagrams
2.1 Block Diagrams

Figure 1 shows the block diagram of the SAK-TC1782-320F180HR / SAK-TC1782-
320F180HL / SAK-TC1782-320F160HR / SAK-TC1782-320F160HL.
Abbreviations:
ICACHE: Instruction Cache
FPU DCACHE Data Cache
PMI DMI SPRAM: Scratch-Pad RAM
LDRAM: Local Data RAM
TriCore 124 KB LDRAM OVRAM: Overlay RAM
24 KB SPRAM LDRAM
CPU 4 KB DCACHE BROM: Boot ROM
16 KB ICACHE PFlash: Program Flash
(Configurable) (Configurable)
DCACHE DFlash: Data Flash
PRAM: Parameter RAM in PCP
CPS
PCODE: Code RAM in PCP
BCU
Local Memory Bus (LMB)
PMU M
DMA
SMIF
2,5 MB PFlash Bridge OCDS L1 Debug
16 channels
128 KB DFlash Interface/ JTAG
8 KB OVRAM M/S
16 KB BROM
MLI0
System Peripheral Bus
(SPB)
MemCheck
16 KB PRAM
Interrupt
FPI-Bus Interface
System
ASC0
Interrupts
PCP2
Core
STM
ASC1
5V (3.3V supported as well)
Ext. ADC Supply
32 KB CMEM
SCU
E-Ray
(2 Channels) ADC0 28
(5V max)
PLL fE -Ray
Ports ADC1
E-RAY
GPTA0 SBCU 4
PLL fCPU
SSC0 FADC (3.3V max)

LTCA2 4
3.3V
SSC1 Ext. FADC Supply
Ext. Multi
Request CAN MSC0
(LVDS) SSC2 BlockDiagram
(3 Nodes,
Unit 128 MO) SAK-TC1782F-320F180HR
SAK-TC1782F-320F180HL
SAK-TC1782F-320F160HR
Figure 1 SAK-TC1782-320F180HR / SAK-TC1782-320F180HL / SAK-TC1782-

320F160HR / SAK-TC1782-320F160HL Block Diagram
Data Sheet 13 V 1.4.1, 2014-05

TC1782
Figure 2 shows the block diagram of the SAK-TC1782N-320F180HR / SAK-TC1782N-

320F180HL / SAK-TC1782N-320F160HR / SAK-TC1782N-320F160HL.
Abbreviations:
24 KB SPRAM LDRAM
CPS
PCODE: Code RAM in PCP
BCU
PMU M
DMA
SMIF
2,5 MB PFlash Bridge OCDS L1 Debug
16 channels
128 KB DFlash Interface/JTAG
8 KB OVRAM M/S
16 KB BROM
MLI0
(SPB)
MemCheck
16 KB PRAM
Interrupt
FPI-Bus Interface
ASC0 System
Interrupts
PCP2
Core
ASC1 STM
Ext. ADC Supply
32 KB CMEM
SCU
ADC0 28
(5V max)
PLL fE -Ray
Ports ADC1
E-RAY
GPTA0 SBCU 4
PLL fCPU

LTCA2 4
3.3V
Ext. Multi
Request CAN MSC0
(3 Nodes, (LVDS ) SSC2
Unit 128 MO) BlockDiagram
SAK-TC1782N-320F180HR
SAK-TC1782N-320F180HL
Figure 2 SAK-TC1782N-320F180HR / SAK-TC1782N-320F180HL / SAK-

TC1782N-320F160HR / SAK-TC1782N-320F160HL /
Block Diagram
Data Sheet 14 V 1.4.1, 2014-05

TC1782
Figure 3 shows the block diagram of the SAK-TC1782N-256F133HR / SAK-TC1782N-

256F133HL.
Abbreviations:
24 KB SPRAM LDRAM
CPS PCODE: Code RAM in PCP
BCU
PMU M
DMA
SMIF
2 MB PFlash Bridge OCDS L1 Debug
16 channels
64 KB DFlash Interface/JTAG
8 KB OVRAM M/S
16 KB BROM
MLI0
(SPB)
MemCheck
16 KB PRAM
Interrupt
FPI-Bus Interface
System
ASC0
Interrupts
PCP2
Core
STM
ASC1
Ext. ADC Supply
32 KB CMEM
SCU
ADC0 28
(5V max)
PLL Ports ADC1

fE -R ay
E-RAY
GPTA0 SBCU 4
PLL fCPU
LTCA2 4
3.3V
Ext. Multi
Request CAN MSC0
(3 Nodes, (LVDS) SSC2
Unit 128 MO) BlockDiagram
Figure 3 SAK-TC1782N-256F133HR / SAK-TC1782N-256F133HL

Block Diagram
Data Sheet 15 V 1.4.1, 2014-05

TC1782
Pinning
3 Pinning
Figure 4 is showing the TC1782 Logic Symbol.
Alternate Functions
PORST
TESTMODE
General Control
ESR0
16 GPTA, SCU, E-RAY,1)
Port 0
MSC0
ESR1 16 GPTA, SSC1,
Port 1 ADC0, OCDS
TRST 14
Port 2 GPTA, SSC0/1,
TCK / DAP0 MLI 0, MSC0
OCDS / 16 GPTA, ASC0/1, SSC0/1,
JTAG Control TDI / BRKIN Port 3
SCU, CAN, MSC0
TDO / DAP2 / 4
BRKOUT Port 4 GPTA, SCU, CAN
TMS / DAP1 16 1)
Port 5 GPTA, MLI0, E-RAY,
Analog Inputs AN[35:0] SSC2
4
VD D M TC1782 Port 6 GPTA, MSC0
VSSM
V D D MF 1) Only available for
SAK-TC1782 F-320 F180HR,
V SSMF SAK-TC1782 F-320 F180HL,
Analog Power V D D AF SAK-TC1782 F-320 F160HR,
Supply SAK-TC1782 F-320F160HL,
V AR EF0 SAK-TC1782 F-320 F133HR and
VAGN D 0 SAK-TC1782 F-320 F133HL
VFAR EF
V FAGN D XTAL1
XTAL2
V D D FL3 V D D OSC Oscillator
9
Digital Circuitry VD D V D D OSC3
Power Supply 10 V SSOSC
VD D P
11
VSS
TC1782_LQFP-176
Figure 4 TC1782 Logic Symbol
Data Sheet 16 V 1.4.1, 2014-05

3.1
Figure 5
Data Sheet
LQFP-176-20.
VDDMF
V DD(SB)
VDD
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN7
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AN35
RXDA1/ T READY0B/OUT 94 /P5. 14
T VALID0B/SLSO16 /P5. 13
T DAT A0 /SLSO07 /OUT 93 /P5. 12
T XENB/ RCLK0B/OUT 92 /P5. 11
T XENA/RREADY0B/OUT 91 /P5. 10
T XDB1 /RVALID0 B/OUT 90/ P5 .9
T XDA1/RDAT A0B/OUT 89 /P5. 8
RXDB1 /T CLK0/OUT 95/P5 .15
SCLK2/ OUT 47/ OUT 15/IN 47/ P5 .7
M T SR2A/OUT 46 /OUT 14 /IN 46/IN 31/ P5 .6
M RST2A/OUT 45 /OUT 13 /IN 45/IN 30/ P5 .5
SLSCO24 /OUT 44 /OUT 12 /SLSI2AIN 44/IN 29/ P5 .4
SLSCO 23/ OUT 43/ OUT 11/IN 43/ P5 .3
SLSCO22 /OUT 42 /OUT 10 /IN 42/IN 28/ P5 .2
SLSCO 21 /OUT 41/ OUT 9/IN 41/IN 27/ P5 .1
SLSCO 20 /OUT 40/ OUT 8/IN 40/IN 26/ P5 .0
V FAREF
V SSMF
V DDAF
V SS
V DDP
V SS
V DDP
V FAGND
9
8
7
6
5
4
3
2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
A N 19 45 17 6 P 0.1 5/IN 15/R EQ 5/O U T1 5/S OP 0 C
A N 18 46 17 5 P 0.1 4/IN 14/R EQ 4/O U T1 4/F CLP 0C
A N 17 47 17 4 P 0.7 /IN 7 /HW C F G7/R E Q 3/O U T7 /OU T 63
A N 16 48 17 3 P 0.6 /IN 6 /HW C F G6/R E Q 2/O U T6 /OU T 62
A N 15 49 17 2 V SS
A N 14 50 17 1 V DDP
V AGND0 51 17 0 V DD(SB)
V AREF 0 52 16 9 P 0.1 3/IN 13/O UT1 3/T X E N B
VSSM 53 16 8 P 0.1 2/IN 12/O UT1 2/T X E N A
V DDM 54 1 67 P 0.5 /IN 5 /HW C F G5/O UT5 /OUT 61
A N 13 55 16 6 P 0.4 /IN 4 /HW C F G4/O UT4 /OUT 60
A N 12 56 16 5 P 2.1 3/IN 13/O UT3 /S LS I1 1/S DI0
A N 11 57 16 4 P 2.8 /S LS O0 4/S LS O 14/ EN0 0
A N 10 58 16 3 P 2.1 2/IN 12/O UT2 /M TS R 1A / SO P 0B
AN9 59 162 P 2.1 1/IN 11/O UT1 /S CLK 1 A/ FCL P0 B
AN8 60 161 P 2.1 0/IN 10/O UT0 /M R ST 1A
AN6 61 160 P 2.9 /S LS O0 5/S LS O 15/ EN0 1
AN5 62 159 P 6.3 /IN 2 5/OU T 7/ OUT 83/ SO P 0A
AN4 63 158 P 6.2 /IN 2 4/OU T 6/ OUT 82/ SO N 0
AN3 64 1 57 P 6.1 /IN 1 5/OU T 5/ OUT 81/ FC L P0 A
TC1782 Pin Configuration
AN2 65 156 P 6.0 /IN 1 4/OU T 4/ OUT 80/ FC L N 0

AN1 66 155 V SS
17
AN0 67 154 V DDP
VDD 68 153 V DD
V DDP 69 15 2 P 0.1 1/IN 11/O UT1 1/T X DB 0
TC1782
V SS 70 15 1 P 0.1 0/IN 10/O UT1 0/T X DA 0
A D 0E M UX 2/OU T1 8/IN 1 8/P 1 .14 71 15 0 P 0.9 /IN 9 /RX DB 0/OU T9/ OUT 65
A D 0E M UX 1/OU T1 7/IN 1 7/P 1 .13 72 14 9 P 0.8 /IN 8 /RX DA 0/OU T8/ OUT 64
A D 0E M UX 0/OU T1 6/IN 1 6/P 1 .12 73 14 8 P 0.3 /IN 3 /HW C F G3/O UT3 /OUT 59
T CLK 0/ OUT 28/ OU T 32/I N32/ P 2.0 74 147 P 0.2 /IN 2 /HW C F G2/O UT2 /OUT 58
S LS O 13/ SL S O03 /OUT 33 /TR E A DY 0A /I N33/ P 2.1 75 14 6 P 0.1 /IN 1 /HW C F G1/O UT1 /OUT 57 /S D I1
T V A LID0 A/ OUT 29/ OU T 34/I N34/ P 2.2 76 14 5 P 0.0 /IN 0 /HW C F G0/O UT0 /OUT 56
T D A TA 0/ OUT 30/ OU T 35/I N35/ P 2.3 77 14 4 P 3.1 1/O UT9 3/R E Q1
OU T 31 /OUT 36 /R CLK 0A /I N36/ P 2.4 78 14 3 P 3.1 2/O UT9 4/R X D CA N0 /RX D0B
R RE A D Y 0A /O UT3 7/OU T1 10/I N37/ P 2.5 79 14 2 P 3.1 3/O UT9 5/T X D CA N0/T X D 0
O U T3 8/O UT1 11/ R V AL ID 0A /I N38/ P 2.6 80 14 1 V DDFL 3
OU T 39/ RD A TA 0A /I N39/ P 2.7 81 14 0 V SS
V SS 82 13 9 V DDP
V DDP 83 13 8 P 3.9 /OU T 91 /R X D 1A
VDD 84 137 P 3.1 0/O UT9 2/R E Q0
V SS 85 13 6 P 3.0 /OU T 84 /R X D 0A
OU T 52 /OUT 28 /IN 52 /IN2 8/R X D CA N2/ P 4.0 86 13 5 P 3.1 /OU T 85 //T XD 0
O UT5 3/O U T2 9/IN 5 3/I N 29/ TX D CA N2/ P 4.1 87 13 4 P 3.1 4/O UT9 6/R X D CA N1 /RX D1B /S DI2
E X T CLK 1/O U T5 4/O U T3 0/IN 54/I N30/ P 4.2 88 13 3 P 3.1 5/O UT9 7/T X D CA N1/T X D 1
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
89
90
91
92
93
94
95
96
97
98
99
V SS
V DD
V SS
V SS
V DD
V DD
V DDP
V DDP
V DDP
ESR1
ESR0
T RST
XT AL1
XT AL2
V SSOSC
V DDOSC
PORST
V DDOSC3
T CK/DAP0
T M S/DAP1
SAK-TC1782F-320F180HR / SAK-TC1782F-320F180HL /
T EST M ODE
P3.2/ OUT 86/ SCLK0
P3.3/ OUT 87/ M RST0
P3.4/ OUT 88/ M T SR0
T DI/BRKIN/BRKOUT
P1 .15 /BRKIN/BRKOUT
P1.2/ IN18 /OUT 18 /OUT 74

P1.3/ IN19 /OUT 19 /OUT 75
P1.5/ IN21 /OUT 21 /OUT 77
P1.6/ IN22 /OUT 22 /OUT 78
P1.7/ IN23 /OUT 23 /OUT 79
P1 .1/IN 17/ OUT 17/ OUT 73
P3.8/ SLSO06 /OUT 90 /T XD1
T DO/DAP2/BRKIN/BRKOUT
SAK-TC1782F-320F160HR / SAK-TC1782F-320F160HL Pinning

P1.4/ IN20 /EM GST OP/OUT 20 /OUT 76
P3.7/ SLSI01 /OUT 89 /SLSO02 /SLSO12
P1.8/ IN24 /IN48 /M T SR1 B/ OUT 24/OUT 48

P1.9/ IN25 /IN49 /M RST1 B/ OUT 25/OUT 49
P1.10 /IN26 /IN50 /OUT 26 /OUT 50 /SLSO 17
P1.11 /IN27 /IN51 /SCLK 1B/OUT 27 /OUT 51
P4.3/ IN31 /IN55 /OUT 31 /OUT 55 /EXT CLK0

P3.5/ SLSO00 /SLSO10 /SLSO 00&SLSO 10
P3.6/ SLSO01 /SLSO11 /SLSO 01&SLSO 11
P1 .0/IN 16/ OUT 16/OUT 72 /BRKIN/ BRKOUT
SAK_TC 1782-320F133HL
SAK_TC 1782-320F160HL
SAK_TC 1782-320F180HL
SAK_TC 1782-320F133HR
SAK_TC 1782-320F160HR
SAK_TC 1782-320F180HR
This chapter shows the pin configuration of the TC1782 package PG-LQFP-176-10 / PG-
PinningTC1782 Pin Configuration
TC1782
V 1.4.1, 2014-05
Figure 6
Data Sheet
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN7
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AN35
T READY0B/ OUT 94/P5 .14
T VALID0B/SLSO 16/P5 .13
T DAT A0/SLSO 07/ OUT 93/P5 .12
RCLK0B/ OUT 92/P5 .11
RREADY0B/ OUT 91/P5 .10
RVALID0 B/OUT 90 /P5.9
RDAT A0B/OUT 89 /P5 .8
T CLK0/ OUT 95/ P5 .15
SCLK2 /OUT 47 /OUT 15/ IN47 /P5.7
M T SR2 A/ OUT 46/OUT 14 /IN 46/ IN31 /P5.6
M RST2 A/ OUT 45/OUT 13 /IN 45/ IN30 /P5.5
SLSCO24 /OUT 44 /OUT 12 /SLSI2A/IN 44/ IN29 /P5.4
SLSCO 23 /OUT 43 /OUT 11/ IN43 /P5.3
SLSCO 22/ OUT 42/OUT 10 /IN 42/ IN28 /P5.2
SLSCO21 /OUT 41 /OUT 9/IN 41/ IN27 /P5.1
SLSCO20 /OUT 40 /OUT 8/IN 40/ IN26 /P5.0
V SSMF
V DDMF
V DDAF
V DD(SB)
V SS
V DDP
V SS
V DDP
V FAGND
V DD
V FAREF
9
8
7
6
5
4
3
2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
A N 19 45 17 6 P 0.1 5/IN 15/R EQ 5/O U T1 5/S OP 0 C
A N 18 46 17 5 P 0.1 4/IN 14/R EQ 4/O U T1 4/F CLP 0C
A N 17 47 17 4 P 0.7 /IN7 /H W C F G7/R E Q 3/O U T7 /OUT 63
A N 16 48 17 3 P 0.6 /IN6 /H W C F G6/R E Q 2/O U T6 /OUT 62
A N 15 49 17 2 V SS
A N 14 50 17 1 V DDP
V AGND0 51 17 0 V DD(SB)
V AREF 0 52 16 9 P 0.1 3/IN 13/O UT1 3
VSSM 53 16 8 P 0.1 2/IN 12/O UT1 2
V DDM 54 1 67 P 0.5 /IN5 /H W C F G5/O UT5 /OUT 61
A N 13 55 16 6 P 0.4 /IN4 /H W C F G4/O UT4 /OUT 60
A N 12 56 16 5 P 2.1 3/IN 13/O UT3 /S LS I1 1/S DI0
A N 11 57 16 4 P 2.8 /S LS O0 4/S LS O 14/ EN0 0
A N 10 58 16 3 P 2.1 2/IN 12/O UT2 /M TS R 1A / SO P 0B
A N9 59 162 P 2.1 1/IN 11/O UT1 /S C LK 1 A/ FCL P0 B
A N8 60 161 P 2.1 0/IN 10/O UT0 /M R ST 1A
A N6 61 160 P 2.9 /S LS O0 5/S LS O 15/ EN0 1
A N5 62 159 P 6.3 /IN2 5/OU T 7/ OUT 83/ SO P 0A
A N4 63 158 P 6.2 /IN2 4/OU T 6/ OUT 82/ SO N 0
A N3 64 1 57 P 6.1 /IN1 5/OU T 5/ OUT 81/ FC L P0 A
A N2 65 156 P 6.0 /IN1 4/OU T 4/ OUT 80/ FC L N 0
A N1 66 155 V SS
18
A N0 67 154 V DDP
VDD 68 153 V DD
V DDP 69 15 2 P 0.1 1/IN 11/O UT1 1
TC1782
V SS 70 15 1 P 0.1 0/IN 10/O UT1 0
A D0E M U X 2/OU T1 8/IN 1 8/P 1 .14 71 15 0 P 0.9 /IN9 /OU T 9/O UT6 5
A D0E M U X 1/OU T1 7/IN 1 7/P 1 .13 72 14 9 P 0.8 /IN8 /OU T 8/O UT6 4
A D0E M U X 0/OU T1 6/IN 1 6/P 1 .12 73 14 8 P 0.3 /IN3 /H W C F G3/O UT3 /OUT 59
T C LK 0/ OU T 28/ OU T 32/I N32/ P 2.0 74 147 P 0.2 /IN2 /H W C F G2/O UT2 /OUT 58
S LS O 13/ SL S O03 /OU T 33 /TRE A DY 0A /I N33/ P 2.1 75 14 6 P 0.1 /IN1 /H W C F G1/O UT1 /OUT 57 /S DI1
T V A LID 0 A/ OU T 29/ OU T 34/I N34/ P 2.2 76 14 5 P 0.0 /IN0 /H W C F G0/O UT0 /OUT 56
T DA TA 0/ OU T 30/ OU T 35/I N35/ P 2.3 77 14 4 P 3.1 1/O U T9 3/R E Q1
OUT 31 /OUT 36 /RC LK 0A /I N36/ P 2.4 78 14 3 P 3.1 2/O U T9 4/R X D CA N 0 /RX D0B
R R E A DY 0A /O U T3 7/OU T1 10/I N37/ P 2.5 79 14 2 P 3.1 3/O U T9 5/T X D CA N 0/T X D 0
O UT3 8/O U T1 11/ RV AL ID 0A /I N38/ P 2.6 80 14 1 V DDFL 3
OU T 39/ R DA TA 0A /I N39/ P 2.7 81 14 0 V SS
V SS 82 13 9 V DDP
V DDP 83 13 8 P 3.9 /OUT 91 /R X D 1A
VDD 84 137 P 3.1 0/O U T9 2/R E Q0
V SS 85 13 6 P 3.0 /OUT 84 /R X D 0A
OU T 52 /OU T 28 /IN 52 /IN 2 8/R X D CA N 2/ P 4.0 86 13 5 P 3.1 /OUT 85 /TX D0
O UT5 3/O UT2 9/IN 5 3/I N29/ TX D CA N 2/ P 4.1 87 13 4 P 3.1 4/O U T9 6/R X D CA N 1 /RX D1B /S D I2
E X T C LK 1/O UT5 4/O UT3 0/IN 54/I N30/ P 4.2 88 13 3 P 3.1 5/O U T9 7/T X D CA N 1/T X D 1
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
89
90
91
92
93
94
95
96
97
98
99
V SS
V DD
V SS
V SS
V DD
V DD
V DDP
V DDP
V DDP
ESR1
ESR0
T RST
V SSOSC
V DDOSC
XT AL1
XT AL2
PORST
V DDOSC3
T CK/ DAP0
T M S/DAP1
SAK-TC1782N-320F160HR / SAK-TC1782N-320F160HL /
SAK-TC1782N-320F180HR / SAK-TC1782N-320F180HL /
T EST M ODE
P3.2 /OUT 86 /SCLK0
P3.3 /OUT 87 /M RST0
P3.4 /OUT 88 /M T SR0
T DI/BRKIN/BRKOUT
P1 .15 /BRKIN/BRKOUT
P1.2 /IN18 /OUT 18 /OUT 74

P1.3 /IN19 /OUT 19 /OUT 75
P1.5 /IN21 /OUT 21 /OUT 77
P1.6 /IN22 /OUT 22 /OUT 78
P1.7 /IN23 /OUT 23 /OUT 79
P1.1/ IN17 /OUT 17 /OUT 73
P3.8 /SLSO06 /OUT 90 /T XD1
T DO/DAP2/BRKIN/ BRKOUT
P1.4 /IN20 /EM GST OP/ OUT 20/OUT 76
SAK-TC1782N-256F133HR / SAK-TC1782N-256F133HL / Pinning

P3.7 /SLSI01 /OUT 89 /SLSO02 /SLSO 12
P1.8 /IN24 /IN48 /M T SR1 B/OUT 24/ OUT 48

P1.9 /IN25 /IN49 /M RST1 B/OUT 25/ OUT 49
P1.10 /IN26 /IN 50/ OUT 26/ OUT 50/SLSO 17
P1.11 /IN27 /IN 51/ SCLK1B/OUT 27 /OUT 51
P4.3 /IN31 /IN55 /OUT 31 /OUT 55 /EXT CLK0

P3.5 /SLSO00 /SLSO 10/SLSO 00 &SLSO 10
P3.6 /SLSO01 /SLSO 11/SLSO 01 &SLSO 11
P1 .0/ IN16 /OUT 16/ OUT 72/ BRKIN/BRKOUT
SAK_TC1782N-320F133HL
SAK_TC1782N-320F133HR
TC1782
V 1.4.1, 2014-05
TC1782
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20

Package)
Pin Symbol Ctrl. Type Function
Port 0
145 P0.0 I/O0 A1/ Port 0 General Purpose I/O Line 0
IN0 I PU GPTA0 Input 0
IN0 I LTCA2 Input 0
HWCFG0 I Hardware Configuration Input 0
OUT0 O1 GPTA0 Output 0
OUT0 O3 LTCA2 Output 0
IN1 I LTCA2 Input 1
SDI1 I MSC0 Serial Data Input 1
IN2 I LTCA2 Input 2
Data Sheet 19 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
148 P0.3 I/O0 A1+/ Port 0 General Purpose I/O Line 3
IN3 I LTCA2 Input 3
IN4 I LTCA2 Input 4
IN5 I LTCA2 Input 5
IN6 I LTCA2 Input 6
REQ2 I External Request Input 2
Data Sheet 20 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
IN7 I LTCA2 Input 7
IN8 I LTCA2 Input 8
RXDA0 I E-Ray Channel A Receive Data Input 0 1)
IN9 I LTCA2 Input 9
RXDB0 I E-Ray Channel B Receive Data Input 0 1)
TXDA0 O2 E-Ray Channel A transmit Data Output 1)
Data Sheet 21 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
TXDB0 O2 E-Ray Channel B transmit Data Output 1)
TXENA O2 E-Ray Channel A transmit Data Output enable
1)

TXENB O2 E-Ray Channel B transmit Data Output enable
1)

FCLP0C O2 MSC0 Clock Output Positive C
SOP0C O2 MSC0 Serial Data Output Positive C
Port 1
Data Sheet 22 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
BRKIN I Break Input
BRKOUT O Break Output (controlled by OCDS module)
IN19 I LTCA2 Input 19
EMGSTOP I Emergency Stop Input
Data Sheet 23 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
IN48 I GPTA0 Input 48
MTSR1B I SSC1 Slave Receive Input B (Slave Mode)
MTSR1B O3 SSC1 Master Transmit Output B (Master Mode)
Data Sheet 24 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
MRST1B I SSC1 Master Receive Input B (Master Mode)
MRST1B O3 SSC1 Slave Transmit Output B (Slave Mode)
SLSO17 O3 SSC1 Slave Select Output 7
SCLK1B I SSC1 Clock Input B
SCLK1B O3 SSC1 Clock Output B
IN16 I PU LTCA2 Input 16
AD0EMUX0 O1 ADC0 External Multiplexer Control Output 0
Data Sheet 25 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
BRKIN I PU Break Input
Reserved O1 -
Reserved O2 -
Reserved O3 -
BRKOUT O Break Output (controlled by OCDS module)
Port 2
TCLK0 O2 MLI0 Transmitter Clock Output 0
TREADY0A I MLI0 Transmitter Ready Input A
SLSO03 O2 SSC0 Slave Select Output Line 3
SLSO13 O3 SSC1 Slave Select Output Line 3
TVALID0 O2 MLI0 Transmitter Valid Output
Data Sheet 26 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
TDATA0 O2 MLI0 Transmitter Data Output
RCLK0A I MLI Receiver Clock Input A
RREADY0A O2 MLI0 Receiver Ready Output A
RVALID0A I MLI Receiver Valid Input A
RDATA0A I MLI Receiver Data Input A
Reserved O3 -
Data Sheet 27 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
SLSO04 O1 PU SSC0 Slave Select Output 4
EN00 O3 MSC0 Enable Output 0
EN01 O3 MSC0 Enable Output 1
MRST1A I PU SSC1 Master Receive Input A
MRST1A O1 SSC1 Slave Transmit Output
Reserved O3 -
SCLK1A I PU SSC1 Clock Input A
SCLK1A O1 SSC1 Clock Output A
FCLP0B O3 MSC0 Clock Output Positive B
MTSR1A I PU SSC1 Slave Receive Input A
MTSR1A O1 SSC1 Master Transmit Output A
SOP0B O3 MSC0 Serial Data Output Positive B
Data Sheet 28 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
SLSI11 I PU SSC1 Slave Select Input 1
Reserved O2 -
Reserved O3 -
Port 3
RXD0A I PU ASC0 Receiver Input A (Async. & Sync. Mode)
RXD0A O1 ASC0 Output (Sync. Mode)
RXD0A O2 ASC0 Output (Sync. Mode)
TXD0 O1 PU ASC0 Output
TXD0 O2 ASC0 Output
SCLK0 I PU SSC0 Clock Input (Slave Mode)
SCLK0 O1 SSC0 Clock Output (Master Mode)
MRST0 I PU SSC0 Master Receive Input (Master Mode)
MRST0 O1 SSC0 Slave Transmit Output (Slave Mode)
MRST0 O2 SSC0 Slave Transmit Output (Slave Mode)
Data Sheet 29 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
MTSR0 I PU SSC0 Slave Receive Input (Slave Mode)
MTSR0 O1 SSC0 Master Transmit Output (Master Mode)
SLSOANDO0 O3 SSC0 AND SSC1 Slave Select Output 0
SLSOANDO1 O3 SSC0 AND SSC1 Slave Select Output 1
SLSI01 I PU SSC0 Slave Select Input 1
TXD1 O2 ASC1 Transmit Output
RXD1A I PU ASC1 Receiver Input A
RXD1A O1 ASC1 Receiver Output A (Synchronous Mode)
RXD1A O2 ASC1 Receiver Output A (Synchronous Mode)
Data Sheet 30 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
REQ0 I PU External Request Input 0
Reserved O1 -
Reserved O2 -
REQ1 I PU External Request Input 1
Reserved O1 -
Reserved O2 -
RXDCAN0 I PU CAN Node 0 Receiver Input
RXD0B I ASC0 Receiver Input B
RXD0B O1 ASC0 Receiver Output B (Synchronous Mode)
TXDCAN0 O1 PU CAN Node 0 Transmitter Output
RXDCAN1 I PU CAN Node 1 Receiver Input
RXD1B I ASC1 Receiver Input B
Data Sheet 31 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
TXDCAN1 O1 PU CAN Node 1 Transmitter Output
Port 4
RXDCAN2 I CAN Node 2 Receiver Input
Reserved O3 -
TXDCAN2 O3 CAN Node 2 Transmitter Output
EXTCLK1 O3 External Clock 1 Output
EXTCLK0 O3 External Clock 0 Output
Data Sheet 32 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
Port 5
Data Sheet 33 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
SLSI2A I SSC2 Slave Select Input A
MRST2A I SSC2 Master Receive Input (Master Mode)
MRST2 O3 SSC2 Master Transmit Input (Slave Mode)
MTSR2A I SSC2 Slave Receive Input (Slave Mode)
SCLK2A I SSC2 Clock Input (Slave Mode)
Data Sheet 34 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
RDATA0B I PU MLI0 Receiver Data Input B
Reserved O1 -
TXDA1 O2 E-Ray Channel A transmit Data Output 1)
RVALID0B I PU MLI0 Receiver Data Valid Input B
Reserved O1 -
TXDB1 O2 E-Ray Channel B transmit Data Output 1)
RREADY0B O1 PU MLI0 Receiver Ready Input B
TXENA O2 E-Ray Channel A transmit Data Output enable
1)

RCLK0B I PU MLI0 Receiver Clock Input B
Reserved O1 -
TXENB O2 E-Ray Channel B transmit Data Output enable
1)

TDATA0 O1 PU MLI0 Transmitter Data Output
TVALID0B O1 PU MLI0 Transmitter Valid Input B
Reserved O3 -
Data Sheet 35 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
TREADY0B I PU MLI0 Transmitter Ready Input B
RXDA1 I E-Ray Channel A Receive Data Input 1 1)
Reserved O1 -
Reserved O2 -
RXDB1 I PU E-Ray Channel B Receive Data Input 1 1)
TCLK0 O1 MLI0 Transmitter Clock Output
Reserved O2 -
Port 6
IN14 I F/ LTCA2 Input 14
PU
FCLN0 O1 MSC0 Clock Output Negative
PU
FCLP0A O1 MSC0 Clock Output Positive A
PU
SON0 O1 MSC0 Serial Data Output Negative
Data Sheet 36 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
PU
SOP0A O1 MSC0 Serial Data Output Positive A
Analog Input Port
67 AN0 I D ADC0 Analog Input Channel 0
Data Sheet 37 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
35 AN28 I D ADC1 / FADC Analog Input Channel 28
31 AN32 I D FADC Analog Input P Channel 0
30 AN33 I D FADC Analog Input N Channel 0
29 AN34 I D FADC Analog Input P Channel 1
28 AN35 I D FADC Analog Input N Channel 1
54 VDDM - - ADC Analog Part Power Supply (3.3V - 5V)
53 VSSM - - ADC Analog Part Ground
52 VAREF0 - - ADC0 and ADC1 Reference Voltage
51 VAGND0 - - ADC Reference Ground
24 VDDMF - - FADC Analog Part Power Supply (3.3V)
23 VDDAF - - FADC Analog Part Logic Power Supply (1.3V)
25 VSSMF - - FADC Analog Part Ground
VSSAF - - FADC Analog Part Ground
26 VFAREF - - FADC Reference Voltage
27 VFAGND - - FADC Reference Ground
10, VDD - - Digital Core Power Supply (1.3V)
212),
68,
84,
91,
99,
123,
153,
170
2)
Data Sheet 38 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
11, VDDP - - Port Power Supply (3.3V)
20,
69,
83,
89,
100,
124,
139,
154,
171
12, VSS - - Digital Ground
22,
70,
82,
85,
92,
101,
125,
140,
155,
172
105 VDDOSC - - Main Oscillator and PLL Power Supply (1.3V)
106 VDDOSC3 - - Main Oscillator Power Supply (3.3V)
104 VSSOSC - - Main Oscillator and PLL Ground
141 VDDFL3 - - Power Supply for Flash (3.3V)
102 XTAL1 I Main Oscillator Input
103 XTAL2 O Main Oscillator Output
111 TDI I A2/ JTAG Serial Data Input
BRKIN I PU OCDS Break Input Line
BRKOUT O OCDS Break Output Line
112 TMS I A2/ JTAG State Machine Control Input
DAP1 I/O PD Device Access Port Line 1
Data Sheet 39 V 1.4.1, 2014-05

TC1782

Package) (cont’d)
113 TDO I/O A2/ JTAG Serial Data Output
DAP2 I/O PU Device Access Port Line 2
BRKIN I OCDS Break Input Line
BRKOUT O OCDS Break Output Line
114 TRST I I/ JTAG Reset Input
PD
115 TCK I A1/ JTAG Clock Input
DAP0 I PD Device Access Port Line 0
118 TESTMODE I I/ Test Mode Select Input
PU
120 ESR1 I/O A2/ External System Request Reset Input 1
PD
121 PORST I I/ Power On Reset Input
PD
122 ESR0 I/O A2 External System Request Reset Input 0
Default configuration during and after reset is
open-drain driver. The driver drives low during
power-on reset.
1) Only available for SAK-TC1782F-320F180HR, SAK-TC1782F-320F180HL, and SAK-TC1782F-320F160HR.
2) For the emulation device (ED), this pin is bonded to VDDSB (ED Stand By RAM supply). In the production
devide device, this pin is bonded to a VDD pad.
Legend for Table 2

Column “Ctrl.”:
I = Input (for GPIO port lines with IOCR bit field selection PCx = 0XXXB)
O = Output
O0 = Output with IOCR bit field selection PCx = 1X00B
O1 = Output with IOCR bit field selection PCx = 1X01B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X10B(ALT2)
O3 = Output with IOCR bit field selection PCx = 1X11(ALT3)
Column “Type”:
A1 = Pad class A1 (LVTTL)
A1+ = Pad class A1+ (LVTTL)
A2 = Pad class A2 (LVTTL)
Data Sheet 40 V 1.4.1, 2014-05

TC1782
F = Pad class F (LVDS/CMOS)

D = Pad class D (ADC)
I = Pad class I (LVTTL)
PU = with pull-up device connected during reset (PORST = 0)
PD = with pull-down device connected during reset (PORST = 0)
TR = tri-state during reset (PORST = 0)
Data Sheet 41 V 1.4.1, 2014-05

TC1782
Identification Registers
4 Identification Registers
The Identification Registers uniquely identify the whole device.
Table 3 SAK-TC1782F-320F180HR Identification Registers

Short Name Value Address Stepping
CBS_JDPID 0000 6350H F000 0408H BA
CBS_JTAGID 1018 E083H F000 0464H BA
SCU_CHIPID 8500 9310H F000 0640H BA
SCU_MANID 0000 1820H F000 0644H BA
SCU_RTID 0000 0000H F000 0648H BA
Table 4 SAK-TC1782F-320F180HL Identification Registers

CBS_JDPID 0000 6350H F000 0408H BA
SCU_MANID 0000 1820H F000 0644H BA
SCU_RTID 0000 0000H F000 0648H BA
Table 5 SAK-TC1782N-320F180HR Identification Registers

CBS_JDPID 0000 6350H F000 0408H BA
SCU_MANID 0000 1820H F000 0644H BA
SCU_RTID 0000 0000H F000 0648H BA
Table 6 SAK-TC1782N-320F180HL Identification Registers

CBS_JDPID 0000 6350H F000 0408H BA
Data Sheet 42 V 1.4.1, 2014-05

TC1782
Table 6 SAK-TC1782N-320F180HL Identification Registers (cont’d)

SCU_MANID 0000 1820H F000 0644H BA
SCU_RTID 0000 0000H F000 0648H BA

CBS_JDPID 0000 6350H F000 0408H BA
SCU_MANID 0000 1820H F000 0644H BA
SCU_RTID 0000 0000H F000 0648H BA

CBS_JDPID 0000 6350H F000 0408H BA
SCU_MANID 0000 1820H F000 0644H BA
SCU_RTID 0000 0000H F000 0648H BA
Table 9 SAK-TC1782F-320F160HR Identification Registers

CBS_JDPID 0000 6350H F000 0408H BA
SCU_CHIPID A500 9310H F000 0640H BA
SCU_MANID 0000 1820H F000 0644H BA
SCU_RTID 0000 0000H F000 0648H BA
Data Sheet 43 V 1.4.1, 2014-05

TC1782
Table 10 SAK-TC1782F-320F160HL Identification Registers

CBS_JDPID 0000 6350H F000 0408H BA
SCU_MANID 0000 1820H F000 0644H BA
SCU_RTID 0000 0000H F000 0648H BA

CBS_JDPID 0000 6350H F000 0408H BA
SCU_CHIPID A500 9410H F000 0640H BA
SCU_MANID 0000 1820H F000 0644H BA
SCU_RTID 0000 0000H F000 0648H BA

CBS_JDPID 0000 6350H F000 0408H BA
SCU_MANID 0000 1820H F000 0644H BA
SCU_RTID 0000 0000H F000 0648H BA
Data Sheet 44 V 1.4.1, 2014-05

TC1782
Electrical ParametersGeneral Parameters
5 Electrical Parameters
This specification provides all electrical parameters of the TC1782.
5.1 General Parameters
5.1.1 Parameter Interpretation

The parameters listed in this section partly represent the characteristics of the TC1782
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are marked with an two-letter abbreviation in
column “Symbol”:
• CC
Such parameters indicate Controller Characteristics which are a distinctive feature of
the TC1782 and must be regarded for a system design.
• SR
Such parameters indicate System Requirements which must provided by the
microcontroller system in which the TC1782 designed in.
Data Sheet 45 V 1.4.1, 2014-05

TC1782
5.1.2 Pad Driver and Pad Classes Summary

This section gives an overview on the different pad driver classes and its basic
characteristics. More details (mainly DC parameters) are defined in the Section 5.2.1.
Table 13 Pad Driver and Pad Classes Overview

Class Power Type Sub Class Speed Load Leakage Termination
Supply Grade 1) 150oC 1)
1)
A 3.3 V LVTTL A1 6 MHz 100 pF 500 nA No

I/O, (e.g. GPIO)
LVTTL A1+ 25 50 pF 1 μA Series
outputs (e.g. serial MHz termination
I/Os) recommended
A2 40 50 pF 3 μA Series
(e.g. serial MHz termination
I/Os) recommended
F 3.3 V LVDS – 50 – – Parallel
MHz termination,
100 Ω ± 10% 2)
CMOS – 6 MHz 50 pF –
DE 5V ADC – – – –
I 3.3 V LVTTL – – – –
(input
only)
1) These values show typical application configurations for the pad. Complete and detailed pad parameters are
available in the individual pad parameter table on the following pages.
2) In applications where the LVDS pins are not used (disabled), these pins must be either left unconnected, or
properly terminated with the differential parallel termination of 100 Ω ± 10%.
Data Sheet 46 V 1.4.1, 2014-05

TC1782
5.1.3 Absolute Maximum Ratings

Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 14 Absolute Maximum Rating Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Con
dition
Storage temperature TST SR -65 – 150 °C
Voltage at 1.3 V power supply VDD SR – – 2.0 V
pins with respect to VSS
Voltage at 3.3 V power supply VDDP – – 4.33 V
pins with respect to VSS SR
Voltage at 5 V power supply VDDM SR – – 7.0 V
pins with respect to VSS
Voltage on any Class A input VIN SR -0.6 – VDDP + 0.7 V Whatever
pin and dedicated input pins or max. 4.33 is lower
with respect to VSS
Voltage on any Class D VAIN -0.6 – 7.0 V
analog input pin with respect VAREF0
to VAGND0 SR
Voltage on any shared Class VAINF -0.6 – 7.0 V
D analog input pin with SR
respect to VSSAF, if the FADC
is switched through to the pin.
Input current on any pin IIN -10 – +10 mA
during overload condition
Absolute maximum sum of all IIN -25 – +25 mA
input circuit currents for one
port group during overload
condition1)
Absolute maximum sum of all ΣIIN – – |200| mA
input circuit currents during
overload condition
1) The port groups are defined in Table 19.
Data Sheet 47 V 1.4.1, 2014-05

TC1782
5.1.4 Pin Reliability in Overload

When receiving signals from higher voltage devices, low-voltage devices experience
overload currents and voltages that go beyond their own IO power supplies specification.
Table 15 defines overload conditions that will not cause any negative reliability impact if
all the following conditions are met:
• full operation life-time (24000 h) is not exceeded
• Operating Conditions are met for
– pad supply levels (VDDP or VDDM)
– temperature
If a pin current is out of the Operating Conditions but within the overload parameters,
then the parameters functionality of this pin as stated in the Operating Conditions can no
longer be guaranteed. Operation is still possible in most cases but with relaxed
parameters.
Note: An overload condition on one or more pins does not require a reset.
Table 15 Overload Parameters

Min. Typ. Max. Test Con
dition
Input current on any digital pin IIN -5 – +5 mA
during overload condition
except LVDS pins
Input current on LVDS pins IINLVDS -3 – +3 mA
Absolute sum of all input IING -20 – +20 mA
circuit currents for one port
group during overload
condition1)
Input current on analog pins IINANA -3 – +3 mA
Absolute sum of all analog IINSAS -15 – +15 mA
input currents for analog
inputs of a single ADC during
overload condition
Absolute sum of all input ΣIINS -100 – 100 mA
circuit currents during
overload condition
1) The port groups are defined in Table 19.
Note: FADC input pins count as analog pin as they are overlayed with an ADC pins.
Data Sheet 48 V 1.4.1, 2014-05

TC1782
Table 16 PN-Junction Characterisitics for positive Overload

Pad Type IIN = 3 mA IIN = 5 mA
A1 / A1+ / F UIN = VDDP + 0.6 V UIN = VDDP + 0.7 V
A2 UIN = VDDP + 0.5 V UIN = VDDP + 0.6 V
LVDS UIN = VDDP + 0.7 V -
D UIN = VDDM + 0.6 V -
Table 17 PN-Junction Characterisitics for negative Overload

Pad Type IIN = -3 mA IIN = -5 mA
A1 / A1+ / F UIN = VSS - 0.6 V UIN = VSS - 0.7 V
A2 UIN = VSS - 0.5 V UIN = VSS - 0.6 V
LVDS UIN = VSS - 0.7 V -
D UIN = VSSM - 0.6 V -
Note: A series resistor at the pin to limit the current to the maximum permitted overload
current is sufficient to handle failure situations like short to battery without having
any negative reliability impact on the operational life-time.
Data Sheet 49 V 1.4.1, 2014-05

TC1782
5.1.5 Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the TC1782.
Digital supply voltages applied to the TC1782 must be static regulated voltages which
allow a typical voltage swing of ± 5 %.
All parameters specified in the following tables refer to these operating conditions
(Table 18), unless otherwise noticed in the Note / Test Condition column.
The Voltage Operating Timing Profiles did not increase area of validity of the
parameters defined in table 8 and later.
Table 18 Operating Conditions Parameters

Min. Typ. Max. Test Condition
Overload coupling KOVAN − − 0.000 IOV≤ 0 mA; IOV≥ -

factor for analog inputs, CC 1 2 mA; analog
negative pad= 5.0 V
Overload coupling KOVAP − − 0.000 IOV≤ 3 mA;
factor for analog inputs, CC 01 IOV≥ 0 mA; analog
positive pad= 5.0 V
CPU Frequency fCPU SR − − 133 MHz SAK-TC1782N-
256F133HR / SAK-
TC1782N-
256F133HL
− − 180 MHz SAK-TC1782F-
320F180HR / SAK-
TC1782F-
320F180HL / SAK-
TC1782N-
320F180HR / SAK-
TC1782N-
320F180HL
− − 160 MHz SAK-TC1782F-
320F160HR / SAK-
TC1782F-
320F160HL / SAK-
TC1782N-
320F160HR / SAK-
TC1782N-
320F160HL
Data Sheet 50 V 1.4.1, 2014-05

TC1782
Table 18 Operating Conditions Parameters (cont’d)

FPI bus frequency fFPI SR − − 90 MHz SAK-TC1782F-
320F180HR / SAK-
TC1782F-
320F180HL / SAK-
TC1782N-
320F180HR / SAK-
TC1782N-
320F180HL / SAK-
TC1782F-
256F133HR / SAK-
TC1782F-
256F133HL / SAK-
TC1782N-
256F133HR / SAK-
TC1782N-
256F133HL
− − 80 MHz SAK-TC1782F-
320F160HR / SAK-
TC1782F-
320F160HL / SAK-
TC1782N-
320F160HR / SAK-
TC1782N-
320F160HL
Data Sheet 51 V 1.4.1, 2014-05

TC1782

LMB frequency fLMB CC − − 133 MHz SAK-TC1782N-
256F133HR / SAK-
TC1782N-
256F133HL
− − 180 MHz SAK-TC1782F-
320F180HR / SAK-
TC1782F-
320F180HL / SAK-
TC1782N-
320F180HR / SAK-
TC1782N-
320F180HL
− − 160 MHz SAK-TC1782F-
320F160HR / SAK-
TC1782F-
320F160HL / SAK-
TC1782N-
320F160HR / SAK-
TC1782N-
320F160HL
Data Sheet 52 V 1.4.1, 2014-05

TC1782

PCP Frequency fPCP SR − − 133 MHz SAK-TC1782N-

256F133HR / SAK-
TC1782N-
256F133HL
− − 180 MHz SAK-TC1782F-
320F180HR / SAK-
TC1782F-
320F180HL / SAK-
TC1782N-
320F180HR / SAK-
TC1782N-
320F180HL
− − 160 MHz SAK-TC1782F-
320F160HR / SAK-
TC1782F-
320F160HL / SAK-
TC1782N-
320F160HR / SAK-
TC1782N-
320F160HL
Inactive device pin IID SR -1 − 1 mA All power supply
current voltagesVDDx = 0
Short circuit current of ISC SR -5 − 5 mA
digital outputs1)
Absolute sum of short ΣISC_D − − 100 mA
circuit currents of the CC
device
Absolute sum of short ΣISC_PG − − 20 mA
circuit currents per pin CC
group
Ambient Temperature TA SR -40 − 125 °C
Junction temperature TJ SR -40 − 150 °C
Data Sheet 53 V 1.4.1, 2014-05

TC1782

Core Supply Voltage VDD SR 1.235 1.3 1.365 V SAK-TC1782F-

2)
320F180HR / SAK-
TC1782F-
320F180HL / SAK-
TC1782N-
320F180HR / SAK-
TC1782N-
320F180HL / SAK-
TC1782N-
256F133HR / SAK-
TC1782N-
256F133HL; for
duration limitation
see Voltage
Operating Timing
Profiles
1.17 1.3 1.432) V SAK-TC1782F-
320F160HR / SAK-
TC1782F-
320F160HL / SAK-
TC1782N-
320F160HR / SAK-
TC1782N-
320F160HL; for
duration limitation
see Voltage
Operating Timing
Profiles
Flash supply voltage VDDFL3 2.97 3.3 3.634) V for duration
3.3V SR limitation see
Voltage Operating
Timing Profiles
ADC analog supply VDDM 2.97 3.3 5.53) V
voltage SR
Data Sheet 54 V 1.4.1, 2014-05

TC1782

Oscillator core supply VDDOSC 1.235 1.3 1.3652 V SAK-TC1782F-
)
voltage SR 320F180HR / SAK-
TC1782F-
320F180HL / SAK-
TC1782N-
320F180HR / SAK-
TC1782N-
320F180HL / SAK-
TC1782N-
256F133HR / SAK-
TC1782N-
256F133HL; for
duration limitation
see Voltage
Operating Timing
Profiles
1.17 1.3 1.432) V SAK-TC1782F-
320F160HR / SAK-
TC1782F-
320F160HL / SAK-
TC1782N-
320F160HR / SAK-
TC1782N-
320F160HL; for
duration limitation
see Voltage
Operating Timing
Profiles
Oscillator 3.3V supply VDDOSC3 2.97 3.3 3.634) V for duration
voltage SR limitation see
Voltage Operating
Timing Profiles
Digital supply voltage VDDP SR 2.97 3.3 3.63 4) V for duration
for IO pads limitation see
Voltage Operating
Timing Profiles
Data Sheet 55 V 1.4.1, 2014-05

TC1782

VDDP voltage to ensure VDDPPA 0.65 − − V
defined pad states5) CC
Digital ground voltage VSS SR 0 − − V
Analog ground voltage VSSM SR -0.1 0 0.1 V
for VDDM
Analog core supply VDDAF 1.235 1.3 1.3652 V SAK-TC1782F-
)
SR 320F180HR / SAK-
TC1782F-
320F180HL / SAK-
TC1782N-
320F180HR / SAK-
TC1782N-
320F180HL / SAK-
TC1782N-
256F133HR / SAK-
TC1782N-
256F133HL; for
duration limitation
see Voltage
Operating Timing
Profiles
1.17 1.3 1.432) V SAK-TC1782F-
320F160HR / SAK-
TC1782F-
320F160HL / SAK-
TC1782N-
320F160HR / SAK-
TC1782N-
320F160HL; for
duration limitation
see Voltage
Operating Timing
Profiles
Data Sheet 56 V 1.4.1, 2014-05

TC1782

FADC / ADC analog VDDMF 2.97 3.3 3.634) V for duration
supply voltage SR limitation see
Voltage Operating
Timing Profiles
Analog ground voltage VSSAF -0.1 0 0.1 V
for VDDMF SR
1) Applicable for digital outputs.
2) Voltage overshoot to 1.7V is permissible at Power-Up and PORST low, provided the pulse duration is less than
100 μs and the cumulated sum of the pulses does not exceed 1 h.
5) This parameter is valid under the assumption the PORST signal is constantly at low level during the power-
up/power-down of VDDP.
Voltage Operating Timing Profiles

• 1.3V < VDD / VDDOSC / VDDAF < 1.3V + 5%:
– limited to Operation Lifetime (tOP) (see Table 46)
• 1.3V + 5% < VDD / VDDOSC / VDDAF < 1.3V + 7.5% (overvoltage condition):
– limited to 10000 hour duration cumulative in lifetime, due to the reliability reduction
of the chip caused by the overvoltage stress.
• 1.3V + 7.5% < VDD / VDDOSC / VDDAF < 1.3V + 10% (overvoltage condition):
– limited to 1000 hour duration cumulative in lifetime, due to the reliability reduction
• 3.3V < VDDP / VDDOSC3 / VDDFL3 / VDDMF < 3.3V + 5%:
• VDDP / VDDOSC3 / VDDFL3 / VDDMF< 3.3 V + 10%
– 3.3V + 5% < VDDP / VDDOSC3 / VDDFL3 / VDDMF< 3.3V + 10%
(overvoltage condition):
limited to 1000 hour duration cumulative in lifetime, due to the reliability reduction
• 5V < VDDM < 5V + 10%:
Data Sheet 57 V 1.4.1, 2014-05

TC1782
Table 19 Pin Groups for Overload / Short-Circuit Current Sum Parameter

Group Pins
1 P5.[7:2], P5.15
2 P5.[9:8]
3 P5.[11:10]
4 P5.[14:12]
5 P1.[14:12], P2.0
6 P2.[4:1]
7 P2.[7:5]
8 P4.[2:0]
9 P4.3
10 P1.2, P1.8
11 P1.[10:9]
12 P1.3, P1.11
13 P1.[7:4]
14 P1.[1:0], P1.15
15 P3.[8:5], P3.[3:2]
16 P3.[1:0], P3.4, P3.[10:9], P3.[15:14]
17 P0.[1:0], P3.[13:11]
18 P0.[3:2], P0.[9:8]
19 P0.[11:10]
20 P6.[3:0]
21 P2.[13:8]
22 P0.[5:4], P0.[13:12]
23 P0.[7:6], P0.[15:14], P5.[1:0]
Data Sheet 58 V 1.4.1, 2014-05

TC1782
Electrical ParametersDC Parameters
5.2 DC Parameters
5.2.1 Input/Output Pins
Table 20 Standard_Pads Parameters

Pin capacitance (digital CIO CC − − 10 pF TA= 25 °C;

inputs/outputs) f= 1 MHz
Pull-down current |IPDL| − − 150 μA Vi≥ 0.6 x VDDP V
CC 10 − − μA Vi≥ 0.36 x
VDDP V
Pull-Up current |IPUH| 10 − − μA Vi≤ 0.6 x VDDP V
CC − − 100 μA Vi≤ 0.36 x
VDDP V
Spike filter always blocked tSF1 CC − − 10 ns only PORST pin
pulse duration
Spike filter pass-through tSF2 CC 100 − − ns only PORST pin
pulse duration
Table 21 Standard_Pads Class_A1

Input Hysteresis for A1 HYSA1 0.1 x − − V

pads 1) CC VDDP
Input Leakage Current IOZA1 -500 − 500 nA Vi≥ 0 V;
Class A1 CC Vi≤ VDDP V
Ratio Vil/Vih, A1 pads VILA1 / 0.6 − −
VIHA1
CC
On-Resistance of the RDSONW − 450 600 Ohm IOH< -0.5 mA;
class A1 pad, weak driver CC P_MOS
− 210 340 Ohm IOL< 0.5 mA;
N_MOS
Data Sheet 59 V 1.4.1, 2014-05

TC1782
Table 21 Standard_Pads Class_A1 (cont’d)

On-Resistance of the RDSONM − − 155 Ohm IOH< -2 mA;
class A1 pad, medium CC P_MOS
driver − − 110 Ohm IOL< 2 mA;
N_MOS
Fall time, pad type A1 tFA1 CC − − 150 ns CL= 20 pF; pin
out
driver= weak
− − 50 ns CL= 50 pF; pin
out
driver= medium
− − 140 ns CL= 150 pF; pin
out
driver= medium
− − 550 ns CL= 150 pF; pin
out
driver= weak
− − 18000 ns CL= 20000 pF;
pin out
driver= medium
− − 65000 ns CL= 20000 pF;
pin out
driver= weak
Data Sheet 60 V 1.4.1, 2014-05

TC1782

Rise time, pad type A1 tRA1 CC − − 150 ns CL= 20 pF; pin
out
driver= weak
− − 50 ns CL= 50 pF; pin
out
driver= medium
− − 140 ns CL= 150 pF; pin
out
driver= medium
− − 550 ns CL= 150 pF; pin
out
driver= weak
− − 18000 ns CL= 20000 pF;
pin out
driver= medium
− − 65000 ns CL= 20000 pF;
pin out
driver= weak
Input high voltage class VIHA1 0.6 x − min(V V
A1 pads SR VDDP DDP+
0.3,3.6
)
Input low voltage class A1 VILA1 SR -0.3 − 0.36 x V
pads VDDP
Data Sheet 61 V 1.4.1, 2014-05

TC1782

Output voltage high class VOHA1 VDDP - − − V IOH≥ -1.4 mA;
A1 pads CC 0.4 pin out
driver= medium
2.4 − − V IOH≥ -2 mA; pin
out
driver= medium
VDDP - − − V IOH≥ -400 μA;
0.4 pin out
driver= weak
2.4 − − V IOH≥ -500 μA;
pin out
driver= weak
Output voltage low class VOLA1 − − 0.4 V IOL≤ 2 mA; pin
A1 pads CC out
driver= medium
− − 0.4 V IOL≤ 500 μA;
pin out
driver= weak
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Table 22 Standard_Pads Class_A1+

Input Hysteresis for A1+ HYSA1 0.1 x − − V

pads 1) + CC VDDP
Input Leakage Current IOZA1+ -1000 − 1000 nA
Class A1+ CC
class A1+ pad, weak CC P_MOS
driver − 210 340 Ohm IOL< 0.5 mA;
N_MOS
Data Sheet 62 V 1.4.1, 2014-05

TC1782
Table 22 Standard_Pads Class_A1+ (cont’d)

class A1+ pad, medium CC P_MOS
N_MOS
On-Resistance of the RDSON1+ − − 100 Ohm IOH< -2 mA;
class A1+ pad, strong CC P_MOS
N_MOS
Fall time, pad type A1+ tFA1+ CC − − 150 ns CL= 20 pF; pin
out
driver= weak
− − 28 ns CL= 50 pF;
edge= slow ;
pin out
driver= strong
− − 16 ns CL= 50 pF;
edge= soft ; pin
out
driver= strong
− − 50 ns CL= 50 pF; pin
out
driver= medium
− − 140 ns CL= 150 pF; pin
out
driver= medium
− − 550 ns CL= 150 pF; pin
out
driver= weak
− − 18000 ns CL= 20000 pF;
pin out
driver= medium
− − 65000 ns CL= 20000 pF;
pin out
driver= weak
Data Sheet 63 V 1.4.1, 2014-05

TC1782

Rise time, pad type A1+ tRA1+ CC − − 150 ns CL= 20 pF; pin
out
driver= weak
− − 28 ns CL= 50 pF;
edge= slow ;
pin out
driver= strong
− − 16 ns CL= 50 pF;
edge= soft ; pin
out
driver= strong
− − 50 ns CL= 50 pF; pin
out
driver= medium
− − 140 ns CL= 150 pF; pin
out
driver= medium
− − 550 ns CL= 150 pF; pin
out
driver= weak
− − 18000 ns CL= 20000 pF;
pin out
driver= medium
− − 65000 ns CL= 20000 pF;
pin out
driver= weak
Input high voltage, Class VIHA1+ 0.6 x − min(V V
A1+ pads SR VDDP DDP+
0.3,3.6
)
Input low voltage Class VILA1+ -0.3 − 0.36 x V
A1+ pads SR VDDP
Ratio Vil/Vih, A1+ pads VILA1+ / 0.6 − −
VIHA1+
CC
Data Sheet 64 V 1.4.1, 2014-05

TC1782

Output voltage high class VOHA1+ VDDP - − − V IOH≥ -1.4 mA;
A1+ pads CC 0.4 pin out
driver= medium
VDDP - − − V IOH≥ -1.4 mA;
0.4 pin out
driver= strong
2.4 − − V IOH≥ -2 mA; pin
out
driver= medium
2.4 − − V IOH≥ -2 mA; pin
out
driver= strong
VDDP - − − V IOH≥ -400 μA;
0.4 pin out
driver= weak
2.4 − − V IOH≥ -500 μA;
pin out
driver= weak
Output voltage low class VOLA1+ − − 0.4 V IOL≤ 2 mA; pin
A1+ pads CC out
driver= medium
− − 0.4 V IOL≤ 2 mA; pin
out
driver= strong
− − 0.4 V IOL≤ 500 μA;
pin out
driver= weak
Data Sheet 65 V 1.4.1, 2014-05

TC1782
Table 23 Standard_Pads Class_A2

Input Hysteresis for A2 HYSA2 0.1 x − − V

pads 1) CC VDDP
Input Leakage current IOZA2 -6000 − 6000 nA Vi< VDDP / 2 -
Class A2 CC 1 V; Vi> VDDP / 2
+ 1 V; Vi≥ 0 V;
Vi≤ VDDP V
-3000 − 3000 nA Vi> VDDP / 2 -
1 V; Vi< VDDP / 2
+1V
Ratio Vil/Vih, A2 pads VILA2 / 0.6 − −
VIHA2
CC
class A2 pad, weak driver CC P_MOS
− 210 340 Ohm IOL< 0.5 mA;
N_MOS
class A2 pad, medium CC P_MOS
N_MOS
On-Resistance of the RDSON2 − − 28 Ohm IOH< -2 mA;
class A2 pad, strong driver CC P_MOS
− − 22 Ohm IOL< 2 mA;
N_MOS
Data Sheet 66 V 1.4.1, 2014-05

TC1782

Fall time, pad type A2 tFA2 CC − − 150 ns CL= 20 pF; pin
out
driver= weak
− − 7 ns CL= 50 pF;
edge= medium
; pin out
driver= strong
− − 10 ns CL= 50 pF;
edge= medium-
minus ; pin out
driver= strong
− − 3.7 ns CL= 50 pF;
edge= sharp ;
pin out
driver= strong
− − 5 ns CL= 50 pF;
edge= sharp-
minus ; pin out
driver= strong
− − 16 ns CL= 50 pF;
edge= soft ; pin
out
driver= strong
− − 50 ns CL= 50 pF; pin
out
driver= medium
− − 7.5 ns CL= 100 pF;
edge= sharp ;
pin out
driver= strong
− − 140 ns CL= 150 pF; pin
out
driver= medium
Data Sheet 67 V 1.4.1, 2014-05

TC1782

− − 550 ns CL= 150 pF; pin
out
driver= weak
− − 18000 ns CL= 20000 pF;
pin out
driver= medium
− − 65000 ns CL= 20000 pF;
pin out
driver= weak
Data Sheet 68 V 1.4.1, 2014-05

TC1782

Rise time, pad type A2 tRA2 CC − − 150 ns CL= 20 pF; pin
out
driver= weak
− − 7.0 ns CL= 50 pF;
edge= medium
; pin out
driver= strong
− − 10 ns CL= 50 pF;
edge= medium-
minus ; pin out
driver= strong
− − 3.7 ns CL= 50 pF;
edge= sharp ;
pin out
driver= strong
− − 5 ns CL= 50 pF;
edge= sharp-
minus ; pin out
driver= strong
− − 16 ns CL= 50 pF;
edge= soft ; pin
out
driver= strong
− − 50 ns CL= 50 pF; pin
out
driver= medium
− − 7.5 ns CL= 100 pF;
edge= sharp ;
pin out
driver= strong
− − 140 ns CL= 150 pF; pin
out
driver= medium
Data Sheet 69 V 1.4.1, 2014-05

TC1782

− − 550 ns CL= 150 pF; pin

out
driver= weak
− − 18000 ns CL= 20000 pF;
pin out
driver= medium
− − 65000 ns CL= 20000 pF;
pin out
driver= weak
Input high voltage, class VIHA2 0.6 x − min(V V
A2 pads SR VDDP DDP +
0.3,
3.6)
Input low voltage Class A2 VILA2 SR -0.3 − 0.36 x V
pads VDDP
Output voltage high class VOHA2 VDDP - − − V IOH≥ -1.4 mA;
A2 pads CC 0.4 pin out
driver= medium
VDDP - − − V IOH≥ -1.4 mA;
0.4 pin out
driver= strong
2.4 − − V IOH≥ -2 mA; pin
out
driver= medium
2.4 − − V IOH≥ -2 mA; pin
out
driver= strong
VDDP - − − V IOH≥ -400 μA;
0.4 pin out
driver= weak
2.4 − − V IOH≥ -500 μA;
pin out
driver= weak
Data Sheet 70 V 1.4.1, 2014-05

TC1782

Output voltage low class VOLA2 − − 0.4 V IOL≤ 2 mA; pin
A2 pads CC out
driver= medium
− − 0.4 V IOL≤ 2 mA; pin
out
driver= strong
− − 0.4 V IOL≤ 500 μA;
pin out
driver= weak
Table 24 Standard_Pads Class_F

Input Hysteresis F1) HYSF 0.05 x − − V

CC VDDP
Input Leakage Current IOZF CC -6000 − 6000 nA Vi< VDDP / 2 -
Class F 1 V; Vi> VDDP / 2
+ 1 V; Vi≥ 0 V;
Vi≤ VDDP V
-3000 − 3000 nA Vi> VDDP / 2 -
1 V; Vi< VDDP / 2
+1V
Ratio Vil/ Vih, F pads VILF / 0.6 − −
VIHF CC
class F pad, medium CC P_MOS
driver − − 175 Ohm IOH< -2 mA;
P_MOS;
VDDP≥±5% * VD
DP
− − 145 Ohm IOL< 2 mA;

N_MOS
Data Sheet 71 V 1.4.1, 2014-05

TC1782
Table 24 Standard_Pads Class_F (cont’d)

Fall time, pad type F, tFF CC − − 60 ns CL= 50 pF
CMOS mode
Rise time, pad type F, tRF CC − − 60 ns CL= 50 pF
CMOS mode
Input high voltage, pad VIHF SR 0.6 x − min(V V
class F, CMOS mode VDDP DDP+
0.3,
3.6)
Input low voltage, Class F VILF SR -0.3 − 0.36 x V
pads, CMOS mode VDDP
Output high voltage, class VOHF VDDP- − − V IOH≥ -1.4 mA
F pads, CMOS mode CC 0.4
2.4 − − V IOH≥ -2 mA
Output low voltage, class VOLF CC − − 0.4 V IOL≤ 2 mA
F pads, CMOS mode
Table 25 Standard_Pads Class_I

Input Hysteresis Class I1) HYSI 0.1 x − − V

CC VDDP
Input Leakage Current IOZI CC -1000 − 1000 nA
Ratio between low and VILI / VIHI 0.6 − −
high input threshold CC
Input high voltage, class I VIHI SR 0.6 x − min(V V
pins VDDP DDP+
0.3,
3.6)
Input low voltage, Class I VILI SR -0.3 − 0.36 x V
pads VDDP
Data Sheet 72 V 1.4.1, 2014-05

TC1782
Table 26 LVDS_Pads Parameters

Output impedance, pad RO CC 40 − 140 Ohm

class F, LVDS mode
Fall time, pad type LVDS tFL CC − − 2 ns termination
100 Ω ± 1 %
Rise time, pad type LVDS tRL CC − − 2 ns termination
100 Ω ± 1 %
Pad set-up time tSET_LVD − − 13 μs termination
S CC 100 Ω ± 1 %
Output Differential Voltage VOD CC 150 − 400 mV termination
100 Ω ± 1 %
Output voltage high, pad VOH CC − − 1525 mV termination
class F, LVDS mode 100 Ω ± 1 %
Output voltage low, pad VOL CC 875 − − mV termination
class F, LVDS mode 100 Ω ± 1 %
Output Offset Voltage VOS CC 1075 − 1325 mV termination
100 Ω ± 1 %
Data Sheet 73 V 1.4.1, 2014-05

TC1782
5.2.2 Analog to Digital Converters (ADCx)

ADC parameter are valid for VDD / DDAF = 1.17 V to 1.43 V; VDDM = 4.5 V to 5.5 V.
Table 27 ADC Parameters

Switched capacitance at CAINSW − 9 20 pF
the analog voltage inputs1) CC
Total capacitance of an CAINTOT − 20 30 pF
analog input CC
Switched capacitance at CAREFSW − 15 30 pF
the positive reference CC
voltage input2)3)
Total capacitance of the CAREFTO − 20 40 pF
voltage reference inputs2) T CC
Differential Non-Linearity EADNL -3 − 3 LSB ADC
Error4)5)6)7) CC resolution= 12-
bit 8) 9)
Gain Error4)6)5)7) EAGAIN -3.5 − 3.5 LSB ADC
CC resolution= 12-
bit 8) 9)
Integral Non- EAINL -3 − 3 LSB ADC
Linearity4)6)5)7) CC resolution= 12-
bit 8) 9)
Offset Error4)6)5)7) EAOFF -4 − 4 LSB ADC
CC resolution= 12-
bit 8) 9)
Data Sheet 74 V 1.4.1, 2014-05

TC1782
Table 27 ADC Parameters (cont’d)

Converter clock fADC SC 4 − 90 MHz fADC= fFPI; SAK-
TC1782F-
320F180HR / S
AK-TC1782F-
320F180HL / S
AK-TC1782N-
320F180HR / S
AK-TC1782N-
320F180HL / S
AK-TC1782N-
256F133HR / S
AK-TC1782N-
256F133HL
4 − 80 MHz fADC= fFPI; SAK-
TC1782F-
320F160HR / S
AK-TC1782F-
320F160HL / S
AK-TC1782N-
320F160HR / S
AK-TC1782N-
320F160HL
Internal ADC clock fADCI CC 1 − 18 MHz
10)
Charge consumption per QCONV 70 85 100 pC charge needs to
conversion CC be provided via
VAREF0
Data Sheet 75 V 1.4.1, 2014-05

TC1782

Input leakage at analog IOZ1 CC -100 − 500 nA Vi≤ VDDM V;
inputs11) Vi≥ 0.97 x
VDDM V;
overlayed= No
-100 − 600 nA Vi≥ 0.97 x
VDDM V;
Vi≤ VDDM V;
overlayed= Yes
-500 − 100 nA Vi≤ 0.03 x
VDDM V;
Vi≥ 0 V;
overlayed= No
-600 − 100 nA Vi≤ 0.03 x
VDDM V;
Vi≥ 0 V;
overlayed= Yes
-100 − 200 nA Vi> 0.03 x
VDDM V;
Vi< 0.97 x
VDDM V;
overlayed= No
-100 − 300 nA Vi< 0.97 x
VDDM V;
Vi> 0.03 x
VDDM V;
overlayed= Yes
Input leakage current at IOZ2 CC -2 − 2 μA VAREF0≤ VDDM V
Varef0
Input leakage current at IOZ3 CC -2 − 2 μA VAGND0≤ VDDM V
Vagnd0
ON resistance of the RAIN CC − 900 1500 Ohm
transmission gates in the
analog voltage path
ON resistance for the ADC RAIN7T 180 550 900 Ohm
test (pull down for AIN7) CC
Data Sheet 76 V 1.4.1, 2014-05

TC1782

Resistance of the RAREF − 500 1000 Ohm
reference voltage input CC
path
Sample time tS CC 2 − 257 TADCI
Calibration time after bit tCAL CC − − 4352 cycle
ADC_GLOBCFG.SUCAL s
is set
Total Unadjusted TUE CC -4 − 413) LSB ADC
Error6)5)12) resolution= 12-
bit
Analog reference ground2) VAGND0 VSSM - − VAREF0 V
SR 0.05 -1
Analog input voltage VAIN SR VAGND0 − VAREF0 V
2)
Analog reference voltage VAREF0 VAGND0 − VDDM + V
SR +1 0.0514)
15)
Analog reference voltage VAREF0 - VDDM/2 − VDDM + V

range6)5)2) VAGND0 0.05
SR
1) The sampling capacity of the conversion C-network is pre-charged to VAREF0/2 before the sampling moment.
Because of the parasitic elements the voltage measured at AINx can deviate from VAREF0/2.
2) Applies to AINx, when used as auxiliary reference input.
3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead smaller capacitances are successively switched to the reference voltage.
4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.
5) If a reduced analog reference voltage between 1V and VDDM / 2 is used, then there are additional decrease in
the ADC speed and accuracy.
6) If the analog reference voltage range is below VDDM but still in the defined range of VDDM / 2 and VDDM is used,
then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1),
TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k.
7) If the analog reference voltage is > VDDM, then the ADC converter errors increase.
8) For 10-bit conversions the error value must be multiplied with a factor 0.25.
9) For 8-bit conversions the error value must be multiplied with a factor 0.0625.
10) For a conversion time of 1 µs a rms value of 85µA result for IAREF0.
11) The leakage current definition is a continuos function, as shown in figure ADCx Analoge Input Leakage. The
numerical values defined determine the characteristic points of the given continuous linear approximation -
they do not define step function.
Data Sheet 77 V 1.4.1, 2014-05

TC1782

12) Measured without noise.
13) For 10-bit conversion the TUE is ±2LSB; for 8-bit conversion the TUE is ±1LSB
14) A running conversion may become inexact in case of violating the normal conditions (voltage overshoot).
15) If the reference voltage VAREF0 increase or the VDDM decrease, so that VAREF = (VDDM + 0.05V to VDDM + 0.07V),
then the accuracy of the ADC decrease by 4LSB12.
Table 28 Conversion Time (Operating Conditions apply)

Parameter Symbol Values Unit Note
Conversion tC CC 2 × TADC + (4 + STC + n) × TADCI μs n = 8, 10, 12 for
time with n - bit conversion
post-calibration TADC = 1 / fFPI
Conversion 2 × TADC + (2 + STC + n) × TADCI TADCI = 1 / fADCI
time without
post-calibration
The power-up calibration of the ADC requires a maximum number of 4352 fADCI cycles.
Analog Input Circuitry

REXT RAIN, On
ANx
VAIN = CEXT CAINSW

CAINTOT - CAINSW
VAGNDx RAIN7T
Reference Voltage Input Circuitry
VAREFx RAREF, On
VAREF CAREFTOT - CAREFSW CAREFSW

VAGNDx
Analog_InpRefDiag
Figure 7 ADCx Input Circuits
Data Sheet 78 V 1.4.1, 2014-05

TC1782
Ioz1
Single ADC Input
500nA
200nA VIN[VDDM%]
100nA
-100nA
3% 97% 100%
-500nA
Ioz1
Overlayed ADC/FADC Input
600nA
300nA VIN[VDDM%]
100nA
-100nA
3% 97% 100%
-600nA
Figure 8 ADCx Analog Inputs Leakage
Data Sheet 79 V 1.4.1, 2014-05

TC1782
5.2.3 Fast Analog to Digital Converter (FADC)
Table 29 FADC Parameters

Input current at VFAREF IFAREF − − 120 μA

CC
Input leakage current at IFOZ2 -500 − 500 nA VFAREF≤ VDDMF
VFAREF1) CC V; VFAREF≥ 0 V
Input leakage current at IFOZ3 -500 − 500 nA
VFAGND CC
Data Sheet 80 V 1.4.1, 2014-05

TC1782
Table 29 FADC Parameters (cont’d)

DNL error EFDNL -1 − 1 LSB VIN mode=
CC differential;
Gain = 1 or 2;
Gain = 4 or 8
and
VDDAF / VDDMF≤
±5% * VDDAF / V
DDMF[Typ]
-1 − 1 LSB VIN mode=
single ended;
Gain = 1 or 2;
Gain = 4 or 8
and
VDDAF / VDDMF≤
±5% * VDDAF / V
DDMF[Typ]
differential;
Gain = 4 or 8
and
VDDAF / VDDMF>
±5% * VDDAF / V
2)
DDMF[Typ]
single ended;
Gain = 4 or
8and
VDDAF / VDDMF>
±5% * VDDAF / V
2)
DDMF[Typ]
Data Sheet 81 V 1.4.1, 2014-05

TC1782

GRADient error EFGRAD -5 − 5 % VIN mode=
CC differential ;
Gain≤ 4
-5 − 5 % VIN mode=
single ended ;
Gain≤ 4
-6 − 6 % VIN mode=
differential ;
Gain= 8
-6 − 6 % VIN mode=
single ended ;
Gain= 8
INL error EFINL -4 − 4 LSB VIN mode=
CC differential
single ended
Offset error EFOFF -90 − 90 mV VIN mode=
CC differential ;
Calibration= No
-90 − 90 mV VIN mode=
single ended ;
Calibration= No
differential ;
Calibration= Ye
s 3)4)
single ended ;
Calibration= Ye
s 3)4)
Error of commen mode EFREF -60 − 60 mV
voltage VFAREF/2 CC
Channel amplifier cutoff fCOFF 2 − − MHz
frequency CC
Data Sheet 82 V 1.4.1, 2014-05

TC1782

Converter clock fFADC 1 − 90 MHz fFADC= fFPI;

SC SAK-TC1782F-
320F180HR / S
AK-TC1782F-
320F180HL / S
AK-TC1782N-
320F180HR / S
AK-TC1782N-
320F180HL / S
AK-TC1782N-
256F133HR / S
AK-TC1782N-
256F133HL
1 − 80 MHz fFADC= fFPI;
SAK-TC1782F-
320F160HR / S
AK-TC1782F-
320F160HL / S
AK-TC1782N-
320F160HR / S
AK-TC1782N-
320F160HL
Conversion time tC CC − − 21 1/ For 10-bit
fFADC conversion
Input resistance of the RFAIN 100 − 200 kOh
analog voltage path (Rn, CC m
Rp)
Settling time of a channel tSET CC − − 5 μs
amplifier after changing
ENN or ENP
Analog input voltage VAINF VFAGND − VDDMF V
range SR
Analog reference ground VFAGND VSSAF - − VSSAF V
SR 0.05 + 0.05
Analog reference voltage VFAREF 3.0 − 3.635) V
6)
SR
Data Sheet 83 V 1.4.1, 2014-05

TC1782
1) This value applies in power-down mode.

2) No missing codes.
3) Calibration should be preformed at each power-up. In case of a continous operation, it should be performed
minimium once per week.
4) The offser error voltage drifts over the whole temperature range maximum +-3LSB.
5) Voltage overshoot to 4V is permissible, provided the pulse duration is less than 100 μs and the cumulated sum
of the pulses does not exceed 1 h.
6) A running conversion may become inexact in case of violating the nomal operating conditions (voltage
overshoots).
The calibration procedure should run after each power-up, when all power supply
voltages and the reference voltage have stabilized.
FADC Analog Input Stage
RN
FAINxN -
+
VFAGND VFAREF /2
=
+
RP
FAINxP -
FADC Reference Voltage

Input Circuitry
VFAREF
IFAREF
VFAREF
VFAGND
FADC_InpRefDiag
Figure 9 FADC Input Circuits
Data Sheet 84 V 1.4.1, 2014-05

TC1782
5.2.4 Oscillator Pins
Table 30 OSC_XTAL Parameters

Input current at XTAL1 IIX1 CC -25 − 25 μA VIN<VDDOSC3 ;
VIN>0 V
Input frequency fOSC SR 4 − 40 MHz Direct Input
Mode selected
8 − 25 MHz External Crystal
Mode selected
Oscillator start-up time1) tOSCS − − 10 ms
CC
Input high voltage at VIHX SR 0.7 x − VDDOS V
XTAL12) VDDOS C3 +
C3 0.5
Input low voltage at VILX SR -0.5 − 0.3 x V
XTAL1 VDDOS
C3
Input Hysteresis for HYSAX − − 200 mV
XTAL1 pad 3) CC
1) tOSCS is defined from the moment when VDDOSC3 = 3.13V until the oscillations reach an amplitude at XTAL1 of
0.3 * VDDOSC3. The external oscillator circuitry must be optimized by the customer and checked for negative
resistance as recommended and specified by crystral suppliers.
2) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.4 * VDDOSC3 is
necessary.
Note: It is strongly recommended to measure the oscillation allowance (negative

resistance) in the final target system (layout) to determine the optimal parameters
for the oscillator operation. Please refer to the limits specified by the crystal or
ceramic resonator supplier.
Data Sheet 85 V 1.4.1, 2014-05

TC1782
5.2.5 Temperature Sensor
Table 31 DTS Parameters

Measurement time tM CC − − 100 μs

Temperature sensor TSR SR -40 − 150 °C
range
Sensor Accuracy TTSA CC -6 − 6 °C
(calibrated)
Start-up time after resets tTSST SR − − 20 μs
inactive
The following formula calculates the temperature measured by the DTS in [oC] from the
RESULT bit field of the DTSSTAT register.
(1)
DTSSTAT RESULT – 596

Tj = -------------------------------------------------------------------
2, 03
Data Sheet 86 V 1.4.1, 2014-05

TC1782
5.2.6 Power Supply Current

The total power supply current defined below consists of leakage and switching
component.
Application relevant values are typically lower than those given in the following
two tables and depend on the customer's system operating conditions (e.g.
thermal connection or used application configurations).
The operating conditions for the parameters in the following table are:
VDD=1.365 V, VDDP=3.47 V, VDDM=5.1 V, fLMB=180 / 160 MHz / 133 MHz, TJ=150 oC
The realisic power pattern defines the following conditions:
• TJ=150 oC
• fLMB = fPCP = fCPU = 180 / 160 MHz / 133 MHz
• fFPI = 90 MHz / 80 MHz / 66.5 MHz
• VDD = VDDOSC = VDDAF = 1.326 V
• VDDP = VDDOSC3 = VDDFL3 = VDDMF = 3.366 V
• VDDM = 5.1 V
The max power pattern defines the following conditions:
• TJ=150 oC
• fLMB = fPCP = fCPU = 180 / 160 MHz / 133 MHz
• fFPI = 90 MHz / 80 MHz / 66.5 MHz
• VDD = VDDOSC = VDDAF = 1.365 V / 1.43 V / 1.365 V
• VDDP = VDDOSC3 = VDDFL3 = VDDMF = 3.47 V / 3.63 V / 3.47 V
• VDDM = 5.5 V
Data Sheet 87 V 1.4.1, 2014-05

TC1782
Table 32 Power Supply Parameters

Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Core active IDD CC − − 4863) mA power pattern= max ;
mode supply SAK-TC1782N-256F133HR
current1)2) SAK-TC1782N-256F133HL
− − 5503) mA power pattern= max ;
SAK-TC1782F320F180HR
SAK-TC1782F320F180HL
− − 5503) mA power pattern= max ;
− − 3704) mA power pattern= realistic ;
SAK-TC1782N-
256F133HL; VDD=1.326 V
SAK-TC1782N-
320F180HL; VDD=1.326 V
SAK-TC1782N-
320F160HL; VDD=1.326 V
IDD current at IDD_PORS − − 300 mA
PORST Low T CC − − 291 mA VDD=1.326 V
− − 314 mA VDD=1.43 V
Analog core IDDAF − − 23 mA
supply current CC
Data Sheet 88 V 1.4.1, 2014-05

TC1782
Table 32 Power Supply Parameters (cont’d)

Min. Typ. Max.
Oscillator core IDDOSC − − 4 mA
supply current CC
IDDP current at IDDP_POR − − 2.5 mA
PORST Low ST CC
IDDP current no IDDP CC − − IDDP_P mA including flash read current
pad activity, ORST +
LVDS off 5) 12
− − IDDP_P mA including flash programming
ORST + current 6)
27
− − IDDP_P mA including flash erase current
6)
ORST +
7)
20
Flash memory IDDFL3 − − 56 mA flash read current
current 5) CC − − 21 mA flash programming current 6)
− − 56 mA flash erase current 6)
Oscillator IDDOSC3 − − 15 mA
power supply CC
current, 3.3V
FADC analog IDDMF − − 15 mA
supply current, CC
3.3V
Current ILVDS − − 12 mA for all LVDS pads in total
Consumption of CC
LVDS Pad
Pairs
ADC 5V power IDDM CC − − 2 mA
supply current
Data Sheet 89 V 1.4.1, 2014-05

TC1782
Table 32 Power Supply Parameters (cont’d)

Min. Typ. Max.
Maximum PD CC − − 1143 mW power pattern= max ;
power SAK-TC1782N-256F133HR
dissipation SAK-TC1782N-256F133HL
− − 1231 mW power pattern= max ;
− − 1231 mW power pattern= max ;
− − 957 mW power pattern= realistic ;
SAK-TC1782N-
256F133HL; VDD=1.326 V
SAK-TC1782N-
320F180HL; VDD=1.326 V
SAK-TC1782N-
320F160HL; VDD=1.326 V
1) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each customer
application will most probably be lower than this value, but must be evaluated seperately.
2) This current includes the E-Ray module power consumption, including the PCP operation component.
3) The IDD decreases typically by 68mA if the fCPU decreases by 50MHz, at constant TJ
4) The IDD decreases typically by 30mA if the fCPU decreases by 50MHz, at constant TJ
5) For operations including the D-Flash the required currents are always lower than the currents for non D-Flash
operation.
6) Relevant for the power supply dimensioning, not for thermal considerations.
Data Sheet 90 V 1.4.1, 2014-05

TC1782

7) In case of erase of Program Flash PF, internal flash array loading effects may generate transient current spikes
of up to 15 mA for maximum 5 ms per flash module.
5.2.6.1 Calculating the 1.3 V Current Consumption

The current consumption of the 1.3 V rail compose out of two parts:
• Static current consumption
• Dynamic current consumption
The static current consumption is related to the device temperature TJ and the dynamic
current consumption depends of the configured clocking frequencies and the software
application executed. These two parts needs to be added in order to get the rail current
consumption.
(2)
= 2, 20897 --------- × e 0, 02696 × T J [ C ]

mA
I
0 C
(3)
I 0 = 10, 68 --------- × e 0, 02203 × T J [ C ]

mA
C
Function 2 defines the typical static current consumption and Function 3 defines the
maximum static current consumption. Both functions are valid for VDD = 1.326 V.
For the dynamic current consumption using the application pattern and fLMB = 2 * fFPI the
function 4 applies:
(4)
mA
I D y m = 0, 6 ------------- × f CPU [ MHz ]
MHz
and this finally results in

(5)
I DD = I 0 + I DYM
Data Sheet 91 V 1.4.1, 2014-05

TC1782
Electrical ParametersAC Parameters
5.3 AC Parameters
All AC parameters are defined with maximum driver strength unless otherwise noted.
5.3.1 Testing Waveforms
VD D P
90% 90%
10% 10%
VSS
tR tF
rise_fall
Figure 10 Rise/Fall Time Parameters
VD D P
VD D E / 2 Test Points VD D E / 2
VSS
mct04881_a.vsd
Figure 11 Testing Waveform, Output Delay
VLoad+ 0.1 V Timing VOH - 0.1 V

Reference
VLoad- 0.1 V Points VOL - 0.1 V
MCT04880_new
Figure 12 Testing Waveform, Output High Impedance
Data Sheet 92 V 1.4.1, 2014-05

TC1782
5.3.2 Power Sequencing
V
5.5V
5V
4.5V
3.63V VAREF
3.3V
2.97V
-12%
1.43V
1.3V
1.17V -12%
0.5V 0.5V 0.5V
t
VDDP
PORST
power power t
down fail
Power-Up 10.vsd
Figure 13 5 V / 3.3 V / 1.3 V Power-Up/Down Sequence for 10% Operating

Range
Data Sheet 93 V 1.4.1, 2014-05

TC1782
V
5.5V
5V
4.5V
3.47V VAREF
3.3V
2.97V
-12%
1.365V
1.3V
1.235V -12%
0.5V 0.5V 0.5V
t
VDDP
PORST
power power t
down fail
Power-Up 5.vsd
Figure 14 5 V / 3.3 V / 1.3 V Power-Up/Down Sequence for 5% Operating Range

The following list of rules applies to the power-up/down sequence:
• All ground pins VSS must be externally connected to one single star point in the
system. Regarding the DC current component, all ground pins are internally directly
connected.
• At any moment in time to avoid increased latch-up risk,
each power supply must be higher then any lower_power_supply - 0.5 V, or:
VDD5 > VDD3.3 - 0.5 V; VDD5 > VDD1.3 - 0.5 V;VDD3.3 > VDD1.3 - 0.5 V, see Figure 14.
– The latch-up risk is minimized if the I/O currents are limited to:
– 20 mA for one pin group
– AND 100 mA for the completed device I/Os
– AND additionally before power-up / after power-down:
1 mA for one pin in inactive mode (0 V on all power supplies)
• During power-up and power-down, the voltage difference between the power supply
pins of the same voltage (3.3 V, 1.3 V, and 5 V) with different names (for example
VDDP, VDDFL3 ...), that are internally connected via diodes, must be lower than 100 mV.
On the other hand, all power supply pins with the same name (for example all VDDP),
are internally directly connected. It is recommended that the power pins of the same
voltage are driven by a single power supply.
Data Sheet 94 V 1.4.1, 2014-05

TC1782
1. The PORST signal may be deactivated after all VDD5, VDD3.3, VDD1.3, and VAREF power-
supplies and the oscillator have reached stable operation, within the normal
operating conditions.
2. At normal power down the PORST signal should be activated within the normal
operating range, and then the power supplies may be switched off. Care must be
taken that all Flash write or delete sequences have been completed.
3. At power fail the PORST signal must be activated at latest when any 3.3 V or 1.3 V
power supply voltage falls 12% below the nominal level. If, under these conditions,
the PORST is activated during a Flash write, only the memory row that was the target
of the write at the moment of the power loss will contain unreliable content. In order
to ensure clean power-down behavior, the PORST signal should be activated as
close as possible to the normal operating voltage range.
4. In case of a power-loss at any power-supply, all power supplies must be powered-
down, conforming at the same time to the rules number 2 and 4.
5. Although not necessary, it is additionally recommended that all power supplies are
powered-up/down together in a controlled way, as tight to each other as possible.
6. Additionally, regarding the ADC reference voltage VAREF:
– VAREF must power-up at the same time or later then VDDM, and
– VAREF must power-down either earlier or at latest to satisfy the condition
VAREF < VDDM + 0.5 V. This is required in order to prevent discharge of VAREF filter
capacitance through the ESD diodes through the VDDM power supply. In case of
discharging the reference capacitance through the ESD diodes, the current must
be lower than 5 mA.
Data Sheet 95 V 1.4.1, 2014-05

TC1782
5.3.3 Power, Pad and Reset Timing
Table 33 Reset Timings Parameters

Application Reset Boot tB CC 150 − 810 μs SAK-TC1782N-

Time1)2) 256F133HR
SAK-TC1782N-
256F133HL
150 − 665 μs SAK-
TC1782F320F1
80HR
SAK-
TC1782F320F1
80HL
SAK-TC1782N-
320F180HR
SAK-TC1782N-
320F180HL
150 − 740 μs SAK-TC1782F-
320F160HR
SAK-TC1782F-
320F160HL / S
AK-TC1782N-
320F160HR
SAK-TC1782N-
320F160HL
Power on Reset Boot tBP CC − − 2.5 ms
Time3)4)
HWCFG pins hold time tHDH SR 16 / − − ns
from ESR0 rising edge fFPI
HWCFG pins setup time to tHDS CC 0 − − ns
ESR0 rising edge
Ports inactive after ESR0 tPI CC − − 8 / fFPI ns
reset active
Ports inactive after tPIP CC − − 150 ns
PORST reset active5)
Data Sheet 96 V 1.4.1, 2014-05

TC1782
Table 33 Reset Timings Parameters (cont’d)

Minimum PORST active tPOA CC 10 − − ms
time after power supplies
are stable at operating
levels
TESTMODE / TRST hold tPOH SR 100 − − ns
time from PORST rising
edge
PORST rise time tPOR SR − − 50 ms
TESTMODE / TRST tPOS SR 0 − − ns
setup time to PORST
rising edge
1) The duration of the boot time is defined between the rising edge of the internal application reset and the clock
cycle when the first user instruction has entered the CPU pipeline and its processing starts.
2) The given time includes the time of the internal reset extension for a configured value of
SCU_RSTCNTCON.RELSA = 0x05BE.
3) The duration of the boot time is defined between the rising edge of the PORST and the clock cycle when the
first user instruction has entered the CPU pipeline and its processing starts.
4) The given time includes the internal reset extension time for the System and Application Reset which is visible
through ESR0.
5) This parameter includes the delay of the analog spike filter in the PORST pad.
Data Sheet 97 V 1.4.1, 2014-05

TC1782
VDD P -12%
VD D PPA
V D DPPA
VDDP
VDD
tPOA VD D -12%
tPOA
PORST
tPOH tPOH
TRST
TESTMODE
t hd t hd
ESR0
tHDH tHDH tHDH
HWCFG
t PIP t PIP
tPI tPI
Pads
tPI tPI tPI
t PIP
Pad-state undefined
Tri-state or pull device active

reset_beh2
As programmed
Figure 15 Power, Pad and Reset Timing
Data Sheet 98 V 1.4.1, 2014-05

TC1782
5.3.4 Phase Locked Loop (PLL)
Table 34 PLL_SysClk Parameters

Accumulated Jitter DP CC -7 − 7 ns
PLL base frequency fPLLBASE 50 200 320 MHz
CC
VCO input frequency fREF CC 8 − 16 MHz
VCO frequency range fVCO CC 400 − 720 MHz
PLL lock-in time tL CC 14 − 200 μs N > 32
14 − 400 μs N ≤ 32
Phase Locked Loop Operation

When PLL operation is enabled and configured, the PLL clock fVCO (and with it the LMB-
Bus clock fLMB) is constantly adjusted to the selected frequency. The PLL is constantly
adjusting its output frequency to correspond to the input frequency (from crystal or clock
source), resulting in an accumulated jitter that is limited. This means that the relative
deviation for periods of more than one clock cycle is lower than for a single clock cycle.
This is especially important for bus cycles using wait states and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Two formulas are defined for the (absolute) approximate maximum value of jitter Dm in
[ns] dependent on the K2 - factor, the LMB clock frequency fLMB in [MHz], and the
number m of consecutive fLMB clock periods.
for ( K2 ≤ 100 ) and ( m ≤ ( f LMB [ MHz ] ) ⁄ 2 )

( 1 – 0, 01 × K2 ) × ( m – 1 ) (6)
D m [ ns ] = ⎛⎝ --------------------------------------------- + 5⎞⎠ × ⎛⎝ ---------------------------------------------------------------- + 0, 01 × K2⎞⎠
740
K2 × f LMB [ MHz ] 0, 5 × f LMB [ MHz ] – 1
740 (7)
else D m [ ns ] = --------------------------------------------- + 5
K2 × f LMB [ MHz ]
With rising number m of clock cycles the maximum jitter increases linearly up to a value
of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum
Data Sheet 99 V 1.4.1, 2014-05

TC1782
accumulated jitter remains at a constant value. Further, a lower LMB-Bus clock

frequency fLMB results in a higher absolute maximum jitter value.
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL = 20 pF with the maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
VDDOSC3 and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise
frequencies below 300 KHz and VPP = 40 mV for noise frequencies above
300 KHz.
The maximum peak-to peak noise on the pad supply voltage, measured between
VDDOSC and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise
300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.
Oscillator Watchdog (OSC_WDT)

The expected input frequency is selected via the bit field SCU_OSCCON.OSCVAL. The
OSC_WDT checks for too low frequencies and for too high frequencies.
The frequency that is monitored is fOSCREF which is derived for fOSC.
(8)
fO S C
f O S C R EF = ----------------------------------
-
OSCVAL + 1
The divider value SCU_OSCCON.OSCVAL has to be selected in a way that fOSCREF is

2.5 MHz.
Note: fOSCREF has to be within the range of 2 MHz to 3 MHz and should be as close as
possible to 2.5 MHz.
The monitored frequency is too low if it is below 1.25 MHz and too high if it is above
7.5 MHz. This leads to the following two conditions:
• Too low: fOSC < 1.25 MHz × (SCU_OSCCON.OSCVAL+1)
• Too high: fOSC > 7.5 MHz × (SCU_OSCCON.OSCVAL+1)
Note: The accuracy is 30% for these boundaries.
Data Sheet 100 V 1.4.1, 2014-05

TC1782
5.3.5 ERAY Phase Locked Loop (ERAY_PLL)
Table 35 PLL_ERAY Parameters

Accumulated jitter at DPP CC -0.8 − 0.8 ns

SYSCLK pin
Accumulated_Jitter DP CC -0.5 − 0.5 ns
PLL Base Frequency of fPLLBASE_ 50 250 360 MHz
the ERAY PLL ERAY CC
VCO input frequency of fREF CC 20 − 40 MHz
the ERAY PLL
VCO frequency range of fVCO_ERA 450 − 500 MHz
the ERAY PLL Y CC
PLL lock-in time tL CC 5.6 − 200 μs
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL = 20 pF with the maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
VDDOSC3 and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise
300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.
Data Sheet 101 V 1.4.1, 2014-05

TC1782
5.3.6 JTAG Interface Timing

The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 36 JTAG Interface Timing Parameters

(Operating Conditions apply)
TCK clock period t1 SR 25 – – ns –

TCK high time t2 SR 10 – – ns –
TCK low time t3 SR 10 – – ns –
TCK clock rise time t4 SR – – 4 ns –
TCK clock fall time t5 SR – – 4 ns –
TDI/TMS setup t6 SR 6 – – ns –
to TCK rising edge
TDI/TMS hold t7 SR 6 – – ns –
after TCK rising edge
TDO valid after TCK falling t8 CC – – 13 ns CL = 50 pF
edge1) (propagation delay) t CC 3 – – ns CL = 20 pF
8
TDO hold after TCK falling t18 CC 2 – – ns
edge1)
TDO high imped. to valid t9 CC – – 14 ns CL = 50 pF
from TCK falling edge1)2)
TDO valid to high imped. t10 CC – – 13.5 ns CL = 50 pF
from TCK falling edge1)
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet 102 V 1.4.1, 2014-05

TC1782
t1
0.9 VD D P
0.5 VD D P
0.1 VD D P
t5 t4
t2 t3
MC_ JTAG_ TCK
Figure 16 Test Clock Timing (TCK)
TCK
t6 t7
TMS
t6 t7
TDI
t9 t8 t1 0
TDO
t18
MC_JTAG
Figure 17 JTAG Timing
Data Sheet 103 V 1.4.1, 2014-05

TC1782
5.3.7 DAP Interface Timing

The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 37 DAP Parameters

DAP0 clock period1) tTCK SR 12.5 − − ns

DAP0 high time t12 SR 4 − − ns
1)
DAP0 low time t13 SR 4 − − ns
DAP0 clock rise time t14 SR − − 2 ns
DAP0 clock fall time t15 SR − − 2 ns
DAP1 setup to DAP0 t16 SR 6.0 − − ns
rising edge
DAP1 hold after DAP0 t17 SR 6.0 − − ns
rising edge
DAP1 valid per DAP0 t19 CC 8 − − ns CL= 20 pF;
clock period2) f= 80 MHz
10 − − ns CL= 50 pF;
f= 40 MHz
1) See the DAP chapter for clock rate restrictions in the Active:IDLE protocol state.
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t11
0.9 VD D P
0.5 VD D P
0.1 VD D P
t1 5 t14
t1 2 t1 3
MC_DAP0
Figure 18 Test Clock Timing (DAP0)
Data Sheet 104 V 1.4.1, 2014-05

TC1782
DAP0
t1 6 t1 7
DAP1
MC_ DAP1_RX
Figure 19 DAP Timing Host to Device
t1 1
DAP1
t1 9
MC_ DAP1_TX
Figure 20 DAP Timing Device to Host
Data Sheet 105 V 1.4.1, 2014-05

TC1782
5.3.8 Peripheral Timings
Note: Peripheral timing parameters are not subject to production test. They are verified
by design/characterization.
5.3.8.1 Micro Link Interface (MLI) Timing
MLI Transmitter Timing
t13 t14
t10
t12
TCLKx
t11
t15 t15
TDATAx
TVALIDx
t16
t17
TREADYx
MLI Receiver Timing
t23 t24
t20
t22
RCLKx
t21
t25
t26
RDATAx
RVALIDx
t27 t27
RREADYx
MLI_Tmg_2.vsd
Figure 21 MLI Interface Timing

Note: The generation of RREADYx is in the input clock domain of the receiver. The
reception of TREADYx is asynchronous to TCLKx.
Data Sheet 106 V 1.4.1, 2014-05

TC1782
The MLI parameters are vaild for CL = 50 pF and for strong driver medium edge.
Table 38 MLI Receiver

RCLK clock period t20 SR 1 / fFPI − − ns

RCLK high time1)2) t21 SR − 0.5 x − ns
t20
RCLK low time1)2) t22 SR − 0.5 x − ns
t20
RCLK rise time3) t23 SR − − 4 ns
3)
RCLK fall time t24 SR − − 4 ns
RDATA/RVALID setup t25 SR 4.2 − − ns
time before RCLK falling
edge
RDATA/RVALID hold time t26 CC 2.2 − − ns
after RCLK falling edge
RREADY output delay t27 CC 0 − 16 ns
time
1) The following formula is valid: t21 + t22 = t20.
2) Min and Max values for this parameter can be derived from the typ. value by considering the other receiver
timing parameters.
3) The RCLK max. input rise/fall times are best case parameters for fSYS = 90 MHz. For reduction of EMI, slower
input signal rise/fall times can be used for longer RCLK clock periods.
Table 39 MLI Transmitter

TCLK clock period t10 CC 2x1/ − − ns

fFPI
TCLK high time1)2) t11 CC 0.45 x 0.5 x 0.55 x ns
t10 t10 t10
TCLK low time1)2) t12 CC 0.45 x 0.5 x 0.55 x ns
t10 t10 t10
TCLK rise time t13 CC − − 0.3 x ns
t103)
Data Sheet 107 V 1.4.1, 2014-05

TC1782
Table 39 MLI Transmitter (cont’d)

TCLK fall time t14 CC − − 0.3 x ns
t103)
TDATA/TVALID output t15 CC -3 − 4.4 ns
delay time
TREADY setup time t16 SR 18 − − ns
before TCLK rising edge
TREADY hold time after t17 SR -2 − − ns
TCLK rising edge
1) The following formula is valid: t11 + t12 = t10.
2) The min./max. TCLK low/high times t11/t12 include the PLL jitter of fSYS. Fractional divider settings must be
regarded additionally to t11 / t12.
3) For high-speed MLI interface, strong driver sharp or medium edge selection (class A2 pad) is recommended
for TCLK.
5.3.8.2 Micro Second Channel (MSC) Interface Timing
The MSC parameters are vaild for CL = 50 pF.
Table 40 MSC Parameters

FCLP clock period1)2) t40 CC 2x − − ns

TMSC3)
SOP4)/ENx outputs delay t45 CC -2 − 5 ns ENx with strong
from FCLP4) rising edge driver and
sharp (minus )
edge
-2 − 10 ns ENx with strong
driver and
medium
(minus) edge
0 − 21 ns ENx with strong
driver and soft
edge
Data Sheet 108 V 1.4.1, 2014-05

TC1782
Table 40 MSC Parameters (cont’d)

SDI bit time t46 CC 8x − − ns

TMSC
SDI rise time 5) t48 SR − − 200 ns
5)
SDI fall time t49 SR − − 200 ns
1) FCLP signal rise/fall times are only defined by the pad rise/fall times.
2) FCLP signal high and low can be minimum 1xTMSC
3) TMSC = TSYS = 1 / fSYS.
4) SOP / FCLP either propagated by LVDS or by CMOS strong driver and non soft edge.
5) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application
must take care that the bit is long enough (the baud rate is low enough) so that under worst case conditions
the three sampling points in the middle of the bit are not violated.
t40
0.9 VDDP
FCLP
0.1 VDDP
t45 t45
SOP
EN
t48 t49
0.9 VDDP
SDI
0.1 VDDP
t46 t46
MSC_Tmg_1.vsd
Figure 22 MSC Interface Timing

Note: The data at SOP should be sampled with the falling edge of FCLP in the target
device.
Data Sheet 109 V 1.4.1, 2014-05

TC1782
5.3.8.3 SSC Master/Slave Mode Timing
The SSC parameters are vaild for CL = 50 pF and for strong driver medium edge.
Table 41 SSC Parameters

SCLK clock period1)2)3) t50 CC 2x1/ − − ns
fFPI
MTSR/SLSOx delay form t51 CC 0 − 8 ns
SCLK rising edge
MRST setup to SCLK t52 SR 16.5 − − ns
falling edge3)
MRST hold from SCLK t53 SR 0 − − ns
falling edge3)
SCLK input clock t54 SR 4x1/ − − ns
period1)3) fFPI
SCLK input clock duty t55_t54 45 − 55 %
cycle SR
MTSR setup to SCLK t56 CC 1 / fFPI − − ns
latching edge3)4)
MTSR hold from SCLK t57 CC 1 / fFPI − − ns
latching edge +5
SLSI setup to first SCLK t58 CC 1 / fFPI − − ns
latching edge +5
SLSI hold from last SCLK t59 CC 7 − − ns
latching edge5)
MRST delay from SCLK t60 CC 0 − 16.5 ns
shift edge
SLSI to valid data on t61 CC − − 16.5 ns
MRST
1) SCLK signal rise/fall times are the same as the rise/fall times of the pad.
2) SCLK signal high and low times can be minimum 1xTSSC.
3) TSSCmin = TSYS = 1/fSYS.
4) Fractional divider switched off, SSC internal baud rate generation used.
5) For CON.PH=1 slave select must not be removed before the following shifting edge. This mean, that what ever
is configured (shifting / latching first), SLSI must not be de-actived before the last trailing edge from the pair
of shifting / latching edges.
Data Sheet 110 V 1.4.1, 2014-05

TC1782
t50
SCLK1)2)
t51 t51
MTSR1)
t52
t53
1) Data
MRST
valid
t51
2)
SLSOn
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
2) The transition at SLSOn is based on the following setup: SSOTC.TRAIL = 0

and the first SCLK high pulse is in the first one of a transmission.
SSC_TmgMM
Figure 23 SSC Master Mode Timing
t54
First shift First latching Last latching
SCLK1) SCLK edge SCLK edge SCLK edge
t55 t55
t56 t56
t57 t57
MTSR 1) Data Data
valid valid
t60 t60
1)
MRST
t61 t59
SLSI
t58
1) This timing is based on the following setup: CON.PH = CON.PO = 0.

SSC_TmgSM
Figure 24 SSC Slave Mode Timing
Data Sheet 111 V 1.4.1, 2014-05

TC1782
5.3.8.4 ERAY Interface Timing

The timings of this section are valid for the strong driver and either sharp edge or medium
edge settings of the output drivers with CL = 25 pF.
The ERAY interface is only available for the SAK-TC1782F-320F180HR / SAK-
TC1782F-320F180HL / SAK-TC1782F-320F160HR / SAK-TC1782F-
320F160HL / SAK-TC1782F-320F133HR / SAK-TC1782F-320F133HL.
Table 42 ERAY Parameters

Time span from last BSS t60 CC 997.75 − 1002.2 ns

to FES without the 5
influence of quartz
tolerancies (d10Bit_TX)1)
TxD data valid from t61-t62 − − 1.5 ns Asymmetrical
fsample flip flop txd_reg CC delay of rising
TxDA, TxDB and falling edge
(dTxAsym)2)3) (TxDA, TxDB)
Time span between last t63 SR 966 − 1046.1 ns
BSS and FES without
influence of quartz
tolerancies
(d10Bit_RX)1)4)5)
RxD capture by fsample t64-t65 − − 3.0 ns Asymmetrical
(RxDA/RxDB sampling CC delay of rising
flip-flop) (dRxAsym)5) and falling edge
(RxDA, RxDB)
TxD data delay from dTxdly − − 10.0 ns Px_PDR.PDy =
sampling flip-flop CC 000B
− − 15.0 ns Px_PDR.PDy =
001B
RxD capture delay by dRxdly − − 10.0 ns
sampling flip-flop CC
1) This includes the PLL_ERAY accumulated jitter.
2) Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers.
Quarz tolerance and PLL_ERAY accumulated jitter are not included.
3) E-Ray TxD output drivers have an asymmetry of rising and falling edges of |tFA2 - tRA2| ≤ 1 ns.
4) Limits of 966ns and 1046.1ns correspond to (30%, 70%) * VDDP FlexRay standard input thresholds. For input
thresholds of this product, a correction of - 0.5 ns and +0.1 ns has to be applied.
Data Sheet 112 V 1.4.1, 2014-05

TC1782

5) Valid for output slopes of the bus driver of dRxSlope ≤ 5ns, 20% * VDDP to 80% * VDDP, according to the
FlexRay Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming
signal have to satisfy the following inequality: -1.6ns ≤ tFA2 - tRA2 ≤ 1.3ns.
BSS Last CRC Byte FES

(Byte Start Sequence) (Frame End Sequence)
0.7 VDD
TXD 0.3 VDD
t60
tsample
TXD 0.9 VDD

0.1 VDD
t61 t62
BSS Last CRC Byte FES

(Byte Start Sequence) (Frame End Sequence)
0.7 VDD
RXD 0.3 VDD
t63
tsample
RXD 0.7 VDD

0.3 VDD
t64 t65
ERAY_TIMING
Figure 25 ERAY Timing
Data Sheet 113 V 1.4.1, 2014-05

TC1782
Electrical ParametersPackage and Reliability
5.4 Package and Reliability
5.4.1 Package Parameters
Table 43 Thermal Characteristics of the Package

Device Package RΘJCT1) RΘJCB1) RΘJLead Unit Note
TC1782 PG-LQFP-176- 8,1 0,3 30,9 K/W with soldered
10 / PG-LQFP- exposed pad 2)
176-20
TC1782 PG-LQFP-176- 8,1 12,6 30,9 K/W with not soldered
10 / PG-LQFP- exposed pad
176-20
1) The top and bottom thermal resistances between the case and the ambient (RTCAT, RTCAB) are to be combined
with the thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate
the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the
case and the ambient (RTCAT, RTCAB) depend on the external system (PCB, case) characteristics, and are
under user responsibility.
The junction temperature can be calculated using the following equation: TJ = TA + RTJA × PD, where the RTJA
is the total thermal resistance between the junction and the ambient. This total junction ambient resistance
RTJA can be obtained from the upper four partial thermal resistances.
Thermal resistances as measured by the ’cold plate method’ (MIL SPEC-883 Method 1012.1).
2) It is recommended by Infineon Technologies AG to connect the exposed pad.
Data Sheet 114 V 1.4.1, 2014-05

TC1782
5.4.2 Package Outline
Exposed
DIPAD
Figure 26 Package Outlines PG-LQFP-176-10 / PG-LQFP-176-20
Table 44 Exposed pad Dimensions

Ex 7.8 mm
Ey 7.8 mm
You can find all of our packages, sorts of packing and others in our Infineon Internet
Page “Products”: http://www.infineon.com/products.
5.4.3 Flash Memory Parameters

The data retention time of the TC1782’s Flash memory depends on the number of times
the Flash memory has been erased and programmed.
Data Sheet 115 V 1.4.1, 2014-05

TC1782
Table 45 FLASH32 Parameters

Data Flash Erase Time tERD CC − − 31) s

per Sector
Program Flash Erase tERP CC − − 5 s
Time per 256 KByte
Sector
Program time data flash tPRD CC − − 5.3 ms without
per page2) reprogramming
− − 15.9 ms with two
reprogramming
cycles
Program time program tPRP CC − − 5.3 ms without
flash per page3) reprogramming
− − 10.6 ms with one
reprogramming
cycle
Data Flash Endurance NE CC 60000 − − cycle Min. data
4)
s retention time 5
years
Erase suspend delay tFL_ErSusp − − 15 ms
CC
Wait time after margin tFL_Margin 10 − − μs
change Del CC
Program Flash Retention tRET CC 20 − − year Max. 1000
Time, Physical Sector5)6) s erase/program
cycles
Program Flash Retention tRETL CC 20 − − year Max. 100
Time, Logical Sector5)6) s erase/program
cycles
UCB Retention Time5)6) tRTU CC 20 − − year Max. 4
s erase/program
cycles per UCB
Wake-Up time tWU CC − − 270 μs
Data Sheet 116 V 1.4.1, 2014-05

TC1782
Table 45 FLASH32 Parameters (cont’d)

DFlash wait state WSDF 50 ns x − −

configuration CC fFSI
PFlash wait state WSPF 26 ns x − −
configuration CC fFSI
1) In case of wordline oriented defects (see robust EEPROM emulation in the User's Manual) this erase time can
increase by up to 100%.
2) In case the Program Verify feature detects weak bits, these bits will be programmed up to twice more. Each
reprogramming takes additional 5 ms.
3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The
reprogramming takes additional 5 ms.
4) Only valid when a robust EEPROM emulation algorithm is used. For more details see the User´s Manual.
5) Storage and inactive time included.
6) At average weighted junction temperature Tj = 100°C, or the retention time at average weighted temperature
of Tj = 110°C is minimum 10 years, or the retention time at average weighted temperature of Tj = 150°C is
minimum 0.7 years.
5.4.4 Quality Declarations
Table 46 Quality Parameters

Min. Typ. Max.
Operation tOP – – 24000 hours –2)
Lifetime1)
ESD susceptibility VHBM – – 2000 V Conforming to
according to JESD22-A114-B
Human Body
Model (HBM)
ESD susceptibility VHBM1 – – 500 V –
of the LVDS pins
ESD susceptibility VCDM – – 500 V Conforming to
according to JESD22-C101-C
Charged Device
Model (CDM)
Moisture MSL – – 3 – Conforming to Jedec
Sensitivity Level J-STD-020C for 240°C
Data Sheet 117 V 1.4.1, 2014-05

TC1782
1) This lifetime refers only to the time when the device is powered on.
2) For worst-case temperature profile equivalent to:
1200 hours at Tj = 125...150oC
3600 hours at Tj = 110...125oC
7200 hours at Tj = 100...110oC
11000 hours at Tj = 25...100oC
1000 hours at Tj = -40...25oC
Data Sheet 118 V 1.4.1, 2014-05

TC1782
History
6 History
The following changes where done between Version 0.7 and 0.8 of this document:
• Change product name from SAK-TC1782-320F180HL to SAK-TC1782-320F180HR
• Change product name from SAK-TC1782-256F133HL to SAK-TC1782-256F133HR
• Change DFLASH size from 64Kbyte to 128Kbyte in chapter 1
• Add ADC module abbreviation to table 1 Analog Input Port Function description
• Change SCU_RTID and SCU_CHIPID values to match the step
• Extend VDDOSC3 to -7.5 %
• Add parameter HYSA1+
• Add parameter HYSA2
• Add parameter VILF / VIHF
• Add parameter RDSONF
• Changed typical value of CAINSW from 7 to 9 pF
• Changed typical value of CAINTOT from 25 to 20 pF
• Remove 3.3 V values from ADC section
• Add parameter fADC
• Changed max. value of fADCI from 20 to 18 MHz
• Remove parameter IAIN7T (covered by RAIN7T )
• Replace parameter IAREF by QCONV
• Changed typical value of RAIN from 700 to 900 Ohm
• Add parameter tS
• Add footnote to max value of TUE
• Add parameter fFADC
• Add parameter tC
• Add formula for DTS temperature calculation
• Adapt current values to reduced limits of BA step
• Add clarification to parameter ILVDS
• Remove parameter RTHJA (not required)
• Add clarification to parameter tPOH description
• Add clarification to parameter tPOS description
• Add min. value to parameters tL
• Changed typical value of fPLLBASE_ERAY from 200 to 250 MHz
• Add MSC t45 behavior for CMOS / LVDS usage
• Add RTHs for non soldered exposed pad
• Add table 33
• Change DTS accuracy to 6°C of the complete temperature range
• Remove limitations of the DFLASH and PFLASH operating in extended Range
operating conditions
• Change package version von PG-LQFP-176-6 to PG-LQFP-176-12
• Change package version von PG-LQFP-176-12 to PG-LQFP-176-10
Data Sheet 119 V 1.4.1, 2014-05

TC1782
History
• improve description in table 2 for analog channels

• add class A1+ to type list of table 2
• add clarification that table 7 defines the conditions for all other parameters
• add note the spike filter is only available for the PORST pin
• add Vil to Vih ratio for A1+ pad
• remove irritating Note / Test Conditions
• adapt maximum power dissipation values
• add conditions for MLI, MSC, SSC, parameters
• changed definition for t13 and t14 of the MLI timing
• changed definition for t45 of the MSC timing
• add parameters dTxdly and dRxdly to ERAY parameters
• correct ERAY parameters t60 and t63 values
• correct footnotes for ERAY parameters
• split flash parameters tPRD and tPRP in two conditions
• add conditions to LVDS pad parameters
• Changed VAREFx to VAREF0 and VAGNDx to VAGND0
• remove Pin Reliability in Overload section
• add parameters IIN and Sum IIN to absolute ratings
• adjust thresholds in figure 28 (ERAY)
• add parameter HYSX to PSC_XTAL
• added RDSON values for all driver settings (weak, medium, and strong)
• removed footnote 2 of table 6
• change conditions for RDSON weak parameters
• change load for timing of SSC, MSC, and MLI from CL = 25 pF to CL = 50 pF (typical)
• add type I to legend of table 2
• add SAK-TC1782-320F180HL and SAK-TC1782-256F133HL
• changed timing checkpoints in figure 23
• add section 5.2.6.1
• add to parameters tRF and tFF condition CL = 50 pF
• add new footnote 7) to ADC parameter table
• add min and max value for QCONV and adapt typ value
• add load conditions for tFF1 and tRF1
• add conditions to PLL parameter tL
• change DAP parameter t19 from SR to CC classification
• remove footnote 2 for the FADC
• increase current for IDDP_POR from 2 to 2.5mA
• add footnote 3 to table 9
• change SAK-TC1782-320F180HR / SAK-TC1782-320F180HL to SAK-TC1782F-
320F180HR / SAK-TC1782F-320F180HL
• change SAK-TC1782-256F133HR / SAK-TC1782-256F133HL to SAK-TC1782F-
256F133HR / SAK-TC1782F-256F133HL
• add information for the following products:
– SAK-TC1782N-320F180HR
Data Sheet 120 V 1.4.1, 2014-05

TC1782
History
– SAK-TC1782N-320F180HL
– SAK-TC1182N-320F180HR
– SAK-TC1182N-320F180HL
– SAK-TC1782N-256F133HR
– SAK-TC1782N-256F133HL
– SAK-TC1182N-256F133HR
– SAK-TC1182N-156F133HL
• add section Pin Reliability in Overload
• remove sentence ‘Exposure to conditions within the maximum ratings will not affect
device reliability. To replace this sentence section Pin Reliability in Overload was
added.
• increase values for absolute maximum parameters IIN and SumIIN
• remove capacitance conditions for LVDS pad parameters as loads are defined by
interface (MSC) timings
• remove term typical from load of Peripheral Timings
• add definition of driver strength settings for ERAY Interface Timing
• change footnote 4 wording for ERAY timing back to TC1797 wording
• increase flash parameters tPRD and tPRP values
• rework the 3.3 V current part of the Power Supply Parameters for better description
and usage
– Parameters IDDP_FP, IDDFL3E and IDDFL3R are removed and replaced in the following
way
– IDDP_FP is replaced by IDDP with the condition including flash programming current
– IDDFL3E is replaced by IDDP with the condition including flash erase verify current
– IDDFL3R is replaced by IDDP with the condition including flash read current
– parameter IDDFL3R was renamed to IDDFL3
The rework of the 3.3 V current part of the Power Supply Parameters was done for
simplification and clarification. Former given values could still be used if liked, the new
definition results in the same resulting values or slightly better values. The flash module
is supplied via IDDFL3 and IDDP. For the different flash operating modes in worst case
different allocations for the two domains resulting.
The application typical case ‘flash read’ has max IDDP of 12 mA and max IDDFL3 of 56 mA
resulting is a sum of 68 mA.
The case ‘flash programming’ has max IDDP of 27 mA and max IDDFL3 of 21 mA resulting
is a sum of 48 mA.
The case ‘flash erase verify’ has max IDDP of 20 mA and max IDDFL3 of 56 mA resulting
is a sum of 76 mA.
So for the old parameter IDDP with 15 mA, the new version reads as
IDDP = 12+IDDP_PORST = 14.5 mA for the same application relevant case.
Data Sheet 121 V 1.4.1, 2014-05

TC1782
History
• removed products SAK-TC1182N-320F180HR, SAK-TC1182N-320F180HL, SAK-

TC1182N-256F133HR, and SAK-TC1182N-256F133HL
• improve parameters IDDFL3
• change for parameter NE note from Max. data retention to Min.
• removed the term (typical)
• change description of parameter tCAL for the ADC
• correct typo for class D pads in tables 14 and 15
• adapt Absolute Maximun Rating
• add footnote to Flash parameter tERD
• add note at the end of Pin Reliability in Overload section
• clearify pad supply levels in Pin Reliability in Overload section
• add footnote for D-Flash currents in power section
• add product option SAK-TC1782F-320F160HL, SAK-TC1782F-320F160HR, SAK-
TC1782N-320F160HL and SAK-TC1782N-320F160HR
• update block diagrams to cover new option
• add identification registers for new product option
• rework first sentence for chapter 5.3
• reduce min value for tL for both PLLs
• add for MLI and SSC parameter: valid strong driver medium edge only
• add footnote 5) for SSC parameters
• update FADC parameter EFDNL
• change MLI parameter t17 min value
• rename section Extented Range Operating Conditions to Voltage Operating timing
Profiles and remove limitions on GPIOs
• split RDSONM for class F pads into two conditions
The following changes where done between Version 1.3 and 1.3.1 of this document:
• correct typos in table 1
– SAK-TC1782N-320N160HR -> SAK-TC1782F-320F160HR
– SAK-TC1782N-320N160HL -> SAK-TC1782F-320F160HL
• reduce current for ILVDS from 24mA to 12mA (only 2 pairs are available)
The following changes where done between Version 1.3.1 and 1.4 of this document:
• remove the following product options:
– SAK-TC1782F-256F133HR
– SAK-TC1782F-256F133HL
• change t48 from 100ns to 200ns in table 42
• change t49 from 100ns to 200ns in table 42
• extend KOVAN conditon from IOV≤ 0 mA; IOV≥ -1 mA to IOV≤ 0 mA; IOV≥ -2 mA
• change parameter EFOFF from +-90mV to +-120 for condition Calibration = No
The following changes where done between Version 1.4 and 1.4.1 of this document:
• change parameter EFOFF from +-120mV to +-90 for condition Calibration = No
Data Sheet 122 V 1.4.1, 2014-05

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Data Sheet I-1 V 1.4.1, 2014-05

5.4.3 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-115

Data Sheet I-2 V 1.4.1, 2014-05

Data Sheet 3 V 1.4.1, 2014-05

Data Sheet 4 V 1.4.1, 2014-05

Data Sheet 1 V 1.4.1, 2014-05

Data Sheet 2 V 1.4.1, 2014-05

The SAK-TC1782N-320F180HR / SAK-TC1782N-320F180HL has the following

Data Sheet 3 V 1.4.1, 2014-05

Data Sheet 4 V 1.4.1, 2014-05

The SAK-TC1782N-256F133HR / SAK-TC1782N-256F133HL has the following

Data Sheet 5 V 1.4.1, 2014-05

Data Sheet 6 V 1.4.1, 2014-05

The SAK-TC1782F-320F160HR / SAK-TC1782F-320F160HL has the following

Data Sheet 7 V 1.4.1, 2014-05

Data Sheet 8 V 1.4.1, 2014-05

The SAK-TC1782N-320F160HR / SAK-TC1782N-320F160HL has the following

Data Sheet 9 V 1.4.1, 2014-05

Data Sheet 10 V 1.4.1, 2014-05

Table 1 TC1782 Derivative Synopsis

Data Sheet 11 V 1.4.1, 2014-05

System Overview of the TC1782

2 System Overview of the TC1782

Data Sheet 12 V 1.4.1, 2014-05

System Overview of the TC1782Block Diagrams

2.1 Block Diagrams

SSC0 FADC (3.3V max)

Figure 1 SAK-TC1782-320F180HR / SAK-TC1782-320F180HL / SAK-TC1782-

Data Sheet 13 V 1.4.1, 2014-05

System Overview of the TC1782Block Diagrams

Figure 2 shows the block diagram of the SAK-TC1782N-320F180HR / SAK-TC1782N-

SSC0 FADC (3.3V max)

Figure 2 SAK-TC1782N-320F180HR / SAK-TC1782N-320F180HL / SAK-

Data Sheet 14 V 1.4.1, 2014-05

System Overview of the TC1782Block Diagrams

Figure 3 shows the block diagram of the SAK-TC1782N-256F133HR / SAK-TC1782N-

PLL Ports ADC1

SSC0 FADC (3.3V max)

Figure 3 SAK-TC1782N-256F133HR / SAK-TC1782N-256F133HL

Data Sheet 15 V 1.4.1, 2014-05

Figure 4 TC1782 Logic Symbol

Data Sheet 16 V 1.4.1, 2014-05

AN2 65 156 P 6.0 /IN 1 4/OU T 4/ OUT 80/ FC L N 0

P1.2/ IN18 /OUT 18 /OUT 74

SAK-TC1782F-320F160HR / SAK-TC1782F-320F160HL Pinning

P1.8/ IN24 /IN48 /M T SR1 B/ OUT 24/OUT 48

P4.3/ IN31 /IN55 /OUT 31 /OUT 55 /EXT CLK0

P1 .0/IN 16/ OUT 16/OUT 72 /BRKIN/ BRKOUT

P1.2 /IN18 /OUT 18 /OUT 74

P1.4 /IN20 /EM GST OP/ OUT 20/OUT 76

SAK-TC1782N-256F133HR / SAK-TC1782N-256F133HL / Pinning

P1.8 /IN24 /IN48 /M T SR1 B/OUT 24/ OUT 48

P4.3 /IN31 /IN55 /OUT 31 /OUT 55 /EXT CLK0

P1 .0/ IN16 /OUT 16/ OUT 72/ BRKIN/BRKOUT

PinningTC1782 Pin Configuration

Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20

Data Sheet 19 V 1.4.1, 2014-05

PinningTC1782 Pin Configuration