TMS320C6413/C6418 EVM: Reference Technical

TMS320C6413/C6418 EVM
2004 DSP Development Systems

Reference
Technical
TMS320C6413/C6418 EVM
Technical Reference
507265-0001 Rev. B
October 2004
SPECTRUM DIGITAL, INC.
12502 Exchange Drive, Suite 440 Stafford, TX. 77477
Tel: 281.494.4505 Fax: 281.494.5310
[email protected] www.spectrumdigital.com
IMPORTANT NOTICE
Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any
product or service without notice. Customers are advised to obtain the latest version of relevant
information to verify that the data being relied on is current before placing orders.
Spectrum Digital, Inc. warrants performance of its products and related software to current
specifications in accordance with Spectrum Digitals standard warranty. Testing and other quality
control techniques are utilized to the extent deemed necessary to support this warranty.
Please be aware that the products described herein are not intended for use in life-support
appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for
the product described herein to be used in other than a development environment.
Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein. Nor does Spectrum
Digital warrant or represent any license, either express or implied, is granted under any patent right,
copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any
combination, machine, or process in which such Digital Signal Processing development products or
services might be or are used.
WARNING
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can
radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable
protection against radio frequency interference. Operation of this equipment in other environments
may cause interference with radio communications, in which case the user at his own expense will be
required to take whatever measures necessary to correct this interference.
Copyright 2004 Spectrum Digital, Inc.
Contents
1 Introduction to the TMS320C6413/C6418 EVM Module . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Provides you with a description of the TMS320C6413/C6418 EVM Module, key features, and
block diagram.
1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3 Display/Keypad Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.4 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.5 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.6 Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6.1 CLKMODE Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.6.2 CLKINSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.6.3 Oscillator Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.6.4 Endian Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.7 EMIFA Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.7.1 Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.7.2 EMIFA Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.8 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
2 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Describes the operation of the major board components on the TMS320C6413/C6418 EVM.
2.1 CPLD (programmable Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.1 CPLD Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.2 CPLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.1.3 USER_REG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.1.4 DC_REG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.1.5 Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.1.6 MISC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.1.7 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.1.8 C6413/C6418 EVM Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2 AIC23 Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.3 Synchronous Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.4 Flash ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.5 SBRAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.6 LEDs and DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.7 Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.8 TL16550 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
3 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Describes the physical layout of the TMS320C6413/C6418 EVM and its connectors.
3.1 TMS320C6413/C6418 EVM Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Keypad/display Module Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Connector Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4 Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4.1 P1, Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.4.2 P2, Peripheral Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.4.3 P3, HPI Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.5 Audio Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.5.1 J1, Microphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.5.2 J2, Audio Line In Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.5.3 J3, Audio Line Out Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.5.4 J4, Headphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.6 Power Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.6.1 J5, +5V Main Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.6.2 J6, Alternate Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.7. Miscellaneous Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.7.1 J8, RS-232 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.7.2 J7, External JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.7.3 JP1, PLD Programming Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.8 P5, Keypad/Display Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.9 System LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.10 Reset Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Contains the schematics for the TMS320C6413/C6418 EVM and Keypad/display Module
A.1 TMS320C6413/C6418 EVM Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A.2 Keypad/display Module Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-26
B Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Contains the mechanical information about the TMS320C6413/C6418 EVM and Keypad/display
Module
B.1 TMS320C6413/C6418 EVM Mechanical Information . . . . . . . . . . . . . . . . . . . . . . B-2
B.2 Keypad/display Module Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
About This Manual
This document describes the board level operations of the TMS320C6413/C6418
Evaluation Module (EVM). The EVM is based on the Texas Instruments
TMS320C6413/C6418 Digital Signal Processor.
The TMS320C6413/C6418 EVM is a table top card to allow engineers and software
developers to evaluate certain characteristics of the TMS320C6413/C6418 DSP to
determine if the processor meets the designers application requirements. Evaluators
can create software to execute onboard or expand the system in a variety of ways.
Notational Conventions
This document uses the following conventions.
The TMS320C6413/C6418 will sometimes be referred to as the C641x.
The TMS320C6413/C6418 EVM will sometimes be referred to as the EVM.
Program listings, program examples, and interactive displays are shown is a special
italic typeface. Here is a sample program listing.
equations
!rd = !strobe&rw;
Information About Cautions
This book may contain cautions.
This is an example of a caution statement.
A caution statement describes a situation that could potentially damage your software,
or hardware, or other equipment. The information in a caution is provided for your
protection. Please read each caution carefully.
Related Documents
Texas Instruments TMS320C64XX DSP CPU Reference Guide
Texas Instruments TMS320C64XX DSP Peripherals Reference Guide
Table 1: Hardware History
Revision History
A Alpha Release
Table 2: Manual History
Revision History
A Alpha Release
B Text Updates
1-1
Chapter 1
Introduction to the
TMS320C6413/C6418 EVM
Chapter One provides a description of the TMS320C6413/C6418 EVM
along with the key features and a block diagram of the circuit board.
Topic Page
1.1 Key Features 1-2
1.2 Functional Overview 1-3
1.3 Display/Keypad Overview 1-4
1.4 Basic Operation 1-4
1.5 Memory Map 1-5
1.6 Jumper Settings 1-6
1.6.1 CLKMODE Multiplier 1-7
1.6.2 CLKINSEL 1-7
1.6.3 Oscillator Disable 1-7
1.6.4 Endian Select 1-8
1.7 EMIFA Configuration Options 1-8
1.7.1 Boot Options 1-8
1.7.2 EMIFA Clock Select 1-9
1.8 Power Supply 1-9
Spectrum Digital, Inc
1-2 TMS320C6413/C6418 EVM Module Technical Reference
1.0 Key Features
The C6413/C6418 EVM is a standalone development platform that enables users to
evaluate and develop applications for the TI C64XX DSP family. The EVM also serves
as a hardware reference design for the TMS320C6413/C6418 DSP. Schematics, logic
equations and application notes are available to ease hardware development and
reduce time to market.
The EVM comes with a full compliment of on-board devices that suit a wide variety of
application environments. Key features include:
A Texas InstrumentsC6413/C6418 DSP operating at 500/600 MHz
An TLC320AIC23B stereo codec
8 Mbytes of synchronous DRAM
1 Mbyte of synchronous Burst RAM
1 Mbyte of non-volatile Flash memory
TL16C550 UART with RS-232 Drivers
4 user accessible LEDs and DIP switches
Software board configuration through registers implemented in CPLD
128 LCD display and keypad
Standard expansion connectors for daughter card use
Figure 1-1, Block Diagram C6413/C6418 EVM
External
JTAG
AIC23
Codec
H
o
s
t

P
o
r
t

I
n
t
Peripheral Exp
LED DIP
EMIF
HPI
McBSPs
0 1 2 3 0 1 2 3
Memory Exp
C
L
K
_
S
E
L
O
S
C
E
N
D
I
A
N
6418
DSP S
y
n
c
D
R
A
M
32
5 7 6
Config
32
O
P
T
8
CPLD
S
y
n
c
S
R
A
M
Keypad
Display
C
L
K
M
0
C
L
K
M
1
C
L
K
M
2
C
L
K
M
3
RS-232
Flash Flash
32
1 3 2 4
UART
8
I
2
C
ROM
P
W
R
MIC IN
LINE OUT
HP OUT
LINE IN
E
X
T

P
W
R
I
2
C Bus
McASPs
1-3
JTAG emulation via external emulator
Single voltage power supply (+5V)
1.2 Functional Overview of the TMS320C6413/C6418 EVM
The DSP interfaces to external SDRAM, SBRAM, Flash memory and an expansion
memory interface connector through its 32-bit External Memory Interface (EMIF). The
SDRAM accesses are in 32-bit mode in chip enable 0 memory space. The EMIF
provides the necessary refresh signals. The Flash accesses are in 8,16, or 32-bit
asynchronous mode in the bottom half of chip enable 1 space. The default mode of the
EVM for CE1 is 8 bit mode. The SBRAM is accessed via chip enable 3, if it is not routed
to the expansion connector which is controlled by the CPLD control register. The EMIF
signals are brought out to the daughter card expansion connectors which use chip
enables 2 and 3.
An on-board AIC23 codec allows the DSP to transmit and receive analog signals.
The I
2
C bus is used for the codec control interface and McBSP1 is used for data.
Analog I/O is done through four 3.5mm audio jacks that correspond to microphone
input, line input, line output and headphone output. The codec input is software
selectable between the microphone or the line input as the active input. The analog
output is driven to both the line out (fixed gain) and headphone (adjustable gain)
connectors. McBSP1 can be re-routed to the expansion connectors in software.
A programmable logic device called a CPLD is used to implement glue logic that ties
the board components together. The CPLD has a register based user interface that
lets the user configure the board by reading and writing to the CPLD registers. The
registers reside in the upper half of chip enable 1.
The EVM includes 4 LEDs and 4 position DIP switch as a simple way to provide the
user with interactive feedback. Both are accessed by reading and writing to the CPLD
registers.
A separate Keypad/LCD display card is interfaced via CPLD registers and I
2
C
accesses. This module provides a flexible input/output mechanism for application
programs
An included 5V external power supply is used to power the board. On-board voltage
regulators provide the +1.2V or +1.4V DSP core voltage, +3.3V digital and +3.3V
analog voltages. Voltage supervisors integrated into the regulators monitor voltage
regulation, and will hold the board in reset until the supplies are within operating
specifications and the reset button is released.
1.3 Display/Keypad Overview
The universal display/keypad module interfaces to the EVM via a 16 pin 2mm. ribbon
cable.
The display module features a 128 x 64 LCD, 4 I
2
C A/D converters, 2 potentiometers,
9 user keys, and a jog wheel. All switches are accessed via the I
2
C A/Ds, while the
display is accessed via an SPI interface generated internally in the CPLD
Figure 1-2 below shows a block diagram of the display/keypad module.
1.4 Basic Operation
The EVM is designed to work with TIs Code Composer Studio development
environment and is available in an optional package with the board. Code Composer
communicates with the board through the JTAG emulator. To start, follow the
instructions in the emulators Quick Start Guide to install Code Composer. This process
will install all of the necessary development tools, documentation and drivers.
Figure 1-2, BLOCK DIAGRAM OF DISPLAY/KEYPAD
I
2
C
SPI
A/D
JOG WHEEL
DISPLAY
SWITCHES
A/D
POT
POT EVM
Universal Display
A/D
A/D
CPLD
1-5
1.5 Memory Map
The C64xx family of DSPs has a unified program and data space. Both programs and
data can reside anywhere in the unified memory space.
The address reach of the C6413/C6418 is 32 bits. The external memory interface
controller (EMIF) divides the off chip address space into 4 equally sized chip enable
(CE) spaces when dealing with external memory. The lower 20 address bits are driven
on the EMIF as address lines while the upper addresses are decoded and driven as the
chip enable for that particular region.
The figure above shows a generic memory space map for a C64xx family processor
and a second map specific to the components on a C6413/C6418 EVM. The SDRAM
occupies chip enable 0. The Flash, UART, and memory mapped registers of the CPLD
share CE1. The Flash accesses start at the lower addresses of the CE1, and occupy
locations 0x900000000 to 0x900EFFFF and the CPLD in the bottom half. The last
remaining locations 0x900F0000 - 0x900FFFFF are mapped to the CPLD and UART.
CE2 is used for expansion daughter card access and CE3 is optionally mapped into
SBRAM or expansion connector access.
Internal memory on the C6413/C6418 starts at address 0 and takes precedence over
any external memory.
Figure 1-2, Memory Map, C6413/C6418 EVM
Internal
Memory
Reserved
or
Peripheral
SDRAM
Flash
CPLD
and
UART
Daughter
Card
or
SBRAM
Internal Memory
Reserved Space
or
Peripheral Regs
EMIF CE0
EMIF CE1
EMIF CE2
EMIF CE3
641x EVM
C64xx Family
Memory Type
Address
0x00000000
0x00030000
0x80000000
0x90000000
0xA0000000
0xB0000000
0x900F0000
Daughter
Card
1.6 Jumper Settings
TheC6413/C6418 EVM has 7 on-board CPU configuration jumpers that define the
DSPs boot configuration and reset state along with one OPT jumper for user
implementation. The figure below shows these jumpers for the C6413.
The figure below shows the jumpers for the C6418.
The jumpers drive signals that directly correspond to the input on one of the DSPs
configuration pins. If the jumper is on, the signal is driven to a logic 0. If the jumper is
off, the signal is driven to a logic 1.
Figure 1-3, JP4, C6413 DSP Boot Configuration - Default Setting
C
L
K
M
2
C
L
K
M
3
C
L
K
I
N
S
E
L
C
L
K
M
1
C
L
K
M
0
O
S
C

*
E
N
D
I
A
N
O
P
T
* Always populated
Figure 1-4, JP4, C6418 DSP Boot Configuration - Default Setting
C
L
K
M
2
C
L
K
M
3
C
L
K
I
N
S
E
L
C
L
K
M
1
C
L
K
M
0
O
S
C

*
E
N
D
I
A
N
O
P
T
* Always populated
1-7
1.6.1 CLKMODE Multiplier
TheC6413/C6418 has a number of clock multiplier modes that are selected at reset by
sampling the CLKMODE[3-0] pins. These pins can be configured with the on-board
jumpers. The jumper configuration is shown in the table below.
Note: * default on C6413
** default on C6418
1.6.2 CLKINSEL
The C6413/C6418 has the option of using an external clock oscillator or internal
oscillator to operate the PLL which controls the internal CPU clock. This clock is input
is selected at reset by the CLKINSEL pin. The EVM provides a configuration jumper to
select either the internal or external oscillator which controls the PLL. When CLKINSEL
is high (installed) AECLKIN is selected for PLL logic. When CLKINSEL is low
(removed) the internal oscillator controls the PLL clock. On theC6413/C6418 EVM
AECLKIN is driven by an external 25 Mhz oscillator, the internal oscillator is connected
to the external crystal which is 25 Mhz
Table 1: TMS320C6413/C6418 EVM CLKMODE Multiplier
CLKM3 CLKM2 CLKM1 CLKM0 Multiplier
Off Off Off Off x24 **
Off Off Off On x22
Off Off On Off x21
Off Off On On x20 *
Off On Off Off x19
Off On Off On x18
Off On On Off x16
Off On On On x12
On Off Off Off x11
On Off Off On x10
On Off On Off x9
On Off On On x8
On On Off Off x7
On On Off On x6
On On On Off x5
On On On On Bypass
1.6.3 Oscillator Disable
The OSC_DIS pin is used to enable the on chip oscillator. On the EVM an external
oscillator is used as the default configuration. However, the board is populated with a
25 Mhz crystal which is enabled by populating JP4 (11 to 12).
For proper operation the CLKINSEL jumper needs to be in configured appropriately to
enable the on board oscillator to control the PLL logic when using enabling or disabling
the on chip oscillator.
1.6.4 Endian Select
The C6413/C6418 can be operated in little endian or big endian memory modes. The
default mode on the EVM is little endian (jumper JP4-13 to 14 removed). When the
jumper is installed the board operates in big endian mode.
1.7 EMIFA Configuration Options
External addresses lines A19-A22 are used to configure the boot mode and EMIF
clock selection at reset. Four pull up and four pull down resistor locations are available
on the EVM to control this configuration. The selections are outlined.
1.7.1 Boot Options
At reset address lines A21 and A22 are sampled to determine the boot option of the
processor. although there are four modes available only 2 modes are not reserved.
These are 8 bit boot from CE1 which is the default on the EVM and no boot.
NOTE:
OSC_DIS jumper should always be populated.
Disabling the oscillator is for chip test functions
only.
1-9
1.7.2 EMIFA Clock Select
Address lines A19 and A20 are sampled at reset and determine the EMIF clock
configuration selection. The EMIF clock is either a divider of the internal CPU clock
controlled by the PLL or is driven directly at the frequency supplied on the AECLKIN
pin.
On the EVM an external PLL is available to drive the AECLKIN pin. The default
frequency of the ICS512 PLL device is 125 Mhz.
Pull ups and pull downs are provided on the EVM to configure the clock selection. The
choices for the EMIF clock configuration are CPUCLK divided by four, CPUCLK divided
by six, AECLKIN. The table below details the choices.
* default
1.8 Power Supply
The EVM operates from a single +5V external power supply connected to the main
power input (J5). Internally, the +5V input is converted into +1.2V or 1.4V and +3.3V
using Texas Instruments voltage regulators. The +1.2V or 1.4V supply is used for the
DSP core while the +3.3V supply is used for the DSP's I/O buffers and all other chips
on the board. The power connector is a 2.5mm barrel-type plug.
There are two power test points on the EVM at JP2 and JP3. All board current passes
through JP2 (the +5V supply). All DSP core current passes through JP3. Normally
these jumpers are both closed. To measure the current passing through remove the
jumpers and connect the pins with a current measuring device.
The EVM also provides +3.3V, supply for the daughter card. It is also possible to
provide the daughter card with +12V and -12V when the optional external power
connector is used.
Table 2: EMIFA Clock Select
A20 A19 R123 R124 R125 R126 Selection
0 0 No-pop 1K No-pop 1K AECLKIN *
0 1 No-pop 1K 1K No-pop CPU/4 Clock Rate
1 0 1K No-pop No-pop 1K CPU/6 Clock Rate
1 1 1K No-pop 1K No-pop Reserved
2-1
Chapter 2
Board Components
This chapter describes the operation of the major board components on
the TMS320C6413/C6418 EVM.
Topic Page
2.1 CPLD (Programmable Logic) 2-2
2.1.1 CPLD Overview 2-2
2.1.2 CPLD Registers 2-3
2.1.3 USER_REG Register 2-4
2.1.4 DC_REG Register 2-4
2.1.5 Version Register 2-5
2.1.6 MISC Register 2-5
2.1.7 LCD Interface 2-6
2.1.8 C6413/C6418 EVM Interface Register 2-7
2.2 AIC23 Codec 2-8
2.3 Sychronous DRAM 2-9
2.4 Flash Memory 2-9
2.5 SBRAM Memory 2-9
2.6 LEDs and DIP Switches 2-9
2.7 Daughter Card Interface 2-10
2.8 TL16C550 UART 2-11
2.1 CPLD (Programmable Logic)
The C6413/C6418 EVM uses an Altera EPM3128TC100-10 Complex Programmable
Logic Device (CPLD) device to implement:
Memory-mapped control/status registers that allow software
control of various board features.
Address decode and memory access logic.
Control of the daughter card interface and signals.
SPI for LCD serial interface.
Assorted "glue" logic that ties the board components together.
2.1.1 CPLD Overview
The CPLD logic is used to implement functionality specific to the EVM. Your own
hardware designs will likely implement a completely different set of functions or take
advantage of the DSPs high level of integration for system design and avoid the use
of external logic completely.
The EMIF on theC6413/C6418 can support several heterogeneous memory types with
a glueless interface. However, to reserve CE2 and CE3 for potential daughter-card use
on the EVM, CE1 is split to include the Flash in its bottom half and the CPLD
memory-mapped registers in its top half. The address decode logic is used to
implement the split.
The CPLD implements simple random logic functions that eliminate the need for
additional discrete devices. In particular, the CPLD aggregates the various reset
signals coming from the reset button and power supervisors and generates a global
reset.
The EPM3128TC100-10 is a 3.3V (5V tolerant), 100-pin QFP device that provides
128 macrocells, 80 I/O pins, and a 10 ns pin-to-pin delay. The device is
EEPROM-based and is in-system programmable via a dedicated JTAG interface
(a 10-pin header on the EVM). The CPLD source files are written in the industry
standard VHDL (Hardware Design Language) and are included with the EVM on the
installation CD-ROM.
2-3
2.1.2 CPLD Registers
The multiple CPLD memory-mapped registers allows users to control CPLD functions
in software. On theC6413/C6418 EVM the registers are primarily used to access the
LEDs and DIP switches, provide LCD interface, and control the daughter card interface.
The registers are mapped into the EMIF data space at word address 0x900F010, in the
upper portion of CE1. They appear as 8-bit registers with a simple 8-bit asynchronous
memory interface. The following table gives a high level overview of the CPLD
registers and their bit fields:
The table below shows the bit definitions for the 7 registers in CPLD.
Table 1: CPLD Register Definitions
Offset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 USER_REG USR_SW3
R
USR_SW2
R
USR_SW1
R
USR_SW0
R
USR_LED3
R/W
0(Off)
USR_LED2
R/W
0(Off)
USR_LED1
R/W
0(Off)
USR_LED0
R/W
0(Off)
1 DC_REG DC_DET
R
Reserved DC_STAT1
R
DC_STAT0
R
DC_RST
R
0(No reset)
0 DC_CNTL1
R/W
0(low)
DC_CNTL0
R/W
0(low)
2 Reserved
3 Reserved
4 VERSION CPLD_VER[3.0]
R
0 BOARD VERSION[2.0]
R
5 Reserved
6 MISC McBSP0
On/Off
R/W
0
(Onboard)
Reserved Reserved Reserved Reserved Reserved McBSP2
ON/OFF
Board
R/W
0
(Onboard)
McBSP1
ON/OFF
Board
R/W
0
(Onboard)
7 Reserved
8 LCD_REG0 SHIFT
DATA7
SHIFT
DATA6
SHIFT
DATA5
SHIFT
DATA4
SHIFT
DATA3
SHIFT
DATA2
SHIFT
DATA1
SHIFT
DATA0
9 LCD_REG1 SHIFT
DATA7
SHIFT
DATA6
SHIFT
DATA5
SHIFT
DATA4
SHIFT
DATA3
SHIFT
DATA2
SHIFT
DATA1
SHIFT
DATA0
A BOARD LCD Busy
R
1 BUSY
LCD Reset
R/W
0
Reserved
R
Reserved
R
SBRAM
Enable
R/W
(0 Disabled)
Expansion
I
2
C Port 1
R/W
(0 Off)
Expansion
I
2
C Port 0
R/W
(0 Off)
Reserved

2.1.3 USER_REG Register
USER_REG is used to read the state of the 4 DIP switches and turn the 4 LEDs on or
off to allow the user to interact with the EVM. The DIP switches are read by reading the
top 4 bits of the register and the LEDs are set by writing to the low 4 bits.
2.1.4 DC_REG Register
DC_REG is used to monitor and control the daughter card interface. DC_DET detects
the presence of a daughter card. DC_STAT and DC_CNTL provide simple
communications with the daughter card through readable status lines and writable
control lines.
The daughter card is released from reset when the DSP is released from reset.
DC_RST can be used to put the card back in reset.
Table 2: CPLD USER_REG Register
Bit Name R/W Description
7 USER_SW3 R User DIP Switch 3(1 = Off, 0 = On)
3 USER_LED3 R/W User-defined LED 3 Control (0 = Off, 1 = On)
Table 3: DC_REG Register
7 DC_DET R Daughter Card Detect (1= Board detected)
6 0 R Always 0
5 DC_STAT1 R Daughter Card Status 1 (0=Low, 1 = High)
4 DC_STAT0 R Daughter Card Status 0 (0=Low, 1 = High)
3 DC_RST R/W Daughter Card Reset (0=No Reset, 1 = Reset)
2 0 R Always zero
1 DC_CNTL1 R/W Daughter Card Control 1(0 = Low, 1 = High)
0 DC_CNTL0 R/W Daughter Card Control 0(0 = Low, 1 = High)
2-5
2.1.5 VERSION Register
The VERSION register contains two read only fields that indicate the BOARD and
CPLD versions. This register will allow your software to differentiate between
production releases of the EVM and account for any variances. This register is not
expected to change often, if at all.
2.1.6 MISC Register
The MISC register is used to provide software control for miscellaneous board
functions. On theC6413/C6418 EVM, the MISC register controls how auxiliary signals
are brought out to the daughter-card connectors.
McBSP0SEL, McBSP1SEL and McBSP2SEL control the McBSP0, McBSP1 and
McBSP2 respectively. Usually these ports are used to interface ports to the on-board
AIC23 codec, the RS-232 UART driver, or SPI Serial ROM as examples. The
power-on state of these bits (both 0s) represents that situation. Setting the
corresponding bit to 1 enables the McBSP to the expansion daughter-card instead
interface.
Table 4: Version Register Bit Definitions
Bit # Name R/W Description
7 CPLD_VER3 R Most Significant CPLD Version Bit
6 CPLD_VER2 R CPLD Version Bit
5 CPLD_VER1 R CPLD Version Bit
4 CPLD_VER0 R Least Significant CPLD Version Bit
3 0 R Always 0
2 EVM_VER2 R Most Significant EVM Board Version Bit
1 EVM_VER1 R EVM Board Version Bit
0 EVM_VER0 R Least Significant EVM Board Version Bit
Table 5: MISC Register
7 McBSP0SEL0 R/W McBSP0 on/off board (0 = on-board, 1 = off-board)
6 Reserved R Reserved
1 MCBSP2SEL R/W McBSP2 on/off board (0 = on-board, 1 = off-board)
0 MCBSP1SEL R/W McBSP1 on/off board (0 = on-board, 1 = off-board)
2.1.7 LCD Interface
The Liquid Crystal Display (LCD) is a write only interface. It is interfaced via an 8-bit
shift register.
Two locations are used when interfacing the LCD panel. Allowing the address bit of the
interface to be directly programmed. The shift clock frequency is 5 megahertz.
Writing register LCD0 sets the LCD address line A0 to 0. Writing register LCD1 sets the
LCD address line A0 to 1. The write operation to either of these locations starts an
internal shift register serializing the data into an 8-bit sequence to the displays.
The table below shows the relationship of the DSP data bits to the LCD data bits.
The figure below shows the LCD data transfer timing. the CPLD automatically
generates this timing.
After any write operations the CPLD sets the LCD BUSY bit in the C6413/C6418 EVM
interface Register as the output is being serialized. The user should check this bit prior
to starting another write operation. When LCD BUSY is high, the LCD shift register is
busy, when is low the shift register is ready.
Table 6: LCD Interface
D7 D6 D5 D4 D3 D2 D1 D0
LCD D7 LCD D6 LCD D5 LCD D4 LCD D3 LCD D2 LCD D1 LCD D0
LCDCLK
LCD Address
LCD Data D7 D6 D5 D4 D3 D2 D1 D0
Figure 2-3, LCD Data Transfer Timing
2-7
2.1.8 C6413/C6418 EVM Interface Register
The C6413/C6418 EVM Interface Register implements specific logic for the C6413/
C6418 EVM. The bits used in this register and their function are described in the table
below.
LCD Busy indicates the status of the CPLD implemented shift register which interfaces
to the LCD panel. A 1 logic level indicates the shift register is busy, A 0 logic level
indicates the shift register is ready.
LCD Reset allows the LCD Reset bit to be toggled under software control. A 1 logic
level forces the LCD panel into reset. A 0 logic level removes the LCD reset to normal
state.
SBRAM Enable determines if Chip Enable 3 is used to interface to the on board
SBRAM or the daughter card interface. The default (logic 0) is that the SBRAM is
enabled.
I
2
C Expansion bit enables/disables driving the I
2
C interface to the daughter card
expansion bus. A 1 logic level enables the I
2
C bus to the daughter card interface. A
0 logic level disables the interface. Default state is disabled.
Table 7: C6413/C6418 EVM Interface Register
7 LCD Busy R 0 = busy, not ready, 1 = not busy, ready
6 LCD Reset R/W 0 = removes reset from LCD, 1 = forces LCD into reset
5 Reserved
4 Reserved
3 SBRAM
Disable
R/W 0 = SBRAM Enabled, 1 = SBRAM Disabled
2
I
2
C Expansion
Port 0
R/W
0 = Disables I
2
C interface to expansion connector
1 = Enables I
2
1 2
C Expansion
Port 1
R/W
0 = Disables I
2
1 = Enables I
2
0 Reserved R
2.2 AIC23 Codec
The EVM uses a Texas Instruments AIC23 (part #TLV320AIC23) stereo codec for input
and output of audio signals. The codec samples analog signals on the microphone or
line inputs and converts them into digital data so it can be processed by the DSP.
When the DSP is finished with the data it uses the codec to convert the samples back
into analog signals on the line and headphone outputs so the user can hear the output.
The codec communicates using two serial channels, one to control the codecs internal
configuration registers and one to send and receive digital audio samples. The I
2
C bus
is used as the unidirectional control channel. The control channel is only used when
configuring the codec, it is generally idle when audio data is being transmitted,
McBSP1 is used as the bi-directional data channel. All audio data flows through the
data channel. Many data formats are supported based on the three variables of
sample width, clock signal source and serial data format. The EVM examples generally
use a 16-bit sample width with the codec in master mode so it generates the frame
sync and bit clocks at the correct sample rate without effort on the DSP side. The
preferred serial format is DSP mode which is designed specifically to operate with the
McBSP ports on TI DSPs.
The codec has a 12MHz system clock. The 12MHz system clock corresponds to USB
sample rate mode, named because many USB systems use a 12MHz clock and can
use the same clock for both the codec and USB controller. The internal sample rate
generate subdivides the 12MHz clock to generate common frequencies such as
48KHz, 44.1KHz and 8KHz. The sample rate is set by the codecs SAMPLERATE
register. The figure below shows the Codec interface on the C6413/C6418 EVM.
Figure 2-1, TMS320C6413/C6418 EVM CODEC INTERFACE
MIC IN
LINE IN
LINE OUT
HP OUT
ADC
DAC
McBSP1
DSP Format
0 LEFTINVOL
1 RIGHTINVOL
2 LEFTHPVOL
3 RIGHTHPVOL
4 ANAPATH
5 DIGPATH
6 POWERDOWN
7 DIGIF
8 SAMPLERATE
9 DIGACT
15 RESET
C
o
n
t
r
o
l

R
e
g
i
s
t
e
r
s
LRCIN
BCLK
DIN
DOUT
LRCOUT
FSX1
DX1
CLKX1
FSR1
CLKR1
DR1
AIC23 Codec
Digital Analog
MIC IN
LINE IN
LINE OUT
HP OUT
SCLK
SDIN
I
2
C
Control
SCL0
SDA0
I
2
C Format
2-9
2.3 Synchronous DRAM
The EVM uses an industry standard 64 megabit Synchronous SDRAM. It uses a 32-bit
interface and is used with up a maximum 100 MHz. memory clock. Since the DSP runs
at 500 or 600 MHz, the EMIF must be programmed to use the SDRAM at a divider of
the core clock rate or use the alternate EMIF Clock input.
The SDRAM occupies chip enable 0.
SDRAM must be constantly refreshed to maintain the integrity of its contents. This
SDRAM must update one row every 15.6 microseconds to meet its minimum
requirements. The EMIF can be programmed to automatically generate refresh signals
based on this time period.
2.4 Flash Memory
The EVM provides two devices each consisting of 256K x 16-bit words of external
Flash memory. The board itself is pinned out to allow expansion to 1M 32 bit words.
Typically the Flash is mapped into CE1 space because that is where the bootloader
looks for a boot image when booting from the Flash. Because the bootloader default
configuration is 8 bit boot mode usually only the Flash on D0-D7 is used. The CE1
space is shared by the CPLD, UART, and the Flash, but the CPLD timings are
subsetted by the Flash so the Flash is the critical factor in configuring CE1.
The Flash itself is a 70ns device but some additional delays are incurred in the CPLD
logic that separates the Flash and CPLD registers. Because of this, the EMIF should
be programmed for an access time of at least 80ns, and typically 100 ns.
2.5 SBRAM Memory
The EVM has 1 megabyte of SBRAM optionally mapped in CE3 space. If the SBRAM is
not used CE3 can be used for expansion daughter card accesses by disabling the
secondary chip select on the SBRAM via the Board Register in the CPLD.
2.6 LEDs and DIP Switches
The EVM includes 4 software accessible LEDs (DS1-DS4) and DIP switches (S2) that
provide the user a simple form of input/output. Both are accessed through the CPLD
USER_REG register.
2.7 Daughter Card Interface
The EVM provides three expansion connectors that can be used to accept plug-in
daughter cards. The daughter card allows users to build on their EVM platform to
extend its capabilities and provide customer and application specific I/O. The
expansion connectors are for memory, peripherals, and the Host Port Interface (HPI)
The memory connector provides access to the DSPs asynchronous EMIF signals to
interface with memories and memory mapped devices. It supports byte addressing on
32 bit boundries. The peripheral connector brings out the DSPs peripheral signals like
McBSPs, timers, and clocks. Both connectors provide power and ground to the
daughter card
The HPI is a high speed interface that can be used to allow multiple DSPs to
communicate and cooperate on a given task. The HPI connector brings out the HPI
specific control signals as well as McBSP2.
Most of the expansion connector signals are buffered so that the daughter card cannot
directly influence the operation of the EVM board. The use of TI low voltage, 5V tolerant
buffers, and CBT interface devices allows the use of either +5V or +3.3V devices to be
used on the daughter card.
Other than the buffering, most daughter card signals are not modified on the board.
However, a few daughter card specific control signals like DC_RESET and
DC_DET exist and are accessible through the CPLD DC_REG register. The EVM
also multiplexes the Mc_BSP0, McBSP1, and McBSP2 for on-board or external use.
This function is controlled through the CPLD MISC register.
The timer signals on the peripheral expansion connector have connections for both
inputs and outputs. These map to the TIN and TOUT pins on the C6413/C6418 device.
2-11
2.8 TL16C550 UART
The C6413/C6418 EVM has an on board TLC16C550 UART. The UART is buffered
with a SN75LV4737A RS-232 line driver and is routed to a male 9 pin D-connector, P4.
The pin positions for the P4 connector as viewed from the edge of the printed
circuit board are shown below.
The pin numbers and their corresponding signals are shown in the table below. This
corresponds to a standard dual row to DB-9 connector interface used on personal
computers.

The UART occupies 8 locations mapped at address 0x900F0000 - 0x900F000F in
CE1 space with the EMIF in 8 bit synchronous memory mode. The UART uses the NMI
interrupt for interrupt based communication.
Table 8: P4, RS-232 Pinout
Pin #
Target
Signal Name
Target
Direction
1 Reserved Not Used
2 TXD Out
3 RXD In
4 DSR In
5 GND N/A
6 DTR Out
7 CTS In
8 RRTS Out
9 Reserved Not Used
9
5 4 3 2 1
8 7 6
Figure 3-9, P4, DB9 Male Connector
3-1
Chapter 3
Physical Description
This chapter describes the physical layout of the TMS320C6413/C6418
EVM and its connectors.
Topic Page
3.1 TMS320C6413/C6418 EVM Board Layout 3-2
3.2 Keypad/display Module Layout 3-3
3.3 Connector Index 3-4
3.4 Expansion Connectors 3-4
3.4.1 P1, Memory Expansion Connector 3-5
3.4.2 P2, Peripheral Expansion Connector 3-6
3.4.3 P3, HPI Expansion Connector 3-7
3.5 Audio Connectors 3-8
3.5.1 J1, Microphone Connector 3-8
3.5.2 J2, Audio Line In Connector 3-8
3.5.3 J3, Audio Line Out Connector 3-9
3.5.4 J4, Headphone Connector 3-9
3.6 Power Connectors 3-10
3.6.1 J5, +5 Volt Connector 3-10
3.6.2 J6, Alternate Power Connector 3-10
3.7 Miscellaneous Connectors 3-11
3.7.1 J8, RS-232 Connector 3-11
3.7.2 J7, External JTAG Connector 3-11
3.7.3 JP1, PLD Programming Connector 3-12
3.8 P5, Keypad/Display Connector 3-12
3.9 System LEDs 3-12
3.10 Reset Circuitry 3-12
3.1 TMS320C6413/C6418 EVM Board Layout
The C6413/C6418 EVM is a 8.25 x 4.5 inch (210 x 115 mm.) multi-layer board which is
powered by an external +5 volt only power supply. The figure below shows the layout of
the C6413/C6418 EVM.
Figure 3-1, TMS320C6413/C6418 EVM
P1
JP4
J2
J5
J6
J1
P2
P3
JP1
J3
J4
J7 S1
S2
DS1-4 DS5 DS7 P5 P4
JP2
JP5
JP3
3-3
3.2 Keypad/display Module Layout
The Keypad/display Module is a 3.1 x 4.4 inch (79 x 112 mm.) multi-layer board
which is powered from the EVM. The figure below shows the layout of the
Keypad/display Module.
Figure 3-2, Keypad/display Module

3.3 Connector Index
The TMS320C6413/C6418 EVM has many connectors which provide the user access
to the various signals on the EVM.
Note: * Not populated
3.4 Expansion Connectors
The TMS320C6413/C6418 EVM supports three expansion connectors that follow the
Texas Instruments interconnection guidelines. The expansion connector pinouts are
described in the following three sections.
The three expansion connectors are all 80 pin 0.050 x 0.050 inches low profile
connectors from Samtec or AMP. The Samtec SFM Series (surface mount) connectors
are designed for high speed interconnections because they have low propagation
delay, capacitance, and cross talk. The connectors present a small foot print on the
EVM. Each connector includes multiple ground, +5V, and +3.3V power signals so that
the daughter card can obtain power directly from the EVM. The peripheral expansion
connector additionally provides both +12V and -12V to the daughter card, if the
alternate power supply connector is used to power the board. The recommended
mating connector, whose part number is TFM-140-32-S-D-LC, is a surface mount
connector that provides a 0.465 mated height.
Note: I is on an Input pin
O is on an Output pin
Z is on a High Impedance pin
Table 1: TMS320C6413/C6418 EVM Connectors
Connector # Pins Function
P1 80 Memory
P2 80 Peripheral
P3 80 HPI
P4 9 RS-232 Port
P5 16 Display - Keypad
J1 2 Microphone
J2 2 Line In
J3 2 Line Out
J4 2 Speaker
J5 2 +5 Volt
J6 * 4 Alternate Power Connector
J7 14 External JTAG
3-5
3.4.1 P1, Memory Expansion Connector
Table 2: P1, Memory Expansion Connector
Pin # Signal Name I/O/Z Pin # Signal Name I/O/Z
1 +5 Volts O 2 +5 volts O
3 A21 O 4 A20 O
5 A19 O 6 A18 O
7 A17 O 8 A16 O
9 A15 O 10 A14 O
11 GND O 12 GND O
13 A13 O 14 A12 O
15 A11 O 16 A10 O
17 A9 O 18 A8 O
19 A7 O 20 A6 O
21 +5 Volts O 22 +5 Volts O
23 A5 O 24 A4 O
25 A3 O 26 A2 O
27 BE3n O 28 BE2n O
29 BE1n O 30 BE0n O
31 GND O 32 GND O
33 D31 I/O/Z 34 D30 I/O/Z
35 D29 I/O/Z 36 D28 I/O/Z
37 D27 I/O/Z 38 D26 I/O/Z
39 D25 I/O/Z 40 D24 I/O/Z
41 +3.3 Volts O 42 +3.3 Volts O
43 D23 I/O/Z 44 D22 I/O/Z
45 D21 I/O/Z 46 D20 I/O/Z
47 D19 I/O/Z 48 D18 I/O/Z
49 D17 I/O/Z 50 D16 I/O/Z
51 GND O 52 GND O
53 D15 I/O/Z 54 D14 I/O/Z
55 D13 I/O/Z 56 D12 I/O/Z
57 D11 I/O/Z 58 D10 I/O/Z
59 D9 I/O/Z 60 D8 I/O/Z
61 GND O 62 GND O
63 D7 I/O/Z 64 D6 I/O/Z
65 D5 I/O/Z 66 D4 I/O/Z
67 D3 I/O/Z 68 D2 I/O/Z
69 D1 O 70 D0 O
71 GND O 72 GND O
73 REn O 74 WEn O
75 OEn O 76 RDYn I
77 CE3n O 78 CE2n O
79 GND O 80 GND O
3.4.2 P2, Peripheral Expansion Connector
* Enable via CPLD Bit
Table 3: P2, Peripheral Expansion Connector
1 +12 Volts * O 2 -12 Volts * O
3 GND O 4 GND O
7 GND O 8 GND O
11
* I
2
C SCL1
O/Z 12
* I
2
C SDA1
I/O/Z
13 RESERVED 14 RESERVED
19 +3.3 Volts O 20 +3.3 Volts O
21 CLKX0 I/O/Z 22 CLKS0
23 FSX0 I/O/Z 24 DX0 O/Z
25 GND O 26 GND O
27 CLKR0 I/O/Z 28 RESERVED
29 FSR0 I/O/Z 30 DR0 I
31 GND O 32 GND O
33 CLKX1 I/O/Z 34 CLKS1 I
35 FSX1 I/O/Z 36 DX1 O/Z
37 GND O 38 GND O
39 CLKR1 I/O/Z 40 RESERVED
41 FSR1 I/O/Z 42 DR1 Z
43 GND O 44 GND O
45 TOUT0 Z 46 TIN0 I
47 INT0n I 48 INT5n I
49 TOUT1 O 50 TIN1 I
51 GND O 52 GND O
53 INT4n I 54 IACKn I
55 RESERVED 56 INT7n O
57 RESERVED 58 RESERVED I
59 RESETn O 60 RESERVED
61 GND O 62 GND O
63 DC_CNTL1 O 64 DC_CNTL0 O
65 DC_STAT1 I 66 DC_STAT0 I
67 INT6n I 68 RESERVED
75 DETECTn I 76 GND O
77 GND O 78 CLKOUT O
79 GND O 80 GND O
3-7
3.4.3 P3, HPI Expansion Connector
Table 4: P3, HPI Expansion Connector
1 Reserved O 2 +5 Volts O
3 GND I/O/Z 4 HPI_RESET I/O/Z
5 GP0 I/O/Z 6 GP3 I/O/Z
7 HD30 O/Z 8 HD31 I
9 GND I/O 10 GND I
11 HD28/AMUTE1 O 12 HD29/AMUTEIN1 O
13 HD26/AHCHKR1 I 14 HD27/AHCLKX1 I
15 HD24/ACLKX1 I 16 HD25/ACLKR1 I
17 HD22/AFSX1 I/O 18 HD23/AFSR1 I/O
19 GND I 20 GND I
21 HD20/AXR1[4] O 22 HD21/AXR1[5] O
23 HD18/AXR1[2] O/Z 24 HD19/AXR1[3] O/Z
25 HD16/AXr1[0] I 26 HD17/AXR1[1] I
27 HD14/GP14 I 28 HD15/GP15 I
29 GND I 30 GND I
31 HD12/GP12 O 32 HD13/GP13 O
33 HD10/GP10 I 34 HD11/GP11 I
35 HD8/GP8 I 36 HD9/GP9 I
37 HD6 I 38 HD7 I
39 GND I 40 GND I
41 HD4 O 42 HD5 O
43 HD2 I 44 HD3 I
45 HD0 I 46 HD1 I
47 HCTL1/EATCLK I 48 HRDY/ATCLK I
49 GND I 50 GND I
51 HAS/ACLKR1[1] O 52 HINT/MODCLK O
53 HCS/ACLKR1[2] I/O/Z 54 HCTL0/AFSR1[1] I/O/Z
55 HDS1/ACLKR1[3] I/O/Z 56 HWIL/AFSR1[2] I/O/Z
57 HDS2 I/O/Z 58 HRW/AFSR1[3] I/O/Z
59 GND I/O/Z 60 GND I/O/Z
61 AXR0[2] O 62 AXR0[0] O
63 AXR0[4] I/O/Z 64 AXR0[1] I/O/Z
65 AXR0[5] I/O/Z 66 AXR0[3] I/O/Z
67 AHCLKX0 I/O/Z 68
I
2
C SCL0
I/O/Z
69 ACLKX0 I/O/Z 70 GND I/O/Z
71 AHCLKR0 O 72
I
2
C SDA0
O
73 ACLKR0 O/Z 74 GND I
75 AFSR0 I 76 AMUTE0 I/O
77 AFSX0 O 78 AMUTEIN0 I
79 GND O 80 GND O
3.5 Audio Connectors
The C6413/C6418 EVM has 4 audio connectors. They are described in the following
sections.
3.5.1 J1, Microphone Connector
The input is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it is
monaural. The signals on the plug are shown in the figure below.
3.5.2 J2, Audio Line In Connector
The audio line in is a stereo input. The input connector is a 3.5 mm stereo jack. The
signals on the mating plug are shown in the figure below.
Microphone In
Ground
Figure 3-3, Microphone Stereo Jack
Microphone Bias
Left Line In
Ground
Figure 3-4, Audio Line In Stereo Jack
Right Line In
3-9
3.5.3 J3, Audio Line Out Connector
The audio line out is a stereo output. The output connector is a 3.5 mm stereo jack. The
signals on the mating plug are shown in the figure below.
3.5.4 J4, Headphone Connector
Connector J4 is a headphone/speaker jack. It can drive standard headphones or a high
impedance speaker directly. The standard 3.5 mm jack is shown in the figure below
.
Left Line Out
Ground
Figure 3-5, Audio Line Out Stereo Jack
Right Line Out
Left Headphone
Ground
Figure 3-6, Headphone Jack
Right Headphone
3.6 Power Connectors
The C6413/C6418 EVM has 2 power connectors. They are described in the following
sections.
3.6.1 J5, +5 Volt Connector
Power (+5 volts) is brought onto the TMS320C6413/C6418 EVM via the J5 connector.
The connector has an outside diameter of 5.5 mm. and an inside diameter of 2.5 mm.
The A diagram of J5 is shown below.
3.6.2 J6, Alternate Power Connector
Connector J6 is an alternate power connector. It will operate with the standard personal
computer power supply. To populate this connector use a Molex #53109-0410. The
table below shows the voltages on the respective pins.
Table 5: J6, Optional Power Connector
Pin # Voltage Level
1 +12 Volts
2 -12 Volts
3 Ground
4 +5 Volts
PC Board
J5
+5V
Ground
Front View
Figure 3-7, TMS320C6413/C6418 EVM Power Connector
WARNING !
Do not plug into J5 and J6 at the same time.
3-11
3.7 Miscellaneous Connectors
The C6413/C6418 EVM has 3 additional connectors to aid the user in developing with
this product. They are described in the following sections.
3.7.1 P4, RS-232 Connector
Connector P4 is a female RS-232 providing an interface to the UART. The signals on
this connector are shown in the below.
3.7.2 J7, External JTAG Connector
The TMS320C6413/C6418 EVM is supplied with a 14 pin header interface, J7. This is
the standard interface used by JTAG emulators to interface to Texas Instruments
DSPs. The pinout for the connector is shown figure 3-6 below.

Table 6: P4, RS-232 Connector
Pin # Signal Name Direction
1 Reserved
2 Transmit Data Output
3 Receive Data Input
4 Reserved
5 Ground Output
6 Reserved
7 CTS Input
8 RTS Output
9 Reserved
1 2
3 4
5 6
7 8
9
10
11
12
13 14
TMS
TDI
PD (+3.3V)
TDO
TCK-RET
TCK
EMU0
TRST-
GND
no pin (key)
GND
GND
GND
EMU1
Header Dimensions
Pin-to-Pin spacing, 0.100 in. (X,Y)
Pin width, 0.025-in. square post
Pin length, 0.235-in. nominal
Figure 3-8, JTAG INTERFACE
3.7.3 JP1, PLD Programming Connector
This connector interfaces to the Altera CPLD, U2. It is used in the in the factory for the
programming of the CPLD. This connector is not intended to be used outside the
factory.
3.8 P5, Keypad/Display Connector
The EVM supports a 16 pin 2 mm. connector which interfaces to the keypad/display
unit. The signals on the 8 x 2 connector are shown in the table below.
3.9 System LEDs
TheTMS320C6413/C6418 EVM has two system light emitting diodes (LEDs). These
LEDs indicate various conditions on the EVM. These function of each LED is shown in
the table below.
3.10 Reset Circuitry
There are three resets on the TMS320C6413/C6418 EVM. The first reset is the power
on reset. This circuit waits until power is within the specified range before releasing the
power on reset pin to the TMS320C6413/C6418.
External sources which control the reset are push button S1, and HPI Reset from the
expansion connector.
Table 7: System LEDs
Pin # Signal Pin # Signal
1 2 1
3 4 1
5 6
7 8
9 10
11 12
13 14
15 16
Table 8: System LEDs
Reference
Designator
Color Function
On Signal
State
DS6 Green +5 Volt present 1
DS5 Orange RESET Active 1
A-1
Appendix A
Schematics
This appendix contains the schematics for the TMS320C6413/C6418 EVM
and the keypad/display module.
Topic Page
A.1 TMS320C6413/C6418 EVM Schematics A-2
A.2 Keypad/display Module Schematics A-26
A-2 TMS320CC6413/6418 EVM Module Technical Reference
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B-1
Appendix B
Mechanical Information
This appendix contains the mechanical information about the
TMS320C6413/C6418 EVM and Keypad/display Module produced by
Spectrum Digital.
Topic Page
B.1 TMS320C6413/C6418 EVM Mechanical Information B-2
B.2 Keypad/display Module Mechanical Information B-3
B-2 TMS320C6418 EVM Module Technical Reference
T
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E
B-4 TMS320C6418 EVM Module Technical Reference

Printed in U.S.A., October 2004
507265-0001 Rev. B

TMS320C6413/C6418 EVM: Reference Technical

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