TC1724 DS v12-785810

32-Bit
Microcontroller
TC1724
32-Bit Single-Chip Microcontroller
Data Sheet
V1.2 2014-06
Microcontrollers
Edition 2014-06
Published by
Infineon Technologies AG
81726 Munich, Germany
2014 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
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32-Bit
Microcontroller
TC1724
32-Bit Single-Chip Microcontroller
Data Sheet
V1.2 2014-06
Microcontrollers
TC1724
Table of Contents
Table of Contents
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2 System Overview of the TC1724 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
4 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
5 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1.2 Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.1.4 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.1.5 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.2.1 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.2.2 Analog to Digital Converters (ADCx) . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
5.2.3 Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . . 5-34
5.2.4 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39
5.2.5 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40
5.2.5.1 Calculating the 1.3 V Current Consumption . . . . . . . . . . . . . . . . . 5-45
5.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47
5.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47
5.3.2 Power Sequencing 5V Supply Only . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48
5.3.3 Power Sequencing 3.3V Supply Only . . . . . . . . . . . . . . . . . . . . . . . . 5-50
5.3.4 Power Sequencing all Voltages supplied from External . . . . . . . . . . 5-52
5.3.5 Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54
5.3.6 EVR Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57
5.3.7 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60
5.3.8 ERAY Phase Locked Loop (ERAY_PLL) . . . . . . . . . . . . . . . . . . . . . . 5-62
5.3.9 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63
5.3.10 DAP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65
5.3.11 Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67
5.3.11.1 Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . 5-67
5.3.11.2 Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . 5-69
5.3.11.3 SSC Master/Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 5-72
5.3.11.4 ERAY Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-75
5.4 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-77
5.4.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-77
5.4.2 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78
Data Sheet I-1 V1.2, 2014-06

TC1724
Table of Contents
5.4.3 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78

5.4.4 Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-80
5.5 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-81
Data Sheet I-2 V1.2, 2014-06

TC1724
Summary of Features
1 Summary of Features
The SAK-TC1724F-192F133HL / SAK-TC1724F-192F133HR has the following
features:
High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline
Superior real-time performance
Strong bit handling
Fully integrated DSP capabilities
Single precision Floating Point Unit (FPU)
133 MHz operation at full temperature range
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
8 Kbyte Parameter Memory (PRAM)
24 Kbyte Code Memory (CMEM)
Multiple on-chip memories
1.5 Mbyte Program Flash Memory (PFLASH) with ECC
64 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
120 Kbyte Data Memory (LDRAM)
Instruction Cache: up to 8Kbyte (ICACHE, configurable)
24 Kbyte Code Scratchpad Memory (SPRAM)
Data Cache: up to 4 Kbyte (DCACHE, configurable)
8 Kbyte Overlay Memory (OVRAM)
16 Kbyte BootROM (BROM)
16-Channel DMA Controller
Sophisticated interrupt system with 2 255 hardware priority arbitration levels
serviced by CPU or PCP2
High performing on-chip bus structure
64-bit Local Memory Buses between CPU, Flash and Data Memory
32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
One bus bridge (LFI Bridge)
Versatile On-chip Peripheral Units
Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
Four High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
One serial Micro Second Bus interface (MSC) for serial port expansion to external
power devices
One High-Speed Micro Link interface (MLI) for serial inter-processor
communication
One MultiCAN Module with 3 CAN nodes and 64 free assignable message objects
for high efficiency data handling via FIFO buffering and gateway data transfer
One FlexRayTM module with 2 channels (E-Ray).
Data Sheet 1-1 V1.2, 2014-06

TC1724
Summary of Features
One General Purpose Timer Array Module (GPTA) providing a powerful set of
digital signal filtering and timer functionality to realize autonomous and complex
Input/Output management
Two Capture/Compare Unit 6 (CAPCOM6) kernels
Two General Purpose Timer (GPT12) modules
28 analog input lines for ADC
2 independent kernels (ADC0 and ADC1)
Analog supply voltage range from 3.3 V to 5 V (single supply)
Broken wire detection
2 different FADC input channels
channels with impedance control and overlaid with ADC1 inputs
Extreme fast conversion, 21 cycles of fFADC clock
10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
95 digital general purpose I/O lines (GPIO)
Digital I/O ports with 3.3 V capability
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
Dedicated Emulation Device chip available (TC1724ED)
multi-core debugging, real time tracing, and calibration
four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
Power Management System
Clock Generation Unit with PLL
Data Sheet 1-2 V1.2, 2014-06

TC1724
Summary of Features
The SAK-TC1724N-192F133HR has the following features:

Strong bit handling
power devices
communication
Data Sheet 1-3 V1.2, 2014-06

TC1724
Summary of Features

Data Sheet 1-4 V1.2, 2014-06

TC1724
Summary of Features
The SAK-TC1724N-192F80HL / SAK-TC1724N-192F80HR has the following features:

Strong bit handling
power devices
communication
Data Sheet 1-5 V1.2, 2014-06

TC1724
Summary of Features

Data Sheet 1-6 V1.2, 2014-06

TC1724
Summary of Features
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
The derivative itself, i.e. its function set, the temperature range, and the supply
voltage
The package and the type of delivery.
For the available ordering codes for the TC1724 please refer to the Product Catalog
Microcontrollers, which summarizes all available microcontroller variants.
This document describes the derivatives of the device.The Table 1 enumerates these
derivatives and summarizes the differences.
Table 1 TC1724 Derivative Synopsis

Derivative Ambient CPU/PCP Flash ERAY Wire
Temperatur Freq. Size Bond
e Range (TA) Material
SAK-TC1724F-192F133HL -40oC to 133 MHz 1.5 MB Yes Au
+125oC
SAK-TC1724F-192F133HR1) -40oC to 133 MHz 1.5 MB Yes Cu
+125oC
SAK-TC1724N-192F133HR -40oC to 133 MHz 1.5 MB No Cu
+125oC
SAK-TC1724N-192F80HL -40oC to 80 MHz 1.5 MB No Au
+125oC
SAK-TC1724N-192F80HR2) -40oC to 80 MHz 1.5 MB No Cu
+125oC
1) This derivative has the same features as the SAK-TC1724F-192F133HL, except the wire-bonding material.
2) This derivative has the same features as the SAK-TC1724N-192F80HL, except the wire-bonding material.
Data Sheet 1-7 V1.2, 2014-06

TC1724
System Overview of the TC1724
2 System Overview of the TC1724

The TC1724 combines three powerful technologies within one silicon die, achieving new
levels of power, speed, and economy for embedded applications:
Reduced Instruction Set Computing (RISC) processor architecture
Digital Signal Processing (DSP) operations and addressing modes
On-chip memories and peripherals
DSP operations and addressing modes provide the computational power necessary to
efficiently analyze complex real-world signals. The RISC load/store architecture
provides high computational bandwidth with low system cost. On-chip memory and
peripherals are designed to support even the most demanding high-bandwidth real-time
embedded control-systems tasks.
Additional high-level features of the TC1724 include:
Efficient memory organization: instruction and data scratch memories, caches
Serial communication interfaces flexible synchronous and asynchronous modes
Peripheral Control Processor standalone data operations and interrupt servicing
DMA Controller DMA operations and interrupt servicing
General-purpose timers
High-performance on-chip buses
On-chip debugging and emulation facilities
Flexible interconnections to external components
Flexible power-management
The TC1724 is a high-performance microcontroller with TriCore CPU, program and data
memories, buses, bus arbitration, an interrupt controller, a peripheral control processor
and a DMA controller and several on-chip peripherals. The TC1724 is designed to meet
the needs of the most demanding embedded control systems applications where the
competing issues of price/performance, real-time responsiveness, computational power,
data bandwidth, and power consumption are key design elements.
The TC1724 offers several versatile on-chip peripheral units such as serial controllers,
timer units, CAPCOM6 and Analog-to-Digital converters. Within the TC1724, all these
peripheral units are connected to the TriCore CPU/system via the Flexible Peripheral
Interconnect (FPI) Bus and the Local Memory Bus (LMB). Several I/O lines on the
TC1724 ports are reserved for these peripheral units to communicate with the external
world.
Data Sheet 2-1 V1.2, 2014-06

TC1724
2.1 Block Diagrams

Figure 1 shows the block diagram of the SAK-TC1724F-192F133HL / SAK-TC1724F-
192F133HR.
Abbreviations:
ICACHE: Instruction Cache
DCACHE Data Cache
FPU SPRAM: Scratch-Pad RAM
PMI DMI LDRAM: Local Data RAM
TriCore OVRAM: Overlay RAM
16 KB SPRAM CPU 116 KB LDRAM BROM: Boot ROM
8 KB ICACHE TC1.3.1 4 KB DCACHE PFlash: Program Flash
133MHz
(Configurable) DFlash: Data Flash
(Configurable) PRAM: Parameter RAM in PCP
CMEM: Code RAM in PCP
CPS
Optional Ext. Supply

LBCU
Local Memory Bus (LMB) 1.3V, 3.3V EVR
Embedded 5V, 3.3V
Int. Supply Voltage
Single-source
PMU M Regulator
Ext. Supply
1,5 MB PFlash DMA
SMIF
64 KB Dflash LFI Bridge 16 channels
16 KB BROM
8 KB OVRAM M/S
OCDS L1 Debug
Interface
System Peripheral Bus

(SPB) JTAG/DAP
8 KB PRAM
Interrupt
FPI-Bus Interface
ASC0 System MLI0

Interrupts
PCP2
Core
ASC1 STM
MemCheck
24 KB CMEM
E-Ray SCU
(2 channels)
FCE
CAPCOM Ports
(CCU60, CCU61)
5V
Ext. ADC Supply
GPT12 BMU
(GPT 120)
ADC0 16
PLL (5V max,
fE -Ray 16 channels )
GPT12 E-RAY SSC0
(GPT 121) SBCU ADC1 8
PLL fCPU (5V max,
4
24 channels )
SSC1
GPTA 0 FADC
(3.3V max,
2 differential
channels )
SSC2
Ext. MultiCAN
Request (3 Nodes,
MSC0 SSC3
64 MO)
BlockDiagram
Unit TC1724F
V0.8
Figure 1 SAK-TC1724F-192F133HL / SAK-TC1724F-192F133HR Block

Diagram
Data Sheet 2-2 V1.2, 2014-06

TC1724
Figure 2 shows the block diagram of the SAK-TC1724N-192F133HR.
Abbreviations:
DCACHE Data Cache
4 KB DCACHE PFlash: Program Flash
8 KB ICACHE TC1.3.1
133MHz
(Configurable) DFlash: Data Flash
CPS

LBCU
Local Memory Bus (LMB) EVR
1.3V, 3.3V Embedded 5V, 3.3V
Int. Supply Voltage
Single-source
PMU M Regulator
Ext. Supply
1,5 MB PFlash DMA
SMIF
16 KB BROM
8 KB OVRAM M/S
OCDS L1 Debug
Interface

(SPB) JTAG/DAP
8 KB PRAM
Interrupt
FPI-Bus Interface
ASC0 System MLI0

Interrupts
PCP2
Core
STM
ASC1 MemCheck
24 KB CMEM
SCU
FCE
CAPCOM Ports
(CCU60, CCU61)
5V
Ext. ADC Supply
GPT12 BMU
(GPT 120)
ADC0
16
(5V max,
16 channels )
GPT12 SSC0
(GPT 121)
SBCU ADC1 8
PLL fCPU (5V max,
4
24 channels )
SSC1
GPTA 0 FADC
(3.3V max,
2 differential
channels )
SSC2
Ext. MultiCAN
Request (3 Nodes,
MSC0 SSC3
64 MO)
BlockDiagram
Unit TC1724N
V0.8
Figure 2 SAK-TC1724N-192F133HR Block Diagram
Data Sheet 2-3 V1.2, 2014-06

TC1724
Figure 3 shows the block diagram of the SAK-TC1724N-192F80HL / SAK-TC1724N-

192F80HR.
Abbreviations:
DCACHE Data Cache
8 KB ICACHE TC1.3.1 4 KB DCACHE PFlash: Program Flash
80MHz (Configurable) DFlash: Data Flash
CPS

LBCU
Embedded 5V, 3.3V
Int. Supply Voltage
Single-source
PMU M Regulator
Ext. Supply
1,5 MB PFlash DMA
SMIF
16 KB BROM
8 KB OVRAM M/S
OCDS L1 Debug
Interface

(SPB) JTAG/DAP
8 KB PRAM
Interrupt
FPI-Bus Interface
ASC0 System MLI0

Interrupts
PCP2
Core
ASC1 STM
MemCheck
24 KB CMEM
SCU
FCE
CAPCOM Ports
(CCU60, CCU61)
5V
Ext. ADC Supply
GPT12 BMU
(GPT 120)
ADC0 16
(5V max,
16 channels )
GPT12 SSC0
PLL fCPU (5V max,
4
24 channels )
SSC1
GPTA 0 FADC
(3.3V max,
2 differential
channels )
SSC2
Ext. MultiCAN
Request (3 Nodes,
MSC0 SSC3
64 MO)
BlockDiagram
Unit TC1724N
V0.8
Figure 3 SAK-TC1724N-192F80HL / SAK-TC1724N-192F80HR Block Diagram
Data Sheet 2-4 V1.2, 2014-06

TC1724
Figure 4 shows the block diagram of the SAK-TC1724F-192F80HR.
Abbreviations:
DCACHE Data Cache
4 KB DCACHE PFlash: Program Flash
8 KB ICACHE TC1.3.1
80MHz (Configurable) DFlash: Data Flash
CPS

LBCU
Embedded 5V, 3.3V
Int. Supply Voltage
Single-source
PMU M Regulator
Ext. Supply
1,5 MB PFlash DMA
SMIF
16 KB BROM
8 KB OVRAM M/S OCDS L1 Debug
Interface

(SPB) JTAG/DAP
8 KB PRAM
Interrupt
FPI-Bus Interface
ASC0 System MLI0

Interrupts
PCP2
Core
ASC1 STM
MemCheck
24 KB CMEM
E-Ray SCU
(2 channels)
FCE
CAPCOM Ports
(CCU60, CCU61)
5V
Ext. ADC Supply
GPT12 BMU
(GPT 120)
ADC0 16
PLL (5V max,
fE -Ray 16 channels )
GPT12 E-RAY SSC0
PLL fCPU (5V max,
4
24 channels )
SSC1
GPTA 0 FADC
(3.3V max,
2 differential
channels )
SSC2
Ext. MultiCAN
Request (3 Nodes,
MSC0 SSC3
64 MO)
BlockDiagram
Unit TC1724F
V0.8
Figure 4 SAK-TC1724F-192F80HR Block Diagram
Data Sheet 2-5 V1.2, 2014-06

TC1724
Pinning
3 Pinning
Figure 5 shows the logic symbol for TC1724
Alternate Functions
12 GPTA, SCU, E-RAY1), MSC0,
PORST Port 0 CCU6
TESTMODE 9
General Control SCU, GPTA, SSC1,
ESR0 Port 1
OCDS, CCU6, GPT12
ESR1 14 GPTA, SSC0/1, MSC0, MLI0,
Port 2
CCU6, GPT12
16 GPTA, ASC0/1, SSC0/1, SCU,
TRST Port 3
CAN, MSC0
OCDS / 2
TCK / DAP0 GPTA, SCU,
JTAG Control Port 4
CCU6, GPT12
TMS / DAP1 16
Port 5 GPTA, E-RAY 1), SSC0/2, CAN,
AN[16:0], CCU6, GPT12, SCU, ADC1
AN19, AN23, 9
Analog Inputs AN25, TC172 4 Port 8 CCU6, GPT12, SSC3, GPTA
AN[39:32] 9
Port 9 GPTA, CCU6, CAN, OCDS/JTAG
V DD M
4
Analog Power VSSM Port 11 Overlaid digital /analog inputs
Supply V AR EF0 4
VAGN D 0 Port 12 Overlaid digital /analog inputs
4
V5
5 XTAL1
Digital Circuitry VD D XTAL2 Oscillator
Power Supply 4
VD D P
2
VSS
1 )On ly a va ila b le fo r
EVR Pass 1 SAK -TC 1 7 2 4F-1 9 2F1 3 3H L, SAK- TC1 7 2 4F-1 9 2F13 3HR
Device Gate V PD G
TC1724_LogSym_144
Figure 5 TC1724 Logic Symbol
Data Sheet 3-1 V1.2, 2014-06

TC1724
Pinning
P2.13/SLSI11/SDI0/CTRAPA/T12HRE/SLSO16/T6OUT
P0.12/IN12/OUT12/TXENA /OUT68/CTRAPB/T13HRE
P0.0/IN0/HWCFG0/OUT0/OUT56/CC60/CC60INA/B
P0.14/IN14/REQ4/OUT14/OUT70/CC61INC/CC61
P0.1/IN1/HWCFG1/OUT1/OUT57/SDI1/COUT60
P0.7/IN7/REQ3/HWCFG7/OUT7/OUT63/EVTO3
P0.6/IN6/REQ2/HWCFG6/OUT6/OUT62/EVTO2
P8.1/MRST3/CCPOS1C/T3EUDA/B/OUT49
P0.15/IN15/REQ5/OUT15/OUT71/COUT61
P0.5/IN5/HWCFG5/OUT5/OUT61/EVTO1
P0.4/IN4/HWCFG4/OUT4/OUT60/EVTO0
P8.2/MTSR3/CCPOS2C/T4INA/B/OUT50
P8.0/SCLK3/CCPOS0C/T3INA/B/OUT48
P3.14/RXDCAN1/RXD1B/OUT96/SDI2
P0.13/IN13/OUT13/TXENB /OUT69
P0.3/IN3/HWCFG3/OUT3/OUT59
P0.2/IN2/HWCFG2/OUT2/OUT58
P3.12/RXDCAN0/RXD0B/OUT94
P3.13/TXDCAN0/TXD0/OUT95
P3.15/TXDCAN1/TXD1/OUT97
P2.8/SLSO04/SLSO14/EN00
P2.9/SLSO05/SLSO15/EN01
P9.4/CC62INC/CC62/OUT84
1)
1)
P3.0/OUT84/RXD0A/REQ6
P2.11/SCLK1A/FCLP0B
P2.12/MTSR1A/SOP0B
P9.2/COUT63/OUT82
P9.3/OUT83/COUT62
P3.9/RXD1A/OUT91
P3.11/REQ1/OUT93
P3.10/REQ0/OUT92
P3.1/TXD0/OUT85
P2.10/MRST1A
VDDP
VDD
V5
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
REQ7/CC62/CC62INA/B/CAPINA/B/SLSO20/OUT40/IN40/P5.0 1 108 P3.4/MTSR0/OUT88
SLSO21/OUT41/IN41/P5.1 2 107 P3.7/SLSO02/SLSO12/SLSI0/OUT89
COUT62/SLSO22/OUT42/IN42/P5.2 3 106 P3.3/MRST0/OUT87
SLSO23/OUT43/IN43/P5.3 4 105 P3.2/SCLK0/OUT86
RXDCAN 2/OUT80/P9.0 5 104 P3.8/SLSO06/TXD1/OUT90/REQ14
TXDCAN2/OUT81/P9.1 6 103 P3.6/SLSO01/SLSO11/SLSOANDO1
SLSI2A/SLSO24/OUT44/IN44/P5.4 7 102 P3.5/SLSO00/SLSO10/SLSOANDO0
MRST2A/OUT45/IN45/P5.5 8 101 P8.13/OUT4/COUT60
MTSR2A/OUT46/IN46/P5.6 9 100 P8.3/SLSI3/CC61INC/CC61/OUT51/SLSO30
SCLK2A/OUT47/IN47/P5.7 10 99 P8.4/OUT99/COUT62/SLSO31
1)
TXDCAN0/OUT37/RXDB1 /P5.15 11 98 ESR0
VDD 12 97 PORST
CC60INC/CC60/OUT87/P9.7 13 96 ESR1
COUT60/OUT88/P9.8 14 95 P1.1/IN17/OUT17/OUT73/T13HRE/CTRAPB
1)
CC61/CC61INA/B/OUT6/TXDA1 /P5.8 15 94 TESTMODE
1)
OUT7/RXDCAN0/TXDB1 /P5.9 16 93 P1.15/BRKIN/BRKOUT
COUT61/OUT8/TXENA 1)/P5.10 92
1)
COUT63/OUT9/TXENB /P5.11
17
18 TC1724 91
P1.0/REQ15/IN16/OUT16/OUT72/T3OUT/BRKIN/BRKOUT
TCK/DAP0
CCPOS0A/T12HRB/T3INA/B/AD1EMUX0/SLSO07/OUT19/P5.12 19 90 TRST
CCPOS1A/T13HRB/T3EUDA/B/OUT20/AD1EMUX1/P5.13 20 89 P9.6/TDO/BRKIN/BRKOUT
CCPOS2A/T12HRC/T13HRC/T4INA/B/OUT36/AD1EMUX2/RXDA1 1)/P5.14 21 88 TMS/DAP1
VDDP 22 87 P9.5/TDI/BRKIN/BRKOUT
1) VDD 23 86 V5
V5 24 85 V DDP
V PDG 25 84 V DD
AN39/DIG19/P12.3 26 83 V SS
AN38/DIG18/P12.2 27 82 XTAL2
AN37/DIG17/P12.1 28 81 XTAL1
AN36/DIG16/P12.0 29 80 VSS
AN35 30 79 P1.4/IN20/EMGSTOP/OUT20/OUT76/COUT61
AN34 31 78 P1.3/IN19/OUT19/OUT75/COUT63
AN33 32 77 P1.11/IN27/IN51/SCLK1B/OUT27/OUT51/CCPOS0C/T2INA/B
AN32 33 76 P1.10/IN26/IN50/OUT26/OUT50/SLSO17
AN7 34 75 P1.9/IN25/IN49/MRST1B/OUT25/OUT49/CCPOS1C/T2EUDA/B
AN25/DIG9/P11.9 35 74 P1.8/IN24/IN48/MTSR1B/OUT24/OUT48/CCPOS2C/T4EUDA/B
AN23/DIG7/P11.7 36 73 P4.3/IN31/IN55/OUT31/OUT55/EXTCLK0/T12HRE/CTRAPA
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VDDP
AN19/DIG3/P11.3
AN16/DIG0/P11.0
AN15
AN14
VAGND0
VAREF0
AN13
AN12
AN11
AN10
AN9
AN8
AN6
AN5
AN4
AN3
AN2
AN1
AN0
V5
CC62/CC62INA/B/TCLK0/OUT32/IN32/P2.0
CCPOS0A/T12HRB/T2INA/B/SLSO13/SLSO03/OUT33/TREADY0A/IN33/P2.1
CC61/CC61INA/B/TVALID0A/OUT34/IN34/P2.2
T12HRC/T13HRC/CCPOS2A/T4EUDA/B/TDATA0/OUT35/IN35/P2.3
COUT63/OUT36/RCLK0A/IN36/P2.4
CC60/CC60INA/B/RREADY0A/OUT37/IN37/P2.5
COUT62/OUT38/RVALID0A/IN38/P2.6
COUT60/OUT39/RDATA0A/IN39/P2.7
SLSO32/OUT100/CC60/CC60INC/P8.5
COUT61/OUT101/P8.6
CC62INC/CC62/OUT102/P8.7
T13HRB/CCPOS1A/T2EUDA/B/EXTCLK1/OUT54/OUT30/IN54/IN30/P4.2
VSSM
VDDM
VDD
1) This pin is used as standby

power supply in emulation device.
1) Only available for

SAK-TC1724F-192F133HL, SAK-TC1724F-192F133HR
TC1724_QFP144
Figure 6 TC1724 Pinning for PG-LQFP-144-17 package
Table 3-1 Pin Definitions and Functions (PG-LQFP-144-17 package)

Pin Symbol Ctrl. Type Function
Port 0
Data Sheet 3-2 V1.2, 2014-06

TC1724
Pinning
Table 3-1 Pin Definitions and Functions (PG-LQFP-144-17 package) (contd)

121 P0.0 I/O0 A1/ Port 0 General Purpose I/O Line 0
IN0 I PU GPTA0 Input 0
CCU60 I CC60INA
CCU61 I CC60INB
HWCFG0 I Hardware Configuration Input 0
OUT0 O1 GPTA0 Output 0
CCU60 O3 CC60
SDI1 I MSC0 Serial Data Input 1
CCU60 O3 COUT60
Reserved O3 -
124 P0.3 I/O0 A1+/ Port 0 General Purpose I/O Line 3
Reserved O3 -
Data Sheet 3-3 V1.2, 2014-06

TC1724
Pinning

IN4 I PD GPTA0 Input 4
EVTO0 O3 MCDS event output 0
IN5 I PD GPTA0 Input 5
REQ2 I External Request Input 2
Data Sheet 3-4 V1.2, 2014-06

TC1724
Pinning

CCU60 I CTRAPB
CCU61 I T13HRE
TXENA O3 E-Ray Channel A transmit Data Output
enable1)
TXENB O3 E-Ray Channel B transmit Data Output
enable1)
CCU61 I CC61INC
CCU60 O3 CC61
CCU60 O3 COUT61
Port 1
Data Sheet 3-5 V1.2, 2014-06

TC1724
Pinning

REQ15 I PU External Request Input 15
IN16 I GPTA0 Input 16
BRKIN I Break Input
GPT120 O3 T3OUT
BRKOUT O Break Output (controlled by OCDS module)
CCU60 I T13HRE
CCU61 I CTRAPB
Reserved O3 -
CCU61 O3 COUT63
EMGSTOP I Emergency Stop Input
CCU61 O3 COUT61
Data Sheet 3-6 V1.2, 2014-06

TC1724
Pinning

MTSR1B I SSC1 Slave Receive Input B (Slave Mode)
CCU61 I CCPOS2C
GPT120 I T4EUDB
GPT121 I T4EUDA
MTSR1B O3 SSC1 Master Transmit Output B (Master Mode)
MRST1B I SSC1 Master Receive Input B (Master Mode)
CCU61 I CCPOS1C
GPT120 I T2EUDB
GPT121 I T2EUDA
MRST1B O3 SSC1 Slave Transmit Output B (Slave Mode)
SLSO17 O3 SSC1 Slave Select Output 7
Data Sheet 3-7 V1.2, 2014-06

TC1724
Pinning

SCLK1B I SSC1 Clock Input B
CCU61 I CCPOS0C
GPT120 I T2INB
GPT121 I T2INA
SCLK1B O3 SSC1 Clock Output B
BRKIN I PU Break Input
Reserved O1 -
Reserved O2 -
Reserved O3 -
BRKOUT O Break Output (controlled by OCDS module)
Port 2
CCU60 I CC62INB
CCU61 I CC62INA
TCLK0 O2 MLI0 Transmitter Clock Output 0
CCU61 O3 CC62
Data Sheet 3-8 V1.2, 2014-06

TC1724
Pinning

TREADY0A I MLI0 Transmitter Ready Input A
CCU61 I CCPOS0A
CCU60 I T12HRB
GPT120 I T2INA
GPT121 I T2INB
SLSO03 O2 SSC0 Slave Select Output Line 3
SLSO13 O3 SSC1 Slave Select Output Line 3
CCU60 I CC61INB
CCU61 I CC61INA
TVALID0A O2 MLI0 Transmitter Valid Output
CCU61 O3 CC61
CCU60 I T12HRC
CCU60 I T13HRC
CCU61 I CCPOS2A
GPT120 I T4EUDA
GPT121 I T4EUDB
TDATA0 O2 MLI0 Transmitter Data Output
Reserved O3 -
Data Sheet 3-9 V1.2, 2014-06

TC1724
Pinning

RCLK0A I MLI Receiver Clock Input A
CCU61 O2 COUT63
Reserved O3 -
CCU60 I CC60INB
CCU61 I CC60INA
RREADY0A O2 MLI0 Receiver Ready Output A
CCU61 O3 CC60
RVALID0A I MLI Receiver Valid Input A
Reserved I -
CCU61 O2 COUT62
Reserved O3 -
RDATA0A I PU MLI Receiver Data Input A
CCU61 O2 COUT60
Reserved O3 -
SLSO04 O1 PU SSC0 Slave Select Output 4
EN00 O3 MSC0 Enable Output 0
Data Sheet 3-10 V1.2, 2014-06

TC1724
Pinning

EN01 O3 MSC0 Enable Output 1
MRST1A I PU SSC1 Master Receive Input A
MRST1A O1 SSC1 Slave Transmit Output
Reserved O2 -
Reserved O3 -
SCLK1A I PU SSC1 Clock Input A
SCLK1A O1 SSC1 Clock Output A
Reserved O2 -
FCLP0B O3 MSC0 Clock Output Positive B
MTSR1A I PU SSC1 Slave Receive Input A
MTSR1A O1 SSC1 Master Transmit Output A
Reserved O2 -
SOP0B O3 MSC0 Serial Data Output Positive B
SLSI11 I PU SSC1 Slave Select Input 1
CCU60 I CTRAPA
CCU61 I T12HRE
Reserved O1 -
GPT120 O3 T6OUT
Port 3
Data Sheet 3-11 V1.2, 2014-06

TC1724
Pinning

RXD0A I PU ASC0 Receiver Input A (Async. & Sync. Mode)
RXD0A O1 ASC0 Output (Sync. Mode)
Reserved O2 -
TXD0 O1 PU ASC0 Output
Reserved O2 -
SCLK0 I PU SSC0 Clock Input (Slave Mode)
SCLK0 O1 SSC0 Clock Output (Master Mode)
Reserved O2 -
MRST0 I PU SSC0 Master Receive Input (Master Mode)
MRST0 O1 SSC0 Slave Transmit Output (Slave Mode)
Reserved O2 -
MTSR0 I PU SSC0 Slave Receive Input (Slave Mode)
MTSR0 O1 SSC0 Master Transmit Output (Master Mode)
Reserved O2 -
SLSOANDO0 O3 SSC0 AND SSC1 Slave Select Output 0
Data Sheet 3-12 V1.2, 2014-06

TC1724
Pinning

SLSOANDO1 O3 SSC0 AND SSC1 Slave Select Output 1
SLSI0 I PU SSC0 Slave Select Input 1
TXD1 O2 ASC1 Transmit Output
RXD1A I PU ASC1 Receiver Input A
RXD1A O1 ASC1 Receiver Output A (Synchronous Mode)
Reserved O2 -
Reserved O1 -
Reserved O2 -
Reserved O1 -
Reserved O2 -
Data Sheet 3-13 V1.2, 2014-06

TC1724
Pinning

RXDCAN0 I PU CAN Node 0 Receiver Input
RXD0B I ASC0 Receiver Input B
RXD0B O1 ASC0 Receiver Output B (Synchronous Mode)
Reserved O2 -
TXDCAN0 O1 PU CAN Node 0 Transmitter Output
RXD1B I ASC1 Receiver Input B
RXD1B O1 ASC1 Receiver Output B (Synchronous Mode)
Reserved O2 -
Port 4
Data Sheet 3-14 V1.2, 2014-06

TC1724
Pinning

CCU60 I T13HRB
CCU61 I CCPOS1A
GPT120 I T2EUDA
GPT121 I T2EUDB
EXTCLK1 O3 External Clock 1 Output
CCU60 I T12HRE
CCU61 I CTRAPA
EXTCLK0 O3 External Clock 0 Output
Port 5
CCU60 I CC62INA
CCU61 I CC62INB
GPT120 I CAPINB
GPT121 I CAPINA
CCU60 O2 CC62
Data Sheet 3-15 V1.2, 2014-06

TC1724
Pinning

Reserved O2 -
CCU60 O2 COUT62
Reserved O2 -
SLSI2A I SSC2 Slave Select Input A
Reserved O2 -
MRST2A I SSC2 Master Receive Input A (Master Mode)
Reserved O2 -
Data Sheet 3-16 V1.2, 2014-06

TC1724
Pinning

MTSR2A I SSC2 Slave Receive Input (Slave Mode)
Reserved O2 -
SCLK2A I SSC2 Clock Input A (Slave Mode)
Reserved O2 -
CCU60 I PU CC61INA
CCU61 I CC61INB
TXDA1 O2 E-Ray Channel A transmit Data Output1)
CCU60 O3 CC61
TXDB1 O2 E-Ray Channel B transmit Data Output1)
Reserved O3 -
OUT8 O1 PU GPTA0 Output 8
TXENA O2 E-Ray Channel A transmit Data Output
enable1)
CCU60 O3 COUT61
Data Sheet 3-17 V1.2, 2014-06

TC1724
Pinning

TXENB O2 E-Ray Channel B transmit Data Output
enable1)
CCU60 O3 COUT63
CCU60 I PU CCPOS0A
CCU61 I T12HRB
GPT120 I T3INA
GPT121 I T3INB
AD1EMUX0 O3 ADC1 External Multiplexer Control Output 0
CCU60 I PU CCPOS1A
CCU61 I T13HRB
GPT120 I T3EUDA
GPT121 I T3EUDB
Reserved O2 -
RXDA1 I PU E-Ray Channel A Receive Data Input 11)
CCU60 I CCPOS2A
CCU61 I T12HRC
CCU61 I T13HRC
GPT120 I T4INA
GPT121 I T4INB
Reserved O2 -
Data Sheet 3-18 V1.2, 2014-06

TC1724
Pinning

RXDB1 I PU E-Ray Channel B Receive Data Input 11)
Reserved O2 -
TXDCAN0 O3 CAN Node 0 Transmitter Output
Port 8
SCLK3 I PU SSC3 Clock Input (Slave Mode)
CCU60 I CCPOS0C
GPT120 I T3INB
GPT121 I T3INA
Reserved O1 -
MRST3 I PU SSC3 Master Receive Input (Master Mode)
CCU60 I CCPOS1C
GPT120 I T3EUDB
GPT121 I T3EUDA
Reserved O1 -
MTSR3 I PU SSC3 Slave Receive Input (Slave Mode)
CCU60 I CCPOS2C
GPT120 I T4INB
GPT121 I T4INA
Reserved O1 -
Data Sheet 3-19 V1.2, 2014-06

TC1724
Pinning

SLSI3 I PU SSC3 Slave Select Input B
CCU60 I CC61INC
CCU61 O1 CC61
CCU61 O2 COUT62
CCU60 I PU CC60INC
CCU61 O2 CC60
Reserved O2 -
CCU61 O3 COUT61
CCU60 I PU CC62INC
Reserved O2 -
CCU61 O3 CC62
Reserved O2 -
CCU61 O3 COUT60
Port 9
Data Sheet 3-20 V1.2, 2014-06

TC1724
Pinning

Reserved O1 -
Reserved O3 -
Reserved O3 -
Reserved O1 PU -
CCU60 O3 COUT63
Reserved O1 PU -
CCU60 O3 COUT62
CCU61 I PU CC62INC
Reserved O1 -
CCU60 O3 CC62
TDI I PU JTAG Serial Data Input
BRKIN I OCDS Break Input
Reserved O1 -
Reserved O2 -
Reserved O3 -
BRKOUT O OCDS Break Output (controlled by OCDS
module)
Data Sheet 3-21 V1.2, 2014-06

TC1724
Pinning

TDO I PU JTAG Serial Data Output
BRKIN I OCDS Break Input
Reserved O1 -
Reserved O2 -
Reserved O3 -
BRKOUT O OCDS Break Output (controlled by OCDS
module)
TDO O JTAG Serial Data Output (controlled by OCDS
module)
CCU61 I PU CC60INC
Reserved O1 -
CCU60 O3 CC60
Reserved O1 PU -
CCU60 O3 COUT60
Port 11
38 P11.0 I D / S Port 11 General Purpose I/O Line 02)
Dig0 I Digital Input 0
AN16 I Analog Input : ADC1.CH0 3)
Data Sheet 3-22 V1.2, 2014-06

TC1724
Pinning

Port 12
Analog Input Port
57 AN0 I D Analog Input 0: ADC0.CH0 3)
Data Sheet 3-23 V1.2, 2014-06

TC1724
Pinning

38 AN16 I D / S Analog Input 16: ADC1.CH0, Dig0 3)
33 AN32 I D Analog Input 32: FADC_FADIN0P 4)
32 AN33 I D Analog Input 33: FADC_FADIN0N 4)
31 AN34 I D Analog Input 34: FADC_FADIN1P 4)
30 AN35 I D Analog Input 35: FADC_FADIN1N 4)
44 VDDM - - ADC Analog Part Power Supply (3.3V - 5V)
43 VSSM - - ADC Analog Part Ground
42 VAREF0 - - ADC0 and ADC1 Reference Voltage
41 VAGND0 - - ADC Reference Ground
VDD - - Digital Core Power Supply (1.3V)
12,
235),
58,
84,
125
22, VDDP - - Port Power Supply (3.3V)

59,
85,
126
Data Sheet 3-24 V1.2, 2014-06

TC1724
Pinning

24, V5 - - EVR Power Supply (5V)
60,
86
127
25 VPDG - - EVR Pass Device Gate

If this pin is connected to ground, the internal pass
devices are used and the external pass device
bypassed.
80, VSS - - Digital Ground
83
81 XTAL1 I Main Oscillator Input

82 XTAL2 O Main Oscillator Output
88 TMS I A2/ JTAG State Machine Control Input
DAP1 I/O PD Device Access Port Line 1
90 TRST I A1/ JTAG Reset Input
PD
91 TCK I A1/ JTAG Clock Input
DAP0 I PD Device Access Port Line 0
94 TESTMODE I I/PU Test Mode Select Input
96 ESR1 I/O A2/ External System Request Reset Input 1
PD
97 PORST I I/PU Power On Reset
98 ESR0 I/O A2 External System Request Reset Input 0
Default configuration during and after reset is
open-drain driver. The driver drives low during
power-on reset.
1) Only applicable for SAK-TC1724F-192F133HL, SAK-TC1724F-192F133HR.
2) Analog input overlayed with digital input functionality. The related port logic is used to configure the input as
either analog input (default after reset) or digital input. The related port logic supports only the port input
features as the connected pads are input only pads.
3) IOZ1 valid for this pin is the parameter with overlayed = No in the ADC parameter table.
4) IOZ1 valid for this pin is the parameter with overlayed = Yes in the ADC parameter table.
5) For the emulation device (ED), this pin is bonded to VDDSB (ED Stand By RAM supply). In the production
devide device, this pin is bonded to a VDD pad.
Data Sheet 3-25 V1.2, 2014-06

TC1724
Pinning
Legend for Table 3-1

Column Ctrl.:
I = Input (for GPIO port lines with IOCR bit field selection PCx = 0XXXB)
O = Output
O0 = Output with IOCR bit field selection PCx = 1X00B
O1 = Output with IOCR bit field selection PCx = 1X01B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X10B(ALT2)
O3 = Output with IOCR bit field selection PCx = 1X11(ALT3)
Column Type:
A1 = Pad class A1 (LVTTL)
A1+ = Pad class A1+ (LVTTL)
A2 = Pad class A2 (LVTTL)
D = Pad class D (ADC)
I = Pad class I (LVTTL)
S = Pad class D (ADC) / Pad class S (Digital)
PU = with pull-up device connected during reset (PORST = 0)
PD = with pull-down device connected during reset (PORST = 0)
TR = tri-state during reset (PORST = 0)
Data Sheet 3-26 V1.2, 2014-06

TC1724
Identification Registers
4 Identification Registers
The Identification Registers uniquely identify the device.
Table 2 SAK-TC1724F-192F133HL Identification Registers

Short Name Value Address Stepping
CBS_JDPID 0000 6350H F000 0408H AB
CBS_JTAGID 101D 0083H F000 0464H AB
SCU_MANID 0000 1820H F000 0644H AB
SCU_CHIPID 0300 A601H F000 0640H AB
SCU_RTID 0000 0001H F000 0648H AB
Table 3 SAK-TC1724F-192F133HR Identification Registers

CBS_JDPID 0000 6350H F000 0408H AB
SCU_MANID 0000 1820H F000 0644H AB
SCU_CHIPID 8300 A601H F000 0640H AB
SCU_RTID 0000 0001H F000 0648H AB
Table 4 SAK-TC1724F-192F133HR Identification Registers

CBS_JDPID 0000 6350H F000 0408H AC
CBS_JTAGID 101D 0083H F000 0464H AC
SCU_MANID 0000 1820H F000 0644H AC
SCU_CHIPID 8300 A601H F000 0640H AC
SCU_RTID 0000 0002H F000 0648H AC
Table 5 SAK-TC1724N-192F133HR Identification Registers

CBS_JDPID 0000 6350H F000 0408H AC
SCU_MANID 0000 1820H F000 0644H AC
Data Sheet 4-1 V1.2, 2014-06

TC1724
Identification Registers
Table 5 SAK-TC1724N-192F133HR Identification Registers (contd)

SCU_CHIPID 8300 9B01H F000 0640H AC
SCU_RTID 0000 0002H F000 0648H AC
Table 6 SAK-TC1724N-192F80HL Identification Registers

CBS_JDPID 0000 6350H F000 0408H AB
SCU_MANID 0000 1820H F000 0644H AB
SCU_CHIPID 1300 9B01H F000 0640H AB
SCU_RTID 0000 0001H F000 0648H AB

CBS_JDPID 0000 6350H F000 0408H AB
SCU_MANID 0000 1820H F000 0644H AB
SCU_CHIPID 9300 9B01H F000 0640H AB
SCU_RTID 0000 0001H F000 0648H AB

CBS_JDPID 0000 6350H F000 0408H AC
SCU_MANID 0000 1820H F000 0644H AC
SCU_CHIPID 9300 9B01H F000 0640H AC
SCU_RTID 0000 0002H F000 0648H AC
Data Sheet 4-2 V1.2, 2014-06

TC1724
Electrical Parameters
5 Electrical Parameters
This specification provides all electrical parameters of the TC1724.
5.1 General Parameters
5.1.1 Parameter Interpretation

The parameters listed in this section partly represent the characteristics of the TC1724
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are marked with an two-letter abbreviation in
column Symbol:
CC
Such parameters indicate Controller Characteristics which are a distinctive feature of
the TC1724 and must be regarded for a system design.
SR
Such parameters indicate System Requirements which must provided by the
microcontroller system in which the TC1724 designed in.
Data Sheet 5-1 V1.2, 2014-06

TC1724
5.1.2 Pad Driver and Pad Classes Summary

This section gives an overview on the different pad driver classes and its basic
characteristics. More details (mainly DC parameters) are defined in the Section 5.2.1.
Table 9 Pad Driver and Pad Classes Overview

Class Power Type Sub Class Speed Load Leakage1) Termination
Supply Grade 150C
A 3.3 V LVTTL A1 6 MHz 100 pF 500 nA No
I/O, (e.g. GPIO)
LVTTL A1+ 25 50 pF 1 A Series
outputs (e.g. serial MHz termination
I/Os) recommended
A2 40 50 pF 3 A Series
(e.g. serial MHz termination
I/Os) recommended
DE 5V ADC
I 3.3 V LVTTL
(input
only)
1) Two values are given: for TJ = 150 C and a 50% higher value for TJ = 160 C.
Data Sheet 5-2 V1.2, 2014-06

TC1724
5.1.3 Absolute Maximum Ratings

Stresses above the values listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 10 Absolute Maximum Rating Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Con
dition
Storage temperature TST SR -65 160 C
Voltage at 1.3 V power supply VDD SR 2.0 V
pins with respect to VSS
Voltage at 3.3 V power supply VDDP 4.33 V
pins with respect to VSS SR
Voltage at 5 V power supply VDDM SR 7.0 V
pins with respect to VSS
Voltage on any Class A input VIN SR -0.6 VDDP + 0.5 V Whatever
pin and dedicated input pins or max. 4.33 is lower
with respect to VSS
Voltage on any Class D VAIN -0.6 7.0 V
analog input pin with respect VAREFx
to VAGND SR
Voltage on any shared Class VAINF -0.6 7.0 V
D analog input pin with
respect to VSSAF, if the FADC SR
is switched through to the pin.
Input current on any pin IIN -10 +10 mA
during overload condition
Absolute maximum sum of all IIN -75 +75 mA
input circuit currents for one
port group during overload
condition1)
Absolute maximum sum of all IIN |200| mA
input circuit currents during
overload condition
Data Sheet 5-3 V1.2, 2014-06

TC1724
1) The port groups are defined in Table 15.
Data Sheet 5-4 V1.2, 2014-06

TC1724
5.1.4 Pin Reliability in Overload

When receiving signals from higher voltage devices, low-voltage devices experience
overload currents and voltages that go beyond their own IO power supplies specification.
Table 11 defines overload conditions that will not cause any negative reliability impact if
all the following conditions are met:
full operation life-time (24000 h) is not exceeded
Operating Conditions are met for
pad supply levels (VDDP or VDDM)
temperature
If a pin current is out of the Operating Conditions but within the overload parameters,
then the parameters functionality of this pin as stated in the Operating Conditions can no
longer be guaranteed. Operation is still possible in most cases but with relaxed
parameters.
Note: An overload condition on one or more pins does not require a reset.
Table 11 Overload Parameters

dition
Input current on any digital pin IIN -5 +5 mA
during overload condition
Absolute sum of all input IING -70 +70 mA
circuit currents for one port
group during overload
condition1)
Input current on analog pins IINANA -3 +3 mA
Absolute sum of all analog IINSAS -15 +15 mA
input currents for analog
inputs of a single ADC during
overload condition
Absolute sum of all input IINS -100 100 mA
circuit currents during
overload condition
1) The port groups are defined in Table 15.
Note: FADC input pins count as analog pin as they are overlayed with an ADC pins.
Data Sheet 5-5 V1.2, 2014-06

TC1724
Table 12 PN-Junction Characterisitics for positive Overload

Pad Type IIN = 3 mA IIN = 5 mA
A1 / A1+ UIN = VDDP + 0.6 V UIN = VDDP + 0.7 V
A2 UIN = VDDP + 0.5 V UIN = VDDP + 0.6 V
D/S UIN = VDDM + 0.6 V -
Table 13 PN-Junction Characterisitics for negative Overload

Pad Type IIN = -3 mA IIN = -5 mA
A1 / A1+ UIN = VSS - 0.6 V UIN = VSS - 0.7 V
A2 UIN = VSS - 0.5 V UIN = VSS - 0.6 V
D/S UIN = VSSM - 0.6 V -
Note: A series resistor at the pin to limit the current to the maximum permitted overload
current is sufficient to handle failure situations like short to battery without having
any negative reliability impact on the operational life-time.
Data Sheet 5-6 V1.2, 2014-06

TC1724
5.1.5 Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the TC1724. All parameters specified in the following tables
refer to these operating conditions, unless otherwise noticed.
Digital supply voltages applied to the TC1724 from external must be static regulated
voltages which allow a typical voltage swing of 5 %.
All parameters specified in the following tables refer to these operating conditions
(Table 14), unless otherwise noticed in the Note / Test Condition column.
Table 14 Operating Conditions Parameters

Min. Typ Max. Test Condition
.
Overload coupling KOVAN CC 0.0001 IOV -2 mA;
factor for analog IOV 0 mA; analog
inputs, negative pad= 5.0 V
Overload coupling KOVAP CC 0.00001 IOV 0 mA;
factor for analog IOV 3 mA; analog
inputs, positive pad= 5.0 V
CPU Frequency fCPU SR 133 MHz SAK-TC1724F-
192F133HL;
SAK-TC1724F-
192F133HR;
SAK-TC1724N-
192F133HR
80 MHz SAK-TC1724N-
192F80HL;
SAK-TC1724N-
192F80HR
Data Sheet 5-7 V1.2, 2014-06

TC1724
Table 14 Operating Conditions Parameters (contd)

.
FPI Frequency fFPI SR 110 MHz SAK-TC1724F-
192F133HL;
SAK-TC1724F-
192F133HR;
SAK-TC1724N-
192F133HR
80 MHz SAK-TC1724N-
192F80HL;
SAK-TC1724N-
192F80HR
LMB Frequency fLMB SR 133 MHz SAK-TC1724F-
192F133HL;
SAK-TC1724F-
192F133HR;
SAK-TC1724N-
192F133HR
80 MHz SAK-TC1724N-
192F80HL;
SAK-TC1724N-
192F80HR
PCP Frequency fPCP SR 133 MHz SAK-TC1724F-
192F133HL;
SAK-TC1724F-
192F133HR;
SAK-TC1724N-
192F133HR
80 MHz SAK-TC1724N-
192F80HL;
SAK-TC1724N-
192F80HR
Inactive device pin IID SR -1 1 mA All power supply
current voltages
VDDx = 0
Short circuit current ISC SR -5 5 mA
of digital outputs1)
Data Sheet 5-8 V1.2, 2014-06

TC1724
Table 14 Operating Conditions Parameters (contd)

.
Absolute sum of ISC_D CC 100 mA
short circuit currents
of the device
Absolute sum of ISC_PG CC 70 mA
short circuit currents
per pin group
Ambient TA SR -40 125 C
Temperature
Junction TJ SR -40 160 C
temperature
Core Supply Voltage VDD SR 1.17 1.3 1.432) V Only required if
externally supplied5)
ADC analog supply VDDM SR 2.97 5.0 5.53) V
voltage
EVR supply voltage V5 SR 4.00 5.0 5.5 V 5.0V single supply
2.97 3.3 3.63 V 3.3V single supply
4)
Digital supply voltage VDDP SR 2.97 3.3 3.63 V Only required if
for IO pads externally supplied5)
VDDP voltage to VDDPPA CC 0.65 V
ensure defined pad
states6)
Digital ground VSS SR 0 V
voltage
Analog ground VSSM SR -0.1 0 0.1 V
voltage for VDDM
1) Applicable for digital outputs.
2) Voltage overshoot to 1.7V is permissible at Power-Up and PORST low, provided the pulse duration is less than
100 s and the cumulated sum of the pulses does not exceed 1 h.
5) No external inductive load permissable if EVR is used.
6) This parameter is valid under the assumption the PORST signal is constantly at low level during the power-
up/power-down of VDDP.
Data Sheet 5-9 V1.2, 2014-06

TC1724
Table 15 Pin Groups for Overload / Short-Circuit Current Sum Parameter

Group Pins
1 P5.[15:2], P9.[1:0], P9.[8:7]
2 P0.[7:0], P0.[15:12], P2.[13:8], P3.[1:0], P3.[4:3], P3.7, P3.[15:9], P5.[1:0],
P8.[2:0], P9.[4:2]
3 P1.[1:0], P1.15, P3.2, P3.[6:5], P3.8, P8.[4:3], P8.13, P9.[6:5]
4 P1.[4:3], P1.[11:8], P2.[7:0], P4.[3:2], P8.[7:5]
Data Sheet 5-10 V1.2, 2014-06

TC1724
5.2 DC Parameters
5.2.1 Input/Output Pins
Table 16 Standard_Pads Parameters

Min. Typ. Max. Test Condition
Pin capacitance (digital CIO CC 10 pF TA= 25 C;

inputs/outputs) f= 1 MHz
Pull-down current |IPDL| CC 150 A Vi 0.6 x VDDP V
10 A Vi 0.36 x
VDDP V
Pull-Up current |IPUH| CC 10 A Vi 0.6 x VDDP V
100 A Vi 0.36 x
VDDP V
Spike filter always tSF1 CC 10 ns only PORST pin
blocked pulse duration
Spike filter pass-through tSF2 CC 120 ns only PORST pin
pulse duration
Table 17 Standard_Pads Class_A1

Input Hysteresis for HYSA CC 0.1 x V

pads of all A classes1) VDDP
Input Leakage Current IOZA1 CC -500 500 nA Vi VDDP V; Vi 0 V;
Class A1 -40C TJ 150C
-750 750 nA Vi VDDP V; Vi 0 V;
150C < TJ 160C
Ratio Vil/Vih, A1 pads VILA1 / 0.6
VIHA1 CC
Data Sheet 5-11 V1.2, 2014-06

TC1724
Table 17 Standard_Pads Class_A1 (contd)

On-Resistance of the RDSONW 450 600 Ohm IOH> -0.5 mA;
class A1 pad, weak CC P_MOS
driver 210 340 Ohm IOL< 0.5 mA;
N_MOS
On-Resistance of the RDSONM 155 Ohm IOH> -2 mA;
class A1 pad, medium CC P_MOS
driver 110 Ohm IOL< 2 mA;
N_MOS
Fall time,pad type A1 tFA1 CC 150 ns CL= 20 pF; pin out
driver= weak
50 ns CL= 50 pF; pin out
driver= medium
driver= medium
driver= weak
18000 ns CL= 20000 pF; pin
out driver= medium
65000 ns CL= 20000 pF; pin
out driver= weak
Rise time, pad type A1 tRA1 CC 150 ns CL= 20 pF; pin out
driver= weak
driver= medium
driver= medium
driver= weak
18000 ns CL= 20000 pF; pin
out driver= medium
65000 ns CL= 20000 pF; pin
out driver= weak
Data Sheet 5-12 V1.2, 2014-06

TC1724

Input high voltage, VIHA1 SR 0.6 x min(VD V
class A1 pads VDDP DP +
0.3,
3.6)
Input low voltage, class VILA1 SR -0.3 0.36 x V
A1 pads VDDP
Output voltage high, VOHA1 CC VDDP V IOH -1.4 mA; pin out
class A1 pads - 0.4 driver= medium
2.4 V IOH -2 mA; pin out
driver= medium
VDDP V IOH -400 A; pin
- 0.4 out driver= weak
2.4 V IOH -500 A; pin
out driver= weak
Output voltage low, VOLA1 CC 0.4 V IOL 2 mA; pin out
class A1 pads driver= medium
0.4 V IOL 500 A; pin out
driver= weak
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cant be
guaranteed that it suppresses switching due to external system noise.
Table 18 Standard_Pads Class_A1+

Parameter Symbo Values Unit Note /
l Min. Typ Max. Test Condition
.
Input Hysteresis for HYSA1 0.1 x VDDP V
A1+ pads 1) + CC
Input Leakage IOZA1+ -1000 1000 nA
Current Class A1+ CC
Data Sheet 5-13 V1.2, 2014-06

TC1724
Table 18 Standard_Pads Class_A1+ (contd)

.
On-Resistance of RDSONW 450 600 Ohm IOH> -0.5 mA;
the class A1+ pad, CC P_MOS
weak driver 210 340 Ohm IOL< 0.5 mA;
N_MOS
On-Resistance of RDSONM 155 Ohm IOH> -2 mA;
medium driver 110 Ohm IOL< 2 mA;
N_MOS
On-Resistance of RDSON1+ 110 Ohm IOH> -2 mA;
strong driver 80 Ohm IOL< 2 mA;
N_MOS
Fall time, pad type tFA1+ 150 ns CL= 20 pF; pin out
A1+ C driver= weak
C 28 ns CL= 50 pF;
edge= slow; pin out
driver= strong
16 ns CL= 50 pF;
edge= soft ; pin out
driver= strong
driver= medium
driver= medium
driver= weak
driver= medium
driver= weak
Data Sheet 5-14 V1.2, 2014-06

TC1724

.
Rise time, pad type tRA1+ 150 ns CL= 20 pF; pin out
A1+ C driver= weak
C 28 ns CL= 50 pF;
edge= slow ; pin out
driver= strong
16 ns CL= 50 pF;
edge= soft ; pin out
driver= strong
driver= medium
driver= medium
driver= weak
driver= medium
driver= weak
Input high voltage, VIHA1+ 0.6 x VDDP min(VD V
Class A1+ pads SR DP +
0.3,
3.6)
Input low voltage, VILA1+ -0.3 0.36 x V
Class A1+ pads SR VDDP
Ratio Vil/Vih, A1+ VILA1+ / 0.6
pads VIHA1+
CC
Data Sheet 5-15 V1.2, 2014-06

TC1724

.
Output voltage high, VOHA1+ VDDP - 0.4 V IOH -1.4 mA; pin out
class A1+ pads CC driver= medium
VDDP - 0.4 V IOH -1.4 mA; pin out
driver= strong
driver= medium
driver= strong
VDDP - 0.4 V IOH -400 A; pin out
driver= weak
2.4 V IOH -500 A; pin out
driver= weak
Output voltage low, VOLA1+ 0.4 V IOL 2 mA; pin out
class A1+ pads CC driver= medium
0.4 V IOL 2 mA; pin out
driver= strong
0.4 V IOL 500 A; pin out
driver= weak
Table 19 Standard_Pads Class_A2

Input Hysteresis HYSA2 0.1 x VDDP V

for A2 pads 1) CC
Data Sheet 5-16 V1.2, 2014-06

TC1724

Input Leakage IOZA2 CC -6000 6000 nA Vi< VDDP / 2 - 1 V;
current Class A2 Vi> VDDP / 2 + 1 V;
Vi 0 V;
Vi VDDP V
-3000 3000 nA Vi> VDDP / 2 - 1 V;
Vi< VDDP / 2 + 1 V
Ratio Vil/Vih, A2 VILA2 / 0.6
pads VIHA2 CC
On-Resistance RDSONW 450 600 Ohm IOH> -0.5 mA;
of the class A2 CC P_MOS
pad, weak driver 210 340 Ohm IOL< 0.5 mA;
N_MOS
On-Resistance RDSONM 155 Ohm IOH> -2 mA;
of the class A2 CC P_MOS
pad, medium 110 Ohm IOL< 2 mA;
driver N_MOS
On-Resistance RDSON2 CC 42 Ohm IOH> -2 mA;
of the class A2 P_MOS
pad, strong driver 22 Ohm IOL< 2 mA;
N_MOS
Data Sheet 5-17 V1.2, 2014-06

TC1724

Fall time, pad tFA2 CC 150 ns CL= 20 pF;
type A2 pin out
driver= weak
7 ns CL= 50 pF;
edge= medium ;
pin out
driver= strong
10 ns CL= 50 pF;
edge= medium-
minus ; pin out
driver= strong
3.7 ns CL= 50 pF;
edge= sharp ; pin
out driver= strong
5 ns CL= 50 pF;
edge= sharp-
minus ; pin out
driver= strong
16 ns CL= 50 pF;
edge= soft ; pin
out driver= strong
driver= medium
7.5 ns CL= 100 pF;
edge= sharp ; pin
out driver= strong
140 ns CL= 150 pF;
pin out
driver= medium
Data Sheet 5-18 V1.2, 2014-06

TC1724

550 ns CL= 150 pF; pin
out driver= weak
18000 ns CL= 20000 pF;
pin out
driver= medium
65000 ns CL= 20000 pF; pin
out driver= weak
Rise time, pad tRA2 CC 150 ns CL= 20 pF; pin out
type A2 driver= weak
7.0 ns CL= 50 pF;
edge= medium ;
pin out
driver= strong
10 ns CL= 50 pF;
edge= medium-
minus ; pin out
driver= strong
3.7 ns CL= 50 pF;
edge= sharp ; pin
out driver= strong
5 ns CL= 50 pF;
edge= sharp-
minus ; pin out
driver= strong
16 ns CL= 50 pF;
edge= soft ; pin
out driver= strong
driver= medium
7.5 ns CL= 100 pF;
edge= sharp ; pin
out driver= strong
out
driver= medium
Data Sheet 5-19 V1.2, 2014-06

TC1724

out driver= weak
18000 ns CL= 20000 pF;
pin out
driver= medium
65000 ns CL= 20000 pF; pin
out driver= weak
Input high VIHA2 SR 0.6 x VDDP min(VDDP V
voltage, class A2 + 0.3,
pads 3.6)
Input low voltage, VILA2 SR -0.3 0.36 x V
Class A2 pads VDDP
Output voltage VOHA2 CC VDDP - 0.4 V IOH -1.4 mA; pin
high, class A2 out
pads driver= medium
VDDP - 0.4 V IOH -1.4 mA; pin
out driver= strong
driver= medium
driver= strong
VDDP - 0.4 V IOH -400 A; pin
out driver= weak
2.4 V IOH -500 A; pin
out driver= weak
Output voltage VOLA2 CC 0.4 V IOL 2 mA; pin out
low, class A2 driver= medium
pads 0.4 V IOL 2 mA; pin out
driver= strong
0.4 V IOL 500 A; pin
out driver= weak
Data Sheet 5-20 V1.2, 2014-06

TC1724
Table 20 Standard_Pads Class_I

Min. Typ. Max. Test Condit
ion
Input Hysteresis Class I1) HYSI CC 0.1 x V
VDDP
Input Leakage Current IOZI CC -1000 1000 nA -40C TJ
150C
-1500 1500 nA 150C < TJ
160C
Ratio between low and VILI / VIHI CC 0.6
high input threshold
Input high voltage, class I VIHI SR 0.6 x min(VD V
pins VDDP DP +
0.3,
3.6)
Input low voltage, Class I VILI SR -0.3 0.36 x V
pads VDDP
Class S pad parameters are only valid for VDDM = 4.75 V to 5.25 V.
Table 21 Standard_Pads Class_S

Input Hysteresis for HYSS CC 0.3 V

class S pads1)
Input leakage current IOZS CC 300 300 nA
Input voltage high VIHS CC 3.6 V
Data Sheet 5-21 V1.2, 2014-06

TC1724
Table 21 Standard_Pads Class_S (contd)

Input voltage low VILS CC 1.9 V
VILS Delta 2) VILSD CC -50 50 mV Maximum input
low state
treshold
variation over
1ms
(VDDP = consta
nt)
2) VILSD is implemented to ensure J2716 specification. It cant be guaranteed that it suppresses switching due to
external noise.
Data Sheet 5-22 V1.2, 2014-06

TC1724
5.2.2 Analog to Digital Converters (ADCx)

ADC parameter in Table 22 are valid for VDD = 1.235 V to 1.365 V; VDDM = 4.75 V to
5.25 V; TJ = 150C.
Table 22 5V ADC Parameters

Switched capacitance at CAINSW 9 20 pF

the analog voltage CC
inputs1)
Total capacitance of an CAINTOT 20 30 pF
analog input CC
Switched capacitance at CAREFSW 15 30 pF
the positive reference CC
voltage input2)3)
Total capacitance of the CAREFTOT 20 40 pF
voltage reference inputs2) CC
Differential Non-Linearity EADNL -3 3 LSB ADC
Error4)5)6)7) CC resolution= 12-
bit
8) 9)
Gain Error4)5)6)7) EAGAIN -3.5 3.5 LSB ADC

CC resolution= 12-
bit 8) 9)
Integral Non- EAINL -3 3 LSB ADC
Linearity4)5)6)7) CC resolution= 12-
bit8) 9)
Offset Error4)5)6)7) EAOFF -4 4 LSB ADC
CC resolution= 12-
bit 8) 9)
Data Sheet 5-23 V1.2, 2014-06

TC1724
Table 22 5V ADC Parameters (contd)

Converter clock fADC 4 110 MHz SAK-TC1724F-
SR 192F133HL;
SAK-TC1724F-
192F133HR;
SAK-TC1724N-
192F133HR
4 80 MHz SAK-TC1724N-
192F80HL;
SAK-TC1724N-
192F80HR
10)
Internal ADC clock fADCI CC 1 20 MHz
Charge consumption per QCONV 70 8511) 100 pC charge needs to
conversion CC be provided via
VAREF0
Data Sheet 5-24 V1.2, 2014-06

TC1724

Input leakage at analog IOZ1 -100 500 nA Vi 0.97 x
inputs12) CC VDDM V;
Vi VDDM V;
overlayed= No
-100 600 nA Vi 0.97 x
VDDM V;
Vi VDDM V;
overlayed= Yes
-500 100 nA Vi 0 V;
Vi 0.03 x
VDDM V;
overlayed= No
-600 100 nA Vi 0.03 x
VDDM V;
Vi 0 V;
overlayed= Yes
-100 200 nA Vi> 0.03 x

VDDM V;
Vi< 0.97 x
VDDM V;
overlayed= No
-100 300 nA Vi> 0.03 x
VDDM V;
Vi< 0.97 x
VDDM V;
overlayed= Yes
Input leakage current at IOZ2 CC -2 2 A VAREF0 0V;

Varef0 VAREF0 VDDM V
Input leakage current at IOZ3 CC -2 2 A VAGND0 0V;
Vagnd0 VAGND0 VDDM V
ON resistance of the RAIN 900 1500 Ohm
transmission gates in the CC
analog voltage path
Data Sheet 5-25 V1.2, 2014-06

TC1724

ON resistance for the RAIN7T 180 550 900 Ohm Test feature
ADC test (pull down for CC available only
AIN7) for odd AINx
pins
Resistance of the RAREF 500 1000 Ohm 500 Ohm
reference voltage input CC increased if
path AIN[1:0] used
as reference
input
13)
Broken wire detection tBWG CC 50
delay against VAGND
14)
Broken wire detection tBWR CC 50
delay against VAREF
Sample time tS CC 2 257 TADCI
Calibration time after bit tCAL CC 4352 cycles
ADC_GLOBCFG.SUCAL
is set
Total Unadjusted TUE CC -4 416) LSB ADC
Error5)6)15) resolution= 12-
bit
Wakeup time from analog tAWAF 5 s
powerdown, fast mode CC
Wakeup time from analog tAWAS 10 s
powerdown, slow mode CC
Analog reference VAGND0 VSSM - VAREF0 V
ground2) SR 0.05 -
VDDM/2
Analog input voltage VAIN SR VAGND0 VAREF0 V
Analog reference VAREF0 VAGND0 VDDM + V
voltage2) SR + 0.0517)
18)
VDDM/2
Analog reference voltage VAREF0 - VDDM/2 VDDM + V
range5)6)2) VAGND0 0.05
SR
Data Sheet 5-26 V1.2, 2014-06

TC1724
1) The sampling capacity of the conversion C-network is pre-charged to VAREF/2 before the sampling moment.
Because of the parasitic elements the voltage measured at AINx can deviate from VAREF/2.
2) Applies to AINx, when used as auxiliary reference input.
3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead smaller capacitances are successively switched to the reference voltage.
4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.
5) If the analog reference voltage range is below VDDM but still in the defined range of VDDM / 2 and VDDM is used,
then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1),
TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k.
6) If a reduced analog reference voltage between 1V and VDDM / 2 is used, then there are additonal decrease in
the ADC speed and accuracy.
7) If the analog reference voltage is > VDDM, then the ADC converter errors increase.
8) For 10-bit conversions the error value must be multiplied with a factor 0.25.
10) If the alternate reference is used or fADCI is more than 16 MHz, the accuracy of the ADC may decrease.
11) For a conversion time of 1 s a rms value of 85A result for IAREF0.
12) The leakage current definition is a continous function,as shown in figure ADCx Analoge Input Leakage. The
numerical values defined determine the characteristic points of the given countinuous linear approximation -
they do not define step function.
13) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a
conversion rate of not more than 250s. Results below 10% (199H).
14) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a
conversion rate of not more than 10s. This function is influenced by leakage current, in particular at high
temperature.Results above 60% (999H).
15) Measured without noise.
16) For 10-bit conversion the TUE is 2LSB; for 8-bit conversion the TUE is 1LSB
17) A running conversion may become inexact in case of violating the normal conditions (voltage overshoot).
18) If the reference voltage VAREF increase or the VDDM decrease, so that VAREF = (VDDM + 0.05V to VDDM + 0.07V),
then the accuracy of the ADC decrease by 4LSB12.
Data Sheet 5-27 V1.2, 2014-06

TC1724
ADC parameter in Table 23 are valid for VDD = 1.235 V to 1.365 V; VDDM = 3.135 V to
3.465 V; TJ = 150C.
Table 23 3.3V ADC Parameters

l Min. Typ. Max. Test Condition
Switched capacitance at CAINSW 9 20 pF

the analog voltage CC
inputs1)
Total capacitance of an CAINTOT 20 30 pF
analog input CC
Switched capacitance at CAREFS 15 30 pF
the positive reference W CC
voltage input2)3)
Total capacitance of the CAREFTO 20 40 pF
voltage reference inputs2) T CC
Differential Non-Linearity EADNL -4 4 LSB ADC
Error4)5)6)7) CC resolution= 12-
bit
8) 9)
4)5)6)7)
Gain Error EAGAIN -3.5 3.5 LSB ADC
CC resolution= 12-
bit 8) 9)
Integral Non- EAINL -4 4 LSB ADC
Linearity4)5)6)7) CC resolution= 12-
bit8) 9)
Offset Error4)5)6)7) EAOFF -4 4 LSB ADC
CC resolution= 12-
bit 8) 9)
Converter clock fADC 4 110 MHz SAK-TC1724F-
SR 192F133HL;
SAK-TC1724F-
192F133HR;
SAK-TC1724N-
192F133HR
192F80HL;
SAK-TC1724N-
192F80HR
Data Sheet 5-28 V1.2, 2014-06

TC1724
Table 23 3.3V ADC Parameters (contd)

10)
Internal ADC clock fADCI 1 20 MHz
CC
Charge consumption per QCONV 70 pC charge needs to
conversion11) CC be provided via
VAREF0
Input leakage at analog IOZ1 -100 500 nA Vi 0.97 x
inputs12) C VDDM V;
C Vi VDDM V;
overlayed= No
-100 600 nA Vi 0.97 x
VDDM V;
Vi VDDM V;
overlayed= Yes
-500 100 nA Vi 0 V;
Vi 0.03 x
VDDM V;
overlayed= No
-600 100 nA Vi 0.03 x
VDDM V; Vi 0 V;
overlayed= Yes
-100 200 nA Vi> 0.03 x
VDDM V;
Vi< 0.97 x
VDDM V;
overlayed= No
-100 300 nA Vi> 0.03 x
VDDM V;
Vi< 0.97 x
VDDM V;
overlayed= Yes
Input leakage current at IOZ2 CC -2 2 A VAREF0 VDDM V
Varef
Input leakage current at IOZ3 CC -2 2 A VAGND0 VDDM V
Vagnd
Data Sheet 5-29 V1.2, 2014-06

TC1724
Table 23 3.3V ADC Parameters (contd)

ON resistance of the RAIN 3500 9000 Ohm
transmission gates in the C
analog voltage path C
ON resistance for the RAIN7T 180 800 1800 Ohm Test feature
ADC test (pull down for CC available only
AIN7) for odd AINx
pins
Resistance of the RAREF 1700 3000 Ohm 500 Ohm
reference voltage input CC increased if
path AIN[1:0] used
as reference
input
13)
Broken wire detection tBWG 50
delay against VAGND CC
14)
Broken wire detection tBWR CC 50
delay against VAREF
Sample time tS CC 2 257 TADCI
Calibration time after bit tCAL CC 4352 cycles
ADC_GLOBCFG.SUCAL
is set
Total Unadjusted TUE -4.5 4.516) LSB ADC
Error5)6)15) CC resolution= 12-
bit
Analog reference VAGND0 VSSM - VAREF0 V
ground2) SR 0.05 -
VDDM/2
Analog input voltage VAIN SR VAGND0 VAREF0 V
Analog reference VAREF0 VAGND0 VDDM + V
voltage2) SR + 0.0517)
18)
VDDM/2
Analog reference voltage VAREF0 - VDDM/2 VDDM + V
range5)6)2) VAGND0 0.05
SR
1) The sampling capacity of the conversion C-network is pre-charged to VAREF/2 before the sampling moment.
Because of the parasitic elements the voltage measured at AINx can deviate from VAREF/2.
Data Sheet 5-30 V1.2, 2014-06

TC1724
2) Applies to AINx, when used as auxiliary reference input.
3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead smaller capacitances are successively switched to the reference voltage.
4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.
5) If the analog reference voltage range is below VDDM but still in the defined range of VDDM / 2 and VDDM is used,
then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1),
TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k.
6) If a reduced analog reference voltage between 1V and VDDM / 2 is used, then there are additonal decrease in
the ADC speed and accuracy.
7) If the analog reference voltage is > VDDM, then the ADC converter errors increase.
10) If the alternate reference is used, or fADCI is more than 16 MHz, or STC is lower than 8, the accuracy of the ADC
may decrease.
11) QCONV is calculated as QCONV = CAREF*VAREF. The Qconv can be calculated according to this formula.
12) The leakage current definition is a continous function,as shown in figure ADCx Analoge Input Leakage. The
numerical values defined determine the characteristic points of the given countinuous linear approximation -
they do not define step function.
13) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a
conversion rate of not more than 250s. Results below 10% (199H).
14) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a
conversion rate of not more than 10s. This function is influenced by leakage current, in particular at high
temperature.Results above 60% (999H).
15) Measured without noise.
16) For 10-bit conversion the TUE is 2LSB; for 8-bit conversion the TUE is 1LSB
17) A running conversion may become inexact in case of violating the normal conditions (voltage overshoot).
18) If the reference voltage VAREF increase or the VDDM decrease, so that VAREF = (VDDM + 0.05V to VDDM + 0.07V),
then the accuracy of the ADC decrease by 4LSB12.
Table 24 Conversion Time (Operating Conditions apply)

Parameter Symbol Values Unit Note
Conversion tC CC 2 TADC + (4 + STC + n) TADCI s n = 8, 10, 12 for
time with n - bit conversion
post-calibration TADC = 1 / fFPI
Conversion 2 TADC + (2 + STC + n) TADCI TADCI = 1 / fADCI
time without
post-calibration
Data Sheet 5-31 V1.2, 2014-06

TC1724
Analog Input Circuitry

REXT RAIN, On
ANx
VAIN = CEXT CAINSW

CAINTOT - CAINSW
VAGNDx RAIN7T
Reference Voltage Input Circuitry
VAREFx RAREF, On
VAREF CAREFTOT - CAREFSW CAREFSW

VAGNDx
Analog_InpRefDiag
Figure 7 ADCx Input Circuits
Data Sheet 5-32 V1.2, 2014-06

TC1724
Ioz1
Single ADC Input
500nA
200nA VIN[VDDM%]
100nA
-100nA
3% 97%100%
-500nA
Ioz1
Overlayed ADC/FADC Input
600nA
300nA VIN[VDDM%]
100nA
-100nA
3% 97% 100%
-600nA
Figure 8 ADCx Analog Inputs Leakage
Data Sheet 5-33 V1.2, 2014-06

TC1724
5.2.3 Fast Analog to Digital Converter (FADC)

FADC parameter are valid for VDDM = 4.75 V to 5.25 V;TJ = 150C.
Table 25 FADC Parameters with VDDM = 5V

DNL error EFDNL CC -1 1 LSB VIN mode=

differential
Gain = 1, 2
-1 1 LSB VIN mode=
single ended
Gain = 1, 2
-2 2 LSB VIN mode=
differential
Gain = 4, 8
TJ = 150C 1)
-2.5 2.5 LSB VIN mode=
differential
Gain = 4, 8
TJ = 160C 1)
-2 2 LSB VIN mode=
single ended
Gain = 4, 8
TJ = 150C 1)
-2.5 2.5 LSB VIN mode=
single ended
Gain = 4, 8
TJ = 160C 1)
Data Sheet 5-34 V1.2, 2014-06

TC1724
Table 25 FADC Parameters with VDDM = 5V (contd)

GRADient error EFGRAD -5 5 % VIN mode=
CC differential ;
Gain< 4
-5 5 % VIN mode=
single ended ;
Gain< 4
-5.5 5 % VIN mode=
differential ;
Gain= 4
-5.5 5 % VIN mode=
single ended ;
Gain= 4
-6 6 % VIN mode=
differential ;
Gain= 8
-6 6 % VIN mode=
single ended ;
Gain= 8
INL error EFINL CC -4 4 LSB VIN mode=
differential
-4 4 LSB VIN mode=
single ended
Data Sheet 5-35 V1.2, 2014-06

TC1724

Offset error EFOFF CC -90 90 mV VIN mode=
differential ;
Calibration= No
-90 90 mV VIN mode=
single ended ;
Calibration= No
-20 20 mV VIN mode=
differential ;
Calibration= Yes
2)3)
-20 20 mV VIN mode=

single ended ;
Calibration= Yes
2)3)
Error of common mode EFREFI -80 80 mV

voltage VFAREFI/2 CC
Channel amplifier cutoff fCOFF CC 2 MHz
frequency
Converter clock fFADC 4 110 MHz SAK-TC1724F-
SR 192F133HL;
SAK-TC1724F-
192F133HR;
SAK-TC1724N-
192F133HR
192F80HL;
SAK-TC1724N-
192F80HR
Conversion time tC CC 21 1/ For 10-bit
fFADC conversion
Input resistance of the RFAIN CC 100 200 kOh
analog voltage path (Rn, m
Rp)
Data Sheet 5-36 V1.2, 2014-06

TC1724

Settling time of a channel tSET CC 5 s

amplifier after changing
ENN or ENP
Analog input voltage VAINF SR VSSM VDDP V
range4)
Wakeup time from analog tFWAF CC 5 s
powerdown, fast mode
Wakeup time from analog tFWAS CC 10 s
powerdown, slow mode
Analog reference ground VFAGNDI 0 V Internally
CC generated
Analog reference voltage VFAREFI 3.3 5)6) V Internally
CC generated
1) No missing codes.
2) Calibration should be preformed at each power-up. In case of a continous operation, it should be performed
minimium once per week.
3) The offser error voltage drifts over the whole temperature range maximum +-3LSB.
4) The accuracy values is valid between 5% and 90%of VAINF
5) Voltage overshoot to 4V is permissible, provided the pulse duration is less than 100 s and the cumulated sum
of the pulses does not exceed 1 h.
6) A running conversion may become inexact in case of violating the nomal operating conditions (voltage
overshoots).
The calibration procedure should run after each power-up, when all power supply
voltages and the reference voltage have stabilized.
Data Sheet 5-37 V1.2, 2014-06

TC1724
FADC Analog Input Stage
RN
FAINxN -
+
VSSM VFAREF/2
+
RP
FAINxP -
FADC Reference Voltage

VFAREF Input Circuitry
(from IVR)
IFAREF
VFAREF
VFAGND
FADC _InpRefDiag
Figure 9 FADC Input Circuits
Data Sheet 5-38 V1.2, 2014-06

TC1724
5.2.4 Oscillator Pins
Table 26 OSC_XTAL Parameters

Input current at XTAL1 IIX1 CC -25 25 A VIN> 0 V;

VIN<VDDP
Input frequency fOSC SR 4 40 MHz Direct Input
Mode selected
8 25 MHz External Crystal
Mode selected
Oscillator start-up time1) tOSCS CC 10 ms
Input high voltage at VIHX SR 0.7 x VDDP + V
XTAL12) VDDP 0.5
Input low voltage at VILX SR -0.5 0.3 x V
XTAL1 VDDP
Input hysteresis for HYSAX 200 mV
XTAL1 pad3) CC
1) tOSCS is defined from the moment when VDDP = 3.13V until the oscillations reach an amplitude at XTAL1 of 0.3
* VDDP. The external oscillator circuitry must be optimized by the customer and checked for negative resistance
as recommended and specified by crystral suppliers.
2) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.3 * VDDP is
necessary.
Note: It is strongly recommended to measure the oscillation allowance (negative

resistance) in the final target system (layout) to determine the optimal parameters
for the oscillator operation. Please refer to the limits specified by the crystal or
ceramic resonator supplier.
Data Sheet 5-39 V1.2, 2014-06

TC1724
5.2.5 Power Supply Current

The total power supply current defined below consists of leakage and switching
component.
Application relevant values are typically lower than those given in the following two
tables and depend on the customer's system operating conditions (e.g. thermal
connection or used application configurations).
The operating conditions for the parameters in the following table are:
VDD=1.365 V, VDDP=3.47 V, VDDM=5.1 V, fLMB=133 / 80 MHz, TJ=160 C
The realisic power pattern defines the following conditions:
TJ=150 C
fLMB = fPCP = fCPU = 133 / 80 MHz
fFPI = 66.5 / 80 MHz
VDD = 1.326 V
VDDP = 3.366 V
VDDM = 5.1 V
The max power pattern defines the following conditions:
TJ=160 C
fLMB = fPCP = fCPU = 133 / 80 MHz
fFPI = 66.5 / 80MHz
VDD = 1.37 V
VDDP = 3.47 V
VDDM = 5.25 V
Data Sheet 5-40 V1.2, 2014-06

TC1724
Table 27 Power Supply Parameters

Parameter Symbol Values Unit Note / Test Condition
Min Typ. Max.
.
Core active mode IDD 310 mA power pattern= max ;
supply current1) CC SAK-TC1724F-192F133HL
SAK-TC1724F-192F133HR
SAK-TC1724N-192F133HR
212 mA power pattern= realistic ;
SAK-TC1724F-192F133HL
248 mA power pattern= max ;
SAK-TC1724N-192F80HL
IDD current at IDD_PORST 110 mA
PORST Low CC
PORST pad IDDPORST 13 mA
output current CC
Sum of all 1.3 V IDDSUM 212 mA power pattern= realistic;
supply currents CC SAK-TC1724F-192F133HL
IDDP current at IDDP_PORS 6 mA
PORST Low T CC
Data Sheet 5-41 V1.2, 2014-06

TC1724
Table 27 Power Supply Parameters (contd)

Min Typ. Max.
.
IDDP current no IDDP CC IDDP_ mA including flash read current
pad activity2) PORST
+ 83
IDDP_ mA including flash programming
PORST current 3)
+ 62
IDDP_ mA including flash erase verify
PORST current 3)
+
914)
ADC 5V power IDDM 32 mA
supply current CC
EVR Supply IV5 375 mA power pattern= max;
current CC mode = 5V only with ext. pass
device;
370 mA power pattern= max;
mode = 5V only with ext. pass
device
280 mA power pattern= real;
device;
device;
Data Sheet 5-42 V1.2, 2014-06

TC1724

Min Typ. Max.
.
EVR Supply IV5 310 mA power pattern= max;
current CC mode = 5V only without ext.
pass device;
mode = 5V only without ext.
pass device;
Maximum power PD 902 mW power pattern= max;
dissipation CC mode = all external;
744 mW power pattern= realistic
mode = all external;
Data Sheet 5-43 V1.2, 2014-06

TC1724

Min Typ. Max.
.
dissipation CC mode = 5V only with ext. pass
device;
1950 mW power pattern= max;
device;
device;
device;

dissipation CC mode = all external;
669 mW power pattern= realistic;
mode = all external;
Data Sheet 5-44 V1.2, 2014-06

TC1724

Min Typ. Max.
.
dissipation CC mode = 5V only without ext.
pass device;
mode = 5V only without ext.
pass device;
1) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each customer
application will most probably be lower than this value, but must be evaluated separately.
2) For operations including the D-Flash the required current is always lower than the current for non-DFlash
operations.
3) Relevant for the power supply dimensioning, not for thermal considerations.
4) In case of erase of Program Flash PF, internal flash array loading effects may generate transient current spikes
of up to 15 mA for maximum 5 ms per flash module.
5.2.5.1 Calculating the 1.3 V Current Consumption

The current consumption of the 1.3 V rail compose out of two parts:
Static current consumption
Dynamic current consumption
The static current consumption is related to the device temperature TJ and the dynamic
current consumption depends of the configured clocking frequencies and the software
application executed. These two parts needs to be added in order to get the rail current
consumption.
(1)
= 0, 674 --------- e 0, 02592 T J [ C ]

mA
I
0 C
(2)
= 3, 9 --------- e 0, 02085 T J [ C ]
mA
I
0 C
Data Sheet 5-45 V1.2, 2014-06

TC1724
Function 1 defines the typical static current consumption and Function 2 defines the
maximum static current consumption. Both functions are valid for VDD = 1.326 V.
For the dynamic current consumption using the application pattern and fLMB
= fPCP = 2 * fFPI the function 4 applies:
(3)
mA
I D m = 0, 76 ------------- f CPU [ MHz ]
y MHz
For the dynamic current consumption using the application pattern and fLMB = fPCP = fFPI
the function 5 applies:
(4)
mA
I D m = 0, 9 ------------- f CPU [ MHz ]
y MHz
and this finally results in

(5)
I DD = I 0 + I DYM
Data Sheet 5-46 V1.2, 2014-06

TC1724
5.3 AC Parameters
All AC parameters are defined with maximum driver strength unless otherwise stated.
5.3.1 Testing Waveforms
VD D P
90% 90%
10% 10%
VSS
tR tF
rise_fall
Figure 10 Rise/Fall Time Parameters
VD D P
VD D E / 2 Test Points VD D E / 2
VSS
mct04881_a.vsd
Figure 11 Testing Waveform, Output Delay
VLoad+ 0.1 V Timing VOH - 0.1 V

Reference
VLoad- 0.1 V Points VOL - 0.1 V
MCT04880_new
Figure 12 Testing Waveform, Output High Impedance
Data Sheet 5-47 V1.2, 2014-06

TC1724
5.3.2 Power Sequencing 5V Supply Only
V
5.5V
5V
4.0V
3.63V
3.3V 2.97
1.43V
1.3V 1.17V
PORST (output)
PORST (input)
A B C D E t
Power-Up_EVR_1.vsd
Figure 13 5 V / 3.3 V / 1.3 V Power-Up/Down Sequence

The events for the above points in the power-up/down sequence
A :external supplied voltage reaches operating level
B: external supplied and internal generated voltages reaches operating levels
C: internal generated voltage drops below operating level
D: internal generated voltage resumes operating level
E: external supplied voltage leaves operating level
P0.4 and P0.5 should be kept at the selected setting of '0' or '1' until external supplied
voltage has reached its operating level.
The following list of rules applies to the power-up/down sequence:
All ground pins VSS must be externally connected to one single star point in the
system. Regarding the DC current component, all ground pins are internally directly
connected.
The latch-up risk is minimized if the I/O currents are limited to:
20 mA for one pin group
AND 100 mA for the completed device I/Os
Data Sheet 5-48 V1.2, 2014-06

TC1724
AND additionally before power-up / after power-down:

1 mA for one pin in inactive mode (0 V on all power supplies)
The PORST signal may be deactivated after all VDD5, and VAREF0 power-supplies
and the oscillator have reached stable operation, within the normal operating
conditions.
At normal power down the PORST signal should be activated within the normal
operating range, and then the power supplies may be switched off. Care must be
taken that all Flash write or delete sequences have been completed.
In case of a power-loss at any power-supply, all power supplies must be powered-
down, conforming at the same time to the rule number 2.
Although not necessary, it is additionally recommended that all power supplies are
powered-up/down together in a controlled way, as tight to each other as possible.
Additionally, regarding the ADC reference voltage VAREF0:
VAREF0 must power-up at the same time or later then VDDM, and
VAREF0 must power-down either earlier or at latest to satisfy the condition
VAREF0 < VDDM + 0.5 V. This is required in order to prevent discharge of
VAREF0 filter capacitance through the ESD diodes through the VDDM power
supply. In case of discharging the reference capacitance through the ESD diodes,
the current must be lower than 5 mA.
Data Sheet 5-49 V1.2, 2014-06

TC1724
5.3.3 Power Sequencing 3.3V Supply Only
V
3.63V
3.3V
2.97V
1.43V
1.3V
1.17V
PORST (output)
PORST (input)
A B C D E
t
Power-Up_EVR_2.vsd
Figure 14 3.3 V / 1.3 V Power-Up/Down Sequence

The events for the above points in the power-up/down sequence
A :external supplied voltage reaches operating level
B: external supplied and internal generated voltages reaches operating levels
C: internal generated voltage drops below operating level
D: internal generated voltage resumes operating level
E: external supplied voltage leaves operating level
P0.4 and P0.5 should be kept at the selected setting of '0' or '1' until external supplied
voltage has reached its operating level.
connected.
Data Sheet 5-50 V1.2, 2014-06

TC1724

The PORST signal may be deactivated after all VDD3.3, and VAREF0 power-
supplies and the oscillator have reached stable operation, within the normal
operating conditions.
down, conforming at the same time to the rule number 2.
Data Sheet 5-51 V1.2, 2014-06

TC1724
5.3.4 Power Sequencing all Voltages supplied from External
V
5.5V
5V
4.5V
3.63V VAREF
3.3V
2.97V
1.43V
1.3V
1.17V
0.5V 0.5V 0.5V
VDDP
PORST
power power
down fail
Power-Up 10.v
Figure 15 5 V / 3.3 V / 1.3 V Power-Up/Down Sequence

P0.4 and P0.5 should be kept at the selected setting until external supplied voltage has
reached its operating level.
connected.
At any moment in time to avoid increased latch-up risk,
each power supply must be higher then any lower_power_supply - 0.5 V, or:
VDD5 > VDDP - 0.5 V; VDD5 > VDD - 0.5 V;VDDP > VDD - 0.5 V, see Figure 15.
Data Sheet 5-52 V1.2, 2014-06

TC1724
During power-up and power-down, the voltage difference between the power supply
pins of the same voltage (3.3 V, 1.3 V, and 5 V) with different names, that are
internally connected via diodes, must be lower than 100 mV. On the other hand, all
power supply pins with the same name (for example all VDDP), are internally directly
connected. It is recommended that the power pins of the same voltage are driven by
a single power supply.
The PORST signal may be deactivated after all VDD5, VDDP, VDD, and VAREF0
power-supplies and the oscillator have reached stable operation, within the normal
operating conditions.
At power fail the PORST signal must be activated at latest when any 3.3 V or 1.3 V
power supply voltage falls 10% below the nominal level. If, under these conditions,
the PORST is activated during a Flash write, only the memory row that was the target
of the write at the moment of the power loss will contain unreliable content. In order
to ensure clean power-down behavior, the PORST signal should be activated as
close as possible to the normal operating voltage range.
down, conforming at the same time to the rules number 2 and 4.
Data Sheet 5-53 V1.2, 2014-06

TC1724
5.3.5 Power, Pad and Reset Timing
Table 28 Reset Timings Parameters

Parameter Symbo Values Uni Note / Test Condition
l Min. Typ. Max. t
Application Reset tB CC 150 810 s SAK-TC1724F-192F133HL

Boot Time1)2) SAK-TC1724F-192F133HR
150 1140 s SAK-TC1724N-192F80HL
Power on Reset tBP 2.5 ms
Boot Time3)4) CC
EVR Startup time tEVR 860 1100 s
from Supply CC
ramp-up till
PORST release
HWCFG pins tHDH 16 / fFPI ns
hold time from SR
ESR0 rising edge
HWCFG pins tHDS 0 ns
setup time to CC
ESR0 rising edge
Ports inactive tPI 8/fFPI ns
after ESR0 reset CC
active
Ports inactive tPIP 150 ns
after PORST CC
reset active5)
6)
Minimum PORST tPOA 4.5 ms
active time after CC
power supplies
are stable at
operating levels
Data Sheet 5-54 V1.2, 2014-06

TC1724
Table 28 Reset Timings Parameters (contd)

Parameter Symbo Values Uni Note / Test Condition
l Min. Typ. Max. t
TESTMODE / TR tPOH 100 ns
ST hold time from SR
PORST rising
edge
PORST rise time tPOR 50 ms
SR
TESTMODE / TR tPOS 0 ns
ST setup time to SR
PORST rising
edge
Application Reset tPOR_APP 40 7) s
inactive after SR
PORST
deassertion
1) The duration of the boot time is defined between the rising edge of the internal application reset and the clock
cycle when the first user instruction has entered the CPU pipeline and its processing starts.
2) The given time includes the time of the internal reset extension for a configured value of
SCU_RSTCNTCON.RELSA = 0x05BE.
3) The duration of the boot time is defined between the rising edge of the PORST and the clock cycle when the
first user instruction has entered the CPU pipeline and its processing starts.
4) The given time includes the internal reset extension time for the System and Application Reset which is visible
through ESR0.
5) This parameter includes the delay of the analog spike filter in the PORST pad.
6) This parameter represents the additional time required to ensure that external crystal is stable and operational
at PORST.
7) Application Reset is assumed not to be extended from external, otherwise the time extends by the time the
Application Reset is extended.
Data Sheet 5-55 V1.2, 2014-06

TC1724
V5
10%
V DDPPA
VDDP V DDPPA
VDD
t BP VDD 12%
t EVR t POA
PORST
t POH t POH
TRST
t hd t hd
ESR0
t HDH t HDH t HDH
HWCFG
t PIP t PIP
t PI t PI
Pads
tPI t PI tPI
t PIP
Padstateundefined
Tristateorpulldeviceactive
Asprogrammed
Figure 16 Power, Pad and Reset Timing
Data Sheet 5-56 V1.2, 2014-06

TC1724
5.3.6 EVR Parameter
Table 29 Pass device detector

Pull-up current at VDPG IPU_VDPG 0.7 2.0 mA VDD5 4.5V;
SR VDD5 5.5V
Input low voltage VIL SR 0 1.5 V
Table 30 EVR Parameters

Min. Typ. Max.
Output COUT33 6.8 F ILOAD > 310 mA;
Capacitance on CC ESR < 50m;
VDDP with external pass device,
additional decoupling
capacitor on each supply pin,
2.2 F ILOAD 310 mA;
ESR < 50m;
with internal pass device,
Data Sheet 5-57 V1.2, 2014-06

TC1724
Table 30 EVR Parameters (contd)

Min. Typ. Max.
Output COUT13 6.8 F ILOAD < 250 mA;
Capacitance on CC ESR < 50m;
VDD additional decoupling
4.7 F ILOAD < 250 mA;
ESR < 50m;
Input CIN5 CC 6.8 F depending on ext. regulator
Capacitance on SAK-TC1724F-192F133HL
V5 SAK-TC1724F-192F133HR
4.7 F depending on ext. regulator
Undervoltage VRST5 2.97 V 3.3V single supply
Reset threshold CC 4.5 V 5.0 single supply
for external
supply
Output VOUT33 -80 +80 mV 4.5V VIN 5.5V;
accuracy of CC 1 mA IOUT 310mA
EVR33 after
trimming
Dynamic Load VLOREG - +225 mV dI / dt = 150mA /10 ns
Regulation of 33CC 225
EVR33
Dynamic Line VLIREG -25 +25 mV dV5 / dt = 1V / ms
Regulation of 33CC 1 310mA,
EVR33 4.5V 5.5V
Data Sheet 5-58 V1.2, 2014-06

TC1724
Table 30 EVR Parameters (contd)

Min. Typ. Max.
Undervoltage VRST33 2.97 V
Reset threshold CC
for EVR33
Current drawn EXI33 30 mA No inductive loads allowed.
from EVR33 for SR Decoupling capacitor >
external 330 nF
devices with
internal pass
devices.
Output VOUT13 -30 +30 mV 2.97V VIN 3.63V;
accuracy of CC 1 mA IOUT 250mA
EVR13 after
trimming
Dynamic Load VLOREG - +100 mV 5.0V/3.3V single supply,
Regulation of 13CC 100 dI / dt = 150mA /10 ns
EVR13
Dynamic Line VLIREG -10 +10 mV 5.0V/3.3V single supply,
Regulation of 13 CC dV5 / dt=1V / ms
EVR13 1 250mA, 2.97V 3.63V
Undervoltage VRST13 1.17 V
Reset threshold CC
for EVR13
Current drawn EXI13 10 mA No inductive loads allowed.
from EVR13 for SR Decoupling capacitor >
external 100 nF
devices
Supply ramp-up SR 50 V/ms
SR
Data Sheet 5-59 V1.2, 2014-06

TC1724
5.3.7 Phase Locked Loop (PLL)
Table 31 PLL_SysClk Parameters

Accumulated Jitter DP CC -7 7 ns
PLL base frequency fPLLBASE CC 50 200 320 MHz
VCO input frequency fREF CC 8 16 MHz
VCO frequency fVCO CC 400 720 MHz
range
PLL lock-in time tL CC 14 200 s N > 32
14 400 s N 32
Phase Locked Loop Operation

When PLL operation is enabled and configured, the PLL clock fVCO (and with it the LMB-
Bus clock fLMB) is constantly adjusted to the selected frequency. The PLL is constantly
adjusting its output frequency to correspond to the input frequency (from crystal or clock
source), resulting in an accumulated jitter that is limited. This means that the relative
deviation for periods of more than one clock cycle is lower than for a single clock cycle.
This is especially important for bus cycles using wait states and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Two formulas are defined for the (absolute) approximate maximum value of jitter Dm in
[ns] dependent on the K2 - factor, the LMB clock frequency fLMB in [MHz], and the
number m of consecutive fLMB clock periods.
for ( K2 100 ) and ( m ( f LMB [ MHz ] ) 2 )

( 1 0, 01 K2 ) ( m 1 ) (6)
D m [ ns ] = --------------------------------------------- + 5 ---------------------------------------------------------------- + 0, 01 K2
740
K2 f LMB [ MHz ] 0, 5 f LMB [ MHz ] 1
740 (7)
else D m [ ns ] = --------------------------------------------- + 5
K2 f LMB [ MHz ]
Data Sheet 5-60 V1.2, 2014-06

TC1724
With rising number m of clock cycles the maximum jitter increases linearly up to a value
of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum
accumulated jitter remains at a constant value. Further, a lower LMB-Bus clock
frequency fLMB results in a higher absolute maximum jitter value.
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL = 20 pF with the maximum driver and sharp edge.
Oscillator Watchdog (OSC_WDT)

The expected input frequency is selected via the bit field SCU_OSCCON.OSCVAL. The
OSC_WDT checks for too low frequencies and for too high frequencies.
The frequency that is monitored is fOSCREF which is derived for fOSC.
(8)
fO S C
f O S C R EF = ----------------------------------
-
OSCVAL + 1
The divider value SCU_OSCCON.OSCVAL has to be selected in a way that fOSCREF is

2.5 MHz.
Note: fOSCREF has to be within the range of 2 MHz to 3 MHz and should be as close as
possible to 2.5 MHz.
The monitored frequency is too low if it is below 1.25 MHz and too high if it is above
7.5 MHz. This leads to the following two conditions:
Too low: fOSC < 1.25 MHz (SCU_OSCCON.OSCVAL+1)
Too high: fOSC > 7.5 MHz (SCU_OSCCON.OSCVAL+1)
Note: The accuracy is 30% for these boundaries.
Data Sheet 5-61 V1.2, 2014-06

TC1724
5.3.8 ERAY Phase Locked Loop (ERAY_PLL)
Table 32 PLL_ERAY Parameters

dition
Accumulated jitter at DPP CC -0.8 0.8 ns
SYSCLK pin
Accumulated_Jitter DP CC -0.5 0.5 ns
PLL Base Frequency of fPLLBASE_ERAY CC 50 250 360 MHz
the ERAY PLL
VCO input frequency of fREF CC 20 40 MHz
the ERAY PLL
VCO frequency range fVCO_ERAY CC 450 500 MHz
of the ERAY PLL
PLL lock-in time tL CC 5.6 200 s
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL = 20 pF with the maximum driver and sharp edge.
Data Sheet 5-62 V1.2, 2014-06

TC1724
5.3.9 JTAG Interface Timing

The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 33 JTAG Parameters

TCK clock period t1 SR 25 ns

TCK high time t2 SR 10 ns
TCK low time t3 SR 10 ns
TCK clock rise time t4 SR 4 ns
TCK clock fall time t5 SR 4 ns
TDI/TMS setup to TCK t6 SR 6.0 ns
rising edge
TDI/TMS hold after TCK t7 SR 6.0 ns
rising edge
TDO valid after TCK falling t8 CC 3.0 ns CL= 20 pF
edge1) 13 ns CL=50 pF
TDO high impedance to t9 CC 14 ns CL= 50 pF
valid from TCK falling
edge2)
TDO valid output to high t10 CC 13.5 ns CL= 50 pF
impedance from TCK
falling edge
TDO hold after TCK falling t18 CC 2 ns
edge
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet 5-63 V1.2, 2014-06

TC1724
t1
0.9 VD D P
0.5 VD D P
0.1 VD D P
t5 t4
t2 t3
MC_ JTAG_ TCK
Figure 17 Test Clock Timing (TCK)
TCK
t6 t7
TMS
t6 t7
TDI
t9 t8 t1 0
TDO
t18
MC_JTAG
Figure 18 JTAG Timing
Data Sheet 5-64 V1.2, 2014-06

TC1724
5.3.10 DAP Interface Timing

The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 34 DAP Parameters

1)
DAP0 clock period tTCK SR 12.5 ns
DAP0 high time t12 SR 4 ns
1)
DAP0 low time t13 SR 4 ns
DAP0 clock rise time t14 SR 2 ns
DAP0 clock fall time t15 SR 2 ns
DAP1 setup to DAP0 t16 SR 6.0 ns
rising edge
DAP1 hold after DAP0 t17 SR 6.0 ns
rising edge
DAP1 valid per DAP0 t19 CC 8 ns CL= 20 pF;
clock period2) f= 80 MHz
10 ns CL= 50 pF;
f= 40 MHz
1) See the DAP chapter for clock rate restrictions in the Active::IDLE protocol state.
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t11
0.9 VD D P
0.5 VD D P
0.1 VD D P
t1 5 t14
t1 2 t1 3
MC_DAP0
Figure 19 Test Clock Timing (DAP0)
Data Sheet 5-65 V1.2, 2014-06

TC1724
DAP0
t1 6 t1 7
DAP1
MC_ DAP1_RX
Figure 20 DAP Timing Host to Device
t1 1
DAP1
t1 9
MC_ DAP1_TX
Figure 21 DAP Timing Device to Host
Data Sheet 5-66 V1.2, 2014-06

TC1724
5.3.11 Peripheral Timings
Note: Peripheral timings are not subjected to production test. They are verified by design
/ characterization.
5.3.11.1 Micro Link Interface (MLI) Timing
MLI Transmitter Timing
t13 t14
t10
t12
TCLKx
t11
t15 t15
TDATAx
TVALIDx
t16
t17
TREADYx
MLI Receiver Timing
t23 t24
t20
t22
RCLKx
t21
t25
t26
RDATAx
RVALIDx
t27 t27
RREADYx
MLI_Tmg_2.vsd
Figure 22 MLI Interface Timing
Data Sheet 5-67 V1.2, 2014-06

TC1724
Note: The generation of RREADYx is in the input clock domain of the receiver. The
reception of TREADYx is asynchronous to TCLKx.
The MLI parameters are valid for CL = 50 pF, strong driver medium edge.
Table 35 MLI Receiver

RCLK clock period t20 SR 1 / fFPI ns

RCLK high time1)2) t21 SR 0.5 x t20 ns
RCLK low time1)2) t22 SR 0.5 x t20 ns
3)
RCLK rise time t23 SR 4 ns
RCLK fall time3) t24 SR 4 ns
RDATA/RVALID setup t25 SR 4.2 ns
time before RCLK falling
edge
RDATA/RVALID hold t26 SR 2.2 ns
time after RCLK falling
edge
RREADY output delay t27 SR 0 16 ns
time
1) The following formula is valid: t21 + t22 = t20.
2) Min and Max values for this parameter can be derived from the typ. value by considering the other receiver
timing parameters.
3) The RCLK max. input rise/fall times are best case parameters for fFPImax. For reduction of EMI, slower input
signal rise/fall times can be used for longer RCLK clock periods.
Table 36 MLI Transmitter

TCLK clock period t10 CC 2x1/ ns

fFPI
TCLK high time1)2) t11 CC 0.45 x 0.5 x 0.55 x t10 ns
t10 t10
TCLK low time1)2) t12 CC 0.45 x 0.5 x 0.55 x t10 ns
t10 t10
Data Sheet 5-68 V1.2, 2014-06

TC1724
Table 36 MLI Transmitter (contd)

TCLK rise time t13 CC 0.3 x t103) ns

TCLK fall time t14 CC 0.3 x t103) ns
TDATA/TVALID t15 CC -3 4.4 ns
output delay time
TREADY setup time t16 SR 18 ns
before TCLK rising
edge
TREADY hold time t17 SR -2 ns
after TCLK rising edge
1) The following formula is valid: t11 + t12 = t10.
2) The min./max. TCLK low/high times t11/t12 include the PLL jitter of fSYS. Fractional divider settings must be
regarded additionally to t11 / t12.
3) For high-speed MLI interface, strong driver sharp or medium edge selection (class A2 pad) is recommended
for TCLK.
5.3.11.2 Micro Second Channel (MSC) Interface Timing

The MSC parameters are valid for CL = 50 pF.
Table 37 MSC Parameters

FCLP clock period1)2) t40 CC 2x ns

TMSC3)
Data Sheet 5-69 V1.2, 2014-06

TC1724
Table 37 MSC Parameters (contd)

SOP4)/ENx outputs delay t45 CC -5 5 ns ENx with strong

from FCLP4) rising edge driver and
sharp (minus )
edge;
CMOS mode
-2 10 ns ENx with strong
driver and
medium
(minus) edge
0 21 ns ENx with strong
driver and soft
edge
SDI bit time t46 CC 8x ns
TMSC
SDI rise time t48 SR 200 ns
SDI fall time t49 SR 200 ns
1) FCLP signal rise/fall times are only defined by the pad rise/fall times.
2) FCLP signal high and low can be minimum 1 / TMSC
3) TMSC = TSYS = 1 / fSYS.
4) SOP / FCLP either propagated by CMOS strong driver and non soft edge.
t40
0.9 VDDP
FCLP
0.1 VDDP
t45 t45
SOP
EN
t48 t49
0.9 VDDP
SDI
0.1 VDDP
t46 t46
MSC_Tmg_1.vsd
Figure 23 MSC Interface Timing
Data Sheet 5-70 V1.2, 2014-06

TC1724
Note: The data at SOP should be sampled with the falling edge of FCLP in the target
device.
Data Sheet 5-71 V1.2, 2014-06

TC1724
5.3.11.3 SSC Master/Slave Mode Timing
The SSC parameters are valid for CL = 50 pF, strong driver medium edge.
Table 38 Parameters
Min. Typ. Max. Test Conditi
on
SCLK clock period1)2)3) t50 CC 2x1/ ns
fFPI
MTSR/SLSOx delay from t51 CC 0 8 ns
SCLK rising edge
MRST setup to SCLK t52 SR 16.5 ns
latching edge3)
MRST hold from SCLK t53 SR 0 ns
latching edge3)
SCLK input clock t54 SR 4x1/ ns
period1)3) fFPI
SCLK input clock duty t55_t54 SR 45 55 %
cycle
MTSR setup to SCLK t56 SR 1 / fFPI ns
latching edge3)4) +1
MTSR hold from SCLK t57 SR 1 / fFPI ns
latching edge +5
SLSI setup to first SCLK t58 SR 1 / fFPI ns
latching edge +5
SLSI hold from last SCLK t59 SR 7 ns
latching edge5)
MRST delay from SCLK t60 CC 0 16.5 ns
shift edge
SLSI to valid data on t61 CC 16.5 ns
MRST
1) SCLK signal rise/fall times are the same as the rise/fall times of the pad.
2) SCLK signal high and low times can be minimum 1xT.
3) Tmin = TSYS = 1/fSYS.
4) Fractional divider switched off, internal baud rate generation used.
Data Sheet 5-72 V1.2, 2014-06

TC1724
5) For CON.PH=1 slave select must not be removed before the following shifting edge. This mean, that what ever
is configured (shifting / latching first), SLSI must not be de-actived before the last trailing edge from the pair
of shifting / latching edges.
t50
SCLK1)2)
t51 t51
MTSR1)
t52
t53
1) Data
MRST
valid
t51
2)
SLSOn
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
2) The transition at SLSOn is based on the following setup: SSOTC.TRAIL = 0

and the first SCLK high pulse is in the first one of a transmission.
SSC_TmgMM
Figure 24 Master Mode Timing
Data Sheet 5-73 V1.2, 2014-06

TC1724
t54
First shift First latching Last latching
SCLK1) SCLK edge SCLK edge SCLK edge
t55 t55
t56 t56
t57 t57
MTSR 1) Data Data
valid valid
t60 t60
1)
MRST
t61 t59
SLSI
t58
1) This timing is based on the following setup: CON.PH = CON.PO = 0.

SSC_TmgSM
Figure 25 Slave Mode Timing
Data Sheet 5-74 V1.2, 2014-06

TC1724
5.3.11.4 ERAY Interface Timing

The timings of this section are valid for the strong driver and either sharp edge or medium
edge settings of the output drivers with CL = 25 pF.
The ERAY interface is only available for the SAK-TC1724F-192F133HL and SAK-
TC1724F-192F133HR .
Table 39 ERAY Parameters

Time span from last BSS t60 CC 997.75 1002.25 ns

to FES without the
influence of quartz
tolerancies (d10Bit_TX)1)
TxD data valid from t61-t62 1.5 ns Asymmetrical
fsample flip flop txd_reg CC delay of rising
TxDA, TxDB and falling edge
(dTxAsym)2)3) (TxDA, TxDB)
Time span between last t63 SR 966 1046.1 ns
BSS and FES without
influence of quartz
tolerancies
(d10Bit_RX)1)4)5)
RxD capture by fsample t64-t65 3.0 ns Asymmetrical
(RxDA/RxDB sampling CC delay of rising
flip-flop) (dRxAsym)5) and falling edge
(RxDA, RxDB)
TxD data delay from dTxdly 10.0 ns Px_PDRz.PDy
sampling flip-flop CC = 000B
15.0 ns Px_PDRz.PDy
= 001B
RxD capture delay by dRxdly 10.0 ns
sampling flip-flop CC
1) This includes the PLL_ERAY accumulated jitter.
2) Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers.
Quarz tolerance and PLL_ERAY accumulated jitter are not included.
3) E-Ray TxD output drivers have an asymmetry of rising and falling edges of |tFA2 - tRA2| 1 ns.
4) Limits of 966ns and 1046.1ns correspond to (30%, 70%) * VDDP FlexRay standard input thresholds. For input
thresholds of this product, a correction of - 0.5 ns and +0.1 ns has to be applied.
Data Sheet 5-75 V1.2, 2014-06

TC1724
5) Valid for output slopes of the bus driver of dRxSlope 5ns, 20% * VDDP to 80% * VDDP, according to the FlexRay
Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming signal have
to satisfy the following inequality: -1.6ns |tFA2 - tRA2| 1.3ns.
BSS Last CRC Byte FES

(Byte Start Sequence) (Frame End Sequence)
0.7 VDD
TXD 0.3 VDD
t60
tsample
TXD 0.9 VDD

0.1 VDD
t61 t62
BSS Last CRC Byte FES

(Byte Start Sequence) (Frame End Sequence)
0.7 VDD
RXD 0.3 VDD
t63
tsample
RXD 0.7 VDD

0.3 VDD
t64 t65
ERAY_TIMING
Figure 26 ERAY Timing
Data Sheet 5-76 V1.2, 2014-06

TC1724
5.4 Package and Reliability
5.4.1 Package Parameters
Table 40 Thermal Characteristics of the Package

Device Package RJCT RJC RJCL Unit Note
1)
B1) 1)
TC1724 PG-LQFP-144-17 9.0 0.4 28.1 K/W

1) The top and bottom thermal resistances between the case and the ambient (RTCAT, RTCAB) are to be combined
with the thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate
the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between
the case and the ambient (RTCAT, RTCAB) depend on the external system (PCB, case) characteristics, and are
under user responsibility.
The junction temperature can be calculated using the following equation: TJ = TA + RTJA PD, where the RTJA
is the total thermal resistance between the junction and the ambient. This total junction ambient resistance
RTJA can be obtained from the upper four partial thermal resistances.
Data Sheet 5-77 V1.2, 2014-06

TC1724
5.4.2 Package Outline
Figure 27 Package Outlines PG-LQFP-144-17
Table 41 Exposed pad Dimensions

Ex 7.5 mm
Ey 7.5 mm
You can find all of our packages, sorts of packing and others in our Infineon Internet
Page Products: http://www.infineon.com/products.
5.4.3 Flash Memory Parameters

The data retention time of the TC1724s Flash memory depends on the number of times
the Flash memory has been erased and programmed.
Data Sheet 5-78 V1.2, 2014-06

TC1724
Table 42 FLASH32 Parameters

Data Flash Erase tERD CC 31) s

Time per Sector
Program Flash Erase tERP CC 5 s
Time per 256 KByte
Sector
Program time data tPRD CC 5.3 ms without
flash per page2) reprogramming
15.9 ms with two
reprogramming
cycles
Program time tPRP CC 5.3 ms without
program flash per reprogramming
page3) 10.6 ms with one
reprogramming
cycle
Data Flash NE CC 60000 cycles Min. data
4)
Endurance retention
5 years
Erase suspend delay tFL_ErSusp CC 15 ms
Wait time after tFL_MarginDel SR 10 s
margin change
Program Flash tRET CC 20 years Max. 1000
Retention Time, erase/
Physical Sector5)6) program cycles
Program Flash tRETL CC 20 years Max. 100 erase/
Retention Time, program cycles
Logical Sector5)6)
UCB Retention tRTU CC 20 years Max. 4 erase/
Time5)6) program cycles
per UCB
Wake-Up time2) tWU CC 270 s
Data Sheet 5-79 V1.2, 2014-06

TC1724
Table 42 FLASH32 Parameters (contd)

DFlash wait state WSDF SR 50ns x
configuration fLMB
PFlash wait state WSPF SR 26ns x
configuration fLMB
1) In case of wordline oriented defects (see robust EEPROM emulation in the User's Manual) this erase time can
increase by up to 100%.
2) In case the Program Verify feature detects weak bits, these bits will be programmed up to twice more. Each
reprogramming takes additional 5 ms.
3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The
reprogramming takes additional 5 ms.
4) Only valid when a robust EEPROM emulation algorithm is used. For more details see the Users Manual.
5) Storage and inactive time included.
6) At average weighted junction temperature Tj = 100C, or the retention time at average weighted temperature
of Tj = 110C is minimum 10 years, or the retention time at average weighted temperature of Tj = 150C is
minimum 0.7 years.
5.4.4 Quality Declarations
Table 43 Quality Parameters

Min. Typ. Max.
Operation tOP 24000 hours 2)
Lifetime1)
ESD susceptibility VHBM 2000 V Conforming to
according to JESD22-A114-B
Human Body
Model (HBM)
ESD susceptibility VCDM 500 V Conforming to
according to JESD22-C101-C
Charged Device
Model (CDM)
Moisture MSL 3 Conforming to Jedec
Sensitivity Level J-STD-020C for 240C
1) This lifetime refers only to the time when the device is powered on.
Data Sheet 5-80 V1.2, 2014-06

TC1724
2) For worst-case temperature profile equivalent to:
1200 hours at Tj = 125...160oC
3600 hours at Tj = 110...125oC
7200 hours at Tj = 100...110oC
11000 hours at Tj = 25...110oC
1000 hours at Tj = -40...25oC
5.5 Revision History

Changes from V0.3 to V0.4D1
Operating Conditions
Added footnote 3 and 4
Updated KOVAN and KOVAP max values
Added fCPU, fLMB, fPCP, fFPImax for SAK-TC1724F-192F133HL, SAK-TC1724F-
192F133HR, SAK-TC1724N-192F80HR, SAK-TC1724N-128F80HR.
Updated limits for VDD, VDDM, VDDP.
Added IIN, IIN
Updated ISC_PG
Standard Pad Class A1
Changed RDSON1 to RDSONM, added new condition PMOS for 140ohms, added a
new condition for NMOS with a max value of 100ohms
Added RDSONW
Changed min value of VIHA1 to 0.6 x VDDP
Changed min value of VILA1 / VIHA1 to 0.6
Standard Pad Class A1+
Added HYSA1+
Added VILA1+ / VIHA1+
Added RDSONW, RDSONM
RDSON1+, added new condition PMOS for 85ohms, added a new condition for
NMOS with a max value of 70ohms
Changed min value of VIHA1+ to 0.6 x VDDP
Deleted -2000nA to 2000nA limits for IOZA1+
Standard Pad Class A2
Added HYSA2
RDSON2, added new condition PMOS for 25ohms, added a new condition for
NMOS with a max value of 20ohms
tFA2, added max 18000ns for CL=20000pF; pinout driver=medium, 65000ns for
CL=20000pF;pinout driver=weak
tRA2, removed 140ns for CL=150pF;pinout driver=weak
tRA2, added 550ns for CL=150pF,pinout driver=weak, 18000ns for CL=20000pF,
pinout driver=medium, 65000ns for CL=20000pF, pinoutdriver=weak
Standard Pad Class F
Added HYSF
Data Sheet 5-81 V1.2, 2014-06

TC1724
Changed min value of VIHF to 0.6 x VDDP

Added min value of VILF / VIHF as 0.6
Deleted note for tFF, tRF
Standard Pad Class I
Changed min value of VIHI to 0.6 x VDDP
Changed min value of VILI / VIHI as 0.6
LVDS Pads
Removed input hysteresis F, HYSF
Added note Parallel termination 100 Ohm +-1% for tFL, tRL, tSET_LVDS
Standard Pad Class S
Changed max value of VIHS to 3.6
Changed min value of VILS to 2.1
Added input leakage current, IOZS
ADC parameters
Changed typ value of CAINSW to 9pF
Changed typ value of CAINTOT to 20pF
Updated notes for EADNL,EAGAIN,TUE,EAINL,EAOFF
Changed fADCI to max 20MHz
Added fADC of 110MHz where ffpimax=110MHz
Added fADC of 80MHz where ffpimax=80MHz
Updated fADC min of 4MHz
Added sample time, tS, 2 to 255 tADCI
Added calibration time after reset, tCAL max 4352 cycles
Included footnote for TUE for 10-bit and 8-bit conversion
Removed IAIN7T (covered by RAIN7T )
Removed IAREF, added QCONV
Updated notes for IOZ2 and IOZ3
Updated typ value of 900Ohm for RAIN
FADC parameters
Updated note for EFGRAD
Updated note for EFOFF
Added fFADC of 110MHz where ffpimax=110MHz
Added fFADC of 80MHz where ffpimax=80MHz
Added conversion time, tC
Added analog input voltage range,VAINF
OSC XTAL parameters
Added fOSC
Changed max value of VIHX to VDDP+0.5V
Changed min value of VILX to -0.5V
Added typ values for internal load capacitors, CL0 to CL3, 2.5pF, 2.5pF, 4pF, 6.5pF
Added HYSAX
Power Supply parameters
Data Sheet 5-82 V1.2, 2014-06

TC1724
Updated IDDP, IDDM, IDDP_FP

Added IDD for fCPU=80MHz for max and realistic patterns
Updated PD values for max and real patterns, all external, fCPU=133MHz
Added text to of fCPU=133MHz to the note for the PD parameter.
Added PD for fCPU=80Mhz for max and realistic patterns for both all external mode
and 5V only with ext.pass device mode
Current consumption for LVDS pad pairs is updated for all LVDS pads in total
Deleted the redundant IDDP
Updated IDDP_FP, IDDP_PORST, IDD_PORST
Deleted RTHJA parameter
Power Sequencing
Added Power Sequencing for 3.3V Supply Only section
Power, Pad and Reset Timing parameters
Removed redundant note for tHDH, tHDS
Added text from note TESTMODE/TRST to the name of tPOH and tPOS, deleted
note
EVR Parameters
Added IPU_VDPG, VIH and VIL parameters in Pass Device Detector Table
Added EVR Parameter Table
PLL SYSCLK parameters
Changed max value for fVCO
Added min value of 50us for tL
Included formula 1 and 2
Removed note for peak-to-peak noise on pad supply voltage
PLL ERAY parameters
Changed typ value to 250MHz for fPLLBASE
Added min value of 50us for tL
Removed note for peak-to-peak noise on pad supply voltage
JTAG Interface parameters
Changed to = signs in the notes for t8, t9 and t10
DAP parameters
Peripheral Timings
Removed note for Peripheral Timings Peripheral timing parameters are not
subject to production test. They are verified by design/characterization.
MLI Timing
Added text for MLI parameters valid for CL=25pF
MLI Receiver parameters
Changed fSYS to 110MHz in footnote 3
MLI Tranmitter parameters
Changed t13, TCLK rise time and t14, TCLK fall time to 0.3 x t10
MSC parameters
Added text for MSC parameters valid for CL=25pF
Added limits for different pad drive strength of t45
Data Sheet 5-83 V1.2, 2014-06

TC1724
parameters
Changed min value of tt52 to 16.5ns
ERAY parameters
Changed min value of t60
Changed max value of t61-t62
Changed min and max values of t63
Changed max value of t64-t65
Added dTxdly, dRxdly
Updated ERAY timing figure
Flash32 parameters
Updated tPRD, tPRP
Changed min value of WSDF to 50ns x fLMB
Updated footnote 3
Package parameters
Added RTHJCT, RTHJCB, RTHJCL for LQFP144
Package outline
Added package outline for LQFP176
Changes from V0.5 to V0.6
Added max limit for VRST5 for 5.0V single supply
Removed note above MLI Transmitter table
Updated conditions for tFL and tRL for LVDS pad parameters
Updated limits for RDSONW and RDSONM for Class A1 pads
Updated limits for RDSONW and RDSONM and RDSON1+ for Class A1+ pads
Updated limits for RDSONW and RDSONM and RDSON2 for Class A2 pads
Updated limits for RDSONW and RDSONM for Class F pads
Added footnote 7 to ADC table
Updated QCONVof ADC table
Updated conditions to tL of PLL Sysclk
Changed t19 of DAP from SR to CC
Removed condition for V5
Added FADC input circuit
Updated max limit for VAGND0 and min limit for VAREF0
tBWG and tBWR are added to ADC table
Updated description of tCAL
Added a placeholder for RAIN, RAIN7T, RAREF, tS, fADCI, EADNL, EAINL, EAGAIN, EAOFF, TUE
at a separate ADC table for VDDM=3.3V
Added a placeholder for tAWAF, tAWAS to both ADC tables for VDDM=5V and VDDM=3.3V
Added a placeholder for tFWAF, tFWAS to FADC table for VDDM=5V, VDDM=3.3V
Removed limits of gain=8 for EFGRAD
Added VFAREFI and VFAGNDI parameters
Updated limit of tSF2 to min 120ns
Typo in Note for IV5 at 80MHz is corrected.
Data Sheet 5-84 V1.2, 2014-06

TC1724
Updated max limit of IIN.

Added IIN.
Added Pin Reliability in Overload subchapter.
Removed sentence Exposure to conditions within the maximum ratings will not
affect device reliability. Replaced with the Pin Reliability in Overload subchapter.
Added definition of driver strength settings, updated footnote 4 for ERAY Interface
Timing
Updated max limits of Flash parameters tPRD, tPRP
Updated representation of IDDP
Updated limits of IDD_PORST to max 110mA
Updated limits of IDDP_PORST to max 6mA
Updated limits of IDD for real pattern, fCPU=133MHz, to max 212mA
Added new parameter IDDSUM
Updated max limit of IDDM to 32mA
Updated TC1724 IV5 for max and real patterns, with and without ERAY, fCPU=133MHz
Updated TC1724 IV5 for max pattern, fCPU=80MHz
Updated PD for real pattern, fCPU=133MHz, all external supplies.
Updated TC1724 PD for max and real patterns, with and without ERAY, fCPU=133MHz,
5V only with external pass device.
Updated TC1724 PD for max and real patterns, fCPU=80MHz, 5V only without external pass device.
Updated limit for RDSON2 of A2 pad, P_MOS
Removed VIH for Pass Device Detector
Updated limits for VIL of Pass Device Detector
Updated limits and test conditions for VLOREG33 and VLIREG33
Updated test condition for 5.0V single supply VLOREG13
Updated limits and test condition for 5.0V single supply VLIREG13
Corrected typ and max limits for COUT33 and COUT13
Added limit and test condition for 3.3V single supply VLOREG13 and VLIREG13
Application reset boot time limits are updated
Added min limit for IOZS
Added a new parameter VILSD
Updated limits for tBP, STT
Removed typical text from load of Peripheral Timing sections.
Limits for EFGRAD with Gain=4 is changed to TBD
Min limit for VDDM is changed to TBD
Added EFREFI
Added a placeholder for RFAIN, EFDNL, EFINL, EFGRAD, EFOFF at a separate ADC table
for VDDM=3.3V
Added max and typ limits for RRAIN for VDDM=3.3V
Updated limits of PD for real pattern, fCPU=80MHz, to max 669mW
Added new variant SAK-TC1724F-192F80HR
Updated text for Note column of NE
Data Sheet 5-85 V1.2, 2014-06

TC1724
Corrected typo for Class D pads in PN-Junction Characteristics for positive/negative

overload tables
Updated limits of IDD for max pattern, fCPU=133MHz, to max 310mA
Updated limits of PD for max pattern, fCPU=133MHz, to max 902mA
Corrected typo for COUT13
Updated load jump current for COUT33 and COUT13 for fCPU=80MHz
Changed min to typ value for CIN5
Name of package is updated
Absolute maximum rating section for is updated for VDDP, VIN, VAIN, VAREF0, VAINF
A footnote is added to tERD
A note is added, updated pad supply levels in Pin Reliability in Overload section
Updated min limit for t17 of MLI
Added a footnote to IDDP
Included text to power sequencing sections for setting of P0.4 and P0.5.
Added limits for EFDNLfor Gain= 4, 8
Changed STT to tEVR, updated Power, Pad and Reset Timing figure
Changed min limit of tL for PLL_ERAY timing
Changed min limit of tL for PLL_Sysclk timing
Removed IPU_VDPG for VDD52.97V, VDD53.63V
Updated limit and test condition for COUT33, COUT13
Updated limit for CIN5
Updated limit and test condition for VLOREG33
Removed PSRR33, PSRR13
Updated test condition for VLOREG13
Updated limit and test condition for VLIREG13
Updated min limit for MSC t45, strong sharp setting, CMOS mode
Added VOUT33, VOUT13 parameters
Updated first sentence for Chapter 5.3
Added text for MLI and SSC parameters for validity of strong driver medium edge
only
Updated description for t52 and t53
Changed SSC parameters from CC to SR for t56, t57, t58, and t59
Changed min to max limit for EVR Supply ramp-up parameter
Updated min limit for IPU_VDPG
Added limits for EFGRAD for Gain= 4, 8
Added limits for EFREFI
Data Sheet 5-86 V1.2, 2014-06

TC1724
Updated VFAGNDI, VFAREFI, changed from SR to CC

A footnote is added for VFAREFI
Updated limit for COUT13
Updated limit for CIN5
Added min limit for V5
Updated limits for fADCI, tBWG, tBWR , tAWAF, tAWAS, tFWAF, , tFWAS
Updated limits for ADC table, VDDM=3.3V, fADCI, tBWG, tBWR , tAWAF, tAWAS, tFWAF, , tFWAS,
RAIN7T, EADNL, EAGAIN, EAINL, , EAOFF, TUE , QCONV
Corrected typo in test condition for RDSON
Removed footnote 2 from ISC_D
Added footnote 3 to VDDM
Corrected typo for Class F in Table 14 and Table 15
Updated max limit for ADC parameter tS
Added footnote 2 for t9 of JTAG parameter
Changed t26, t27 from CC to SR
Updated max limit for ADC parameter VAIN
Added footnote 5 to t59
Added tPOR_APP parameter of Reset Timing parameters
Updated max limit for ERAY parameter t60
Updated limits for ADC table, VDDM=3.3V, fADCI, tBWG, tBWR , tAWAF, tAWAS, RAIN7T,
EADNL, EAGAIN, EAINL , EAOFF, TUE , QCONV
Added new marking options for TC1724
Updated description for tCAL
Added a footnote to QCONV
change t48 from 100ns to 200ns in table 29
change t49 from 100ns to 200ns in table 29
extend KOVAN conditon from IOV 0 mA; IOV -1 mA to IOV 0 mA; IOV -2 mA
clearify leakage definition for A1 and I pads for 150C < TJ 160C
change VILS from 2.1V to 1.9V in table 25
change t56 from 1 / fFPI to 1 / fFPI + 1 in table 30
change RAIN from 4500 Ohm to 9000 Ohm in table 15
remove the following product options:
Data Sheet 5-87 V1.2, 2014-06

TC1724
shift the product SAK-TC1724N-192F133HR from step AB to AC
add for products SAK-TC1724F-192F133HR and SAK-TC1724N-192F80HR step
AC
Data Sheet 5-88 V1.2, 2014-06

w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG

Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
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TC1724N192F80HRACKXUMA2

TC1724 DS v12-785810

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32-Bit

Data Sheet I-1 V1.2, 2014-06

5.4.3 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78

Data Sheet I-2 V1.2, 2014-06

Data Sheet 1-1 V1.2, 2014-06

Data Sheet 1-2 V1.2, 2014-06

The SAK-TC1724N-192F133HR has the following features:

Data Sheet 1-3 V1.2, 2014-06

Two General Purpose Timer (GPT12) modules

Data Sheet 1-4 V1.2, 2014-06

The SAK-TC1724N-192F80HL / SAK-TC1724N-192F80HR has the following features:

Data Sheet 1-5 V1.2, 2014-06

Two General Purpose Timer (GPT12) modules

Data Sheet 1-6 V1.2, 2014-06

Table 1 TC1724 Derivative Synopsis

Data Sheet 1-7 V1.2, 2014-06

System Overview of the TC1724

2 System Overview of the TC1724

Data Sheet 2-1 V1.2, 2014-06

System Overview of the TC1724

2.1 Block Diagrams

Optional Ext. Supply

System Peripheral Bus

ASC0 System MLI0

Figure 1 SAK-TC1724F-192F133HL / SAK-TC1724F-192F133HR Block

Data Sheet 2-2 V1.2, 2014-06

System Overview of the TC1724

Figure 2 shows the block diagram of the SAK-TC1724N-192F133HR.

Optional Ext. Supply

System Peripheral Bus

ASC0 System MLI0

Figure 2 SAK-TC1724N-192F133HR Block Diagram

Data Sheet 2-3 V1.2, 2014-06

System Overview of the TC1724

Figure 3 shows the block diagram of the SAK-TC1724N-192F80HL / SAK-TC1724N-

Optional Ext. Supply

System Peripheral Bus

ASC0 System MLI0

Figure 3 SAK-TC1724N-192F80HL / SAK-TC1724N-192F80HR Block Diagram

Data Sheet 2-4 V1.2, 2014-06

System Overview of the TC1724

Figure 4 shows the block diagram of the SAK-TC1724F-192F80HR.

Optional Ext. Supply

System Peripheral Bus

ASC0 System MLI0

Figure 4 SAK-TC1724F-192F80HR Block Diagram

Data Sheet 2-5 V1.2, 2014-06

Figure 5 TC1724 Logic Symbol

Data Sheet 3-1 V1.2, 2014-06

1) This pin is used as standby

1) Only available for

Figure 6 TC1724 Pinning for PG-LQFP-144-17 package

Table 3-1 Pin Definitions and Functions (PG-LQFP-144-17 package)

Data Sheet 3-2 V1.2, 2014-06

Table 3-1 Pin Definitions and Functions (PG-LQFP-144-17 package) (contd)

Data Sheet 3-3 V1.2, 2014-06

Table 3-1 Pin Definitions and Functions (PG-LQFP-144-17 package) (contd)

Data Sheet 3-4 V1.2, 2014-06

Table 3-1 Pin Definitions and Functions (PG-LQFP-144-17 package) (contd)