Nanomanufacturing and Metrology

https://doi.org/10.1007/s41871-018-0016-9 (0123456789().,-volV)(0123456789().,-volV)

REVIEW PAPERS

Promising Lithography Techniques for Next-Generation Logic Devices

Rashed Md. Murad Hasan1 • Xichun Luo1

Received: 23 January 2018 / Revised: 26 March 2018 / Accepted: 16 April 2018

 The Author(s) 2018

Abstract
Continuous rapid shrinking of feature size made the authorities to seek alternative patterning methods as the conventional
photolithography comes with its intrinsic resolution limit. In this regard, some promising techniques have been proposed as
next-generation lithography (NGL) that has the potentials to achieve both high-volume production and very high reso-
lution. This article reviews the promising NGL techniques and introduces the challenges and a perspective on future
directions of the NGL techniques. Extreme ultraviolet lithography (EUVL) is considered as the main candidate for sub-10-
nm manufacturing, and it could potentially meet the current requirements of the industry. Remarkable progress in EUVL
has been made and the tools will be available for commercial operation soon. Maskless lithography techniques are used for
patterning in R&D, mask/mold fabrication and low-volume chip design. Directed self-assembly has already been realized
in laboratory and further effort will be needed to make it as NGL solution. Nanoimprint lithography has emerged
attractively due to its simple process steps, high throughput, high resolution and low cost and become one of the
commercial platforms for nanofabrication. However, a number of challenging issues are waiting ahead, and further
technological progresses are required to make the techniques significant and reliable to meet the current demand. Finally, a
comparative study is presented among these techniques.

Keywords Nanolithography
Throughput
Resolution
Defect density
Overlay

Abbreviations EUVL Extreme ultraviolet lithography

AIMSTM Aerial image measurement systemTM FEL Free-electron laser
BCP Block copolymer FIBL Focused ion beam lithography
CAR Chemically amplified resist HIM Helium ion microscope
CD Critical dimension HP Half pitch
CDU Critical dimension uniformity HSQ Hydrogen silsesquioxane
CHIPS Chemo-epitaxy induced by pillar HVM High-volume manufacturing
structures IC Integrated circuit
CMG Chemically modified graphene ITRS International technology roadmap for
CoO Cost of ownership semiconductors
COOL Coordinated line epitaxy LADI Laser-assisted direct imprint
DPP Discharge produced plasma LAN Laser-assisted nanoimprint
DRAM Dynamic random access memory LELE Litho-etch-litho-etch
DSA Directed self-assembly LER Line edge roughness
EBL Electron-beam lithography LiNe Liu–Nealey chemo-epitaxy
EPE Edge placement error LPP Laser produced plasma
EUV Extreme ultraviolet LWR Line width roughness
MEBDW Multiple E-beam direct write
NA Numerical aperture
& Xichun Luo NDM Nano-defect management
[email protected] NGL Next-generation lithography
1 NIL Nanoimprint lithography
Centre for Precision Manufacturing, Department of Design,
Manufacture and Engineering Management, University of NPGS Nanometer pattern generation system
Strathclyde, Glasgow, UK OAI Off-axis illumination

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OPC Optical proximity correction These new devices will also push patterning to manu-
PMMA Poly(methyl methacrylate) facture even smaller nanostructures. Although this rapid
PS-b-PDMS Polystyrene-block- shrinking of feature size permits for faster processing with
poly(dimethylsiloxane) more power efficiency at a lower cost, it intensely enhances
P2VP-b-PDMS Poly(2-vinylpyridine)-block- the design complexity and introduces various manufactur-
poly(dimethylsiloxane) ing challenges. Table 1 shows the ITRS roadmap require-
RESCAN Reflective-mode EUV mask scanning ments for the lithography techniques. Consequently,
lensless imaging microscope lithography must accomplish the stringent industrial
RET Resolution enhancement technologies requirements with excellent capability to meet the future
RLS Resolution LER sensitivity challenges.
RTP Roll-to-plate Photolithography has been the dominant method of
RTR Roll-to-roll patterning nanoscale features for the microelectronics
R&D Research and development industries since the commencement of the ICs. Resolution
SADP Self-aligned double patterning enhancement technologies (RET) and immersion method
SAQP Self-aligned quadruple patterning enables the photolithography with patterning beyond its
SEM Scanning electron microscope intrinsic resolution limit. RET improves the quality of an
SMARTTM Surface modification for advanced image. It generally includes phase shift mask, optical
resolution technologyTM proximity correction (OPC), modified or off-axis illumi-
SMO Source-mask optimization nation (OAI) and multiple patterning. Although they have
SPIE Society of Photographic Instrumentation extended the capability of the lithography process, these
Engineers methods experience some restrictions as well. Phase shift
STEM Scanning transmission electron method has some limitations on implementation of mask
microscope due to phase termination problems and mask fabrication
S-FIL Step-and-flash imprint lithography difficulties. The OPC technique introduces layout restric-
193i 193-nm Immersion lithography tions and prohibitive costs to make the corrected masks,
while OAI presents complexity to the illumination source
in the wafer stepper and to the mask design.
Multiple patterning is the main technique for current
sub-20-nm volume manufacturing, which enables to print
1 Introduction the patterns that are smaller than the single exposure
lithographic resolution limit using multiple process steps.
In the last few decades, the semiconductor industries had There are many different techniques to implement multiple
followed the Moore’s law; the number of transistors per patterning including litho-etch-litho-etch (LELE), self-
chip had been doubling each process generation. Figure 1 aligned double patterning (SADP) and self-aligned
shows the logic transistor density over the last decade and quadruple patterning (SAQP). However, more and more
the future trend using a quantity density metric. The linear masks will be required for finer process nodes, resulting in
scale implies a doubling of density every 2 years. Intel has prohibitively expensive manufacturing cost and it requires
announced the new 10-nm process that achieves 100.8 much tighter overlay control than single patterning [4].
million transistors per square millimeter. This provides 193-nm immersion lithography (193i) has given influential
notable 2.7 times transistor density improvement over its boost to the further development of microelectronics, and
predecessor and suggests that Moore’s law is likely not the 22- and 14-nm nodes are currently manufactured with
slowing down. This enhancement of transistor density has multi-patterning immersion ArF lithography [5]. However,
been done by shrinking the sizes of the transistors. How- this technique brings enormous process challenges like
ever, the industries have demanded sub-10-nm nodes pat- leaching, immersion defects and the filling methods of a
terning to meet the growing requirements. As reported by purified medium. Despite the challenges, it has been the
the International Technology Roadmap for Semiconductors mainstream lithographic technique used in manufacturing
2015 (ITRS2015), new type of logic devices (Gate-all- industries since last decade. Now it is reaching its intrinsic
around structures) have already been introduced [1]. These limits.
new devices will replace the fin structures soon. This report Despite the high-resolution capabilities, X-ray lithogra-
also demonstrates the development of many new types of phy (utilizes X-rays wavelength of 0.4–4 nm) techniques
memory devices that can be the possible alternatives in the were proved unsuccessful to provide an economically
future. attractive lithographic process due to some difficulties. One
of them was to find the right combination of materials and

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Fig. 1 Logic transistor density [2]

Table 1 ITRS roadmap

Specification (mm) 2017 2018 2019 2020 2021 2022
requirements [3]
Minimum critical level Half Pitch (HP) 13 12 11 10 9 8
Minimum hole dimension 18 16 14 13 11 10
Line width roughness (LWR) 1.4 1.3 1.1 1.0 0.9 0.8
Minimum pattern defect size 10 10 10 10 10 10
Overlay 3.4 3.0 2.7 2.4 2.1 1.9
Minimum hole critical dimension uniformity (CDU) 0.5 0.4 0.4 0.3 0.3 0.3

wavelength. Wrapping of absorber material due to internal is difficult to achieve high resolution, low line edge
stresses is an issue to mitigate. Furthermore, the most roughness (LER) and low sensitivity simultaneously due to
critical point is the failure to furnish suitable masks as these an inherent trade-off relationship between each other (RLS
masks had to be unity magnification and the requirement of trade-off). Therefore, the development of advanced resist
creating the mask from adequately X-ray absorbing mate- materials will be required to break the RLS trade-off
rials. Again, the requirement of thick absorber layers and relationship. In addition, the next-generation resists must
membranous nature of the substrate made X-ray lithogra- have the ability to mitigate the stochastic barrier. The
phy unpopular in nanofabrication arena. advancement of new resist materials is entering a new age
As the conventional photolithography has approached with the accompanied challenges and opportunities to ful-
its ultimate limits, considerable efforts have been devoted fill the stringent requirements for the future patterning
to NGL techniques by various research laboratories and techniques. In this review report, we will discuss the
industries around the globe. These techniques are extreme mechanism, overall status and the challenging issues for
ultraviolet lithography (EUVL), electron-beam lithography the NGL techniques as well as the general issues related to
(EBL), focused ion beam lithography (FIBL), nanoimprint resist materials.
lithography (NIL) and directed self-assembly (DSA). They
have the potentials as the replacement to conventional
photolithography. 2 Extreme Ultraviolet Lithography
With the increasing in patterning resolution, resist is one
of the key challenges for the adoption of the patterning 2.1 Mechanism
techniques in HVM industries. The next-generation
potential techniques drive the need for resist materials with Due to wavelength limitations, current attentions are
high resolution, high sensitivity and low LWR. However, it directed toward developing EUVL which uses extreme

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ultraviolet radiation to increase efficiency, reduces manu- beyond [10]. ASML, a leading company involved in the
facturing cost and supports the development of processing development of EUVL tools, revealed that more than 1000
power. In the last decade, researchers put extensive interest wafers per day had been exposed on its NXE:3300B EUV
in EUVL as a ‘next wavelength’ replacement for 193-nm system over multiple weeks’ duration [8]. They have also
dense-UV lithography [6]. EUVL utilizes 13.5-nm photons claimed that the throughput specification of 125–150
that are obtained typically from a plasma source. EUV light wafers per hour has been achieved on TWINSCAN
is then collected by an optical element called a ‘collector.’ NXE:3400B lithography system [11]. Although, the tar-
Light from the collector is focused into the illuminator geted 4-week average availability (80%) has been achieved
(formed of multilayer-coated normal incidence mirrors as by 2016, it needs to continue to improve further [8].
well as grazing incidence mirrors) through an intermediate In terms of production timescales, ASML predicts it will
focus. The illuminator illuminates the right amount of light go into production in 2018 [1]. The source power, masks
and guides it onto the reticle stage (i.e., a mask). The and resist materials still have critical issues for mass pro-
reflected image of the reticle arrives into the projection duction. For the future technology at the 5-nm node and
optics (consist of six or more multilayer mirrors) with a beyond, sources powers of 500–1000 W at a reduced
demagnification. Finally, the image is focused onto the operational cost per wafer may be required [12]. Laser
wafer stage to form a pattern into a substrate coated with a produced plasma (LPP) and discharge produced plasma
photoresist. Every step is operated in a low-hydrocarbon, (DPP) are two main techniques to produce EUV sources.
high-vacuum environment. Figure 2 shows a schematic of The source power has been improved ten times in last 5
a EUVL exposure system [7]. years [13]. Mizoguchi et al. [14] reported that more than
250 W LPP-EUV powers could be generated by using
2.2 Status and Challenges plasma generation schemes. Another approach by using
FEL (free-electron laser), many tens of kilowatts power can
Over the last few years, considerable progress has been be produced [15]. Mitsubishi electric has successfully
made to move EUVL toward increased high-volume explored a higher average power CO2 laser more than
manufacturing (HVM) viability. Most remarkably, there 20 kW at output power [16]. Now they are developing new
have been substantial developments to exposure through- high-power HVM LPP-EUV source with more than 25 kW
put, reliability, variance control and patterning materials CO2 driver laser system. Although EUV source technology
for the high resolution required [8, 9]. Currently, EUVL is is very close to the requirements, some cost of ownership
projected to use in manufacturing at the 7-nm node or issues need to be investigated before the insertion of EUVL

Fig. 2 Schematic of a EUVL system [7]

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into HVM. For further improvement, novel approaches for reaches the resist surface can be an effective way to avoid
power sources are being still investigated [17, 18]. this problem. Moreover, mechanically strong resists are
A key factor for adoption of EUVL in HVM is the less susceptible to the damage due to the capillary forces
choice of EUV resist with high sensitivity, high resolution, [35]. Another way could be controlling the thickness of the
low LER, low LWR and better contact hole CDU. Chem- resist film properly as thin film can avoid pattern collapse
ically amplified resists (CARs) have effectively achieved during development and rinse. Some other processes were
the scaling requirements of the semiconductor industry studied to decrease pattern collapse with increased reso-
[19]. RLS performance and stochastic variations are the lution [36, 37]. However, traditional resolution enhance-
key issues for the CARs as well as for other resist mate- ment techniques are used to extend the EUVL including
rials. High-sensitivity (\ 20 mJ/cm2) resist materials are OPC and source-mask optimization (SMO). By using SMO
required to reduce the development cost of high-power method, edge placement error (EPE) can be reduced sig-
exposure sources that in turn leads to large LER values. nificantly [38]. Over the last few years some organization
Acid diffusion in CARs influences these performances. like CNSE of SUNY Polytech associated with SUNY
Vesters et al. [20] have reported that by selecting an Polytech SEMATECH have supported the investigation of
appropriate ratio of quencher to PAG (photo-acid genera- EUV resist materials and various EUV resists evaluation.
tor), an EUV dose reduction of up to 12% can be achieved Mask blank defects and yield limit the applicability of
with 240 s PEB (post-exposure bake) time, while keeping EUVL. They are continuing to improve. However, exten-
LWR and resolution constant. sive researches are still needed to improve mask materials,
For better optimization of these parameters, some other fabrication processes, defect inspection and disposition
resist materials and approaches have been studied. Non- metrology and mask protection. To specify, pellicle and
chemically amplified resists (non-CARs) show high-reso- mask inspection are two critical matters to improve overall
lution capability, high sensitivity and low LER as they process defectivity. Highly transmitted and long-lasting
have no acid diffusion issues. Some researchers have pellicles are desirable. The interaction between the oblique
reported the development of the metal containing pho- incident EUV light and the patterned absorber may cause
toresist that has high sensitivity performance, which will be the mask 3D effects at wafer level. Philipsen et al. [39]
very helpful for the low-energy power source to realize have suggested some alternate absorber materials (nickel
EUVL [21, 22]. Some other new techniques including and cobalt) to reduce the mask 3D effects and improving
nanoparticle photoresists with high sensitivity have been the overall imaging window. For the defect-free mask
reported [23–26]. Lately at the 2016 SPIE Advanced manufacturing, an EUV aerial image metrology system, the
Lithography conference, a good amount of papers was AIMSTM EUV, has been developed by ZEISS and the
presented demonstrating the substantial research on Pho- SUNY POLY SEMATECH EUVL Mask Infrastructure
tosensitized CARs [27–31]. Moreover, some approaches consortium to actinic review of EUV mask [40]. These
have been introduced to improve sensitivity, LWR and actinic tools are very useful for blank inspection, pattern
local CDU from many directions [32, 33]. mask inspection, and defect repair verification.
However, it is urgent need to mitigate the stochastic However, Mochi et al. [41] have developed a reflective-
failures such as broken line, nano-bridge, merging holes mode EUV mask scanning lensless imaging microscope
and closing holes. These nano-failures are influenced by (RESCAN) which has the capability of actinic patterned
many factors including aerial image quality, photon mask inspection for defects and patterns with high reso-
absorption, acid shot noise and acid diffusion. The proba- lution and high throughput. In support of EUVL roadmap,
ble solutions lie with the co-optimization of variety of micro-field exposure tools (13.5 nm, 0.5 NA R&D) have
different aspects (materials used, hardware, metrology been developed by Zygo Corporation [42]. According to
etc.). Exposure dose can be an effective knob to drive down ITRS2015 report, ASML is going to produce a 0.55 NA
the failures. Higher dose absorber materials can reduce the EUV scanner with different magnification in both x and y
stochastics. Moreover, the substrate underneath the resist directions, and it could be available to use in manufactur-
influences the exposure dose and the LWR, and therefore, ing in 2021 [1]. ASML has also introduced of its fifth-
optimization of the substrates could be a potential generation EUV scanner, the NXE:3400B, with improved
improvement knob to the exposure dose and LWR reduc- resolution, overlay and focus [11]. However, the accom-
tion [34]. plishment of EUVL as part of the integrated patterning
Pattern collapse is another challenging issue faced by techniques remains a critical issue and therefore the
the resists patterned at high resolution. Several strategies workability of EUVL as a patterning technique continues
have been proposed to mitigate this problem. Since the to accelerate.
capillary forces are one of the reasons for pattern collapse,
eradicating any process steps where liquid–air interface

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2.3 Advantages and Disadvantages been pursued with nanometer resolution, using [ 10,000
e-beams writing in parallel [43]. To make direct write
Advantages of EUVL are high throughput, wide process practicable for wafers, significant developments in pro-
windows and extendibility to future nodes. It uses a smaller ductivity will be required. In recent years, some progresses
wavelength which leads to more densely packed compo- have been reported including MAPPER (a 5 kV raster
nents on the microchip, creating faster processing power. wafer writer) [44], IMS (50 kV raster mask writer, single
Hence, faster computer processors can be achieved with source, many spots in single lens field) [45] and multibeam
EUVL. This technique has the potential to provide eco- wafer writer [46]. These are the promising solutions in
nomic sustainability with its applications in nearly every exposure cost reduction for 20-nm half pitch and beyond.
field including engineering and medical fields. Another Mapper’s 3rd generation platform (FLX) using 650,000
advantage of EUVL is cost-effectiveness. Reduced power beamlets has been introduced with a target of 40 wafers per
consumption and a lessened number of exposures make the hour throughput [47].
EUVL more cost-effective in most patterning processes. As the feature size is shrinking, the resist material plays
Disadvantages of this lithography technique are higher a significant role for attaining required resolution in EBL.
startup costs, complexity, reliability and relative infras- Because of its high sensitivity, sharp contrast and better
tructure immaturity. roughness, PMMA is one of the high-resolution resists that
is commonly used in EBL process. Like EUVL, same
CARs are often used in EBL and they also suffer the same
3 Maskless Lithography problem to minimize the RLS trade-off. One of the
examples of commercially successful inorganic non-CAR
3.1 Mechanism resists used for EBL is Hydrogen silsesquioxane (HSQ)
which shows high-resolution (sub - 5 nm) capability, high
EBL and FIBL are maskless techniques that are widely etch resistance and small local CDU [48, 49]. However,
used in nanostructure patterning and IC fabrications with these resists display relatively low sensitivity. Hence, new
its ability to form arbitrary two-dimensional patterns down high-resolution inorganic resist materials with high sensi-
to the nanometer scale. EBL uses an accelerated electron tivity have been proposed such as metal containing resists.
beam to dramatically modify the solubility of a resist Mapper Lithography, CEA-Leti and Raith are the lead-
material during a subsequent development step. The elec- ing providers and are working to develop turnkey solutions
tron beam is focused on the resist and then scanned on the for EBL and FIB systems. In the last decade, less than
surface of the resist with the diameter as small as a couple 10-nm resolution capability by maskless lithography has
of nanometers in a dot by dot fashion. Then the patterns been repeatedly reported [50–52]. Electron microscope
can be transferred to the substrate material by etching like equipped with pattern generator modules enables nanoscale
other lithographic methods. patterning within desired areas. The nanometer pattern
Similarly, FIBL involves the exposure by an accelerated generation system (NPGS) is one of the popular SEM
ion beam to directly hit the sample surface. When high- (scanning electron microscope) lithography system that
speed ions hit the sample surface, energy is transmitted to provides a powerful, versatile and user-friendly system for
atoms on the surface, which leads to five possible reactions: doing advanced EBL or ion beam lithography using a
(1) sputtering of neutral ionized and excited surface atoms, commercial SEM, scanning transmission electron micro-
(2) electron emission, (3) displacement of atoms in the scope (STEM) or helium ion microscope (HIM) [53].
solid, (4) emission of photons, and (5) chemical reactions. According to ITRS roadmap, the key challenges for these
Based on these phenomena, FIBL systems are also maskless technologies is to build a pilot tool for patterning
employed for depositing materials such as tungsten, plat- entire wafers with chip like patterns and overlay control.
inum, and carbon via ion-beam-induced deposition and the The earliest insertion of such kind of technology is
implantation that can modify a material surface. Figure 3 expected in 2021, and the target would be the ‘5 nm’ logic
shows the process steps of EBL and FIBL system. node [1].

3.2 Status and Challenges 3.3 Advantages and Disadvantages

However, both methods suffer from low throughput that Electron beam and focused ion beam lithography have
limits their applications within research and mask/mold advantages of high resolution, high density, high sensitivity
fabrication. To increase the system throughput, multiple and high reliability. As these techniques are maskless, they
e-beam direct write (MEBDW) lithography concepts have are the ideal tools for flexible generation for low-volume
applications. Due to their intrinsically high resolution,

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Fig. 3 The process steps of

a EBL and b FIBL system

excellent pattern definition can be achieved. They are connected with two moveable springs through the pullers.
highly automated and very accurate control of pattern with Replicating of ultra-precision micron scale structures can
direct writing. EBL has greater depth of focus and also a be achieved with this thermal roller imprinting process at
great choice for the formation of masks and templates for the scan speed of 0.1–10 mm/s.
the optical lithography and nanoimprint lithography. On UV-NIL is a room temperature and low-pressure imprint
the other hand, it has the drawback of low speed and low technique which involves coating of the sample surface
throughput. It is complicated and expensive system as well. with a UV-curable liquid resist. The resist material is
It also suffers from scattering and over exposure problems. exposed to the UV light and the subsequent solidification
Hence this method is not efficient for industrial processing. of the resist under UV radiation. Afterward, an optically
transparent mold is pressed into the substrate to extract the
patterns. An advantage of using transparent mold is to offer
4 Nanoimprint Lithography the possibility for easy optical and high-precision align-
ment. This benefit is employed in step-and-flash imprint
4.1 Mechanism lithography (S-FIL), an advanced version of UV-NIL,
which can nanopattern the whole wafer in a reduced pro-
Nanoimprint lithography is an advanced nanofabrication cessing time. In S-FIL, the imprint material (low-viscosity,
method that is capable of high-throughput patterning of photo-curable monomer) is dispensed dropwise on the
nanostructures with high resolution (down to the 5-nm substrate.
regime). Because of the low cost, reduced process steps The laser-assisted direct imprint (LADI) is a resistless
and high fidelity, NIL became an attractive technique for a technique that does not require etching. With this tech-
wide range of applications. Nanoimprint lithography nique, a single excimer laser pulse is exposed through the
methods can be classified into four categories: thermal transparent quartz mold to melt a thin surface layer of
NIL, UV-NIL, laser-assisted NIL and electrochemical silicon substrate. Then, the resulting liquid layer is
nanoimprints. The basic steps of NIL process are shown in embossed by the quartz mold. Finally, the mold is released
Fig. 4. after the substrate has cooled down. Various nanostructures
In thermal NIL, a fine film of a thermoplastic polymer with sub-10-nm resolution could be imprinted into silicon
(imprint resist) is deposited first by spin coating onto the wafer using LADI with the embossing time below 250 ns.
substrate. The next step is to press the prefabricated mold The capability of high-resolution and high-speed patterning
with the substrate together under a certain pressure. Sub- makes the LADI as a promising technique for a variety of
sequent heating is used above the polymer’s glass transi- applications, and it can be extended to other materials
tion point to achieve the softened polymeric film. In the (polysilicon, Ge, and dielectrics) and processing tech-
post-thermal cooling process, the substrate is cooled down, niques. Similarly, laser-assisted nanoimprint (LAN)
and mold is removed from it, while keeping the pattern lithography utilizes a single excimer laser pulse to melt the
resist on the substrate. Finally, an etching process is used to polymer. Then a fused quartz mold is used to pattern the
remove the resist residual layer. Youn et al. [54] described nanostructures. This technique can be used in patterning
a thermal roller NIL approach where the stamp is various polymer films on a Si or quartz substrate with high

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Fig. 4 Basic NIL process steps

fidelity over the entire mold area. Using LAN technique, the contamination to the underlying adhesion layer.
the imprinting time could be less than 500 ns. The heating Another reason for these defects is shorter resist spread
and expansion of the substrate and mold can also be times. During separation process, shear forces imparted
reduced significantly so that better overlay alignment between the mask and wafer can slit the feature. Careful
between the two can be achieved. controlling of the system during separation can mitigate
Electrochemical nanoimprinting is a resistless approach these defects. To reduce the particle defects, which are
that uses a mold fabricated from a superionic conductor. In located on the wafer and mask, some approaches have been
this process, a voltage is applied between the mold and the taken including air curtain system and polishing [55, 56].
target substrate. Once the surfaces of the mold are in Recently, it has been revealed that defectivity level has
contact with the substrate, current flows between them. The been lessened to below 1 pcs per cm2 at a throughput of 15
strong electric flux from the protrusive parts of the mold to wafers per hour [57]. Another key issue of NIL that should
the substrate results anodic oxidation of the substrate sur- be realized is nano-defect management (NDM) technology
face corresponding to the protrusive parts of the mold with that includes defect inspection of templates and imprinted
the moisture present between the mold and the substrate. wafer, the resist material innovation and the defect miti-
Subsequently, the substrate is etched to achieve the gation. These problems can be mitigated through intensive
nanostructures like other methods. collaboration with various providers. Moreover, substantial
studies are required on post-etching resist defects and resist
4.2 Status and Challenges pattern etching resistance under sub-20-nm node [58].
One of the critical issues for NIL is high overlay accu-
Nevertheless, some challenges have prohibited NIL from racy. Generally, the current devices now require an overlay
being adopted on a larger scale such as defectivity, con- of better than 4 nm, 3 r. For the demanded overlay accu-
tamination, throughput and overlay issues. Defectivity racy, a lot of technology enhancements are required such as
plays a significant role to meet the cost of ownership (CoO) the improvement in overlay control accuracy, image
requirements. Defectivity in NIL process includes non-fil- placement accuracy and mix-and-match technique. Fuku-
led defects, solid phase defects during separation process hara et al. [59] demonstrated that an overlay of 4.5 nm 3 r
and particle defects. Non-filled defects are formed due to and 7.5 nm 3 r can be achieved for the NIL-to-NIL process

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and NIL-to-optical process, respectively, using current NIL designed pattern is changed slightly. Another disadvantage
tool. They also confirmed the overlay residual of 2.5 nm 3 is the current reliance on other lithography techniques to
r for NIL-to-NIL and 4.5 nm 3 r for NIL-to-optical. It is fabricate the mold, and the mold fabrication needs lots of
very close to the target, but it requires further improvement money and time.
to meet the future demand. However, the CDU and LER
are found to be less than 2 nm [57].
The throughput of a nanoimprint system is influenced by 5 Directed Self-Assembly
several parameters. One of the contributors is resist fill
time. By careful optimization of several parameters (resist 5.1 Mechanism
drop volume, system controls, material engineering, design
for imprint and system controls), fill time can be decreased. DSA is one of the promising techniques for high-volume
It has been reported that throughput per imprint station low-cost manufacturing at a sub-lithographic resolution.
improved significantly to 15 wafers per hour with a 1.5 s DSA enables finer resolution that attracted a great deal of
fill time [60]. Now it is targeted at 80 wafers per hour on a interest from major semiconductor manufacturers. Recent
four station. One of the major influences of NIL technology developments in DSA materials and processing make it
is the capability of large-area printing. Large-area pat- compelling next-generation patterning techniques. There
terning with high density and high fidelity has been are two types of DSA processes: ‘epitaxial self-assembly’
reported in the earlier reports [61, 62]. For high-resolution (Chemo-epitaxy) and ‘graphoepitaxy.’ In epitaxial self-
large-area patterning, roll-type UV-NIL process with a assembly, dense chemical patterns are employed to direct
flexible transparent thin stamp has been proposed [63]. Last block copolymer (BCP) self-assembly. Highly ordered
few years significant development of a high-speed and nanopatterns can be achieved if the period of the surface
large-area roll-to-roll (RTR) and roll-to-plate (RTP) NIL chemical pattern is proportionate with the equilibrium
apparatus for large-area patterning of flexible substrates period of the BCP self-assembled nanostructure.
have been demonstrated [64–67]. Graphoepitaxy guides patterning by topographical geome-
The effect of the imprinting parameters need to be try for DSA. The selective wetting of a BCP component at
realized such as temperature, loading force, aspect ratio the trench side walls enforces the lateral ordering of the
and imprinting velocity on formability. In addition, it is self-assembled BCP nanodomains along the trenches.
necessary to optimize the etching process carefully for Thus, it improves the pattern density by subdividing the
high-resolution replica fabrication. To accelerate this topographical pre-pattern. Figure 5 presents the schematic
technology adoption, recently CEA-Leti and EV Group illustration of the two processes [70].
initiated a new program called INSPIRE to diversify the
NIL applications beyond semiconductors [68]. Canon also 5.2 Status and Challenges
designs nanoimprint lithography tools by collaborating
with other vendors and the end users [69]. DSA pattern defects, pattern uniformity, pattern placement
accuracy, material quality control, cost and ease of inte-
4.3 Advantages and Disadvantages gration into manufacturing flows are the critical issues to
adopt DSA technology on semiconductor manufacturing.
NIL is the extremely simple process and offers a promising Missing and bridge holes are the typical defect types of
low-cost alternative lithography technology with some
other advantages such as high resolution, CDU and smaller
LER. NIL is a fast process. Since it can be used to fabricate
nanopatterns at a large scale in a short time, this can be a
high-throughput technique. It has also low cost of owner-
ship and high-resolution extendibility. Nevertheless, NIL
could offer its 3D patterning capability for the advance-
ment of 3D chip technology. Because of its flexibility and
ability to combine with other techniques, it has created
huge opportunities for the future lithographic techniques
for many others potential applications. However, low
overlay structure accuracy and thermal expansion effects
are the disadvantages of the NIL. One of the drawbacks of
NIL over other nanofabrication techniques is the flexibility
of patterning. The mold must be remanufactured when the Fig. 5 Schematic illustration of DSA processes [70]

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DSA holes in physical guide. Researchers are also focusing sub-5-nm process nodes. They have the potential to widen
on recognizing the factors that are responsible for the the area of applications for DSA. Morita et al. [85]
assembly defects (dislocations and line-period bridges). described a low-cost lithography process for making sub-
The sources for these defects are guide pattern mismatch- 15-nm pattern using DSA on nanoimprinting guide.
ing, particles on the substrate and chemical issues. Missing Developments of several new processes have been reported
defects are related to critical dimension (CD) and the sur- such as CHIPS flow [86], LiNe process [87], SMARTTM
face affinity of the guide pattern, while the dislocation process [88] and COOL process [89]. Recently, several
defects are associated with insufficient bake process [71]. application fields for DSA other than semiconductor device
Pathangi et al. [72] presented the 14-nm half-pitch DSA process such as flexible/transferable DSA technology uti-
line/space patterning into the Si substrate with reduced lizing chemically modified graphene (CMG) have been
defectivity. More recently it has been claimed that a dense demonstrated [90, 91]. Several DSA consortiums (CEA-
(pitch 120 nm) contact area superior to 0.01 mm2 free of Leti, IBM and IMEC) are involved in systematic investi-
DSA-related defects is achieved [73]. Moreover, to gation to integrate DSA effectively into commercial
improve pattern quality, some experiments have been semiconductor process. However, further research will be
performed on various etch mask materials and etch process required on process optimization, perfect defect control,
conditions [74]. effective pattern transfer and relevant material develop-
LER is another challenge of DSA line patterns. For ment to make DSA capable of various commercial device
HVM industries, the LER number should be about 10% of manufacturing as a next-generation lithography solution.
the target critical dimension. It has been suggested that
optimization of pattern transfer process is one of the 5.3 Advantages and Disadvantages
effective ways to improve the LER of DSA pattern. By
using this method, LER can be improved less than 2 nm By DSA, the overall resolution can be increased to a level
[75]. Further improvement is required for the sub-10-nm that is compatible with the 7- and 5-nm logic nodes. DSA
pattering node. The interfacial length between the two could simplify and reduce the process steps. It can ease
domains has an effect on the LER of DSA lines. Since, it is process integration and provide low-cost processing in
related to the Flory–Huggins interaction parameter (v) of advanced semiconductor processes. The other advantages
BSPs, one solution to improve the LER could be the of DSA are reduced defectivity through material and pro-
adoption of BCPs with a higher v number. However, the cess optimization, increased pattern fidelity, better material
high v block copolymers are still not easily available. quality control at HVM and high throughput. The block
Another issue of DSA of BCPs is the pattern density. copolymers have defects repair tendency in the patterns
Some pattern density enhancement approaches have been manufactured by other photolithographic techniques. With
proposed including ‘thermal flow process,’ ‘lift-off pro- this ability, DSA can play a major role in the future of
cess,’ and ‘pattern trimming process’ [76–80]. By utilizing semiconductor fabrication. In addition, required pattern
a low-topography resist, pre-pattern * 5 teradot/in2 dot geometries are all possible using designed DSA. By DSA,
arrays with long-range order have been demonstrated [74]. it is possible to define accurately the orientation, structural
Highly ordered patterns using PS-b-PDMS have been dimensions and pattern density. However, in terms of LER
reported in some publications [81, 82]. The minimum and CD control, DSA seems still to be well behind EUVL.
feature size is inherently determined by v of BSPs. High v Other disadvantages are defectivity, limited pattern types,
BCP, P2VP-b-PDMS has been reported that can generate random orientation and relative long processing time.
6-nm scale line/space pattern [82]. Recently, a research
group from the Argonne National Laboratory has devel-
oped a new way to create some of the world’s thinnest 6 Comparison and Discussion
wires using DSA process that could enable mass manu-
facturing with standard types of equipment [83]. Table 2 shows the comparison of the various lithography
DSA can also integrate bottom-up self-assembly with techniques in terms of resolution size, overlay accuracy,
top-down conventional lithography. It can enhance the throughput, defect density and cost. Each technique has its
capabilities of other lithographic techniques that enable own strengths and limitations. Although, these lithography
manufacturing at a drastically reduced cost. The probable techniques show the promising capability to meet the
integration of DSA with ArF immersion photolithography future demand, they need further improvement in some
for 16-nm line/space DRAM process scheduled in 2018 aspects. They are shown in spider charts in Fig. 6. In terms
[84]. Researchers are investigating the possibility of hybrid of resolution, all the next-generation lithography methods
DSA processes (combination of both chemo- and have the ability to achieve resolution levels 10 nm and
graphoelements) which can be possible alternatives for beyond. However, maskless and nanoimprint lithography

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Table 2 Comparison of NGL techniques

Parameters 193 ArF EUVL Maskless NIL DSA
[94]

Resolution 10 nm \ 10 nm [11] \ 5 nm [95] \ 10 nm [69] \ 10 nm [83, 98]

SAQP
Overlay \ 2.3 nm \ 2 nm [8] \ 20 nm 4.5 nm [59] \ 2 nm [99]
[96]
Throughput [ 250 [ 150 wafers/h 40 wafers/h 15 wafers/h per imprint *150 wafers/h track process with 5 min anneal
wafers/h [11] [47] station [60] time [100]
Defect \ 1 cm-2 \ 1 cm-2 [8] \ 1 cm-2 \ 1 cm-2 [57] * 0 cm-2 [73]
density [97]
Cost High Very High High Low Low

are limited by low throughput. Slow blanking speed is one 7 Conclusion

of the major issues for the EBL system speed and the
system complexity let it difficult to improve. In NIL, some For many years, nanolithography technology has con-
factors are responsible for low throughput such as imprint tributed to the advance in the nanomanufacturing industry
time, mold modification and imprinting process. Large- and is influencing the future of nanoscience and technol-
area patterning may enhance the throughput, but further ogy. Flexibility, high throughput, high resolution, high
improvement is needed to meet the industrial requirements. reliability, high efficiency and low cost are the require-
High overlay accuracy is one of the significant issues in ments for the nanolithography techniques to meet the
NGL techniques. Within 2020, the required overlay is future demand. Conventional photolithography has been
anticipated to be 3–4 nm for DRAM, flash and logic the main lithography technique that meets the current
devices [92]. Overlay in NIL has been achieved below throughput demand for the semiconductor industry but
5 nm while tens of nm in maskless lithography. For better comes with its resolution limit. In the last decade, con-
overlay accuracy, a lot of technology improvements are siderable effort has been made in the development of
required such as overlay control accuracy for tools, the nanolithography techniques for mass production of inte-
metrology to precisely measure alignment and image grated circuits. Through this review, an overall status of the
placement accuracy. potential next-generation lithography techniques has been
However, the probability of defects increases with the provided.
enhanced resolution. Although, it is difficult to improve
• EUVL is expected to be available shortly with high-
defect density due to the contact nature in NIL process,
resolution capability but its adoption in HVM industry
substantial researches are taking place to improve it close
remains uncertain. The EUVL infrastructure needs
to the required value. Along with other issues, defectivity is
substantial progress including source reliability, LER/
still the main challenge to DSA implementation to various
LWR improvement and defectivity. More studies are
commercial device manufacturing situations as a NGL
required to develop the issues related to cost of
solution. In last 2 years, defect density has been improved
ownership. EUVL can be more cost-effective by
significantly from 24 cm-2 to * 0 defect cm-2 [73, 93].
enabling new integration schemes through other tech-
Two more orders of magnitude are still needed to meet the
niques (planarization, DSA). It can also include multi-
industrial requirement of 0.01 defects cm-2. Finally yet
patterning (Double expose), LELE process to prepare
importantly, the deciding factor for the lithography tech-
this technique for next-generation patterning in future.
niques is its cost efficiency rather than its technical per-
• Although, EBL and FIBL techniques have high-density
formance. EUVL infrastructure and tools are costly and
ultra-high-resolution patterning capability, patterning
large numbers of mask steps required make the technique
speed significantly limits their application within low-
relatively expensive. Maskless lithography is also costly
volume production. To attain high performance from
due to its expensive electronics. On the contrary, NIL and
these techniques, the tool, the resist parameters, and the
DSA are the promising low-cost techniques for the future
overall lithography process must be optimized.
patterning nodes.
• NIL has demonstrated the potentials to achieve the
increasing demand for high-volume production.
Despite of the huge commercial success, there are still
many challenges that lie in NIL fabrication processes.

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Fig. 6 Spider charts comparing promising NGL techniques

Defectivity and overlay accuracy remains the main All these techniques are still being developed to reach
concerns and further improvements are required to the roadmap requirements and are expected to come across
meet the industrial requirements. as a novel next-generation lithography technique.
• DSA is considered as a promising patterning option that
can reduce multi-patterning strategies. Despite being
made satisfactory progress, some issues related to
Acknowledgements The authors gratefully acknowledge the financial
defectivity, placement accuracy and tool design need to support from the EPSRC (EP/K018345/1) for this study.
be investigated properly. In addition, the challenges of
DSA integration into fab flow and designing chips Open Access This article is distributed under the terms of the Creative
Commons Attribution 4.0 International License (http://creative
around the technology also need to be addressed before
commons.org/licenses/by/4.0/), which permits unrestricted use, dis-
the complete implementation in manufacturing. tribution, and reproduction in any medium, provided you give
appropriate credit to the original author(s) and the source, provide a
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