INTERNATIONAL

TECHNOLOGY ROADMAP
FOR
SEMICONDUCTORS

2013 EDITION

LITHOGRAPHY SUMMARY

THE ITRS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY
COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS OR EQUIPMENT.

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Table of Contents
Lithography ........................................................................................................................... 1
Scope ........................................................................................................................................... 1
Difficult Challenges ....................................................................................................................... 1
Lithography Technology Requirements......................................................................................... 2
Lithography Potential Solutions..................................................................................................... 3
Crosscut Needs and Potential Solutions ....................................................................................... 4
Impact of Future Emerging Research Materials ............................................................................ 4
References ................................................................................................................................... 4

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 Lithography 1

LITHOGRAPHY
SCOPE
This chapter discusses the different lithography methods that are potentially available to meet the resolution and pattern
quality requirements needed to meet the device needs of the ITRS roadmap. Table LITH1, Lithography Technology
Requirements, shows these basic patterning requirements from 2014 to 2028. For the first time, this table also includes
contact hole pitches and finFET fin half pitches. FinFETs were introduced into production in 2012 and the fins are the
smallest half pitches in a finFET containing chip. Contact holes and other hole types patterns such as vias and cuts for
complementary lithography are some of the most difficult patterns to image. The minimum half pitches that can be
achieved are always larger than what can be resolved for lines and spaces. The projected line and space half pitches and
fin half pitches come from the basic device roadmap. Overlay and CD control requirements are calculated from these half
pitches. The logic minimum contact hole pitches come from basic design requirements of CMOS logic devices. The
memory contact hole pitches come from actual device construction data and are extrapolated assuming a similar ratio
contact hole pitch to line and space pitch in the future. The table also shows chip size and wafer flatness requirements
along with relevant tool numerical apertures (NAs).

DIFFICULT CHALLENGES
In the near term, most of the key challenges relate to multiple patterning and EUV. The advent of quadruple patterning
does not increase mask pattern complexity, but it does drive overlay, CD control mask image placement and process cost
and cycle time. For EUV, the biggest issue is source power. Without enough source power, the cost of EUV is very high
because throughput is very low. In 2013 it was reported that an EUV pilot tool was running at 2 to 3 wafers per hour. 1
There are EUV sources reported with powers in the range of 40 to 55 watts at intermediate focus, 2 which should give 43
wafers per hour with 15mJ/cm2 resist, 3 but there are not yet any reports of such sources being used in the field. Even if
there is enough source power, there are other key short term challenges. EUV mask infrastructure needs to be in place to a
large enough extent that customers can buy a reasonable number of defect free masks. And resists and resist post
processing have to improve to give sufficient pattern quality to make functioning devices that meet performance targets.
Directed Self-Assembly (DSA) is a possibility in the short term for simple patterns, but it needs to demonstrate
sufficiently low defects and good pattern registration in order to be viable.
In the long term EUV source power has to increase. Not only will this reduce cost, but it will help with potential shot
noise and resist performance issues that are expected to arise as the roadmap moves to smaller feature sizes. EUV will
also need to be extended to NAs higher than 0.40. But such NAs require a wider range of reflection angles from the
mirrors making up an EUV lens. This can create problems in lens design and problems in consistent reflectivity from
EUV mirrors at different angles. One approach to this issue is to change the magnification factor of the lens. This requires
either smaller exposure field sizes or larger masks, both of which create challenges of their own. All of the other
alternative imaging technologies have challenges of their own. DSA will require DSA compatible designs or novel DSA
implementations with more design flexibility. Maskless lithography needs to have actual working tools. Imprint has to
improve its defectivity. Finally, there are many metrology challenges that will need to be addressed, no matter what
patterning technology is used. A summary of these challenges is shown in Table LITH2.

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2 Lithography

Table LITH2 Lithography Difficult Challenges

Near Term Challenges (2013–2016)
1 Cost and cycle time of multiple patterning – especially for more than 2x
2 Process control on key parameters such as overlay, CD control, LWR with multiple patterning
3 EUV Source power
EUV Mask Infrastructure (defect inspection and verification, mitigation, mask lifetime)
4
Defect free EUV mask blanks, mask availability
5 EUV resist and/or process that meets sensitivity, resolution, LER requirements
6 DSA defectivity and positional accuracy
Long Term Challenges (2017 and beyond)
1 Higher source power for EUV
2 Higher NA EUV tool and mask implementation and infrastructure
3 DSA compatible design rules
4 EUV Extension (wavelength, mask, mirrors, resist, etc.)
5 Maskless lithography production tool demonstration
6 Imprint defectivity, throughput and OL matching
7 Metrology tool availability to key parameters such as CDU, thickness control, overlay, defect

LITHOGRAPHY TECHNOLOGY REQUIREMENTS

Lithography, as presently practiced in semiconductor manufacturing, uses projection steppers and scanners at several
wavelengths in order to address the needs of patterning different layers within a semiconductor device. The highest
resolution lithography is done using a wavelength of 193nm (ArF) and immersion scanners with 1.35NA lenses. This type
of lithography is well established. It has a resolution limit of 40nm half pitch for simple patterns of lines and spaces and a
somewhat larger resolution limit for other types of patterns. Smaller half pitches than 40nm are in production now and are
produced by printing a pattern of 40nm half pitch or larger and then using process steps to halve the pitch (pattern
doubling), or by doing more than one exposure per level in a way that combines two printed patterns into one higher
resolution pattern. Relatively simple patterns such as the minimum half pitch patterns of flash memory or the fins in
finFET devices are done with self-aligned double pattering (SADP). This creates lone parallel lines that then require an
additional “cut” step that create shorter line segments. Using line and space patterning followed by “cuts” is known as
complementary lithography. Metal levels in DRAM and Logic chips can have more complicated patterns that can’t be
done with SADP. These metal layers require Litho Etch Litho Etch (LELE) type double patterning rather than SADP.
This technique requires two exposures and pattering steps per layer and is more expensive than SADP. Some further
increases in resolution can be done by pattern quadrupling, where a pattern is doubled and then doubled again solely by
process steps on a wafer patterned with immersion lithography. But this has only been demonstrated for very simple
patterns. Other types of patterns require demonstration of more complicated multiple patterning or implementation of
some new technique.
Historically, lithography resolution has been improved by decreasing the exposure wavelength, by increasing the NA of
exposure tools and by using improved materials and processes. The NA of 193nm exposure tools cannot be extended
since higher index immersion fluids are not available. Smaller optical wavelengths such as 157nm cannot be used due to
lack of a suitable immersion fluid and/or the lack of a lens material. So the industry has been working on extending
resolution by using EUV, which has a wavelength of 13.5nm. EUV exposure tools with 0.33NA started shipping in 2013
for use in chip research and development and pilot production and these tools should be operational in the first half of
2014. These tools have resolution capability of well under 30nm for contact hole half pitch and well under 20nm for line
and space half pitch. But these tools will need source upgrades with brighter light sources if they are to have sufficient
throughput for production use. Such EUV light sources have not yet been demonstrated. So EUV is considered a possible
option for meeting the future needs of the lithographic roadmap. Details of the current capabilities and future challenges
for EUV lithography are described in the chapter section “EUV Lithography”. There are subsections on resist, mask and
tooling challenges for EUV, since each of these areas is critical to EUV’s success.
There are other possible options for higher resolution that are also in development. Pattern multiplication could continue
to be extended to greater multiplication factors. In principle, this can be done by using existing process technology and
adapting it to smaller features and tighter tolerances. However, lithographic exposures are some of the most expensive

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 Lithography 3

processes in a fab and doubling or tripling or more the number of exposures per layer for key layers can quickly become
unaffordable. In addition, many exposures and/or many pattern multiplication process steps create many complicated
tolerance stack ups and may require process control that is undoable. Since pitch multiplication is easier to do on simple
lines and spaces, there has been growth in the use of complementary lithography. These sorts of processes avoid needing
to increase the intrinsic resolution capability of an exposure tool. However, required overlay, CD control and pattern
roughness still scale with the final patterned features size, so tools and processes still have to improve despite the use of
multiple patterning. These are significant challenges. Details of these processes and the challenges of extending them to
smaller features are described in the chapter section “Multiple Patterning/Spacer Technology”.
E-beam lithography or maskless lithography (ML) uses e-beams to do direct write of features in e-beam sensitive resist.
Writing high resolution features with a directed e-beam is intrinsically slow, so in order to get sufficient throughput,
massively parallel writing with thousands of independently directed e-beams is necessary. Two different companies are
developing tools to do this with a projected delivery date of pilot tools to semiconductor companies of sometime in 2016.
The details and challenges of this technology are shown in the chapter section “Maskless Lithography”.
Nanoimprint is a potential solution that involves coating a thin pattern of liquid on a wafer and using a mask with high
resolution relief patterns to physically stamp the wafer and create a relief pattern. The relief pattern can then be used as an
etch mask in much the same way that patterned photoresist is. The leading implementation of this technique using step
and flash, where a transparent mask is used to stamp one chip at a time and enable photochemical curing of the patterned
material before the stamp is lifted from the wafer. Since this is a contact technique, defects are a significant concerns and
a system of master and secondary masks is used to accommodate a short lifetime for the masks used for the actual chip
patterning and improve the defectivity of the process. Pilot tools are available for companies that wish to test this and one
semiconductor has a significant program evaluating the potential of this technology. Details of the capabilities and
challenges of this technique are discussed in the chapter section “Nanoimprint” .
A patterning technique that has shown a lot of progress in the last two years is directed self-assembly (DSA). This
technique takes advantage of the fact that required feature sizes are reaching a size similar to that of polymer molecules
that can be readily made in the lab. The most common implementation uses special polymers called block copolymers,
which consist of two connected polymers each made from a different monomer. If the monomers are selected properly,
the blocks will separate into phase domains when annealed. The phase domains will have a size determined by the size of
the individual polymer blocks and the shapes of the domains will be determined by the ratio of the sizes of each polymer
block. By creating guiding features on a wafer, this domain formation process can be constrained to give line or hole
patterns with the lines and holes in desired locations. Patterns printed with 193nm immersion lithography can be used as
guide patterns and pitch multiplication factors of three or four times are readily accessible. This technique was considered
a research topic two years ago, but now most major semiconductor producers have substantial programs exploring the
possibility of implementing this technique in actual chip production. The details and challenges of this technology are
shown in the chapter section “Directed Self Assembly (DSA)”

LITHOGRAPHY POTENTIAL SOLUTIONS

Based on our assessments of industry needs and the availability and timing of each of these options, we have prepared
possible options roadmaps that show the different paths the industry can take to meet future resolution needs. A key
question for any leading edge patterning technique is what size lines and spaces it can resolve. Figure LITH1A shows
published resolution for the various patterning techniques. The black cells indicate where there are published papers
indicating the use of the technique in production. The gray cells and the cross hatched indicates where techniques have
been demonstrated to be capable of smaller resolution. Resolution down into the 10 to 15nm range for lines and spaces is
clearly demonstrated and further extensions to smaller features are expected. For example, published exposures at high
EUV NAs are not available yet since such tools are not available, but there is clearly potential for further shrinking just
based on scaling principles. Comparing these techniques’ capability and expected time frame for implementation of the
dimensions shown in Table LITH1 gives the options for each pitch range shown in LITH1B and LITH1C. They show
possible options and timing for line and space patterning.
Possible options for contact hole types of layers are shown in Figure LITH1D. The two-dimensional nature of contact
hole arrays means that pattern doubling reduces the minimum achievable pitch of a contact hole array by one over the
square root of two, or by 29%. This is much less shrink than the pattern doubling of lines and spaces, where the minimum
pitch is reduced 50% by pattern doubling. Triple and/or quadruple patterning of contact holes will be needed in 2016 and
more than four exposures in 2019. The implementation of EUV or other novel pattering techniques would shrink the pitch
of contact holes just as much as it shrinks the pitch of lines and spaces. So the expected cost of LELELE and LELELELE

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4 Lithography

processes drives an earlier need for novel pattering technology for contact holes than for lines and spaces. In 2016, EUV
single patterning could replace triple or quadruple patterning for contact holes. If successful at this, it could remain the
technique of choice for contact holes until 2022. But source power has to be enough to make such patterning
manufacturable and cost effective. Other alternative technologies are also possible. They are shown as possibilities for
manufacturing in 2019, when 193nm immersion quadruple pattering no longer meets resolution needs. But they could be
implemented sooner if they are ready and more cost effective than other techniques.
The 2013 Lithography chapter also addresses specific challenges and technology needs for
• Resists
• Optical masks
• Multiple Patterning/Spacer Technology
• EUV Technology – Source Power, Resist, and Masks
• Directed Self Assembly (DSA)
• Nanoimprint

CROSSCUT NEEDS AND POTENTIAL SOLUTIONS

The crosscut technology needs and potential solutions involving Lithography, Design and Process Integration,
Interconnect, Factory Integration, Metrology, and Modeling and Simulation are outlined in this section.

IMPACT OF FUTURE EMERGING RESEARCH MATERIALS

Historically, patterning has made as much resolution progress through the introduction of new materials and processes as
it has through the introduction of new tools. We expect this to trend to continue. Table LITH10 shows areas where new or
improved materials are required, or where new materials that are currently being research or are under development could
be useful. The table is separated into two sections. In the top section, potential improvements to current photoresist
capability are shown. More negative tone materials, improved EUV resists, and new resist technologies for a better
LWR/sensitivity/resolution trade-off and for better etch resistance are needed. DSA is shown separately in the bottom
section because it is an entirely materials based method of improving resolution. DSA has already demonstrated high
resolution, but it requires relatively inflexible designs. New materials are needed that enable more diverse types of
patterns. New materials are also needed to improve defect levels, to simplify or improve the processing and to improve
long range waviness in the lines.

REFERENCES
1
E. Hendrickx et al., 2013 EUV Lithography Symposium, Toyama, Japan.
2
D. Brandt et al., 2013 EUV Lithography Symposium, Toyama, Japan
3
R. Peeters, 2013 SPIE Advanced Lithography, San Jose, CA 8679-50

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