EUV Presentation
EUV Presentation
EUV Presentation
Lithography
Matt Smith
Penn State University
EE 518, Spring 2006
Instructor: Dr. J. Ruzyllo
Outline
Why do we need EUV lithography?
Brief overview of current technology
What exactly is EUV?
System diagram
Challenges associated with EUV
13.5nm source
Optics
Masks
Resists
Why EUV?
Minimum lithographic feature size =
k1*
NA
: Exposure wavelength
NA: Numerical aperture of the lens maximum of 1 in air, a little higher in
immersion lithography (Higher NA means smaller depth of focus, though)
Mask Makers
Holiday:
large k1
Mask Makers
Burden: small k1
ftp://download.intel.com/research/silicon/EUV_Press_Foils_080204.pdf
Mask Makers
Holiday:
large k1
Mask Makers
Burden: small k1
ftp://download.intel.com/research/silicon/EUV_Press_Foils_080204.pdf
1012
100nm (25nm as projected on wafer)
0
200GB
~$800k-1.3M
Reticle
(Mask)
Lens NA ~0.5-0.85
Up to 1.1 for immersion
Exposure field 26x32mm
Steppers capable of >100
300mm wafers per hour
at >100 exposures per
wafer
193 nm Excimer
Laser Source
Wafer
Computer
Console
Exposure
Column
(Lens)
www.tnlc.ncsu.edu/information/ceremony/lithography.ppt
All-reflective optics
(all lens materials are
opaque)
ftp://download.intel.com/technology/silicon/EUV_Press_Foils_080204.pdf (both images)
Tin
http://www.sematech.org/resources/litho/meetings/euvl/20021014/16-Spectro.pdf
Argon
Tin
Tin
http://www.sematech.org/resources/litho/meetings/euvl/20021014/16-Spectro.pdf
ftp://download.intel.com/technology/silicon/EUV_Press_Foils_080204.pdf
All-Reflective Optics
All solids, liquids, and gasses absorb 13.5nm photons
- So fused silica lenses are OUT
- Indeed, all refracting lenses are OUT
Making EUV mirrors is no cakewalk, either
50 or more alternating Mo/Si layers give the mirror its
reflectivity
Each layer is 6.7nm thick and requires atomic
precision
Since the angle of incidence changes across the
mirror, so do the required Mo/Si layer thicknesses
Acceptable surface roughness: 0.2nm RMS
Aspheric
Net reflectance: ~70%
http://www.zeiss.com/C1256A770030BCE0/WebViewAllE/D6279194C2955B2EC12570CF0044E537
Development-size field:
> 500,000 exposures per
300mm wafer
-In July 2005, Carl Zeiss shipped the first 0.25NA full-field
optics system to ASML for integration in an EUV system
Press release: http://www.zeiss.com/C1256A770030BCE0/WebViewAllE/D6279194C2955B2EC12570CF0044E537
ftp://download.intel.com/research/library/IR-TR-2003-39-ChuckGwynPhotomaskJapan0503.pdf
EUV Masks
ftp://download.intel.com/research/library/IR-TR-2003-39-ChuckGwynPhotomaskJapan0503.pdf
EUV Masks
NO defects are ever allowed in a completed mask
Extremely flat and defect-free substrate, perfected by smoothing layer
All defects in multilayer reflecting stack must be completely repaired
No defects allowed in absorber layer
All defects in final absorber pattern must be completely repaired
(No wonder mask sets are so expensive!)
ftp://download.intel.com/research/library/IR-TR-2003-39-ChuckGwynPhotomaskJapan0503.pdf
EUV Resists
Best Positive Resist
2.3mJ/cm2 LER=7.2nm
3.2mJ/cm2 LER=7.6nm
39nm 3:1
(space:lin
ftp://download.intel.com/research/library/IR-TR-2003-39-ChuckGwynPhotomaskJapan0503.pdf
e)
Conclusion
Will 193nm ever die?
As recently as 2003, EUV was the only viable solution for the 45nm
node
Now Intel wants EUV for the 32nm node, but it may be pushed back
more:
In a nutshell, many believe that EUV will NOT be ready for the 32nm
node in 2009. Some say the technology will get pushed out at
the 22nm node in 2011. Some even speculate that EUV will never
work.
- EE Times, Jan 19, 2006
My opinion: never say never about this industry
A lot of work remains: increase output power of 13.5nm source,
increase NA of reflective lenses, increase lifetime of collector optics
(decrease cost of ownership)
But the potential payoff is sufficient that we will make it work