A TECHNICAL SEMINAR REPORT

ON
FIN-FET

BACHELOR OF
TECHNOLOGY IN
ELECTRONICS AND COMMUNICATION
ENGINEERING 2019-2023
SUBMITTED BY
NAME: K. GOPI
KRISHNA ROLL
NO:19Q91A0429

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

MALLA REDDY COLLEGE OF ENGINEERING

MAISAMMAGUDA, DHULAPALLY, SECUNDERABAD- 500 100(TS)

MALLA REDDY COLLEGE OF ENGINEERING

(MALLA REDDY GROUP OF INSTITUTIONS)
MAISAMMAGUDA, DHULAPALLY, SECUNDRABAD- 500 100(TS)
 CERTIFICATE
This is to certify that technical seminar report “FIN-FET” is
successfully done by the following student of ELECTRONICS AND
COMMUNICATION ENGINEERING department of
our college in partial fulfillment of the requirement for the award of the B.tech
degree in the year 2021-2022.

NAME:K.GOPI KRISHNA
ROLL NO: 19Q91A0429

CO-ORDINATOR HEAD OF THE DEPARTMENT

Mr. P. Venkatapathy Mr. M . Shiva Kumar
(Assistant Professor) (Associate Professor)
 ACKNOWLEDGEMENTS
I hereby express my thanks and gratitude to Almighty, Parents, family
members and friends, without their un-sustained support, I could not have done this
technical seminar.

I am pleased to thank our Chairman Sri Ch. Malla Reddy for providing this
opportunity and director Sri G. Ram Reddy for his constant support throughout the course.

I am very much thankful to our Principal Dr. M. Sreedhar Reddy for supporting us
in all aspects and guiding in all walks of life.

I profoundly thank Head Mr. M . Shiva Kumar of the Department of Electronics and Communication
Engineering who has been an excellent guide and also a great source of inspiration to my work.

I thank my coordinator Mr. P. Venkatapathi for his valuable suggestions and

technical guidance.

The satisfaction and euphoria that accompany the successful completion of the task
would be great but incomplete without the mention of the people who made it possible with
their constant guidance and encouragement crowns all the efforts with success. In this
context, I would like thank all the other staff members, both teaching and non-teaching, who
have extended their timely help and eased my task.

Name of the student

K. GOPI KRISHN(109Q91A0429)
 CONTENTS

ABSTRACT ii
INTRODUCTION v
HISTORY vi
MOSFET vii

1. PARTIALLY DEPLETED (PD)SOI 1

1.1 Parasitic Bipolar Effect 1

1.2 Hysteretic VT Variation 2

2. Scaling Si Film From PD SOI to FD SOI 4
3. Major Design Issues 6
3.1 Gate Oxide Tunneling Leakage 6
3.2 Self Heating 7
3.3 Soft Error Rate 7
3.4 Strained SI channel and High K Gate 8
4.INTRODUCTION to Double Gate CMOS 10
5. Double gate FET 12
5.1 Over coming obstacles by doubling up 12
5.2 Double Gate Taxonomy 12
5.2.0 Type 1 The Planar DG-FET
5.2.1 Type 2 The Planar DG-FET
5.2.3 Type 3 The Planar DG-FET
5.3The Double Gate Challenge
6. Features of FIN FET 14
7.Schematic Explaining the parts of a FIN FET 16
8.Process flow of Fin Fet 17-25
8.0 Fin Fet DG coms Process flow in detail
8.1 How to converter Planar to FIN FET Technology
9 FIN FET Advantages & Disadvantages 28
10.Application FIN FET
11. Over come of Disadvantages form FIN FET 30
12. MBCFET 31
13. Application On MBCFET 32
14. Conclusions 33
15.Rference
 FinFET 1
ABSTRACT

The introduction of FinFET Technology has opened new chapters in Nano-

technology. Simulations show that FinFET structure should be scalable down to 10 nm.
Formation of ultra thin fin enables suppressed short channel effects. It is an attractive
successor to the single gate MOSFET by virtue of its superior electrostatic properties and
comparative ease of manufacturability. Since the fabrication of MOSFET, the minimum
channel length has been shrinking continuously. The motivation behind this decrease has
been an increasing interest in high-speed devices and in very large-scale integrated circuits.
The sustained scaling of conventional bulk device requires innovations to circumvent the
barriers of fundamental physics constraining the conventional MOSFET device structure.
The limits most often cited are control of the density and location of dopants providing
high Ion/Ioff ratio and finite sub threshold slope and quantum-mechanical tunneling of carriers
through thin gate from drain to source and from drain to body.

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1. INTRODUCTION

Since the fabrication of MOSFET, the minimum channel length has been
shrinking continuously. The motivation behind this decrease has been an increasing
interest in high speed devices and in very large scale integrated circuits. The sustained
scaling of conventional bulk device requires innovations to circumvent the barriers of
fundamental physics constraining the conventional MOSFET device structure. The limits
most often cited are control of the density and location of dopants providing high I on /I off
ratio and finite sub threshold slope and quantum-mechanical tunneling of carriers through
thin gate from drain to source and from drain to body. The channel depletion width must
scale with the channel length to contain the off-state leakage I off. This leads to high
doping concentration, which degrade the carrier mobility and causes junction edge leakage
due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness,
becomes much more difficult. The gate oxide thickness tox must also scale with the
channel length to maintain gate control, proper threshold voltage V T and performance. The
thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit
performance, power and noise margin.

Alternative device structures based on silicon-on-insulator (SOI) technology

have emerged as an effective means of extending MOS scaling beyond bulk limits for
mainstream high-performance or low-power applications .Partially depleted (PD) SOI
was the first SOI technology introduced for high-performance microprocessor applications.
The ultra-thin-body fully depleted (FD) SOI and the non-planar FinFET device
structures promise to be the potential “future” technology/device choices.

In these device structures, the short-channel effect is controlled by geometry,

and the off-state leakage is limited by the thin Si film. For effective suppression of the off-
state leakage, the thickness of the Si film must be less than one quarter of the channel
length.

The desired VT is achieved by manipulating the gate work function, such as the
use of midgap material or poly-SiGe. Concurrently, material enhancements, such as the use

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of a) high-k gate material and b) strained Si channel for mobility and current drive
improvement, have been actively pursued.

As scaling approaches multiple physical limits and as new device structures and
materials are introduced, unique and new circuit design issues continue to be presented. In
this article, we review the design challenges of these emerging technologies with particular
emphasis on the implications and impacts of individual device scaling elements and unique
device structures on the circuit design. We focus on the planar device structures, from
continuous scaling of PD SOI to FD SOI, and new materials such as strained-Si channel
and high-k gate dielectric.

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History FIN FET

After the MOSFET was first demonstrated by Mohamed Atalla and Dawon Kahng of Bell Labs in
1960,[4] the concept of a double-gate thin-film transistor (TFT) was proposed by H.R. Farrah (Bendix
Corporation) and R.F. Steinberg in 1967. [5] A double-gate MOSFET was later proposed by Toshihiro
Sekigawa of the Electrotechnical Laboratory (ETL) in a 1980 patent describing the planar XMOS
transistor.[6] Sekigawa fabricated the XMOS transistor with Yutaka Hayashi at the ETL in 1984. They
demonstrated that short-channel effects can be significantly reduced by sandwiching a fully
depleted silicon-on-insulator (SOI) device between two gate electrodes connected together.[7][8]
The first FinFET transistor type was called a "Depleted Lean-channel Transistor" or "DELTA"
transistor, which was first fabricated in Japan by Hitachi Central Research Laboratory's Digh
Hisamoto, Toru Kaga, Yoshifumi Kawamoto and Eiji Takeda in 1989. [7][9][10] The gate of the transistor
can cover and electrically contact the semiconductor channel fin on both the top and the sides or only
on the sides. The former is called a tri-gate transistor and the latter a double-gate transistor. A
double-gate transistor optionally can have each side connected to two different terminal or contacts.
This variant is called split transistor. This enables more refined control of the operation of the
transistor.
Indonesian engineer Effendi Leobandung, while working at the University of Minnesota, published a
paper with Stephen Y. Chou at the 54th Device Research Conference in 1996 outlining the benefit of
cutting a wide CMOS transistor into many channels with narrow width to improve device scaling and
increase device current by increasing the effective device width. [11] This structure is what a modern
FinFET looks like. Although some device width is sacrificed by cutting it into narrow widths, the
conduction of the side wall of narrow fins more than make up for the loss, for tall fins. [12] The device
had a 35 nm channel width and 70 nm channel length.[11]
The potential of Digh Hisamoto's research on DELTA transistors drew the attention of the Defense
Advanced Research Projects Agency (DARPA), which in 1997 awarded a contract to a research
group at UC Berkeley to develop a deep sub-micron transistor based on DELTA technology. [13] The
group was led by Hisamoto along with TSMC's Chenming Hu. The team made the following
breakthroughs between 1998 and 2004.[14]

 1998 – N-channel FinFET (17 nm) – Digh Hisamoto, Chenming Hu, Tsu-Jae King Liu,

Jeffrey Bokor, Wen-Chin Lee, Jakub Kedzierski, Erik Anderson, Hideki Takeuchi, Kazuya
Asano[15]
 1999 – P-channel FinFET (sub-50 nm) – Digh Hisamoto, Chenming Hu, Xuejue Huang,
Wen-Chin Lee, Charles Kuo, Leland Chang, Jakub Kedzierski, Erik Anderson, Hideki
Takeuchi[16]
 2001 – 15 nm FinFET – Chenming Hu, Yang-Kyu Choi, Nick Lindert, P. Xuan, S. Tang,
D. Ha, Erik Anderson, Tsu-Jae King Liu, Jeffrey Bokor[17]
 2002 – 10 nm FinFET – Shibly Ahmed, Scott Bell, Cyrus Tabery, Jeffrey Bokor, David
Kyser, Chenming Hu, Tsu-Jae King Liu, Bin Yu, Leland Chang [18]
 2004 – High-κ/metal gate FinFET – D. Ha, Hideki Takeuchi, Yang-Kyu Choi, Tsu-Jae
King Liu, W. Bai, D.-L. Kwong, A. Agarwal, M. Ameen
They coined the term "FinFET" (fin field-effect transistor) in a December 2000 paper, [19] used to
describe a non-planar, double-gate transistor built on an SOI substrate. [20]
In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and
Technology (KAIST) and the National Nano Fab Center developed a 3 nm transistor, the world's
smallest nanoelectronic device, based on gate-all-around (GAA) FinFET technology.[21][22] In
2011, Rice University researchers Masoud Rostami and Kartik Mohanram demonstrated that
FinFETs can have two electrically independent gates, which gives circuit designers more flexibility to
design with efficient, low-power gates.[23]
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 FinFET 5
In 2020, Chenming Hu received the IEEE Medal of Honor award for his development of the FinFET,
which the Institute of Electrical and Electronics Engineers (IEEE) credited with taking transistors to
the third dimension and extending Moore's law.[24]

MOSFET
MOSFET showing gate (G), body (B), source (S) and drain (D) terminals. The gate is separated from the
body by an insulating layer (pink).
The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a type of
field-effect transistor (FET), most commonly fabricated by the controlled oxidation of silicon. It has an
insulated gate, the voltage of which determines the conductivity of the device. This ability to change
conductivity with the amount of applied voltage can be used for amplifying or switching electronic
signals. A metal-insulator-semiconductor field-effect transistor (MISFET) is a term almost synonymous
with MOSFET. Another synonym is IGFET for insulated-gate field-effect transistor.

The basic principle of the field-effect transistor was first patented by Julius Edgar Lilienfeld in 1925.[1]

Two power MOSFETs in D2PAK surface-mount packages. Operating as switches, each of these
components can sustain a blocking voltage of 120 V in the off state, and can conduct a continuous current
of 30 A in the on state, dissipating up to about 100 W and controlling a load of over 2000 W. A matchstick
is pictured for scale.
The main advantage of a MOSFET is that it requires almost no input current to control the load current,
when compared with bipolar transistors (bipolar junction transistors/BJTs). In an enhancement mode
MOSFET, voltage applied to the gate terminal increases the conductivity of the device. In depletion mode
transistors, voltage applied at the gate reduces the conductivity.[2]

The "metal" in the name MOSFET is sometimes a misnomer, because the gate material can be a layer of
polysilicon (polycrystalline silicon). Similarly, "oxide" in the name can also be a misnomer, as different
dielectric materials are used with the aim of obtaining strong channels with smaller applied voltages.

The MOSFET is by far the most common transistor in digital circuits, as billions may be included in a
memory chip or microprocessor. Since MOSFETs can be made with either p-type or n-type
semiconductors, complementary pairs of MOS transistors can be used to make switching circuits with very
low power consumption, in the form of CMOS logic.

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2. PARTIALLY DEPLETED (PD) SOI

The PD floating-body MOSFET was the first SOI transistor generically adopted
for high-performance applications, primarily due to device and processing similarities to
bulk CMOS device.

The PD SOI device is largely identical to the bulk device, except for the addition
of a buried oxide (“BOX”) layer. The active Si film thickness is larger than the channel
depletion width, thus leaving a quasi-neutral “floating” body region underneath the
channel. The V T of the device is completely decoupled from the Si film thickness, and the
doping profiles can be tailored for any desired VT.

Fig.3.1. Partially depleted (PD) SOI

The device offers several advantages for performance /power improvement:

1) Reduced junction capacitance,

2) Lower average threshold due to positive V BS during switching.

3) Dynamic loading effects, in which the load device tends to be in high VT state during
switching

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FinFET 7

The performance comes at the cost of some design complexity resulting from the
floating body of the device, such as

1) Parasitic Bipolar Effect and

2) Hysteretic VT Variation.

3.1 Parasitic Bipolar Effect

In PDSOI an n-p-n transistor is formed with source and drain as emitter &
collector respectively and body as the base. The topology typically involves an “off”
transistor with the source and drain voltage set up in the “high” state (hence body voltage
at “high”) When the source is subsequently pulled down, large overdrive is developed
across the body-source junction, causing bipolar current to flow through the lateral
parasitic bipolar transistor. This may result in circuit failure.

Fig.3.1.1. Parasitic Bipolar Effect

In SRAM bitline structures, the aggregate parasitic bipolar effect of the

unselected cells on the selected bitline disturbs the read/write operations and limits the
number of cells that can be attached to a bitline pair

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3.2 Hysteretic VT Variation

The hysteretic VT variation is due to long time constants of various body

charging/discharging mechanisms.

A commonly used gauge for hysteretic VT variation (or “history effect” as it is

known in the SOI community) is the disparity in the body voltages and delays between the
so-called “first switch” and “second switch”. The “first switch” refers to the case where a
circuit (e.g., inverter) starts in an initial quiescent state with input “low” and then
undergoes an input-rising transition. In this case, the initial dc equilibrium body potential
of the switching nMOSFET is determined primarily by the balance of the back-to-back
drain-to-body and body-to-source diodes. The “second switch” refers to the case where the
circuit is initially in a quiescent state with input “high.” The input first falls and then rises
(hence, the name “second switch”). For this case, the preswitch body voltage is determined
by capacitive coupling between the drain and the body.

Fig.3.2.1. Input/output waveforms & nMOS body voltage for a PD SOI

CMOS inverter under “first switch” & “second switch” condition

The duty cycle, slew rate, and output load also affect the hysteretic behavior of
the circuits. A higher duty cycle increases hysteretic behavior due to higher switching
activity causing a gain or loss of body charge and less time for the device to return/settle to
its initial equilibrium state

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3. SCALING Si FILM: FROM PD SOI TO FD SOI

The major benefits of scaling/thinning of the Si film are: 1) reduction of junction

capacitance for performance improvement, 2) better short channel roll-off, and 3) better soft
error rate (SER) due to less charge generation and collection volume.

In addition, the history effect (disparity between first switch and second switch)
is also reduced. The reduced junction capacitance improves delays of both the first and
second switches. However, for the second switch the reduced junction capacitance reduces
the capacitive coupling between the drain and the body .The resulting decrease in the pre-
switch body voltage for the second switch partially offsets the performance improvement.

Unfortunately, the thinning of Si film degrades the body resistance, rendering

body contacts less effective and eventually useless. Self-heating becomes more severe.
Furthermore, as the film thickness is scaled below 50nm, the device may become
dynamically fully depleted (or quasi-depleted); the body would become fully depleted
under certain bias conditions or during certain circuit-switching transients. This
necessitates a unified PD/FD device model with smooth and seamless transitions among
different modes of operation. Typically, this is modeled by varying the built-in potential
between the body and source junction, thus changing the amount of body charges the body-
to-source junction diode can sink for a given change in the body potential .The presence of
dynamic full depletion also complicates the static timing methodology. The various body
voltage bounds, established based on the assumption of partial depletion need to be
extended to cover this new phenomenon. Notice that dynamic depletion tends to occur first
in long-channel, low VT devices. For short channel devices, the proximity of the heavily
doped “halo” regions to each other increases the effective body doping, and the device is
less likely to be dynamically fully depleted. In a FD_SOI device, the channel depletion
layer extends through the entire Si film. This significantly reduces the floating body effect
(completely eliminating the floating-body effect with ultra-thin Si films).

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4. MAJOR DESIGN ISSUES

5.1. Gate Oxide Tunneling Leakage

As the gate oxide thickness is scaled to maintain gate control V T and performance,
gate insulator direct tunneling leakage increases. Nitrided oxide, which reduces the leakage
by any order of magnitude, has been widely used in the industry to contain this leakage.
Nevertheless, the oxide tunneling leakage increases by 25* for every 0.1 nm decrease in
oxide thickness. This amounts to over a 30* increase per technology generation. On the
contrary, the channel leakage increases by about 3-5 per technology generation. As such,
the oxide tunneling leakage has quickly approached I off and will surpass Ioff at room
temperature for oxide thickness around 1.0nm or below, thus becoming a serious concern
for overall chip leakage.

Furthermore, at 1.0nm, the tunneling leaking for nitrided oxide reaches

100A/cm2, while the traditional reliability limitation for silicon dioxide gate insulator
leakage is 1.0A/cm2. A recent study showed that, at 100 A/cm 2, static CMOS and domino
circuits in bulk CMOS still exhibit “acceptable functionality and noise margin”.

The oxide tunneling current consists of several components. The electron

tunneling from the valence band (EVB) generates the substrate current in both nMOS and
pMOS .This substrate current component is significantly less than the tunneling current
between the gate and the channel, and its effect can usually be neglected in bulk CMOS .In
PD SOI devices, however, this substrate current charges or discharges the body, thus
changing VT and affecting circuit operation. As this gate-to-body tunneling current has
weaker temperature dependence than the channel current, and other leakage and body
charging/discharging current components, its effect is more pronounced at lower
temperature.

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5.2. Self heating

The heat transfer is dominated by phonon transport in semiconductors and by

electron transport in metals. The thermal conductivity of the buried oxide (1.4 W/m-.C) is
about two orders of magnitude lower than that of Si (120 W/m-.C), giving rise to local self-
heating in SOI devices. This is particularly a concern for devices that are “on” most or all
the time (e.g., biasing elements, current source, current mirror, bleeder, etc.) and for
circuits with high duty cycle and slow slew rate (such as clock distribution, I/O driver).

Scaling of the Si film degrades the thermal conductivity and increases the
thermal resistance. In scaled SOI devices, both the channel length and Si film thickness are
much smaller than the phonon mean free path for Si (~300 nm at room temperature), and
the thermal conductivity is severely degraded due to phonon boundary scattering.

The thermal resistance increase is particularly significant for thinner Si film with
thick buried oxide. As the Si film thickness is scaled further to approach the Phonon
wavelength (~ tens of nm), the phonon confinement effect becomes significant. This is the
mechanical/thermal analogy of the quantum confinement effect in electronic devices with
an ultra-thin Si film. The boundary conditions change from the usual periodic boundary
conditions for bulk materials to essentially zero displacements on the boundaries in SOI.

5.3. Soft Error Rate

The α-generated charges in SOI devices are substantially less than in bulk
devices due to the presence of the buried oxide, and appreciable charge generation can only
occur when an α-particle hits the channel region. While scaling of the device reduces the
charge generation volume, the Qcrit also decreases due to a lower capacitance at the cell’s
storage node and scaled VDD.

In a PD SOI device, the total charges accumulated at the cell storage node can be
significantly higher than the α-generated charges due to the parasitic bipolar effect. For
properly scaled PD SOI devices, the parasitic bipolar gain is reduced, and the resulting
overall single-event-upset-induced failure rate is less than that of bulk silicon. Furthermore,
scaling/thinning of the Si film reduces the charge generation volume and the base-emitter
(body-source) junction area of the parasitic bipolar transistor, thus improving SER as well.

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5.4. Strained-Si channel And High-k Gate

Strained-Si surface channel CMOS has recently emerged as an effective means

of extending scaling for future high-performance applications due to higher mobility and
improved Ion. The lattice mismatch between the Si channel and the underlying relaxed SiGe
layer results in biaxial tensile strain, which reduces the intervalley scattering by increasing
sub-band splitting and enhances carrier transport by reducing conductivity effective mass.

Combining strained si-channel and SOI complements the improved Ion of strained
Si channel device with the benefit of SOI. However, there are numerous design
implications. The narrower bandgap of the SiGe layer causes a heterostructural band offset,
which reduces VT and increases Ioff. The mobility enhancement for nMOS and pMOS may
be quite different due to device design and process integration constraints, which may
upset the established β(p/n strength) ratio of existing designs. The tensile strain is
“biaxial”, so mobility enhancements (therefore Ion improvement) are the same along X- and
Y-axis. However, in some high-density design (eg: SRAM cell), “bent gates” at a 45° angle
are sometimes used, which would result in disparity in mobility enhancement and Ion
improvement. The SiGe layer with 20% Ge has a 70% higher dielectric constant and a 10%
lower built-in potential due the narrower band gap, resulting in higher junction capacitance.
Furthermore, higher body doping density could be needed to compensate for the V T
reduction which further increases the junction capacitance. The thermal conductivity of the
SiGe layer is about 15X lower than that for Si thus aggravating the self- heating effect.

High-k gate dielectric has recently been pursued to contain the gate leakage
and extend device scaling. Most of the potential high-k gate insulators have lower bandgap
than SiO2 and therefore must be thicker to keep the tunneling leakage down. These
materials also have charge-trapping related V T instability and mobile degradation. The
integration of high-k gate dielectric with strained-Si channel significantly enhances the
mobility. Notice that, as the high-k gate material offers higher gate capacitance per unit
area, some circuit resizing/retuning may be necessary, especially in the critical paths where
device capacitances tend to dominate.

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5. INTRODUCTION TO DOUBLE_GATE CMOS

Innovative device architectures will be necessary to continue the benefits that

previously acquired through rote scaling. Double-gate CMOS (DGCMOS) offers distinct
advantages for scaling to very short gate lengths. Furthermore, adoption of gate dielectrics
with permittivity substantially greater than that of SiO2 (so-called “high-k materials”) may
be deferred if a DGCMOS architecture is employed. Previously, serious structural
challenges have made adoption of DGCMOS architecture untenable. Recently, through use
of the delta device, now commonly referred to as the FinFET, significant advances in
DGCMOS device technology and performance have been demonstrated. Fabrication in
FinFET-DGCMOS is very close to that of conventional CMOS process, with only minor
disruptions, offering the potential for a rapid deployment to manufacturing. Planar product
designs have been converted to FinFET–DGCMOS without disruption to the physical area,
thereby demonstrating its compatibility with today’s planar CMOS design methodology
and automation techniques.

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6. DOUBLE GATE FET

Double-gate CMOS (DGCMOS) offers distinct advantages for scaling to very

short gate lengths. Fabrication of FinFET-DGCMOS is very close to that of conventional
CMOS process, with only minor disruptions, offering the potential for a rapid deployment
to manufacturing. Planar product designs have been converted to FinFET-DGCMOS
without disruption to the physical area, thereby demonstrating its compatibility with
today’s planar CMOS design methodology and automation techniques.

7.1. Overcoming Obstacles By Doubling Up

CMOS technology scaling has traversed many anticipated barriers over the past
20 years to rapidly progress from 2 µm to 90nm rules. Currently, two obstacles, namely
subthreshold and gate-dielectric leakages, have become the dominant barrier for further
CMOS scaling, even for highly leakage-tolerant applications such as microprocessors.

Double-gate (DG) FETs, in which a second gate is added opposite the traditional
(first) gate, have better control over short-channel effects [SCEs]. SCE limits the minimum
channel length at which an FET is electrically well behaved.

Fig.7.1.1. Figure schematically illustrates the advantage of DG-FETs.

As the channel length of an FET is reduced, the drain potential begins to strongly
influence the channel potential, leading to an inability to shut off the channel current with

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FinFET 15

the gate. This short-channel effect is mitigated by use of thin gate oxide (to increase the
influence of the gate on the channel) and thin depletion depth below the channel to the
substrate, to shield the channel from the drain. Gate oxide thickness has been reduced to
the point where, at 90 nm CMOS, the power drain from gate leakage is comparable to the
power used for switching of circuits. Thus, further reduction of the thickness would lead to
unreasonable power increases.

Alternatively, further decrease of the depletion region X D degrades gate influence

on the channel and leads to a slower turn on of the channel region.

In DG-FETs, the longitudinal electric field generated by the drain is better screened
from the source end of the channel due to proximity to the channel of the second gate,
resulting in reduced short-channel effects, in particular, reduced drain induced- barrier
lowering (DIBL) and improved subthreshold swing (S). Therefore, as CMOS scaling
becomes limited by leakage currents, DGCMOS offers the opportunity to proceed beyond
the performance of single-gate (SG) bulk-silicon or PDSOI CMOS. Both the DIBL and
subthreshold swing for the DG device are dramatically improved relative to those of the
bulk-silicon counterpart. From a bulk-silicon device design perspective, increased body
doping concentration could be employed to reduce DIBL; however, at some point it would
also increase the subthreshold swing, thereby requiring higher threshold voltage V T to keep
the subthreshold current adequately low. Similarly, decreasing the body doping
concentration could improve the subthreshold swing but degrade DIBL. Hence a
compromise is necessary for the bulk-silicon device design. Note that, for a scaled bulk-
silicon (or PD SOI ) device, a highly doped channel/halo must be used to control severe
SCEs, and lower S for extremely short Leff could not be achieved by use of low
channel/halo doping.

7.2. DOUBLE-GATE TAXONOMY

Numerous structures for DG-FETs have been proposed and demonstrated. These
structures may be classified into one of the three basic categories.

7.2.1. Type I, The Planar DG-FET:

This is a direct extension of a planar CMOS process with a second, buried gate

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FinFET 16

7.2.2.
Type

Fig.7.2.1.1. The Planar DG-FET

II, The Vertical DGFET:

Here bthe silicon body has been rotated to a vertical orientation on the silicon
wafer with the source and drain on the top and bottom boundaries of the body, and the
gates on either side.

Fig.7.2.2.1. The Vertical DGFET

7.2.3. Type III Non Planar FinFET:

In FinFET the silicon body has been rotated on its edge into a vertical
orientation so only the source and drain regions are placed horizontally about the body, as
in a conventional planar FET. Referred to as FinFETs, as the silicon resembles the dorsal
fin of a fish.

Fig.7.2.3.1. Non Planar FinFET

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7.3. THE DOUBLE-GATE CHALLENGE

DG-FETs have been the subject of much research for over 20 years; hence, if
DGCMOS offers significant advantage over SG devices, one must question why DG
devices have not played a significant role on the CMOS technology scene to date.

There are four major obstacles to DGCMOS. The first three issues are closely related to
one another and consist of

1. Definition of both gates to the same image size accurately

2. Self-alignment of the source/drain regions to both top and bottom gates

3. Alignment of the two gates to one another.

These three goals are critical for short devices to provide high drive current and low
gate capacitance simultaneously.

4. The fourth obstacle is that of providing an area-efficient means of connecting the two
gates with a low-resistance path

Type I planar DG-FETs are severely challenged to deliver all of the first three
requirements since the “second” gate is buried below a layer of active silicon. The fourth
hurdle also challenges the planar DG-FET; a process module is required to define the
additional contact to the buried gate if space is not to be lost to it, and a low-resistance gate
material must be introduced in the buried oxide.

Type II vertical DG-FETs typically address problems 1 and 4 quite successfully.

In this case the gate length is usually defined by the thickness of a deposited gate-electrode
material, which automatically makes both gates the same length and self-aligned to each
other. Similarly, the source and drain junctions can be symmetrically defined to have the
same alignment to both gates; however, unique challenges are presented to defining both
self-alignment of the bottom junction to the gates and to keeping the parasitic series
resistances associated with the bottom junction low. Furthermore, a space-efficient low-
capacitance contact scheme to the lower junction requires a high-wire act in process
integration. While high drive currents have been achieved with Type II structures, high
performance (e.g., low capacitance) and CMOS integration have met with limited progress.

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Type III vertical fin-type DG-FETs have the advantages access to both gates, and
both sides of source and drain, from the front of the wafer. Gate length is conventionally
defined since the direction of the current is in the wafer plane. Gate width, however, is no
longer controlled by lithography; rather, the width is given by twice the height of the
silicon fin HFin.

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8. FEATURES OF FINFET

Fig.8.1. Perspective view of FinFET

Finfet consists of a vertical Si fin controlled by self_aligned double gate.

Main Features of Finfet are

1) Ultra thin Si fin for suppression of short channel effects

2) Raised source/drain to reduce parasitic resistance and improve current drive

3) Gate_last process with low_T, high_k gate dielectrics

4) Symmetric gates yield great performance, but can built asymmetric gates that target
VT

Finfets are designed to use multiple fins to achieve larger channel widths.
Source/Drain pads connect the fins in parallel. As the number of fins is increased, the

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current through the device increases. For e.g.: A 5 fin device 5 times more current than
single fin device.

9. SCHEMATIC EXPLAINING THE PARTS OF A FINFET

Fig.9.1. Schematic explaining the parts of a FinFET

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FinFET 21

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FinFET 22

10. PROCESS FLOW OF FINFET

Fig.10.1. Process Flow of FinFET

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10.1. FinFET-DGCMOS Process Flow in Detail

A conventional SOI wafer can be used as starting material, except that the
alignment notch of the wafer is preferably rotated 45° about the axis of symmetry of the
wafer. The reason for this deviation is to provide{100} planes on silicon fins that are
oriented along the conventional “x” and “y” directions on the wafer.

The process of defining fins and source/drain silicon is very similar to that used to
define trench isolation in today’s CMOS. Patterns are defined and etched into the active
top silicon layer in both processes. The conventional process requires additional processing
to fill and planarize the isolation trenches; the FinFET process, on the other hand, proceeds
directly to channel processing, such as sacrificial oxidations, masked ion implantations for
channels, or specialized passive elements, followed by the gate dielectric module.

Gate deposition and etch are very similar, with less-severe demands on the
selectivity of the gate-electrode etch to gate oxide, since the oxide surface is orthogonal to
the etch direction. Ion implantation of source/drain species and halos( or pockets) must
differ for obvious geometrical reason but otherwise are largely similar to conventional
planar implantation steps. Conventional CoSi2 or NiSi2 processes are used to silicide the
tops of the mesas and the gate, for contacts to source/drain and gate, respectively.

10.2. How to Convert Planar To FinFET Technology

As described above, FinFET processing on SOI wafers uses standard

manufacturing process modules. To etch the ultra thin (TSI=15nm) fins, spacer lithography
[side wall image transfer] is used. Since the SIT process always generates an even number
of fins, an extra process step is needed for removal of fins to allow odd number of fins or
otherwise break fin” “loops” where needed. This means, that for conversion of an existing
design, two additional levels have to be introduced, namely the “ fin” and the “Trim” level.
All other design levels remain the same.

Consider now a planar design to be converted for processing in the 90 nm

FinFET technology node. The FinFET height HFin together with the fin pitch (determined
by photolithography) defines the FinFET device width WFin within the given silicon width

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FinFET 24

of the planar device, to get the same or better device strength . For automatic Fin and Trim
generation, Fin-GEN, a software tool, has been developed, which takes the active area and
poly gate levels, and, based on special FinFET ground rules, generates the additional
levels.the circuit (as well as other β-ratio sensitive circuitry) may additionally require
manual adjustment on the number of fins in the N- and P-devices after automatic addition
of fins in the N- and P- devices after automatic addition of the FinFET levels.

Besides device width quantization, other factors like width variation, threshold
variation, and self-heating must be taken into account when designing with FinFETs. A
process with multiple threshold voltages and multiple gate oxide thickness is required to
take full advantage of this new device.

As already discussed, the width quantization imposes some restrictions on the

device strength flexibility, but most of them can be absorbed easily when converting an
existing design or starting a new design, respectively. Of course, as stated earlier, latches,
dynamic circuit styles in general, and SRAM cells need careful optimization when designing
with FinFETs.

Discrete devices and circuits for analog applications require special attention. As
an example, consider a driver/receiver circuit with an ESD protection diode. In a planar
process the protection voltage is proportional junction length of the diode. In FinFET
technology the same junction length per fin pitch may be only about one-eigth of that of the
planar device.

Another example is the total output driver impedance matching, which is usually
implemented with a planar resistor requiring a silicon block resistor, on a silicon island to
adjust output impedance (including the wire to the pad) to 50 Ω. For such applications, and
analog circuits in general, special devices may be necessary for optimized designs using
FinFETs.

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FinFET Advantages

 Better control over the channel

 Suppressed short-channel effects

 Lower static leakage current

 Faster switching speed

 Higher drain current (More drive-current per footprint)

 Lower switching voltage

FinFET Disadvantages

 Difficult to control dynamic Vth

 Quantized device-width. It is impossible to make fractions of the fins,
whereby designers can only specify the devices’ dimensions in multiples of
whole fins.
 Higher parasitics due to 3-D profile
 Very high capacitances
 Corner effect: electric field at the corner is always amplified compared to
the electric field at the sidewall. This can be minimized using a nitrate layer
in corners.
 High fabrication cost

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11. APPLICATIONS OF FinFETs

DG devices like Fin FETs offer unique opportunities for microprocessor

design.compared to a planar process in the same technology node, FinFETs have reduced
channel and gate leakage currents. This can lead to considerable power reductions when
converting a planar design to fin FET technology. Utilizing fin FETs would lead to a
reduction in total power by a factor of two, without compromising performance.

Another possibility to save power arises when both gates can be controlled
separately. The second gate can be used to control the threshold voltage of the device,
thereby allowing fast switching on one side and reduced leakage currents when circuits are
idle.

Finally, separate access to both gates could also be used to design simplified logic
gates. This would also reduce power, and save chip area, leading to smaller, more cost-
efficient designs. However chip designs using finFETs must cope with quantization of
device width, since every single transistor consists of an integral number of fins,each fin
having the same height.

.
 Low power design in digital circuit, such as RAM, because of its low off-state current.
Power amplifier or other application in analog area which requires good linearity.
In apple also using for chip design(finFET)

 MBCFET ADVANTAGES:
High Drive Currents(IN THE OF 2021 YEAR )

It is 3nm

This due to the vertically stacked multibridge channels

Reduced operating Voltage (0.75v)

Additional area is not required to improve speed

Batter gate control

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12. CONCLUSIONS

Simulations show that this structure should be scalable down to 10 nm. Formation
of ultra thin fin (0.7 Lg, for a lightly doped body) is critical for suppressing short channel
effects. This structure was fabricated by forming the S\D before the gate, a technique that
may be needed for future high-k dielectric and metal-gate technologies that cannot tolerate
the high temperatures required for S\D formation. Further performance improvement is
possible by using a thinner gate dielectric and thinner spacers. Despite its double gate
structure, the FinFET is similar to the conventional MOSFET with regard to layout and
fabrication. It is an attractive successor to the single gate MOSFET by virtue of its superior
electrostatic properties and comparative ease of manufacturability. Industrial research
groups such as Intel, IBM and AMD have shown interests in developing similar devices, as
well as mechanisms to migrate mask layouts from Bulk-MOS to FinFETs. Issues such as
gate work function engineering, high quality ultra thin fin lithography and source\drain
resistance need to be resolved and a high-yield process flow needs to be established by
process researchers before FinFETs can be used in commercial ICs. Device researchers
need to understand and model quantum effects, and circuit design researchers need to
exploit the packing density afforded by the quasi-planar device to design efficient
architectures.

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1. S.Thompson, P.Packan and M.Bohr, “MOS scaling , Transistor challenges for the 21st
century,” Intel Tech.J.,vol.Q3, pp1-19,1998

2. C.H.Wann, H.Noda, T.Tanaka, M.Yoshida and C.Hu, “A comparative study of advanced

MOSFET concepts”, IEEE Trans. Electron Devices, vol. 43, no. 10, pp 1742-1753,
Oct. 1996

3. D.Hisamoto, W.C.Lee, J.Keidzerski, H.Takeuchi, K.Asano, C.Kuo, T.J.King, J.Bokor

and C.Hu, “A folded channel MOSFET for deep-sub-tenth micron era”, in IEDM
Tech. Dig. 1998, pp 1032-1034

4. D.Hisamoto, W.C. Lee, J.Keidzerski, H.Takeuchi, K.Asano, C.Kuo. T.J.King, J.Bokor

and C.Hu, “FinFET-a self-aligned double-gate MOSFET scalable beyond 20 nm,”
IEEE Trans.Electron Devices, vol.47, pp. 2320-2325, Dec. 2000.

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H.Takeuchi, Y.K. Choi, K.Asano, V.Subramanian, T.J.King, J.Bokor, C.Hu, “ Sub-50
nm FinFET: PMOS,” in IEDM Tech. Dig.1999.,pp 67-70

6. H.S.Wong, K. Chan and Y.Taur, “Self-aligned ( top and bottom) double-gate MOSFET
with a 25 nm thick silicon channel,” in IEDM Tech.,Dig.1997,pp. 427-430

7. J.Hergenrother et al, “The vertical replacement-gate (VRG) MOSFET: A 50 nm vertical

MOSFET with lithography-independent gate length,” in IEDM Tech. Dig. 1999 ,
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Dept. Of Electronics Production Technology GPTC, Cherthala