This document provides an overview of finFET technology. It includes:
1) An introduction to finFETs and how they attempt to overcome short channel effects like drain-induced barrier lowering by raising the channel above the surface and using a triple-gate structure for better electrostatic control.
2) Details on the different types of finFET structures including planar, vertical, and non-planar designs.
3) The fabrication process for finFETs including creating thin fins less than 20nm wide using selective etching and depositing the gate material to form the triple-gate structure.
4) Challenges from imperfections in fabrication like non-vertical fin sidewalls and corner effects.
This document provides an overview of finFET technology. It includes:
1) An introduction to finFETs and how they attempt to overcome short channel effects like drain-induced barrier lowering by raising the channel above the surface and using a triple-gate structure for better electrostatic control.
2) Details on the different types of finFET structures including planar, vertical, and non-planar designs.
3) The fabrication process for finFETs including creating thin fins less than 20nm wide using selective etching and depositing the gate material to form the triple-gate structure.
4) Challenges from imperfections in fabrication like non-vertical fin sidewalls and corner effects.
This document provides an overview of finFET technology. It includes:
1) An introduction to finFETs and how they attempt to overcome short channel effects like drain-induced barrier lowering by raising the channel above the surface and using a triple-gate structure for better electrostatic control.
2) Details on the different types of finFET structures including planar, vertical, and non-planar designs.
3) The fabrication process for finFETs including creating thin fins less than 20nm wide using selective etching and depositing the gate material to form the triple-gate structure.
4) Challenges from imperfections in fabrication like non-vertical fin sidewalls and corner effects.
This document provides an overview of finFET technology. It includes:
1) An introduction to finFETs and how they attempt to overcome short channel effects like drain-induced barrier lowering by raising the channel above the surface and using a triple-gate structure for better electrostatic control.
2) Details on the different types of finFET structures including planar, vertical, and non-planar designs.
3) The fabrication process for finFETs including creating thin fins less than 20nm wide using selective etching and depositing the gate material to form the triple-gate structure.
4) Challenges from imperfections in fabrication like non-vertical fin sidewalls and corner effects.
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CONTENTS
Chapter No: List of figures List of abbreviations 1 2 3 4 Introduction
Working of typical n-channel MOSFET Moores Law Transistor scaling 4.1 Reasons for MOSFET scaling 4.2 Difficulties arising due to MOSFET size reduction. 4.2.1 Higher subthreshold conduction 4.2.2 Increased gate-oxide leakage 4.2.3 Increased junction leakage 4.2.4 Lower output resistance 4.2.5 Lower transconductance 4.2.6 Interconnect capacitance 4.2.7 Heat production 4.2.8 Process variations
Short channel effects 5.1 Various Short-Channel Effects 5.1.1 Drain-induced barrier lowering and punchthrough 5.1.2 Surface scattering 5.1.3 Velocity saturation 5.1.4 Impact ionization 5.1.5 Hot electrons
11 11 12 12 13 13
Introduction to double gate CMOS 6.1 Overcoming Obstacles By Doubling Up
6.2 Double Gate Threshold Voltage 6.3.1 Type I, the Planar DG-FET 6.3.2 Type II, the Vertical DGFET 6.3.3 Type III, the Non Planar DG-FET (FinFET) 7 FINFET 7.1 Features of FinFET 7.2 FinFET fabrication process 7.3 Recent Fabrication efforts on FinFETs 7.4 Effects due to imperfections in fabrication 7.4.1 Effect of non-vertical fin sidewall 7.4.2 Corner effects 7.4.3 Channel width quantization problem 8 9 Application of FINFET Conclusion Reference
Title No: Cross section and circuit symbol of MOSFET Top view of N - type MOSFET V-I Characteristics of n-type MOSFET Agreement with Moores law Scaling of gate length w.r.t Moores law MOSFET version of gain osted current mirror TRM-800 audio amplifier Surface scattering Hot Electrons Schematically illustrates the advantage of DG-FETs. V-I characteristics of DG and Bulk (SG) MOSFETS Type I, the Planar DG-FET Type II, the Vertical DGFET Type III, the Non Planar DG-FET (FinFET) Structure of a FinFET High level FinFET fabrication The sidewall image transfer (SIT) technique Id-Vg plot of asymmetric FinFETs Id-Vg plot of symmetric FinFETs Corner effects
CMOS SOI DGCMOS SCE FET DG-FET PD FD SG-FET S/D SIT RSD RIE
Complementary metaloxidesemiconductor Silicon-on-insulator Double-gate CMOS Short-channel effects Field effect transistor Double gate FET Partially depleted Fully depleted Single gate FET Source/Drain The sidewall image transfer Raised source drain Reactive ion etching
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ABSTRACT The finFET is a transistor design, first developed by Chenming Hu and colleagues at the University of California at Berkeley, which attempts to overcome the worst types of shortchannel effect encountered by deep submicron transistors, such as drain-induced barrier lowering (DIBL). These effects make it harder for the voltage on a gate electrode to deplete the channel underneath and stop the flow of carriers through the channel in other words, to turn the transistor off. By raising the channel above the surface of the wafer instead of creating the channel just below the surface, it is possible to wrap the gate around up to three of its sides, providing much greater electrostatic control over the carriers within it. There are a number of subtly different forms of trigate transistor structure that are being described as finFETs. The architecture typically takes advantage of self-aligned process steps to produce extremely narrow features that are much smaller than the wavelength of light generally used to pattern devices on a silicon wafer. It is possible to create very thin fins of 20nm in width or less on the surface of a silicon wafer using selective-etching processes, although they typically cannot currently be made less than 20nm to 30nm because of the limits of lithographic resolution. The fin is used to form the raised channel. The gate is then deposited so that it wraps around the fin to form the trigate structure. As the channel is extremely thin the gate has much greater control over the carriers within it but, when the device is switched on, the shape limits the current through it to a low level. So, multiple fins are used in parallel to provide higher drive strengths. Originally, the finFET was developed for use on silicon-on-insulator (SOI) wafers. Recent developments have made it possible to produce working finFETs on bulk silicon wafers and improve the performance of certain parameters. The steep doping profile used to control leakage into the bulk substrate has a beneficial impact on DIBL, although increased doping has a negative impact on variability.
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ACKNOLEDGEMENT I am bounded to thank GOD ALMIGHTY for His grace and blessings He showered on me throughout this endeavour. I express my sincere thanks to our Principal Dr. K.T MATHEW for his kind cooperation in all aspects. I am very much grateful to Prof. JOSE P. VARGHESE, Head of the DepartmentElectronics and Communication Engineering, for helping me to take up this venture and for fostering the excellent academic climate in the Department. It is with pleasure and a deep sense of gratitude that I acknowledge here the invaluable guidance & constant encouragement given by our guide Mr.KRISHNENDU K, Assistant Professor, Electronics and communication Engineering. I am thankful to all staffs of Electronics Department Laboratories for all their help and support. I also express my heartfelt thanks to our seniors who helped me selflessly throughout my work and gave me necessary advice and support. I am indebted to all others, who constantly suggested better ways to process my work. This would not have been a success without the prayers and blessings of my parents.
