Finfet: 5Nm Technology: Presented by Syed Hussain Razavi (Ece-19-38)

FinFET: 5nm Technology
Presented by Syed Hussain Razavi (ECE-19-38)

Prolouge:
● Moore's Law is based on a theory
that the number of transistors that
can be placed on silicon doubles
every two years
1) Moore’s law graph
● Holt said that manufacturing smaller chips with

more features becomes a challenge as chips
could be more sensitive to a “wider class of
defects”.
2) Transistor on silicon wafer
Expected Learning:
● Short channel Effect.
● Gate geometry and electrostatic Integrity.
● Double Gate SOI MOSFET
● FinFET Profile.
● Working of FinFET.
● Conclusion.
Introduction:
● As the size decreases, the device will suffer from the short channel effects (SCE),which
result in the severe leakage problem and mobility degradation,
● Fin-typed FET (FinFET) is one of the most promising device structures to address short
channel effects and leakage issues in the deeply nano-scale transistor
Short Channel Effect:
Contd...
● EI is the Electrostatic integrity which depends on the device geometry and is a measure of the
way the Electric field lined from the drain influence the channel region, thus causing SCE and
DIBL
Contd...
● As can be seen from these expressions, short-channel effects can be

minimized by reducing the junction depth and the gate oxide thickness.
They can also be minimized by reducing the depletion depth through an
increase in doping concentration
Gate geometry and electrostatic integrity
● Short-channel effects can be reduced in FDSOI MOSFETs by
using a thin buried oxide and an underlying ground plane. In
that case, most of the electric field lines from the source and
drain terminate on the buried ground plane instead of the
channel region. This approach, however, has the inconvenience of
increased junction capacitance and body effect
● In a double-gate device, both gates are connected

together. The electric field lines from source and drain
underneath the device terminate on the bottom gate
electrode and cannot, therefore, reach the channel
region. Only the field lines that propagate through the
silicon film itself can encroach on the channel region
and degrade short-channel characteristics.
Double Gate SOI MOSFET:
● A : DELTA MOSFET
● B : FinFET
FinFET Profile:
● Taller fins can provide stronger drive current but will cause more parasitic capacitance.
●
● The narrow fin gives better DIBL performance, however, it also causes Vth increase by
quantum confinement effect.
●
● It is advantage to make more vertical Fin profile because the steeper slope of fin profile can
provide better gate control, larger drive current, and lower SS.
Working of FinFET:
● the gate voltage determines whether a current flow between the drain and source will happen
or not. Let’s see further. When a sufficiently positive Vgs voltage is applied to the gates of
NMOS, the positive charges are placed over the gate as shown in. These positive charges
will repel the minority carriers of p-type substrate i.e. holes from the substrate, leaving
behind negative charge acceptor ions which create depletion region. If we increase Vgs
further, at some potential level it will even make the surface attractive to electrons. So,
plenty of electrons are attracted to the surface. This situation is called inversion because the
surface of p-type body normally has a large number of holes but the newer surfaces have a
large numbers of electrons. Drain-to-body and source-to-body are kept in reverse bias. Here
in, source-to-body is kept at zero bias. As drain-to- body potential is more positive than
source-to-body potential, the reverse bias across drain-to-body is larger resulting in deeper
depletion under drain region compared to source side.
● When positive potential across drain-to-source is applied, electrons flow from the source
through the conducting channel and are drained by the drain. So, a positive current Id flows
from drain-to-source.
Conclusion:
● The 5nm technology FinFET, whether it is Trigate, gates all around etc.
● Important parameter is the channel control of FET, which is possible through gates,
● It up-brings various challenges like SCE and other parasitic capacitance and resistances. So in
order to overcome that problems the fin profile has an important role in miniaturizing the
transistor
● There have been many simulations related to the 5nm FinFET in order to achieve their goal for
miniaturizing the transistors and the results were outstanding, the results depicted that, since we
shrink the transistors still we can control the channel, and overcome SCE and other parasatic
hindrances, and gave us a belief that the FinFET has the ability to extent to 5nm technology
node
● The 5nm FinFET has been evaluatef by density measurment that it occupies 120-300 transistor
per millimeter squared
References:
● REFERENCES
● [1] J.-P. Colinge. FinFET and other multi-gate transistors. 2007.
● [2] Wenqiao Chen Shaojian Hu Shoumian Chen Enming Shang Yu Ding. “The
● Effect of Fin Structure in 5 nm FinFET Technology”. In: Shanghai IC RD
● Center, Shanghai, China 201210 1 (2019).
● [3] Xin Luo Enming Shang Shaojian Hu Shoumian Chen Yu Ding Yongfeng Cao
● and Yuhang Zhao. “A Device Design for 5 nm Logic FinFET Technology”.
● In: hanghai Integrated Circuit Research and Development Center, No. 497
● Gaosi Road, Pudong New Area, Shanghai, China, 201210 2 Shanghai Huali
● Microelectronics Corporation, No. 1399 Zu Chongzhi Road, Pudong New Area,
● Shanghai, China, 201214 (2020).
● [4] R. Sibson. “SLINK: An optimally efficient algorithm for the single-link cluster
● method”. In: Comput. J. 16.1 (1973), pp. 30–34. DOI: 10.1093/comjnl/
● 16.1.30.
● [5] Utmel. URL: https://www.utmel.com/blog/categories/transistors/
● introduction-to-finfet

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FinFET: 5nm Technology

Presented by Syed Hussain Razavi (ECE-19-38)

1) Moore’s law graph

● Holt said that manufacturing smaller chips with

● As can be seen from these expressions, short-channel effects can be

● In a double-gate device, both gates are connected

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