A Mini-Project Report

On

A PROTOTYPE XXXXXX MxxXXXXXOR BASED ON XXXX

HDL
Submitted for partial fulfillment of the requirements for the award of the degree
of

MASTER OF TECHNOLOGY
IN

VLSI System Design

BY

XXXX (20641D5704)

Under the Guidance of

XXXXXXX
Assistant/Associate Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

VAAGDEVI COLLEGE OF ENGINEERING

(Autonomous, Affiliated to JNTUH, NAAC ‘A’ Grade and NBA Accredited)

BOLLIKUNTA, WARANGAL - 506 005 2020-2021

 CERTIFICATE

This is to certify that the mini-project work entitled “A xxxxxxxxxxxxxxx VERILOG HDL ” is a
bonafide work carried out by Ms. xxxxxx (20641D5704) in partial fulfillment of the requirements for
the award of degree of Master of Technology in VLSI System Design from Vaagdevi College of
Engineering, (Autonomous) during the academic year 2021-2022.

xxxxxxxxxxxxx Dr. M. Shashidhar

Assistant Professor, Dept of ECE Head of the Department

Project Guide
 DECLARATION

I declare that the work reported in the mini-project entitled “A PROTOTYPE DESIGN FOR
MICROPROCESSOR BASED ON VERILOG HDL ” is a record of work done by us in the partial
fulfillment for the award of the degree of Master of Technology in VLSI System Design VAAGDEVI
COLLEGE OF ENGINEERING (Autonomous), Affiliated to JNTUH, Accredited By NAAC, under
the guidance of xxxxxxx Assistant/Associate Professor, ECE Department, I/We hereby declare that
this mini-project work bears no resemblance to any other project submitted at Vaagdevi College of
Engineering or any other university/college for the award of the degree.

Ms. xxxxxxxx (20641D5704)

 ACKNOWLEDGEMENT

The development of the project though it was an arduous task, it has been made by the help of many
people. We are pleased to express our thanks to the people whose suggestions, comments, criticisms
greatly encouraged us in betterment of the project.
I would like to express my sincere gratitude and indebtedness to my project Guide xxxxxxx, Dept of
ECE for his/her valuable suggestions and interest throughout the course of this project.
I would like to express my sincere thanks and profound gratitude to Dr. K. Prakash, principal of
Vaagdevi College of Engineering, for his support, guidance and encouragement in the course of our
project.
Iam also thankful to the Head of the Department Dr. M. Shashidhar, Associate Professor
forproviding excellent infrastructure and a nice atmosphere for completing this project successfully.
Iam highly thankful to the Project Coordinators fortheir valuable suggestions, encouragement and
motivations for completing this project successfully.
Iam thankful to all other faculty members for their encouragement
I convey my heartfelt thanks to the lab staff for allowing me to use the required equipment whenever
needed.
Finally, I would like to take this opportunity to thank my family for their support through the work. I
sincerely acknowledge and thank all those who gave directly or indirectly their support in completion of
this work.

Ms. xxxxxx(20641D5704)
 TABLE OF CONTENTS
PAGE NOS.

ABSTRACT. ............................................................................................................. i

LIST OF TABLES ...................................................................................................... ii

LIST OF FIGURES .................................................................................................... iii

LIST OF ACRONYMS ............................................................................................... iv

CHAPTER I INTRODUCTION 1-4

CHAPTER 2 LITERATURE OVERVIEW 5-6

CHAPTER 3 PROPOSED SYSTEM ARCHITECTURE 7-10

3.1 design of 4 bit alu 7-8

3.2 design of 16*4 ram 8-9

3.3 design of instruction decoder 9-10

CHAPTER 4 VERILOG 11-29

4.1 verilog 11

4.2 program structure 11-14

4.3 operators 14-17

4.4 operator priority 17-18

4.6 net 18-19

4.7 arrays 19-20

4.8 system tasks 20

4.9 dataflow design elements 20-23

4.10 behavioral modeling 23-29

CHAPTER 5 XILINX SOFTWARE 30-46

CAHPTER 6 RESULT 47-48

CONCLUSION 49

REFERENCE 50
 ABSTRACT
Nowadays for developing any embedded system the microprocessor is used extensively, but they
comes to any developer as an black-box in which signals are provided from one side and corresponding
output is extracted out from other side. So if developer knows what is hardware present inside the
processor which he/she is currently using, then it would be helpful for making his/her design simple &
optimized. In this paper, we have represented the design and simulation result of basic three elementary
modules of microprocessor i.e. ALU, RAM and Instruction decoder and finally combined all three
modules using Structural modelling .This four bit processor has been designed as a prototype for
designing advanced processors.

i
 LIST OF TABLES

3.1: Operations performed by ALU - 7

4.1: Verilog operator precedence. - 17

4.2: Operator precedence details - 18

4.3: Basic gate primitives in Verilog - 22

4.4: Rules for deciding the output values of gate primitives - 23

ii
 LIST OF FIGURES

1.1: Generic block diagram for four bit processor - 2

3.1: Pin diagram of four bit ALU - 8

3.2: Pin diagram of four bit RAM - 9

3.3: FSM design for instruction decoder - 10

3.4: Pin diagram of instruction decoder - 10

4.1: Program structure - 12

4.3: Flow chat of execution of if-else loop - 27

4.4: Flow chart of execution of for loop - 28

4.5: Flow chart for execution for while loop - 29

iii
 LIST OF ACRONYMS

ALU – Arithmetic and logical unit

RAM – Radom access memory

ID – Instruction decoder

VHDL – Verilog hardware description language

ISE – Integrated system environment

RTL – Register transfer level

CLK – clock

RST - Reset

iv
 CHAPTER 1

INTRODUCTION
The first 4-bit processor was TMS 1000 developed by Texas Instruments, the world's first single-
chip microprocessor, was a 4-bit CPU; it had a Harvard architecture, with an on-chip instruction ROM
with 8-bit-wide instructions and an on-chip data RAM with 4-bit words. But, The Intel 4004 is generally
regarded as the first commercially available microprocessor
.The Intel 4004 is having following specifications:
1. Separate program and data storage.
2. 12-bit addresses
3. 8-bit instructions
4. 4-bit data words
5. Instruction set contained 46 instructions (of which 41 were 8 bits wide and 5 were 16 bits wide)
6. Register set contained 16 registers of 4 bits each
Besides this we had refereed the architecture of various other processor like Intel 4040, Atmel
MARC4 core [4] Mature, Toshiba TLCS-47 series, HP Saturn (microprocessor), NEC PD75X, Epson
S1C63 family, etc. From the reference it was clear that processor mainly contains 3 core elements
Arithmetic and Logic Unit (ALU): It is a digital circuit that performs integer arithmetic and logical
operations.
Memory & Registers: The RAM or Random Access Memory is used to store the incoming data,
intermediate data originated under execution, output of processor which has to be stored for further
execution.
Instruction Decoder: The instruction decoder is the part of the CPU that converts the bits stored in the
instruction register into the control signals that control the other parts of the CPU. So if these three
elements are designed properly, then a main module of processor can be created (as per problem
statement) which will include all the core modules like ALU, RAM, Instruction Decoder, etc.

1
 Figure 1.1 Generic block diagram for four bit processor

A microprocessor is a computer processor that incorporates the functions of a central processing

[1] [2]
unit on a single integrated circuit (IC), or at most a few integrated circuits. The microprocessor is a
multipurpose, clock driven, register based, digital integrated circuit that accepts binarydata as input,
processes it according to instructions stored in its memory and provides results as output.
Microprocessors contain both combinational logic and sequential digital logic. Microprocessors
operate on numbers and symbols represented in the binary number system.
The integration of a whole CPU onto a single or a few integrated circuits greatly reduced the cost of
processing power. Integrated circuit processors are produced in large numbers by highly automated
metal-oxide-semiconductor (MOS) fabrication processes, resulting in a low unit price. Single-chip
processors increase reliability because there are many fewer electrical connections that could fail. As
microprocessor designs improve, the cost of manufacturing a chip (with smaller components built on a
semiconductor chip the same size) generally stays the same according to Rock's law.

2
 Before microprocessors, small computers had been built using racks of circuit boards with many
medium- and small-scale integrated circuits. Microprocessors combined this into one or a few large-
scale ICs. Continued increases in microprocessor capacity have since rendered other forms of computers
almost completely obsolete (see history of computing hardware), with one or more microprocessors
used in everything from the smallest embedded systems and handheld devices to the largest mainframes
and supercomputers.
The complexity of an integrated circuit is bounded by physical limitations on the number of
transistors that can be put onto one chip, the number of package terminations that can connect the
processor to other parts of the system, the number of interconnections it is possible to make on the chip,
and the heat that the chip can dissipate. Advancing technology makes more complex and powerful chips
feasible to manufacture.
The ability to put large numbers of transistors on one chip makes it feasible to integrate memory on
the same die as the processor. This CPU cache has the advantage of faster access than off-chip memory
and increases the processing speed of the system for many applications. Processor clock frequency has
increased more rapidly than external memory speed, so cache memory is necessary if the processor is
not delayed by slower external memory.
Thousands of items that were traditionally not computer-related include microprocessors. These
include large and small household appliances, cars (and their accessory equipment units), car keys, tools
and test instruments, toys, light switches/dimmers and electrical circuit breakers, smoke alarms, battery
packs, and hi-fi audio/visual components (from DVD players to phonograph turntables). Such products
as cellular telephones, DVD video system and HDTV broadcast systems fundamentally require
consumer devices with powerful, low-cost, microprocessors.
In the mid-1980s to early 1990s, a crop of new high-performance reduced instruction set computer
(RISC) microprocessors appeared, influenced by discrete RISC-like CPU designs such as the IBM 801
and others. RISC microprocessors were initially used in special-purpose machines and Unix
workstations, but then gained wide acceptance in other roles.
The first commercial RISC microprocessor design was released in 1984, by MIPS Computer
Systems, the 32-bit R2000 (the R1000 was not released). The R3000 made the design truly practical,
and the R4000 introduced the world's first commercially available 64-bit RISC microprocessor.
Competing projects would result in the IBM POWER and Sun SPARC architectures. Soon every

3
 major vendor was releasing a RISC design, including the AT&T CRISP, AMD 29000, Intel i860 and
Intel i960, Motorola 88000, DEC Alpha.
In the late 1990s, only two 64-bit RISC architectures were still produced in volume for non-
embedded applications: SPARC and Power ISA, but as ARM has become increasingly powerful, in the
early 2010s, it became the third RISC architecture in the general computing segment.

4
 CHAPTER-2

LITERATURE OVERVIEW

In this paper the measurements taken for the development of instruction-level energy models for
microprocessors are presented and analyzed. An appropriate measuring environment and a suitable
measuring methodology were developed for taking the necessary measurements. The energy of an
instruction is defined as a sum of three components. The pure base energy cost, the inter-instruction cost
and the effect of the energy sensitive factors (instruction parameters). These components are
characterized for each instruction of the ARM7TDMI embedded processor and their values are
analyzed. Using the resulted models estimates of the energy consumption of real software kernels with
only up to 5% error was determined.
We discuss the design of a high-performance field programmable gate array (FPGA) architecture
that efficiently prototypes asynchronous (clockless) logic. In this FPGA architecture, low-level
application logic is described using asynchronous dataflow functions that obey a token-based compute
model. We implement these dataflow functions using finely pipelined asynchronous circuits that
achieve high computation rates. This asynchronous dataflow FPGA architecture maintains most of the
performance benefits of a custom asynchronous design, while also providing postfabrication logic
reconfigurability. We report results for two asynchronous dataflow FPGA designs that operate at up to
400 MHz in a typical TSMC 0.25 /spl mu/m CMOS process.
In this paper, we analyze MIPS instruction format instruction data path decoder module function and
design theory based on RISC CPU instruction set. Furthermore, we design instruction fetch (IF) module
of 32-bit CPU based on RISC CPU instruction set. Function of IF module mainly includes fetch
instruction and latch module address arithmetic module check validity of instruction module
synchronous control module. Through analysis of function and theory of RISC CPU instruction decoder
module, we design instruction decoder (ID) module of 32-bit CPU by pipeline theory. The instruction
decoder includes register file, write back data to register file, sign bit extend, relativity check, and it is
simulated on QuartusII successfully. Static time sequence shows the instruction fetch & decode module
completing required function.Microprocessors is a typical subject within the Computer Architecture
field of scope. It is quite common to use simulators in practical sessions, due to the complexity of its
contents. In this paper a new methodology based on practical sessions with

5
 real devices and chips is proposed. Simple designs of microprocessors are exposed to the students at
the beginning, rising the complexity gradually toward a final design with a multiprocessor integrated in
a single FPGA chip. Finally, assessment results are shown in figure.

6
 CHAPTER 3

PROPOSED SYSTEM ARCHITECTURE

3.1 Design of 4 bit ALU

A 4 bit ALU has been designed to perform various arithmetic and logical operations on 4 bit data.
The ALU has three selection bits (S0S1S2), one carry input bit (Cin), two 4-bit data (A and B) and an
active low reset as input pins and it has four bit storage (F) and one bit storage (Cout) as output pins.
The table given below describes the various operations performed by processor and its pseudo

Table 3.1: Operations performed by ALU

7
 The processor instructions can be broadly divided into two classes. Arithmetic operation and
Logical operation. At the end of execution of each instruction memory write operation is performed to
store the result back to the address specified by the instruction decoder.
As shown in adjoining figure (2), the LHS of RTL (Register Transfer Level) Schematic of
Arithmetic and Logical unit has various inputs like two 4 bits ‘a’ & ‘b’ signals, 3 bits operation
selection signal, carry input from previous execution if multiple fetch and execute cycles are required,
etc. On the other hand the 4 bit result is available along with OVERFLOW flag

Fig 3.1: Pin diagram of 4 bit ALU

3.2 DESIGN OF 16X4 RAM

The RAM is required to store various data helpful for instruction execution purpose. It also contains
the intermediate result for multiple fetch and execute operations. Term 16x4 corresponds that the
memory module is 4-bit wide and 16-bit deep. Therefore the 16x4 RAM stores maximum of 8 byte
data.

8
 We had used two dimensional array declaration to define memory blocks. The declaration by
this fashion also helps in synthesis as Technology schematic will represents the four, 16x1 memory
blocks. Whenever Dataout is not used i.e., when memory is in write mode or if chip select is high, the
Dataout is set to “ZZZZ” (meaning nothing is driven onto bus).

Fig. 3.2: Pin diagram of 4 bit RAM

3.2 DESIGN OF INSTRUCTION DECODER

The instruction decoder can be thought of as a finite state machine which changes its state from the
present state to next state on the rising edge of the clock signal. The instruction decoder module takes
input compromising of a three bit opcode and two 4-bit operands. When asynchronous reset is high the
decoder unit goes to init state. With the positive edge of every subsequent clock the unit cycles between
Fetch , Execute and Load state. At each of these states the operations to be performed are as given
below:
Fetch – Fetches data from the location specified by the first operand. The first operand specifies the
reference by memory allocation. This data is store in operand aInput.
Execute – Execute the Instruction using ALU after setting all control lines depending on instruction.
SelectInput lines are set to the value of opcode, aInput is same as obtained in the Fetch state and bInput
is an immediate data supplied to the instruction.
9
 Fig. 3.3: FSM design for instruction decoder

The figure (5) depicts the RTL (Register Transfer Level) Schematic Pin-Diagram of Instruction
Decoder, the LHS pins are Input ports to the instruction decoder. The operand 1 is reference by address
value of memory, whereas the operand 2 is reference by immediate value. The opcode is 3 bit long so
that all the ALU operations can be enclosed. On the other hand on output side, aInput, bInput & select
are provided to ALU, rest all are given to 16x4 RAM.

Fig. 3.4: Pin diagram of Instruction Decoder

10
 CHAPTER 4
VERILOG

4.1 VERILOG:

❖ Verilog synthesis tools can create logic-circuit structures directly from Verilog behavioral
description and target them to a selected technology for realization (I.e, translate Verilog to
actual hardware).

❖ Using Verilog , we can design ,simulate and synthesis anything from a simple combinational
circuit to a complete microprocessor on chip.

❖ Verilog HDL has evolved as a standard hardware description language. Verilog HDL offers
many useful features for hardware design.

❖ Verilog HDL is a general-purpose hardware description language that is easy to learn and
easy to use. It is similar in syntax to the C programming language. Designers with C
programming experience will find it easy to learn Verilog HDL.

❖ Verilog HDL allows different levels of abstraction to be mixed in the same model. Thus, a
designer can define a hardware model in terms of switches, gates, RTL, or behavioral code.
Also, a designer needs to learn only one language for stimulus and hierarchical design.

❖ Most popular logic synthesis tools support Verilog HDL. This makes it the language of
choice for designers.
4.2 PROGRAM STRUCTURE:

The basic unit and programming in Verilog is ”MODULE”(a text file containing statements and
declarations ).

❖ A Verilog module has declarations that describes the names and types of the module
inputs and outputs as well as local signals, variables, constants and functions that are used
internally to the module ,are not visible outside.

❖ The rest of the module contains statements that specify the operation of the module
output and internal signals.
❖ Verilog is a case-sensitive language like C. Thus sense, Sense, SENSE, sENse,…etc.,
are
all treated as different entities / quantities in Verilog.
11
 Fig 4.1: PROGRAM STRUCTURE.

4.2.1 SYNTAX:

Module Module_Name( PORT_name,….................... port_name);

Input declaration

Output declaration

Net declaration

Variable declaration

Parameter declaration

Function declaration

Task declaration

Concurrent_statements

Endmodule

module signifies the beginning of a module definition.

endmodule signifies the end of a module definition.

4.2.2 IDENTIFIERS:

Any program requires blocks of statements, signals, etc., to be identified with an attached
nametag. Such nametags are identifiers. It is good practice for us to use identifiers, closely related to
the significance of variable, signal, block, etc., concerned. This eases understanding and debugging
of any program.

12
 There are some restrictions in assigning identifier names. All characters of the alphabet or
an underscore can be used as the first character. Subsequent characters can be of alphanumeric type,
or the underscore (_), or the dollar ($) sign .

4.2.3 PORT DECLERATION:

Verilog module declaration begins with a keyword ”module” and ends with”endmodule”.
The input and output ports are signals by which the module communicates with each others.

Syntax:

Input identifier ......................... identifier;

Output identifier ......................... identifier;

Inout identifier ......................... identifier;

Input [msb:lsb] identifier ......................... identifier;

Output[msb:lsb] identifier ......................... identifier;

Inout [msb:lsb] identifier ......................... identifier;

❖ Module definitions contain various components. Keywords module and endmodule

are mandatory. Other components-port list, port declarations, variable and signal
declarations, dataflow statements, behavioral blocks, lower-level module instantiations,
and tasks or functions-are optional and can be added as needed.

❖ Ports provide the module with a means to communicate with other modules or its
environment. A module can have a port list. Ports in the port list must be declared as
input, output, or inout. When instantiating a module, port connection rules are enforced
by the Verilog simulator.

❖ Ports can be connected by name or by ordered list.

❖ Each identifier in the design has a unique hierarchical name. Hierarchical names
allow us to address any identifier in the design from any other level of hierarchy in the
design.

❖ Each port that is named at the beginning of the module ,in the input, output list must
have corresponding input and output declaration

13
 ❖ The signals in a vector can be ascending or descending order.
4.2.4 LOGIC SYSTEM:

Verilog uses 4 –logic system .a 1 –bit signal can take one of only four possible values.

0 LOGIC 0,OR FALSE

1 LOGICAL 1,OR FALSE
X A UNKNOWN LOGICAL
VALUE Z HIGH IMPEDENCE
4.3 OPERATORS:

4.3.1 Arithmetic Operators:

These perform arithmetic operations. The + and - can be used as either unary (-z) or binary
(x-y) operators.
+ (addition)
- (subtraction)

* (multiplication)
/ (division)
%(modulus)
Example :

parameter n = 4;
reg[3:0] a, c, f, g, count;
f = a + c;
g = c - n;
count = (count +1)%16; //Can count 0 thru 15.

4.3.2 Relational Operators:

Relational operators compare two operands and return a single bit 1or 0. These
operators synthesize into comparators.
< (less than)
<= (less than or equal to)
> (greater than)
>= (greater than or equal to)
= (equal to)
!= (not equal to)
14
 Wire and reg variables are positive Thus (-3’b001) = = 3’b111 and (-3d001)>3d110. However
for integers -1< 6.
Example
if (x = = y) e = 1;
else e = 0;
/ Compare in 2’s compliment;
a>b reg [3:0] a ,b ;
if (a[3]= = b[3]) a[2:0] >
b[2:0]; else b[3];

4.3.3 Bit-wise Operators:

Bit-wise operators do a bit-by-bit comparison between two operands. However see
“Reduction Operators” .
~ (bitwise NOT)
& (bitwise AND)
| (bitwise OR)
^ (bitwise XOR)
~^ or ^~ (bitwise XNOR)
Example :
module and2 (a, b, c);
input [1:0] a, b;
output [1:0] c;
assign c = a & b;
end module

4.3.4 Logical Operators:

Logical operators return a single bit 1 or 0. They are the same as bit-wise operators only for
single bit operands. They can work on expressions, integers or groups of bits, and treat all values that
are nonzero as “1”. Logical operators are typically used in conditional (if ... else) statements since
they work with expressions.
! (logical NOT)
&& (logical AND)

15
 | (logical OR)
Example :
wire[7:0] x, y, z; // x, y and z are multibit variables.
reg a;
...
if ((x == y) && (z)) a = 1; // a = 1 if x equals y, and z is nonzero.
else a = !x; // a =0 if x is anything but zero.

4.3.5 Reduction Operators:

Reduction operators operate on all the bits of an operand vector and return a single-bit value.
These are the unary (one argument) form of the bit-wise operators above.
& (reduction AND)
| (reduction OR)
~& (reduction NAND)
~| (reduction NOR)
^ (reduction XOR)
~^ or ^~ (reduction XNOR)

4.3.6 Shift Operators:

Shift operators shift the first operand by the number of bits specified by the second operand.
Vacated positions are filled with zeros for both left and right shifts (There is no sign extension).

< (shift left)

>>(shift right)

4.3.7 Operator Precedence:

The below table shows the precedence of operators from highest to lowest. Operators on the
same level evaluate from left to right. It is strongly recommended to use parentheses to define order
of precedence and improve the readability of your code.

16
 Table 4.1:Verilog Operators Precedence.

4.4 Operator Priority:

A clear understanding of the operator precedence makes room for a compact design
description. But it may lead to ambiguity and to inadvertent errors. Whenever one is not sure of the
operator priorities, it is better to resort to the use of parentheses and ensure clarity and accuracy of
expressions. Further, some synthesizers may not interpret the operator precedence properly. These
too call for the apt use of parentheses.

The operators are arranged in tabular form and shown in below table. The table brings out
the order of precedence. The order of precedence decides the priority for sequence of execution and
circuit realization in any assignment statement. The following form the basic rules for the same:

17
 Table 4.3:Operator precedence details.

❖ Unary operators have the highest priority and execute first.

❖ Subsequently the binary operators execute. Amongst these the algebraic

❖ Operators have the highest precedence. Amongst the algebraic operators *, / and %
have precedence over + and – operators.
❖ Subsequent precedence amongst the binary operators is as shown in the table.
❖ Conditional operator has the lowest precedence and hence is executed last.

4.6 NET:

Nets represent connections between hardware elements. Just as in real circuits, nets have
values continuously driven on them by the outputs of devices that they are connected to.

❖ The default net type is wire, any signal name that appears in a module input /output
list, but not in a net declaration is assumed to be type wire.

❖ Note that net is not a keyword but represents a class of data types such as wire, wand,
wor, tri, triand, trior, trireg, etc. The wire declaration is used most frequently.
❖ The syntax of verilog net declaration is similar to an input/output declaration.
Syntax:

Wire identifier ,… ............... identifier;

Wire [msb:lsb] identifier ,… ............... identifier;

18
 tri [msb:lsb] identifier ,… .......... identifier;

❖ The keyword tri has a function identical to that of wire. When a net is driven by more
than
one tri-state gate, it is declared as tri rather than as wire. The distinction is for better clarity.
4.6.2 VARIABLE:

❖ Verilog variables stores the values during the program execution, and they need not
have

❖ They are used in only procedural code (i.e,behavioral design).A variable value can be
used ina expression and can be combined and assign to other variables, as in conventional
software programming language.
❖ The most commonly used variables are REG and INTEGERS.
❖ Values of registers can be changed anytime in a simulation by assigning a new value to
the register. Register data types are commonly declared by the keyword reg.
Syntax:
Reg identifier ,… ............ identifier;
Reg [msb:lsb] identifier,… ............ identifier;
Integer identifier ,… ............ identifier;

❖ A register variable is a single bit or vector of bits , the value of 1-bit reg variable is
always 0,1,X,Z. the main use of reg variables is to store values in Verilog procedural
code.

❖ An integer variable value is a32-bit or larger integer ,depending on the word length on
the word length used by simulator .An integer variable is typically used to control a
repetitive statements ,such as loop, in Verilog procedural code.

❖ The difference between Verilog net’s and variables is subtle. A variable value can
change only within procedural code with in a module, it cannot be changed from outside
the module.

4.7 ARRAYS:
Arrays are allowed in Verilog for reg, integer, time, and vector register data types. Arrays are not
allowed for real variables. Arrays are accessed by <array_name> [<subscript>]. Multidimensional
arrays are not permitted in Verilog.Syntax:Reg identifier [start:end];

Reg [msb:lsb] identifier [start:end];

Integer identifier [start:end] ;
19
 It is important not to confuse arrays with net or register vectors. A vector is a single element
that is n-bits wide. On the other hand, arrays are multiple elements that are I-bit or n-bits wide .

4.7 SYSTEM TASKS:

During the simulation of any design, a number of activities are to be carried out to
monitor and control simulation. A number of such tasks are provided / available in Verilog. Some
other tasks serve other functions. However, these are described here. The “$” symbol identifies a
system task. A task has the format

$<keyword>

4.8.1 Tasks for Control of Simulation:

Two system tasks are available for control of simulation:

4.8.2 $finish:

$finish task, when encountered, exits simulation. Control is reverted to the Operating System.
Normally the simulation time and location are also printed out by default as part of the exit operation.

4.8.3 $stop:

Stop task, suspends simulation; if necessary the simulation can be resumed by user
intervention. Thus with the stop task, the simulator is in an interactive mode. In contrast with $finish,
simulation has to be started afresh.

4.8 DATAFLOW DESIGN ELEMENTS:

Continuous assignment statement allows to describe a combinational circuit in

terms of the flow of data and operations on the circuit. This style is called “dataflow design or
description”. The basic syntax of a continuous –assignment statement in Verilog is

Syntax:

Assign net-name=expression;

20
 Assign net-name[bit-index]=expression;
Assign net-name[msb:lsb]=expression;
Assign net-concatenation =expression;
❖
“Assign” is the keyword carrying out the assignment operation. This type of assignment
is called a continuous assignment.
❖
The keyword “assign ”is followed by the name of a net, then an”=”sign and finally an
expression giving the value to be assigned
❖
The order continuous–assignment statements in a module doesn’t matter .if the last
statement changes a net value used by the first statement ,then the simulator go back to
that first statement and update it’s result according to the net that just changed.
❖
If a module contains two statements “assign X=Y” and “assign Y=~X”, then the
simulation will loop “forever”(until the simulation times out).
For example:

assign c = a && b;
❖ a and b are operands – typically single-bit logic variables.

❖ “&&” is a logic operator. It does the bit-wise AND operation on the two
❖ operands a and b.
❖ “=” is an assignment activity carried out.
❖ c is a net representing the signal which is the result of the assignment.
4.9.1 Operand types:

❖ A constant number [including real].

❖ Net of a scalar or vector type including part of a vector.

❖ Register variable of a scalar or vector type including part of a vector.
❖ Memory element.
❖ A call to a function that returns any of the above. The function itself can be a user-
defined or of a system type
4.9.2 STUCTURAL DESIGN (OR)GATE LEVEL MODELING :

❖ Structural Design Is the Series of Concurrent Statement .The Most Important

Concurrent Statement In the module covered like instance statements, continuous –
assignment

21
 statement and always block. These gives rise to three distinct styles of circuit design
and description.

❖ Statement of these types, and corresponding design styles, can be freely intermixed
within a Verilog module declaration.

❖ Each concurrent statement in a Verilog module “executes” simultaneously with

other statements in the same module declaration .

❖ In fact, the simulator will propagating changes and updating results until the
simulated circuit stabilizes.
❖ Verilog has several built in gate types, the names of these gates are reserved
words,some
of these are
And xor bufif0

Nand xnor bufif1

Or buf notif0
Nor not notif1

4.9.2 Basic gate primitives in Verilog with details:

Table 4.3: Basic gate primitives in Verilog.

4.9.3 Rules for deciding the output values of gate primitives:

22
 Table 4.4: Rules for deciding the output values of gate primitives.

❖ Two different formats are allowed for the port –associated list. The first format
depends on the order in which port names appears in the original component definition.

❖ The local expression are listed in the same order as the ports to which they are
supposed to connect.

❖ For built in , multi-input gates ,the defined port name order is (output,
input… ........ )and the order among the multiple inputs doesn’t matter.
4.9 BEHAVIORAL MODELING:

Behavioral level modeling constitutes design description at an abstract level. One can
visualize the circuit in terms of its key modular functions and their behavior. The constructs available
in behavioral modeling aim at the system level description.

In other words, the designer describes the behavior of the circuit. Thus, behavioral modeling
represents the circuit at a very high level of abstraction. Design at this level resembles C
programming more than it resembles digital circuit design. Behavioral Verilog constructs are similar
to C language constructs in many ways. Verilog is rich in behavioral constructs that provide the
designer with a great amount of flexibility.

4.10.1 OPERATIONS AND ASSIGNMENTS:

The design description at the behavioral level is done through a sequence of assignments.
These are called ‘procedural assignments’ – in contrast to the continuous assignments at the data
flow level. The procedure assignment is characterized by the following:

23
 The assignment is done through the “=” symbol (or the “<=” symbol) as was the case with
the continuous assignment earlier.
An operation is carried out and the result assigned through the “=” operator to an
operand specified on the left side of the “=” sign – for example,
• N=~N;
All the operands are given in Tables 6.1 to 6.9. The format of using them and the rules
of precedence remain the same.
The operands on the right side can be of the net or variable type. They can be scalars or vectors.
It is necessary to maintain consistency of the operands in the operation expression – e.g.,
• N = m / l;
The operand to the left of the “=” operator has to be of the variable (e.g., reg) type. It has to be
specifically declared accordingly. It can be a scalar, a vector, a part vector, or a concatenated
vector. As soon as a specified operation on the right is carried out, the result is assigned to the
quantity on the left – for example
• N = m + l;
• N1=N*N;
The above form a set of two procedures placed within an always block. Generally
they are carried out sequentially in the order specified; that is, first m and l are added and the result
assigned to N. Then the square of N is assigned to N1. Subsequently the following assignment, if
any, is carried out. However, there can be exceptions to this which will be discussed later.

4.10.2 Structured Procedures:

There are two structured procedure statements in Verilog: always and initial .These statements
are the two most basic statements in behavioral modeling. All other behavioral statements can appear
only inside these structured procedure statements. Verilog is a concurrent programming language unlike
the C programming language, which is sequential in nature. Each always and initial statement represents
a, separate activity flow in Verilog. Each activity flow starts at simulation time 0.

Always:

➢
The key element of Verilog behavioral design is the always block the always block contains
one or more “procedural statements”.

24
 ➢ Another type of procedural statement is a “begin-end” block. But the ALWAYS block
is used in all because of its simplicity, that is why we call it an always block.

➢ Procedural statement in an always block executes sequentially .The always block

executes concurrently with other concurrent statement in the same module.
Syntax:

1).Always @(signal-name ................ signal-name)

Procedural statement

2). Always procedural statements

In the first form of always block ,the@ sign and parenthesized list of signal names called
“sensitivity list “.

➢ A verilog concurrent statement such as always block is either executing or suspend

➢ A concurrent statement initially is in suspend stste ,when any signal value changes its
value ,it resumes execution starting its first procedural statement and continuing until the end.

➢ A properly written concurrent statement will suspend after one or more executions.
However it is possible to write a statement that never suspends(e.g.: assign X=~X), since X
changes for every pass ,the statement will execute forever in zero simulation time(which is
not useful).

4.10.3 Blocking And Non-blocking Assignments:

All assignment within an initial or an always block considered so far are done through an
equality (“=”) operator. These are executed sequentially – that is, one statement is executed, and only
then the following one is executed. Such assignments block the execution of the following lot of
assignments at any time step. Hence they are called “blocking assignments”.

Syntax:
Variable-name=expression;//blocking statements.
Variable-name<=expression;//Non-blocking statements.

4.10.4 BEGIN- END BLOCK:

25
 Begin-end block statements are used to group several statements for use where one statement
is syntactically allowed. Such places include functions, always and initial blocks, if, case and for
statements. Blocks can optional.

Syntax:

1) 2)
begin begin : block_name
procedural statements reg [msb:lsb] reg_variable_list;

: : integer [msb:lsb] integer_list;

: : parameter [msb:lsb] parameter_list;
procedural statements ... statements ...
end end

The syntax of a begin-end block ,simply a list of one or more procedural statements enclosed
by the keyword begin-end.
As shown in the second part of the syntax ,the begin-end block can have its own local
parameters or variable declaration.
Note that the procedural statements within a begin-end block executes sequentially ,not
concurrently like the instance ,continuous –assignment and other “always ” statements in the
module.
4.10.5 IF-ELSE BLOCK:

If the number of assignments associated with the if condition is more than 1, the
whole set of them can be grouped within a begin-end block. Figure 8.3 shows a segment of a design
using the if construct. It is a ring counter, which shifts one bit right at every clock pulse. The shift
operation shifts the a byte right by one bit and fills the vacated bit – a[7] – with a zero. It is set to 1 if
the bit shifted out last – a[0] – was a 1. Figure shows the same in flowchart form. The design
description has two branches; the alternative taken is decided by the condition:

26
 Fig 4.3: Flowchart of execution of If-else loop.

After the execution of assignment1, if the condition is satisfied, alternative1 is followed and
assignment2 and assignment3 are executed. Assignment4 and assignment 5 are skipped and
execution proceeds with assignment6.

4.10.6 For Loops:

Similar to for loops in C/C++, they are used to repeatedly execute a statement or block of
statements. If the loop contains only one statement, the begin ... end statements may be omitted.

Syntax:
for (count = value1;
count </<=/>/>= value2;
count = count +/- step)
begin
... statements ...
End

27
 Fig 4.4: Flowchart of execution of the for loop.

4.10.7 While Loops:

The while loop repeatedly executes a statement or block of statements until the
expression in the while statement evaluates to false. To avoid combinational feedback during
synthesis, a while loop must be broken with an @(posedge/negedge clock) statement . For simulation
a delay inside the loop will suffice.
Syntax:
while (expression)
begin
... statements ...
End

Fig 4.5: Flowchart for execution while loop of the.

28
 Whenever the while construct is used, event or time-based activity flow within the block has to
be ensured.

❖ With the while construct the expression associated with the keyword while must become
false through the execution of assignments inside the block. Otherwise we end up with an
endless looping within the block, causing a deadlock.

❖ There may be situations where we have to wait in a loop while an event external to it changes
to trigger an activity. The wait construct is to be used for such situations and not while. With
the wait construct the activity is scheduled
4.10.8 CASE:
The case statement allows a multipath branch based on comparing the expression with a list
of case choices. Statements in the default block executes when none of the case choice comparisons
are true.
Syntax
case (expression)
case_choice1:
begin
... statements ...
end
case_choice2:
begin
... statements ...
end
default:
begin
... statements ...
end
endcase

29
 5 XILINX SOFTWARE

Xilinx Tools is a suite of software tools used for the design of digital circuits implemented using
Xilinx Field Programmable Gate Array (FPGA) or Complex Programmable Logic Device (CPLD). The
design procedure consists of (a) design entry, (b) synthesis and implementation of the design, (c)
functional simulation and (d) testing and verification. Digital designs can be entered in various ways
using the above CAD tools: using a schematic entry tool, using a hardware description language (HDL)
– Verilog or VHDL or a combination of both. In this lab we will only use the design flow that involves
the use of VerilogHDL.

The CAD tools enable you to design combinational and sequential circuits starting with Verilog
HDL design specifications. The steps of this design procedure are listed below:
1. Create Verilog design input file(s) using template driveneditor.
2. Compile and implement the Verilog designfile(s).

3. Create the test-vectors and simulate the design (functional simulation) without using a PLD
(FPGA orCPLD).
4. Assign input/output pins to implement the design on a targetdevice.

5. Download bitstream to an FPGA or CPLDdevice.

6. Test design on FPGA/CPLDdevice

A Verilog input file in the Xilinx software environment consists of the following segments:
Header: module name, list of input and output ports.
Declarations: input and output ports, registers and wires.
Logic Descriptions: equations, state machines and logic functions.
End: endmodule

All your designs for this lab must be specified in the above Verilog input format. Note that
the state diagram segment does not exist for combinational logic designs.

30
1. Programmable Logic Device:FPGA
In this lab digital designs will be implemented in the Basys2 board which has a Xilinx Spartan3E
–XC3S250E FPGA with CP132 package. This FPGA part belongs to the Spartan family of FPGAs.
These devices come in a variety of packages. We will be using devices that are packaged in 132 pin
package with the following part number: XC3S250E-CP132. This FPGA is a device with about 50K
gates. Detailed information on this device is available at the Xilinx website.

1. Creating a NewProject
Xilinx Tools can be started by clicking on the Project Navigator Icon on the Windows desktop. This
should open up the Project Navigator window on your screen. This window shows (see Figure
1) the last accessed project.

Figure 5.1: Xilinx Project Navigator window (snapshot from Xilinx ISE software)

3.1 Opening a project

31
Select File->New Project to create a new project. This will bring up a new project window
(Figure 2) on the desktop. Fill up the necessary entries as follows

Figure 5.2: New Project Initiation window (snapshot from Xilinx ISE software)

ProjectName: Write the name of your newproject

Project Location: The directory where you want to store the new project (Note: DO NOT
specify the project location as a folder on Desktop or a folder in the Xilinx\bin directory. Your
H: drive is the best place to put it. The project location path is NOT to have any spaces in it
eg: C:\Nivash\TA\new lab\sample exercises\o_gate is NOT to be used)

Leave the top level module type as HDL.

Example: If the project name were “o_gate”, enter “o_gate” as the project name and then click
“Next”.
Clicking on NEXT should bring up the following window:

32
 Figure 5.3: Device and Design Flow of Project (snapshot from Xilinx ISE software)

For each of the properties given below, click on the ‘value’ area and select from the list
of values that appear.
o Device Family: Family of the FPGA/CPLD used. In this laboratory we will
be using the Spartan3EFPGA’s.
o Device: The number of the actual device. For this lab you may enterXC3S250E
(this can be found on the attached prototyping board)
o Package:Thetypeofpackagewiththenumberofpins.TheSpartanFPGAusedin this
lab is packaged in CP132package.
o Speed Grade: The Speed grade is“-4”.
o Synthesis Tool: XST[VHDL/Verilog]
o Simulator: The tool used to simulate and verify the functionality of the design.
Modelsim simulator is integrated in the Xilinx ISE. Hence choose “Modelsim-XE
Verilog” as the simulator or even Xilinx ISE Simulator can beused.
33
 o Then click on NEXT to save theentries.

All project files such as schematics, netlists, Verilog files, VHDL files, etc., will be stored in a
subdirectory with the project name. A project can only have one top level HDL source file (or
schematic). Modules can be added to the project to create a modular, hierarchical design (see
Section 9).

In order to open an existing project in Xilinx Tools, select File->Open Project to show the list
of projects on the machine. Choose the project you want and click OK.

Clicking on NEXT on the above window brings up the following window:

Figure 5.4: Create New source window (snapshot from Xilinx ISE software)

If creating a new source file, Click on the NEW SOURCE.

3.2 Creating a Verilog HDL input file for a combinational logicdesign

In this lab we will enter a design using a structural or RTL description using the Verilog HDL.
You can create a Verilog HDL input file (.v file) using the HDL Editor available in the Xilinx
ISE Tools (or any text editor).

In the previous window, click on the NEW SOURCE

34
 A window pops up as shown in Figure 4. (Note: “Add to project” option is selected by default. If
you do not select it then you will have to add the new source file to the project manually.)

Figure 5.5: Creating Verilog-HDL source file (snapshot from Xilinx ISE software)

Select Verilog Module and in the “File Name:” area, enter the name of the Verilog source
file you are going to create. Also make sure that the option Add to project is selected so that the
source need not be added to the project again. Then click on Next to accept the entries. This pops
up the following window (Figure 5).

35
 Figure 5.6: Define Verilog Source window (snapshot from Xilinx ISE software

In the Port Name column, enter the names of all input and output pins and specify the Direction
accordingly. A Vector/Bus can be defined by entering appropriate bit numbers in the MSB/LSB
columns. Then click on Next> to get a window showing all the new source information (Figure 6). If
any changes are to be made, just click on <Back to go back and make changes. If everything is
acceptable, click on Finish > Next > Next > Finish tocontinue.

36
Figure 5.7: New Project Information window(snapshot from Xilinx ISE software)

Once you click on Finish, the source file will be displayed in the sources window in the Project
Navigator (Figure 1).
If a source has to be removed, just right click on the source file in the Sources in Project window in
the Project Navigator and select Removein that. Then select Project -> Delete Implementation Data
from the Project Navigator menu bar to remove any relatedfiles.
3.3 Editing the Verilog sourcefile
The source file will now be displayed in the Project Navigator window (Figure 8). The source
filewindowcanbeusedasatexteditortomakeanynecessarychangestothesourcefile.All
The input/output pins will be displayed. Save your Verilog program periodically by selecting the
File->Save from the menu. You can also edit Verilog programs in any text editor and add them to
the project directory using “Add Copy Source”.

Figure 5.8: Verilog Source code editor window in the Project Navigator (from Xilinx ISE
software)

37
 Adding Logic in the generated Verilog Source codetemplate:
A brief Verilog Tutorial is available in Appendix-A. Hence, the language syntax and
construction of logic equations can be referred to Appendix-A.

The Verilog source code template generated shows the module name, the list of ports and
also the declarations (input/output) for each port. Combinational logic code can be added
to the verilog code after the declarations and before the endmodule line.
For example, an output z in an OR gate with inputs a and b can be described as,
assign z = a | b;
Remember that the names are case sensitive.

Other constructs for modeling the logicfunction:

A given logic function can be modeled in many ways in verilog. Here is another
example in which the logic function, is implemented as a truth table using a case statement:

moduleor_gate(a,b,z); input a;
input b; output z;

reg z;
always @(a or b) begin
case ({a,b}) 00: z =1'b0;
1: z =1'b1;
10: z =1'b1;

11: z =1'b1;
endcase
end
endmodule

Suppose we want to describe an OR gate. It can be done using the logic equation as shown in
Figure 9a or using the case statement (describing the truth table) as shown in Figure 9b. These
are just two example constructs to design a logic function. Verilog offers numerous such
constructs to efficiently model designs. A brief tutorial of Verilog is available in Appendix-A.
38
Figure 5.9: OR gate description using assign statement (snapshot from Xilinx ISE
software)

39
Figure 5.10: OR gate description using case statement (from Xilinx ISE software)

2. Synthesis and Implementation of theDesign

The design has to be synthesized and implemented before it can be checked for correctness, by
running functional simulation or downloaded onto the prototyping board. With the top-level
Verilog file opened (can be done by double-clicking that file) in the HDL editor window in the
right half of the Project Navigator, and the view of the project being in the Module view
, the implement design option can be seen in the process view. Design entry utilities and
Generate Programming File options can also be seen in the process view. The former can be
used to include user constraints, if any and the latter will be discussed later.
To synthesize the design, double click on the Synthesize Design option in the Processes
window.

To implement the design, double click the Implement design option in the Processes
window. It will go through steps like Translate, Map and Place & Route. If any of these
steps could not be done or done with errors, it will place a X mark in front of that, otherwise

40
 a tick mark will be placed after each of them to indicate the successful completion. If
everything is done successfully, a tick mark will be placed before the Implement Design
option. If thereare

warnings, one can see mark in front of the option indicating that there are some warnings. One
can look at the warnings or errors in the Console window present at the bottom of the
Navigator window. Every time the design file is saved; all these marks disappear asking for a
freshcompilation.

Figure 5.11: Implementing the Design (snapshot from Xilinx ISE software)

The schematic diagram of the synthesized verilog code can be viewed by double clicking
View RTL Schematic under Synthesize-XST menu in the Process Window. This would be a
handy way to debug the code if the output is not meeting our specifications in the proto type
board. By double clicking it opens the top level module showing only input(s) and output(s)
as shown below.

41
 Figure 5.12: Top Level Hierarchy of the design

By double clicking the rectangle, it opens the realized internal logic as

shown below.

Figure 5.13: Realized logic by the XilinxISE for the verilog code

3. Functional Simulation of CombinationalDesigns

42
 5.1 Adding the testvectors

To check the functionality of a design, we have to apply test vectors and simulate the circuit. In
order to apply test vectors, a test bench file is written. Essentially it will supply all the inputs to the
module designed and will check the outputs of the module. Example: For the 2 input OR Gate, the steps
to generate the test bench is as follows:
In the Sources window (top left corner) right click on the file that you want to generate the test
bench for and select ‘New Source’
Provide a name for the test bench in the file name text box and select ‘Verilog test fixture’
among the file types in the list on the right side as shown in figure 11.

Figure 5.14: Adding test vectors to the design (snapshot from Xilinx ISE software)

Click on ‘Next’ to proceed. In the next window select the source file with which you
want to associate the test bench.

43
Figure 5.15: Associating a module to a testbench (snapshot from Xilinx ISE software)

Click on Next to proceed. In the next window click on Finish. You will now be provided
with a template for your test bench. If it does not open automatically click the radio
button next to Simulation .

You should now be able to view your test bench template. The code generated would
be something like this:
moduleo_gate_tb_v;
/ Inputs reg a;
reg b;
/ Outputs wire z;
/ Instantiate the Unit Under Test (UUT) o_gateuut (
.a(a),
.b(b),
.z(z)
);
Initialbegin
/ Initialize Inputs a =
0; b =0;
/ Wait 100 ns for global reset tofinish #100;
/ Add stimulus here
End

The Xilinx tool detects the inputs and outputs of the module that you are going to test an assigns

44
 them initial values. In order to test the gate completely we shall provide all the different input
combinations. ‘#100’ is the time delay for which the input has to maintain the current value.
After 100 units of time have elapsed the next set of values can be assign to the inputs. Complete
the test bench as shown below:

moduleo_gate_tb_v;
/ Inputs reg a; reg b;
/ Outputs wire z;
/ Instantiate the Unit Under Test (UUT) o_gateuut (
.a(a),
.b(b),
.z(z)
);
initialbegin
/ Initialize Inputs a = 0;
b =0
// Wait 100 ns for global reset to finish #100;
a = 0;
b =1;
/ Wait 100 ns for global reset tofinish
#100; a = 1;
b =0;
/ Wait 100 ns for global reset tofinish
#100; a = 1;
b =1;
/ Wait 100 ns for global reset tofinish
#100; End
Endmodule

Save your test bench file using the File menu.

5.2 Simulating and Viewing the OutputWaveforms

Now under the Processes window (making sure that the testbench file in the Sources window is
selected) expand the ModelSim simulator Tab by clicking on the add sign next to it. Double Click on
Simulate Behavioral Model. You will probably receive a complier error. This is nothing to worry about
– answer “No” when asked if you wish to abort simulation. This should cause ModelSim to open. Wait for it to
complete execution. If you wish to not receive the compiler error, right click on Simulate Behavioral Model and
select process properties. Mark the
45
 checkbox next to “Ignore Pre-Complied Library Warning Check”.

Figure 5.16: Simulating the design (snapshot from Xilinx ISE software)

5.3 Saving the simulationresults

To save the simulation results, Go to the waveform window of the Modelsim simulator, Click
on File -> Print to Postscript -> give desired filename and location.
Notethatbydefault,thewaveformis“zoomedin”tothenanosecondlevel.Use the zoom controls to
display the entirewaveform. Else a normal print screen option can be used on the waveform
window and subsequently stored in Paint.

Figure 5.17: Behavioral Simulation output Waveform (Snapshot from ModelSim)

46
 CHAPTER-6
RESULTS
Xilinx ISE was also used for functional verification of our design by incorporating the suitable
testbenches and viewing waveforms on inbuilt Xilinx ISim Simulator. There are various advantages like
ability to launch ISim graphical user interface for command-line users, Ability to set the Verilog
timescale at elaboration time, Ability to change the top-level generic/parameters at runtime, Support for
Verilog source libraries, Ability to load multiple wave configurations per simulation session
By using ISE schematic viewer by Xilinx, various RTL and Technology Schematic diagram were
observed. The figure (6) shows the final processor which acccepts 3 bit opcode, two 4 bit operands,
carry, clock and system reset signal. It produces the 4 bit result and if the result exceeds 4 bit the
overflow flag is set.

Module Processor
Result output(3.0)
Opcode(2.0
)
Operand1(3.0
)
Operand2(3.0
)

Carry
input

clk

rst Carry output

Pin diagram of four bit processor

47
48
 CONCLUSIONS
We have designed and verified the functionality of basic four bit microprocessor using structural
modeling which combines three elementary modules i.e. four bit ALU,16x4 RAM and Instruction
Decoder. The processor design that we carried out is very basic but for understanding and developing
design of new age complex processor architectures like multi-core design, the knowledge of basic
design is inevitable.
As a part of future enhancement to the architecture, various addition are possible like dual-core
processor design, to include more variety of operations to be carried out by ALU, different assortment
of DSP (Digital Signal Processing) functions like convolution, time shifting, Fast Fourier transform
operations can be added. We can also include serial interface block so that RS232 port can be attached
to processor.

49
 REFERENCES
[1] N. Kavvadias, P. Neofotistos, S. Nikolaidis, C. A. Kosmatopoulos, and T. Laopoulos,
“Measurements analysis of the software-related power consumption in microprocessors,”IEEE
Trans. Instrum. Meas., vol. 53, no. 4, pp. 1106–1112, Aug. 2004.
[2]J. Teifel and R. Manohar, “An Asynchronous Dataflow FPGA Architecture,” IEEE Transactions
on Computers, vol. 53, no. 11, pp. 1376–1392, 2004.
[3]Balpande, R.S. and Keote, R.S., "Design of FPGA based Instruction Fetch & Decode Module
of 32-bit RISC (MIPS) Processor," in Proc. of International Conference on Communication Systems
and Network Technologies, pp. 409-413, 2011.
[4]Joaquín Olivares, et all, “Teaching Microprocessor Design Using FPGAs”, IEEE EDUCON
Education Engineering 2010, April 2009, Spain.
[5]Xilinx® Inc., PicoBlaze 8-bit Embedded Microcontroller User Guide, Xilinx® 2005
[6]Wang Min, The Principle of Computer Organization, Electronics Industry Publishing
House, Beijing, 2003
[7]Kilts, Steve, “Advanced FPGA Design.”, John Wiley & Sons, 2007.
[8]M. Morris Mano, “Digital Logic & Computer Design,” Pearson Edition, 1979
[9]Samir Palnitkar, “Verilog HDL A guide to Digital Design and Synthesis,” SunSoft Press.
[10]Rajeev Madhavan, “Quick Reference for Verilog HDL,” Ambit DesignSystem,2001
[11]Eli Sternheim , Rajvir Singh, Rajeev Madhavan , Yatin Trivedi, “Digital Design and Synthesis
with Verilog HDL”. Automata PubCo; 1993.
[12]Behrooz Parhami, “Computer Architecture: From Microprocessors to Supercomputers,”

[13]Xilinx, “The programmable Logic Data Book 2000”, Xilinx San Jose, 2000.
[14]Wolf, Wayne, “FPGA-Based System Design.”, Pearson Education, 2004
[15]Kilts, Steve, “Advanced FPGA Design.”, John Wiley & Sons, 2007.
[16]Xilinx. [Online]. Available: www.xilinx.com.
[17]Intel. [Online]. Available:www.intel.com
[18]Texas Instruments [Online]. Available: www.ti.com/

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