A project report on

MICROBLAZE PROCESSOR
BASED SERIAL COMMUNICATION SYSTEM

Submitted in partial fulfillment for the award of the degree of

B.Tech Electronics and Communication Engineering

with specialization in Embedded Systems

by

R Sravan Kumar (20BES7044)

School of Electronics Engineering (SENSE)

May, 2024
 DECLARATION

I here by declare that the thesis entitled “MICROBLAZE PROCESSOR BASED

SERIAL COMMUNICATION SYSTEM” submitted by me, for the award of the degree of
B. Tech Electronics and Communication Engineering with specialization in Embedded Systems,
VIT is a record of bonafide work carried out by me under the supervision of M. Krishnasamy.

I further declare that the work reported in this thesis has not been submitted and will not be
submitted, either in part or in full, for the award of any other degree or diploma in this institute or
any other institute or university.

Place: Amaravati R Sravan Kumar

Date: 31-05-2024 Signature of the Candidate

CERTIFICATE
 This is to certify that Internship Project titled “MICROBLAZE PROCESSOR
BASED SERIAL COMMUNICATION SYSTEM” that is being submitted by R Sravan Kumar
(20BES7044) is in partial fulfilment of the requirements for the award of Bachelor of Technology, is a
record of bonafide work done under my guidance. The contents of this Project work, in full or in parts,
have neither been taken from any other source nor have been submitted to any other Institute or University
for award of any degree or diploma and the same is certified.

The thesis is satisfactory / unsatisfactory

Internal Examiner-1 Internal Examiner-2

Approved by

PROGRAM CHAIR DEAN

B. Tech. ECE School of Electronics Engineering
 ABSTRACT

In the world of electronics, communication between different devices is crucial. Data is sent
one bit at a time using serial transmission as one method of doing this. We frequently depend on
specialized processors, such as the MicroBlaze CPU, to accomplish this effectively. A soft
processor core that may be customized for certain uses, such as serial communication duties, is
the MicroBlaze processor. We will examine how the MicroBlaze processor enables serial
communication in this introduction, as well as the significance of this feature for tying together
different devices in the modern digital world. This project aims to making use of Microblaze
processor for serial communication in FPGA-based embedded systems, thereby facilitating the
development of versatile and robust communication solutions. The Microblaze soft processor, a
customizable and configurable IP core from Xilinx, offers flexibility and scalability for
integrating serial communication interfaces such as UART, SPI, I2C, and CAN into FPGA-
based designs. The paper discusses the architecture of the Microblaze processor and its
advantages in handling serial communication tasks. Furthermore, it examines various
applications where Microblaze-based serial communication proves beneficial, including
industrial automation, Internet of Things (IoT) devices, and real-time control systems.
Additionally, it highlights design considerations, challenges, and optimization techniques for
implementing efficient and reliable serial communication interfaces using Microblaze processor.
This abstract aims to provide insights into leveraging Microblaze processor for serial
communication in FPGA-based embedded systems, thereby facilitating the development of
versatile and robust communication solutions.

KeyWords: UART, SPI, I2C, IOT,CAN,FPGA-based-serialcommunication

i
 LIST OF CONTENTS

CONTENTS Page No:

ABSTARCT i

LIST OF FIGURES iv-v

CHAPTER 1: INTRODUCTION 1-2

1.1 HISTORY 6

CHAPTER 2: METHODOLOGY 7-10

2.1 HISTORY 7-8

2.2 EXISTING SYSTEM 9

2.3 PROPOSED SYSTEM 10

CHAPTER 3: LITERATURE SURVEY 11-12

CHAPTER 4:HARDWARE & SOFTWARE REQUIREMENTS 13-44

4.1 HARDWARE REQUIREMENTS

4.1 .1 KINTEX-7 (KC-705 EVALUATION BOARD) FPGA BOARD 13-17

4.1.2 J-TAG CONNECTOR 17

4.2 SOFTWARE REQUIREMENTS

4.2.1 XILINX VIVADO 18-22

4.2.2MICROBLAZE PROCESSOR 23-29

4.2.3 UART16550 29-34

4.2.4 AXI BUS ARCHITECTURE 34-44

CHAPTER 5: DESIGN AND IMPLEMENTATION 37-47

5.1 BLOCK DIAGRAM 45

5.2IMPLEMENTATION 46-55

5.2 RESULTS 56

ii
CHAPTER 6: ADVANTAGES & APPLICATIONS 57-59

6.1 ADVANTAGES 57

6.2 APPLICATIONS 59

CHAPTER 7: CONCLUSION 60

REFRENCES 61

iii
 LIST OF FIGURES
Fig No: NAME OF THE FIGURE Page
No:
4.1.1a KC-705 Evaluation Board 13

4.1.1b Parts in KC-705 Evaluation Board 14

4.1.2a J-Tag Connector 17

4.2.2a Microblaze Processor 24

4.2.2b Architecture of Microblaze Processor 26

4.2.3a Architecture of UART16550 30

4.2.3b Rx FIFO (data bits=8) 32

4.2.3c Transmit data fifo (data bits=8) 33

4.2.3d Control registers 33

4.2.3e Status registers 33

4.2.4a Flow of AXI bus architecture 35

4.2.4b AXI Channels 36

4.2.4c Hans-shake Mechanisam 38

iv
4.2.4d Transfer Process 39

4.2.4e Transaction Process 40

4.2.4f Transfer Example 41

5.1 Block Diagram of Project 45

5.2a Design Flow of Implementation 46

5.2b Block Design Dialogue Box 49

5.3 Result of Project 28

v
 CHAPTER 1

INTRODUCTION

1.1 HISTORY

Digital communication and embedded systems are the foundations of the MicroBlaze
processor-based serial communication system. Xilinx created the MicroBlaze processor, a
soft processor core, to be used with their FPGA devices.
Such systems have a long history, stemming from the growing need in embedded
applications for adaptable and scalable processing solutions. Performance and versatility
of traditional microcontrollers were frequently constrained, particularly when managing
intricate communication protocols like I2C (Integrated Digital Circuit), SPI (Serial
Peripheral Interface), and UART (Universal Asynchronous Receiver-Transmitter).
The development of FPGA technology provided a solution to these limitations by
allowing designers to implement custom hardware architectures tailored to specific
applications. Xilinx's introduction of the MicroBlaze soft processor core further extended
this flexibility by enabling the integration of a CPU within the FPGA fabric.
The use of MicroBlaze processors in serial communication systems allowed for the
implementation of various communication protocols alongside other application-specific
functionalities on the same FPGA device. This approach offered advantages such as
reduced component count, lower power consumption, and increased system integration.
The MicroBlaze processor-based serial communication system has been widely used
in a number of sectors over time, including consumer electronics, automotive, aerospace,
and industrial automation as well as telecommunications. Because of its adaptability and
programmability, it may be used in a variety of applications where dependable and
efficient serial communication is necessary. It's crucial to remember that the particular
development, history, and uses of MicroBlaze-based serial communication systems might
change dependent on the situation and the demands of certain projects or finished goods.

6
 CHAPTER-1

METHODOLOGY

2.1 HISTORY
Here's a methodology for developing a MicroBlaze processor-based serial
communication system:
1. Requirements Analysis:
- Identify the specific requirements for the serial communication system, including supported
protocols, data rates, interface compatibility, and performance constraints.

2. System Architecture Design:

- Describe the general architecture of the system, taking into account how the MicroBlaze
CPU is integrated into the FPGA fabric and the serial communication interfaces.
- Determine the peripheral interfaces required for UART, SPI, I2C, and any other
communication protocols needed.
- Allocate resources within the FPGA for the MicroBlaze processor, peripheral interfaces,
memory, and other system components.

3. MicroBlaze Configuration:
- Customize the MicroBlaze processor configuration based on the application requirements,
including the instruction set architecture (ISA), cache size, pipeline depth, and supported
peripherals.
- Configure the memory hierarchy, including instruction and data caches, on-chip memory,
and external memory interfaces.

4. Peripheral Interface Design:

- Create and put into use peripheral interfaces for SPI, I2C, UART, and other protocols.
- Verify that it is compatible with common communication protocols and take into account
any modifications needed for particular applications.

5. Software Development:
- Develop software drivers and application code to control the serial communication
peripherals and interface with other system components.
- Utilize development tools such as Xilinx Vivado SDK or GNU tools for compiling,
debugging, and deploying software onto the MicroBlaze processor.

6. Integration and Testing:

- Integrate the system's hardware and software onto the intended FPGA device.
- Perform functional testing to verify the correct operation of the serial
communication interfaces,data exchange, and system behavior under various
conditions.
- Conduct verification and validation activities to ensure compliance with requirements
and specifications.
7
7. Performance Optimization:
- Profile the system to identify performance bottlenecks and areas for optimization.
- Implement optimizations such as pipelining, parallel processing, and hardware
acceleration to improve system performance and efficiency.

8. Verification and Validation:

- Perform comprehensive validation and verification tests to guarantee the system's
accuracy, robustness, and dependability.
- Verify compliance with industry standards and protocols for serial communication.

9. Documentation and Maintenance:

- Document the system design, implementation details, test results, and
performance optimizations for future reference.
- Establish procedures for software maintenance, including version control, bug tracking,
and software updates.

10. Deployment:
- Deploy the MicroBlaze processor-based serial communication system into the
target application environment.
- Provide support and training for end-users, system integrators, and maintenance personnel.

By following this methodology, developers can systematically design, implement, and

deploy MicroBlaze processor-based serial communication systems tailored to specific
application requirements while ensuring performance, reliability, and scalability.

8
 2.2 EXISTING SYSTEM

Traditional Microcontroller-based Approach: The previous system might have

relied on traditional microcontroller units (MCUs) for processing tasks and managing
serial communication. MCUs have limited processing power and are often constrained in
terms of memory, peripherals, and flexibility. Implementing multiple communication
protocols and complex functionality may require additional external components,
increasing cost and complexity.
Fixed Functionality: The previous system may have been designed with fixed
functionality, with limited ability to adapt to changing requirements or support additional
features. Adding new communication protocols or upgrading existing functionality may
have been challenging and required hardware modifications.
Limited Performance and Scalability: Traditional microcontroller-based
systems may have been limited in terms of performance, especially when handling
multiple concurrent tasks or high-speed serial communication. Scaling the system to
accommodate future enhancements or increasing data rates may have been difficult or
impractical.
Development and Debugging Challenges: Developing software for traditional
microcontroller-based systems often involves using low-level programming languages and
proprietary development environments. Debugging and troubleshooting communication
issues or system faults may have been challenging due to limited visibility into system
internals.

9
2.3 PROPOSED SYSTEM

Flexible Processing Solution:The proposed system utilizes the MicroBlaze soft

processor core, providing flexibility and programmability for processing tasks within the
FPGA
fabric. MicroBlaze allows for customization of processor features, instruction set architecture,
and peripheral interfaces, tailored to the specific requirements of the application.

Integrated Solution with FPGA: By integrating the MicroBlaze processor within the
FPGA fabric, the proposed system offers a highly integrated solution, eliminating the need for
separate microcontroller units and external components. FPGA resources can be efficiently
utilized to implement custom hardware accelerators, peripheral interfaces, and
communication controllers alongside the processor core.

Support for Multiple Protocols and Functionality: The proposed system supports
various serial communication protocols such as UART, SPI, and I2C, along with other
application-specific functionalities. Adding support for additional protocols or features can be
achieved through software updates or reconfiguration of the FPGA, without requiring
hardware changes.

Improved Performance and Scalability: With the MicroBlaze processor's

processing power and FPGA's parallel processing capabilities, the proposed system offers
improved performance and scalability compared to traditional microcontroller-based
systems.The system can efficiently handle high-speed serial communication, real-time data
processing, and concurrent tasks with low latency and high throughput.

10
 CHAPTER 3
LITERATURE SURVEY

A literature survey of MicroBlaze processor-based serial communication systems

reveals a wealth of research and practical applications across various fields.
Research Papers: The design, implementation, and optimization of serial communication
systems based on the MicroBlaze processor are the subject of several academic
articles.Performance analysis, real-world applications, hardware/software co-design approaches,
and embedded system design based on FPGA are among the topics covered.Application Notes
and Technical Documentation: Xilinx, the creator of the MicroBlaze processor, provides
extensive technical documentation, application notes, and tutorials covering aspects of
MicroBlaze-based system design, including serial communication interfaces.These resources
offer practical guidance on integrating MicroBlaze processors with UART, SPI, I2C, and other
communication peripherals.
Conference Proceedings: Papers and talks on MicroBlaze processor-based systems,
including serial communication applications, are often included at academic and industrial
conferences. The most recent developments and case studies in this field are presented in
conference papers such as those from the IEEE International Conference on Field-Programmable
Technology (FPT), International Symposium on Field-Programmable Gate Arrays (FPGA), and
International Conference on Embedded Computer Systems (SAMOS).
Books and Tutorials: Books on FPGA-based embedded systems, digital design, and
real- time systems often include chapters or sections dedicated to MicroBlaze processor-based
designs.Online tutorials and educational resources provide step-by-step guidance on implementing
serial communication systems using MicroBlaze processors, targeting both beginners and
experienced developers.
Industry Case Studies: These case studies show how MicroBlaze processor-based serial
communication systems are used in a variety of industries, including industrial automation,
automotive, aerospace, and telecommunications. The benefits of utilizing MicroBlaze processors
for adaptable and scalable embedded system architectures are demonstrated by these case studies.
Theses and Dissertations: Graduate theses and dissertations contribute to the literature
by presenting in-depth analyses of specific aspects of MicroBlaze processor-based serial
communication systems.These works often include detailed design methodologies, performance
evaluations, and experimental results, offering valuable insights for researchers and
practitioners.

11
 Online Forums and Communities: Online forums, user groups, and community websites
provide platforms for discussions, knowledge sharing, and troubleshooting related to MicroBlaze
processor-based systems. Developers can seek advice, share experiences, and collaborate with
peers to address challenges and explore new opportunities in serial communication system
design.

By surveying the literature on MicroBlaze processor-based serial communication systems,

researchers, engineers, and enthusiasts can gain a comprehensive understanding of the state-of-
the-art techniques, best practices, and emerging trends in this exciting field.

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 CHAPTER-4
HARDWARE & SOFTWARE REQUIREMENTS
4.1 HARDWARE
a. Kintex-7 (kc-705 evaluation board)
b. J-Tag cable
c. Serial communication connector
4.2 SOFTWARE
a. Xilinxs Vivado
b. Microblaze Processor
c. Uart Lite
4.1.1 Kintex-7 (kc-705 evaluation board)

A versatile foundation for developing higher-level systems requiring DDR3,

Gigabit Ethernet, PCI Express, and other serial interfaces is offered by the Kintex-7
FPGA KC705 Evaluation Kit. Industry-standard FMC connections that are
integrated and accept a wide range of current cards make scalability and
customisation easier and startup times faster. Designers can investigate AMS
technology and discover how the feature can save BOM costs by using the AMS
header. The range of advanced capabilities that may be assessed and utilized from
this platform is further expanded by additional communications characteristics, such
as SFP+, SMA connections, and high-speed GTX transceivers.

13
Fig 4.1.1a Kc-705 evaluation board

14
Key Features & Benefits

• Designed to use Kintex 7 FPGAs for fast prototyping of high performance serial
transceiver applications.
• Pre-verified reference designs, design tools, hardware, and intellectual property
• Showcases an end-to-end PCIe setup with either eight lanes at a 2.5 Gb/s connection
rate (Gen1) or four lanes at a 5 Gb/s link rate.
• Using PCIe Gen2x4, SFP+ and SMA Pairs, UART, IIC, and an advanced memory
interface with 1GB DDR3 SODIM Memory to provide serial communication
• Allows for embedded processing using soft 32-bit RISC MicroBlaze
• Create video display applications using HDMI out; • Create networking applications
using 10-100-1000 Mbps Ethernet (GMII, RGMII, and SGMII); • Extend I/O using the
FPGA Mezzanine Card (FMC) interface;

Fig.4.1.1b Parts inkc-705 evaluation board

15
Clocking

• Fixed oscillator with output differential of 200 MHz

• Serves as the FPGA's "system" clock
• Programmable oscillator with a preset output frequency of 156.250 MHz
• The oscillator may be programmed for a variety of end uses, although its default
frequency is intended for Ethernet applications.
• Input of differential SMA clock
• Input of varying SMA GTX reference clock
• Attenuated clock with jitters
• Supported CPRI/OBSAI applications that use user-supplied SFP/SFP+ modules and
utilize them to restore clocks.
Expansion Connectors

• The FMC-HPC (Partial Population) connection supports four GTX transceivers and
116 single-ended or 58 differential user-defined signals (34 LA & 24 HA).
• One GTX transceiver, 68 single-ended or 34 differential user-defined signals, and an
FMC-LPC connection
• Vadj is compatible with 1.8V, 2.5V, and 3.3V.
• IIC
Configuration

 Onboard JTAG configuration circuitry to enable configuration over USB

 JTAG header provided for use with AMD download cables such as the Platform Cable USB II

 128MB (1024Mb) Linear BPI Flash for PCIe® Configuration.

16
 16MB (128Mb) Quad SPI Flash

Communication & Networking

 Gigabit Ethernet GMII, RGMII and SGMII

 SFP / SFP+ cage

 GTX port (TX, RX) with four SMA connectors

 UART To USB Bridge

 PCI Express x8 edge connector

Control & I/O

 5X Push Buttons

 4X DIP Switches

 Diff Pair I/O (1 SMA pair)

 AMS FAN Header (2 I/O)

 7 I/O pins available through LCD header

Memory

 1GB DDR3 SODIMM 800MHz / 1600Mbps

 128MB (1024Mb) Linear BPI Flash for PCIe® Configuration

 16MB (128Mb) Quad SPI Flash

 8Kb IIC EEPROM

 SD Card Slot
17
Display

 HDMI Video output

 External Phy/codec device driving an HDMI Connector

 2x16 LCD display

 8x LEDs

Power

 12V wall adapter or ATX

 Voltage and Current measurement capability of 2.5V, 1.5V, and 1.2V, 1.0V supplies (IIC path
to FPGA) etc…

4.1.2 J-tag connector

JTAG tests the hardware interconnects between many integrated circuits using a boundary-scan
technique.
Reading connection pin values is part of the JTAG system's functionality testing process.

Fig 4.1.2a J-Tag connector

To connect with a JTAG interface device, a JTAG TAP requires only four or five pins to
work. Although there isn't a standard JTAG connector, it has to be a standard male header, such
the TI JTAG 14, ARM JTAG 20, and ARM JTAG 20. The Segger J-Link and J-Trace
connections are comparable to the ARM JTAG 20 and can be used in its place.

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4.2.1 Xilinxs Vivado
The design program for AMD adaptive SoCs and FPGAs is called Vivado. Design
Entry, Synthesis, Place and Route, and Verification/Simulation Tools are among its
features.Design entry in conventional HDL, such as Verilog and VHDL, is supported by
Vivado. Additionally, it supports the IP Integrator (IPI), a graphical user interface-based
tool that enables a Plug-and-play IP Integration Design Environment. With integrated
timing closure and methodological capabilities, the Vivado ML Edition offers the greatest
synthesis and implementation available for today's sophisticated FPGAs and SOCs. The
report on UltraFast methodology (report_methodology), which can be found in Vivado's
default flow, assists users in limiting their design, analyzing outcomes, and closing time.

Features

a. Ip Integrator

With its IP Integrator feature, the VivadoTM ML Edition breaks through the RTL
design productivity plateau by offering the first plug-and-play IP integration design
environment in the market.A graphical and Tcl-based correct-by-construction design
development approach is offered by Vivado IP Integrator. In addition to a robust
debugging capabilities, it offers an interactive environment that is aware of devices and
platforms and allows intelligent auto-connection of critical IP interfaces, one-click IP
subsystem development, real-time DRCs, and interface change propagation.When
connecting IP, designers operate at the "interface" level of abstraction rather than the
"signal" level, which significantly boosts productivity.. Often times this is using industry
standard AXI4 interfaces, but dozens of other interfaces are also supported by IP
integrator.Working at the interface level, design teams can rapidly assemble complex systems that
leverages IP created with Vitis HLS, Model Composer, AMD SmartCore™ and LogiCORE™ IP,
Alliance Member IP as well as your own IP. By leveraging the combination of Vivado IPI and
HLS customers are saving up to 15X in development costs versus an RTL approach.

19
Key Features of Ip Integrator
i. Tight integration within the Vivado Integrated Design Environment

• The overall design's seamless integration of IP Integrator's hierarchical subsystems

• Quickly capturing and repurposing IP Integrator designs

• Assistance with Tcl-based and graphical design flows

• Cross-probing between several design perspectives and rapid simulation

ii. Support for all design domains

• Assistance with CPU-based or processor-less designs

• Combining RTL-level IP with algorithms (Model Composer and Vitis HLS).

• Logic, DSP, video, analog, embedded, and networking combined

• Assistance with project-based DFX Flow

iii. Focus on Designer Productivity

• DRCs on intricate connections at the interface level during design assembly

• Identifying and fixing typical design flaws

• IP parameter propagation to linked IP addresses automatically

• Optimizations at the system level

• Automated support for designers

iv. Enhanced Collaboration Support

• Modular and reusable designs are made possible by team-based designs that use Block
Design Container.
• Improvements to revision control that distinguish source files from produced ones
• To compare two Block Designs, use the Block Design Diff tool.

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 b. Logic Synthesis
With the aid of Vivado logic synthesis, hardware designers may create bespoke designs,
IP, and ideal platforms that cater to all the newest AMD products. Register Transfer Level
(RTL) designs defined in System Verilog, VHDL, and Verilog are translated into a
synthesized netlist of library cells for later implementation through the process of logic
synthesis. Synthesis, knowing the target technology, may deduce functions from RTL
specifications that translate to specific silicon structures such as DSP blocks, shift
registers, LUTRAMs, and Block RAMs. To achieve design objectives, synthesis outputs
are guided by Xilinx Design Constraints (XDC), tool choices, and characteristics. Logic
synthesis is compatible with TCL scripting and Vivado Projects. It serves as a strong basis
for other high-level design techniques that provide RTL descriptions, such as IP integrator
and High-Level Synthesis. Machine Learning has been incorporated using logic synthesis
to aid in compilation speed. Through the prediction of the synthesis optimizations required
for various design components, machine learning models increase overall efficiency.

Key Features of Logic Synthesis

i. Language Support:-
The most recent synthesizable constructions that adhere to industry standards are supported by
logic synthesis:

• Hardware Description Languages (HDLs): SystemVerilog, Verilog, VHDL, and VHDL-2008

• The capacity to combine many HDL types into a single design and provide each type with its
own parameters and generics.
• Language templates to guarantee accurate mappings between appropriate device resources and
inferred complicated functions

Through an expanded design schematic that cross-references to the relevant HDL source code,
HDL descriptions may be visually examined.
ii. Optimization Control:-

 You have complete control over inference and optimization using logic synthesis.Assignments
are possible.

• Using tool and command options globally

Using the BLOCK_SYNTH XDC constraint, on certain modules or instances of logical

20
 hierarchy; on cells and nets; and on HDL properties
iii. Types of control include:-

• Maintaining, reducing, and reestablishing hierarchy

• Determining whether to infer structures particular to a certain technology

• Deciding on the kind of memory resources that are specifically allocated to mapping
memory arrays

• Choosing the encoding type for FSMs, or finite state machines

• Giving performance, use, or power priority

• Using sophisticated optimization techniques like logical retiming

• Converting register enable signals from gated clocks

C. Design Methodology

Applied in conjunction with Vivado, the UltraFast technique facilitates appropriate constraint
definition, facilitates appropriate tool driving and result analysis, and enhances overall
productivity. With many years of experience, Vivado professionals have amassed a set of best
practices for hardware design, which they have combined into the UltraFast Design
Methodology. This methodology has helped them successfully close designs that push the
boundaries of technology and tools for their customers.With Ultra Fast Methodology Reports
integrated into Vivado and created automatically for Vivado projects, compliance with the
UltraFast Methodology rules is made easier. This allows users to take advantage of UltraFast
without ever having to read a single paper. For interactive evaluation, the Report
Methodology function provides a list of methodology breaches detected in the current design,
categorized and ranked according to severity. The best possible start point for implementation
of designs is provided by reviewing and resolving methodological violations, which increases
the likelihood of effective design closure in the least period of time. In order to prevent them
from showing up in reports again, violations that are judged acceptable may be waived.
Providing accurate and comprehensive constraints is a key component of the UltraFast
Methodology. Timing constraints are analyzed by the Timing Constraints Wizard (TCW),
which also offers detailed instructions on how to add missing constraints and correct
erroneous constraints. While faulty constraints might cause compilation effort to be
misdirected toward bogus timing criticality, constraint completeness lowers the likelihood of
hardware defects originating from uncontrolled timing routes. Accurate power analysis
depends on the quality of the power constraint. The Power Constraints Advisor produces
turnkey XDC power constraints for appropriate analysis, evaluates design switching activity,
and identifies regions that seem to be inadequately stated. A confidence level that indicates a
low, medium, or high quality of power constraint definition is also included in Vivado power
21
 reports. This provides feedback on the completeness of the power constraint. The most
accurate power analysis, closely matching hardware data, is ensured by a high confidence
level.

D. Implementation

AMD device placement and routing is handled by the Vivado implementation, which
creates bitstreams and device images from a synthesized netlist. From the tiniest MPSoCs to the
biggest monolithic and Stacked Silicon Interconnect Technology (SSIT) devices with millions of
logic cells, implementation allows the construction of platforms and unique designs of all sizes.
Modern segmentation, placement, and routing algorithms powered by predictors based on
machine learning underpin the Vivado implementation. By using machine learning (ML)
models, implementations may forecast routing delays and congestion with accuracy and achieve
greater Quality-of-Results (QoR) faster. To achieve design objectives for performance,
utilization, and power, implementation is guided by Xilinx Design Constraints (XDC), and
synthesis is done using Tcl scripting and Vivado Projects.

From the simple pushbutton mode for simplicity of use to complex customized Tcl recipes for
handling designs with the highest performance requirements, implementation supports all modes
of operation. It is possible to do a thorough study of time, usage, power, and other design quality
metrics at any compilation step, including post-placement, post-routing, and pre-placement.
Using design checkpoint (DCP) files, the design database may also be saved and restored at any
point throughout the compilation process, allowing the design to be restricted and displayed
appropriately.

22
4.2.2 Microblaze Processor
A soft microprocessor, or a microprocessor core entirely realized by logic synthesis, as
described by the MicroBlaze IP. You may use this type of microprocessor to develop C or C++ code
to execute some little applications on your Xilinx FPGA. Naturally, you may instantiate many
instances of MicroBlaze on your design, allowing you to parallelize your system with multiple
applications (FPGA size allowed).The MicroBlaze has several user-configurable features, including
memory management unit, bus interfaces, integrated peripherals, pipeline depth (3-, 5-, or 8-stage),
cache size, and more. The three-stage pipeline used in the area-optimized version of MicroBlaze
compromises clock frequency in favor of a smaller logic area. With the Virtex UltraScale+ FPGA
family, the performance-optimized version enables high speeds of over 700 MHz by extending the
execution pipeline to five stages. Important processor instructions, such as multiply, divide, and
floating point operations, can also be added or removed selectively. These instructions are less often
utilized but more costly to implement in hardware. Because of this adaptability, a developer may
choose the right architectural trade-offs for a given combination of host hardware and application
software needs.MicroBlaze can host operating systems like the Linux kernel that need hardware-
based paging and protection thanks to the memory management unit. If not, it is restricted to
operating systems like FreeRTOS or Linux that do not support MMUs and have a more
straightforward virtual memory and protection paradigm. Overall throughput for MicroBlaze is
significantly lower than that of a similar hard CPU core (such the ARM Cortex-A9 in the
Zynq).Based on the RISC-V architecture is MicroBlaze V.

32-bit RISC processor includes the following features:

• A collection of orthogonal instructions

• 32 general-purpose registers with a bit length of 32

• Harvard architecture employs separate busses for data and instructions.

• Virtex-II and subsequent devices allow hardware multiplication through built-in interfaces to
IBM's industry-standard On-chip Peripheral Bus (OPB) and fast on-chip memory.

• A complete 32-bit barrel shifter is optional.

23
Key Capabilities of Microblaze Processor

Three Different Configurations:

• Real-time processor: Ensures deterministic real-time processing on an RTOS

• Application processor: Able to run embedded Linux
• Microcontroller: Perfect for executing bare-metal code

Advanced Features:

• Provides customization with more than 70 user configuration options and a list of
peripherals that can be dropped and dragged, including Ethernet subsystems, USB 2.0,
UARTs, and streaming FIFOs.
• Has sophisticated features such as an extensible address bus up to 64 bits, multi-purpose
registers, and a 32-bit instruction set.
• Provides safety for important applications with triple modular redundancy (TMR) and
dual-core lockstep capabilities; optional floating-point unit and power management modes
(sleep, hibernation, and suspend operations) are also included.

High Degree of Design Flexibility:

• Provides a completely integrated design process with the VitisTM and Vivado tools.
• Works with any FPGA or AMD adaptive SoC that the Vivado or IDS design tools support.
• A five-stage pipeline for optimum performance and a three-stage pipeline for the ideal footprint.

Fig 4.2.2a Microblaze Processor

1. Interrupt (Interrupt Request):

External devices or peripherals utilize the interrupt signal to ask the MicroBlaze CPU for
attention. When an interrupt happens, the processor switches to an interrupt service routine (ISR)
to manage the interruption, momentarily stopping the execution of the current program.Handling
events that need to be addressed right away, such time-sensitive jobs or real-time input/output
procedures, calls for the use of interrupts.

24
2. Debug (Debug Request):

The debug signal is primarily used for debugging purposes. It allows external
debuggers, such as JTAG-based debuggers, to halt the MicroBlaze processor and inspect its
internal state, memory contents, and register values.Debugging aids in identifying and fixing
software bugs, optimizing code performance, and understanding system behavior during
runtime.

3. CLK (Clock):

The clock signal is fundamental for the operation of the MicroBlaze processor. It
synchronizes all internal operations, including instruction execution, data processing, and
memory access. The clock signal's frequency controls the processor's operating speed. Higher
clock frequencies generally result in faster processing but may also lead to increased power
consumption and heat generation.

4. Reset:

The reset signal initializes the MicroBlaze processor to a known state when the system
is powered on or reset. It clears the processor's internal registers, resets the program counter, and
initializes control signals. Reset ensures that the processor starts execution from a predictable
state, allowing for consistent behavior during system startup.

5. DLMB (Data Local Memory Bus):

DLMB is part of the memory hierarchy in the MicroBlaze processor and is used for accessing
the data cache, if enabled. To boost efficiency and lower memory access latency, frequently
accessed material is stored in the data cache.The DLMB signal facilitates loading data into the
data cache from memory (during cache misses) and storing data back to memory (upon cache
eviction or write-back).

6. ILMB (Instruction Local Memory Bus):

ILMB is another component of the memory hierarchy and is used for accessing the
instruction cache, if enabled. The instruction cache stores frequently executed
instructions, improving program execution speed by reducing fetch latency .ILMB enables
fetching instructions from the instruction cache for execution by the processor's execution
units.

7. M_AXI_DP (Master AXI Data Port):

Acting as a master for data transfers, M_AXI_DP is the interface between the MicroBlaze CPU
25
and the AXI bus. In many FPGA-based systems, AXI is a commonly utilized high-performance,
high-frequency connection standard.

This signal enables data transfers between the MicroBlaze CPU and additional peripherals,
memory modules, or IP cores linked to the AXI bus. The CPU can effectively communicate with
peripherals or access external memory thanks to its read and write transaction capability.

Together, these signals allow the MicroBlaze processor to perform various tasks like as
calculation, memory access, interrupt management, debugging, and peripheral or external device
interface within a wider system architecture. Every signal is essential to the system's general
functioning and the processor's performance.

Fig 4.2.2b Architecture of Microblaze Processor

PROGRAM COUNTER:

A register known as the program counter (PC) stores the memory location of
the subsequent instruction that will be carried out.

INSTRUCTION BUFFER:

Instruction buffer is a component responsible for temporarily storing fetched

instructions before they are decoded and executed. It acts as a queue where
instructions are held until the processor is ready to process them.
26
INSTRUCTION DECODE:
The act of deciphering fetched instructions from memory and ascertaining the operation
they represent is known as instruction decoding.
REGISTER FILE:
A register file is a group of registers that are used to temporarily store data while a
program is running. 32 general purpose registers (R0, R1, R2,...) exist.R31 is utilized for logical
and mathematical processes as well as data storage.
Input Output Peripheral Base:
It is a special purpose register used to specify the base address of the Input/Output (I/O)
peripherals. It knows where to access and communicate with these I/O peripherals, allowing the
software to control and interact with external devices.

ILMB (Instruction Local Memory Block):

It refers to a memory block dedicated to storing instructions in a cache-like structure. ILMB
is typically used to improve instruction fetch performance by providing faster access to
frequently used instructions.

DLMB (Data Local Memory Block):

It refers to a memory block dedicated to storing data in a cache-like structure. DLMB is
typically used to improve data access performance by providing faster access to frequently used
data.

Microblaze Features:-

The following are some of Microblaze's characteristics. 32 general purpose registers are
present.
• It contains three operands and two addressing modes among its 32-bit instruction
words.
• A 32-bit address bus is used.
• The pipeline is either three or five stages long.
• A block unit ALU equipped with a shifter.
• The Harvard design uses an address bus and 32-bit data.
• Instructions for the local memory bus and data interface.
• The stream interfaces for AX14 and AX14.
• Memory management and floating point units.
• Lockstep is supported.
• Trace and debug the interface.
Standard Bus Interconnects

The LMB (Local Memory Bus) interface for local memory and the IBM On-chip
Peripheral Bus interface are two of the bus interfaces on the instruction and data sides.
Alternatively, we may use a single OPB in tandem with a bus arbiter to distribute resources if

27
 we want to create systems that adhere closely to Harvard architecture.

For on-chip block RAM, the local memory bus ensures a single-cycle entry. This
single-master bus protocol is incredibly effective and straightforward, making it ideal for
connecting rapid local memory. Connecting peripherals and external memory to the
MicroBlaze CPU core is a natural use for the 32-bit wide multi-master bus known as the On-
chip Peripheral Bus, or OPB.

On-chip Peripheral Bus Peripherals

OPB peripherals complete the MicroBlaze hardware system by offering various
functions e.g., UART Lite, SPI, I2C, General purpose I/O, UART 16450/550, Ethernet
10/100 MAC, Watchdog Timer or Timebase, General purpose Timer or Counters, IC
(Interrupt Controller), and various controllers. Furthermore, peripherals can be added and
defined, mostly for bespoke functions or as an interface to an existing FPGA design.
Microblaze Instruction Set

The instruction sets for Microblaze include logic, branching, load/store, and arithmetic. Every
instruction set has a set size. Operands can be supplied at most three registers. The two
instruction forms that Microblaze offers are Type A and Type B, which are displayed below.

Register-register instructions are the primary use case for type A instruction format. Thus, it
has two source registers, one destination register, and the opcode. The opcode, single
destination, and single source registers are examples of register-immediate instructions that
are often written in type B instruction format.& an instantaneous 16-bit value source.

Instruction Formats

The opcode, which is an operation code, is represented by the 5-bit encoded destination
register Rd, the 5-bit encoded source registers Ra and Rb, and the 16-bit value Immediate in
the two instruction forms mentioned above.

Registers
The MicroBlaze processor's design, which consists of 32-bit special purpose registers like the
Program Counter and Machine Status Register as well as 32-bit general purpose registers, is
entirely orthogonal.

28
Pipeline Architecture

The three steps of the pipeline architecture used by MicroBlaze are fetch, decode, and
complete. The hardware determines the data forwarding, branching, and pipeline stall
automatically.

Load or Store Architecture

Three different data sizes for memory are supported by MicroBlaze: 8 bits (byte), 16
bits (halfword), and 32 bits (word). Memory accesses are therefore always data-size
aligned. This CPU is Big-Endian, meaning that when it accesses memory, it employs
both the Big-Endian address and labeling protocols.

Interrupts
When an interrupt occurs, this processor will halt current operations in order to handle
the interrupt request by branching to the interrupt vector location and storing the
address of the instruction that has to be carried out. By removing the IE (Interrupt
Enable) flag from the MSR (Machine Status Register), this processor will put an end to
subsequent interruptions.

4.2.3 AXI UART 16550 Interface

The Advanced Microcontroller Bus Architecture (AMBA) specification's Advanced

eXtensible Interface (AXI) is connected to the AXI Universal Asynchronous Receiver
Transmitter (UART) Lite interface, which serves as the controller interface for
asynchronous serial data transmission.

The Universal Asynchronous Receiver/Transmitter (UART) peripheral, which is often

used in digital systems, has been streamlined into the UART16550. Field-
Programmable Gate Arrays (FPGAs) and other programmable logic devices frequently
contain it.
UART16550 typically supports basic serial communication functionalities, allowing data
transmission between a device and a computer or between different devices. It's commonly used
for debugging, communication between embedded systems, and interfacing with peripheral
devices. The UART 16550 is a popular type of Universal Asynchronous Receiver/Transmitter
(UART) chip used for serial communication in computers and embedded systems.

It's known for its standardization, reliability, and compatibility with older systems. The
16550 features a 16-byte FIFO buffer to improve performance and reduce the risk of data loss
during high-speed communication. It's widely used in various devices for serial
29
communication tasks like connecting peripherals, networking equipment, and communication
interfaces.

30
 It's often used in resource-constrained environments such as Field-Programmable Gate Arrays
(FPGAs) or embedded systems where minimizing hardware resources is crucial.

Fig 4.2.3a Architecture of UART16550 Lite

° Rx Control: This block writes received data to the Receive Data FIFO after sampling it
according to the produced baud rate.

° Tx Control: This block uses the UART Tx interface to send data out after reading it from the
Transmit Data FIFO.

° BRG (Baud Rate Generator) - You may program this block to create different baud rates.

° Interrupt Control: The interrupt enable/disable control is provided by the AXI UART Lite core.
When either the transmit or receive FIFOs are empty, or when interrupts are enabled, a rising-
edge sensitive interrupt is triggered.

Clock Generation and Control

An input clock to the UART is the source of the UART bit clock. Check the handbook specific to
your device to find out the highest data rate that the UART can handle.

• Capable of sending and receiving characters in bits: 8, 7, 6, or 5; one stop bit; odd, even, or no
parity bit. The AXI UART Lite has separate transmit and receive capabilities.

• When either the transmit or receive FIFOs are empty, a rising-edge sensitive interrupt is
generated. An interrupt can be used to hide this interruption.

Turn on or off the signal. In addition to independent 16-character deep transmit and receive
FIFOs, the device has a baud rate generator.
30
Pin Description :-

Below table shows pin description of UART 16550

° An empty receive data FIFO receives a read request. ° When the transmit data FIFO is filled, a
write request is made. The response for all other queries is OKAY. DECERR is never generated
by the AXI UART Lite.

31
Registers:-

UART 16550 registers and their addresses

RX FIFO:-

The AXI UART Lite core receives data into this 16-entry-deep FIFO. Table 2-5 displays the
meanings of the FIFO bits. An empty FIFO will result in an undefined bus error (SLVERR) when
a read request is sent to it. It is a read-only register, the RX FIFO. There is no consequence to
sending a write request to this register.

Fig 4.3.3b Rx FIFO (Data Bits = 8)

TX FIFO :-

The data that the AXI UART Lite core will produce is stored in this 16-entry-deep FIFO. The
figure below displays the definitions of the FIFO bits. This register is written with the data that
will be transferred. A bus error (SLVERR) is raised and the data is not stored into the FIFO when
a write request is made while the FIFO is full. This place can only be written to. The read
acknowledgment is generated with zero data when a read request is sent to the transmit data FIFO.

32
 Fig 4.3.3c Transmit Data FIFO (Data Bits = 8)

Control Register (CTRL_REG) :-

The reset pin and enable interrupt bit for the transmit and receive data FIFO are located in the
control register. This register can only be written to. The read acknowledgment is generated with
zero data when a read request is sent to the control register.

Fig 4.3.3d Control Register

Status Register (STAT_REG):-

When faults are present and interruptions are enabled, the receive and transmit data FIFOs'
statuses are recorded in the status register. This registration can only be read. It has no impact if
you write to this register.
.

Fig 4.3.3f Status Register

33
Clocking:-

On s_axi_aclk, the AXI UART Lite core functions.

Resets:-

When the s_axi_aresetn signal is asserted, the AXI UART Lite core resets. This is a synchronous
active-low reset to s_axi_aclk.
AXI CLK Frequency:-

System clock frequency that powers the AXI UART Lite peripheral (measured in MHz). Note:
When using IP Integrator, the AXI CLK Frequency parameter is predetermined.
Baud Rate:-

The AXI UART Lite core's bit-per-second baud rate. The following rates are supported by the
core: Note: Based on the AXI clock frequency, the GUI accounts for tolerance, enabling the
setting of only legitimate baud rate numbers.

Data Bits.:-

the serial frame's bit count of data. Supported bits by the core are 5, 6, 7, and 8.

. Parity:-

decides whether or not parity is applied. Whether parity is even or odd, if applied.

4.2.4 AXI Bus Architecture

A popular standard for linking IP (Intellectual Property) blocks in intricate digital systems,
especially in FPGA (Field-Programmable Gate Array) designs, is the AXI (Advanced eXtensible
Interface) bus architecture. In a system-on-chip (SoC) or FPGA architecture, it offers a high-
performance and adaptable communication infrastructure for data transmission between various
components.

Rather than defining the interface of an interconnect, AXI is an interface definition that specifies
the interface of IP blocks. How AXI is utilized to interface an interconnect component is depicted
in the following diagram:

34
 Fig 4.3.4a Flow of AXI bus architecture

There are just two AXI interface types in AX3 and AXI4: slave and master. There is symmetry in
these interface types. There are master interfaces and slave interfaces on both ends of every AXI
connection. Since the signals in AXI interconnect interfaces are the same, integrating various IP is
not too difficult. The master and slave interfaces are connected using AXI connections, as seen in
the preceding diagram. Without additional logic, the direct connection provides the greatest
bandwidth between the slave and master components. Additionally, there is just one protocol to
validate when using AXI.
AXI channels

A point-to-point protocol between two interfaces—a slave and a master—is described in the AXI
standard.
The five primary communication channels that each AXI interface employs are depicted in the
following diagram:

35
 Fig 4.3.4b AXI Channels

Write operations use the following channels:

• The slave receives data from the master via the Write Data (W) channel and an address from the
master via the Write Address (AW) channel.
•The received data is written by the slave to the designated address. The slave replies to the master
on the Write Response (B) channel with a message after completing the write operation.

Read operations use the following channels:

• Using the Read Address (AR) channel, the master transmits the address it wishes to read.

• Using the Read Data (R) channel, the slave transmits the desired address's data to the master. On
the Read Data (R) channel, the slave may further provide an error message. Errors might arise due
to several reasons such as invalid addresses, damaged data, or improper security permissions for
access.
Since each channel is unidirectional, replies must be sent back to the master over a different Write
Response channel. But since a read response is sent as part of the read data channel, a read
response channel is not required.

Each of these five channels contains several signals, and all these signals in each channel
have the prefix as follows:

36
• AW for Write Address channel signals

• AR for Read Address channel signals

• W stands for Write Data channel signals.

• R for the Read Data channel signals

• B for Write Response channel signals

Main AXI features

As you can see below, the AXI protocol contains a number of important characteristics that are
intended to reduce transaction delay and increase bandwidth:
separate channels for reading and writing:

One set of channels is supported by AXI for writing operations, and another for read operations.
The bandwidth performances of the interfaces are enhanced by having two separate sets of
channels. This is due to the simultaneous nature of read and write operations.

Multiple outstanding addresses:-

Multiple outstanding addresses are supported by AXI. As a result, a master can start new
transactions without having to wait for older ones to finish. The capability to execute transactions
in parallel is one way that this might enhance system performance. There is no precise time
correlation between data activities and addresses. There is no precise temporal link between
address and data operations when using AXI:

This implies that a master may, for instance, provide a write address on the Write Address
channel; but, the master is not constrained in terms of time when it must supply the associated
data in order to write on the Write Data channel.

Support for unaligned data transfers:-

The initial bytes read in any burst that consists of data transfers larger than one byte may not line
up with the natural address boundary. Consider a 32-bit data

A transmission beginning at byte address 0x1002 is not aligned with the 32-bit address barrier by
default.

Out-of-order transaction:-

fulfillment With AXI, transactions can be completed out of sequence. Transaction IDs are part of
the AXI protocol, thus completing transactions with varied ID values is not restricted.
37
Burst transactions based on start address:-

The beginning address is only provided by AXI masters for the initial transfer. The slave will use
the burst type to determine the next transfer address for any further transfers.
Channel handshake

As outlined in AXI channels, the AXI4 protocol defines five distinct channels. The VALID and
READY signals serve as the foundation for the identical handshake procedure that is shared by all
of these channels, as the graphic below illustrates:

Fig 4.3.4c Hand-Shake Mechanism

The source sends the READY signal to the destination, and the destination sends the VALID
signal to the source.
The channel being utilized determines whether the source or destination is a master or slave. The
master, for instance, is a destination for the Read Data channel but a source for the Read Address
channel.
When valid information is available, the source indicates this by sending out the VALID signal.
Up until the destination accepts the data, the VALID signal has to stay asserted, or set to high.
Sticky signals are those that maintain their assertiveness in this manner. Using the READY
signal, the destination announces when it is ready to receive data.

From the channel source to the channel destination, the READY signal travels. This technique is
not asynchronous; in order for the handshake to be completed, the clock's rising edge must occur.
You need to be aware of the capabilities of the slaves and masters you are connecting while
constructing interconnect fabric. Acquiring this knowledge enables you to incorporate adequate
buffering, tracking, and decoding logic to accommodate the many data transfer ordering options
that provide enhanced performance on faster devices. It is simpler to comprehend the interactions
between linked components when consistent language is used. AXI distinguishes between
transactions and transfers.
• A transfer consists of a single information exchange and a single, READY, and VALID
handshake. This transfer is depicted in the diagram below:

38
 Fig 4.3.4d Transfer Process

An address transfer, one or more data transfers, and, in the case of write sequences, a response
transmission are all included in a transaction. The transaction is depicted in the diagram below.

39
 Fig 4.3.4e Transaction Process

Channel transfer examples

1. Examples of potential handshakes between the source and the destination are looked at in this
section.
It displays many VALID and READY sequence combinations that meet the requirements of the
AXI protocol. In the first scenario, which is depicted in the image below, the VALID and
READY signals come first, then an information bus:
The events in this case go as follows:

1. The legitimate signal, which indicates that the data on the information channel is legitimate,
is asserted in clock cycle 2.

2. The READY signal is asserted in clock cycle 3, which is the next clock cycle.

3. Because both the READY and VALID signals are asserted, the handshake concludes on the
rising edge of clock cycle 4. .
40
 Fig 4.2.4f Channel transfer examples

Write channel signals

The channels used for a write transaction are:

• Write Address

• Write Data

• Write Response

The following table shows the Write Address channel signals:

41
The following table shows the Write Data channel signals:

The following table shows the Write Response channel signals:

• Every channel's signals share the same prefix:

• Write Address Channel (AW)

• W is the channel for writing data.

• B is the channel for writing responses. Regarding the write channels, the AXI4 protocol and
the AXI3 protocol differ in the following ways:
• The AWLEN signal for the AXI4 protocol is broader for the write address channel.

42
.

43
As a result, AXI4 may produce bursts that last longer than AXI3.

As locked transfers are not supported, AXI4 lowers the AWLOCK signal to a single bit in order
to solely allow exclusive transfers.
• The AWQOS signal is added to the AW channel by AXI4. The AXI4 protocol's quality of
service (QoS) idea is supported by this signal. • The AWREGION signal is added to the AW
channel by AXI4. Slave regions, which enable several logical interfaces from a single physical
slave interface, are supported by this signal.
• The WID signal is eliminated from the W channel by AXI4. This is a result of the removal of
the write data reordering feature.
• User-defined signals are added to each channel via AXI4.

Read channel signals

The channels used for a read transaction are:

• Read Address

• Read Data

The following table shows the Read Address channel signals:

44
The following table shows the Read Data channel signals:

Every channel's signals share the same prefix:

• AR for the channel that reads addresses

R stands for Read Data Channel. Regarding the read channels, the AXI4 protocol and the AXI3
protocol differ in the following ways:
• The read address length signal ARLEN is broader for the AXI4 protocol. As a result, AXI4 may
produce read bursts that are longer than those of AXI3.
Locked transfers are not supported, hence AXI4 lowers the ARLOCK signal to a single bit in
order to solely allow exclusive transfers.The ideas of slave regions and quality of service also
apply to read transactions, just as they do to write channel signals. These make use of the AR
channel's ARREGION and ARQOS signals.
• User-defined signals are added to the two read channels by AXI4.

45
 CHAPTER 5
DESIGN & IMPLEMENTATION

5.1 BLOCK DIAGRAM

Figure 5.1: Block Diagram of the Project

46
5.2 IMPLEMENTATION

Design flow
Design

Simulation

Create HDL Wrapper

ADD Constrains (Optional)

Generate Bit Stream

(Run Synthesis + Implementation)

Launch Hardware SDK Program on

FPGA Make connection between FPGA board &

Laptop /PC through Serial Connector

Open Hard Ware Manager

Select Program Target

Verify The Output in Teraterm/

CRO

Fig 5.2a Design Flow of Implementation

47
Terms Related To Designing And Implementing A System Using A Microblaze Processor:

1. Design: Refers to the creation of the overall architecture, components, and connections of a
system. In this context, it involves designing a system that includes a MicroBlaze processor
for serial communication.

2. Simulation: involves predicting the behavior of a system by running a model of it instead of

creating it physically. This aids in spotting any problems and improving the design before going
live.

3. Run synthesis: The process of converting a high-level design description into a hardware-
implementable gate-level representation is called synthesis. To run synthesis is to carry out
this procedure.

4. Generate bit stream: Once synthesis is complete, the design needs to be converted into a
configuration file, typically referred to as a bit stream, which can be loaded onto the FPGA
(Field Programmable Gate Array) device.

5. Open Hardware Manager: This is a software tool used to manage and program FPGA
devices. It allows users to configure FPGA devices and perform various tasks related to
hardware development.

6. Open Target: Refers to selecting the specific FPGA device that you want to program
and interact with using the Open Hardware Manager.

7. Select program device: Once the target FPGA device is chosen, this step involves
selecting the configuration file (bit stream) to be loaded onto the FPGA.

8. Connection between PC and board through serial connector: This refers to establishing
a communication link between a PC and the development board (which contains the FPGA and
MicroBlaze processor) using a serial connector. This connection is typically used for
programming the FPGA and for debugging purposes.

9. Verify output in Tera Term or CRO (Cathode Ray Oscilloscope): Tera Term is a terminal
emulator software used to connect to and communicate with devices over serial ports. CRO, on
the other hand, refers to using a Cathode Ray Oscilloscope to visualize and analyze electrical
signals. In the context of a MicroBlaze processor-based serial communication system, these
tools can be used to verify the correctness of the serial communication protocol and the data
exchanged between the PC and the development board.

48
Now We will see the step by step process

Step 1: Create a Project

1. Click the Vivado desktop icon to launch Vivado 2018.2.

2. Click on the Create Project option from the Quick Start page.
3. Make the following selections in the New Project dialog box:

a. Enter the project name and location in the Project Name dialog box.

b. Verify that the option to "Create project subdirectory" is checked. Select Next.

c. Choose RTL project from the Project Type dialog box. Make sure that the checkbox
labeled "Do not specify sources at this time" is removed. Select Next.

d. Select Verilog or VHDL as the Target language in the Add Sources dialog box. You
can choose Mixed for the Simulator's language.Select Next.

f. Select Next from the Add Constraints dialog box.

g. Select Boards and then the Kintex-7 KC-705 Evaluation Platform from the Default Part
dialog box. Select Next.

h. To create the project, go over the project overview in the New Project overview dialog
box and click Finish.

Step 2: Create an IP Integrator Design

1. Select Create Block Design under IP integrator in Flow Navigator.

2. Indicate the name of the IP subsystem design. You can use any name as the Design
name for this phase. Keep the Directory field with as the default setting. Keep Design
Sources selected as the default option in the Specify source set drop-down box.

3. In the Create Block Design dialog box—which is seen in the accompanying figure—

49
 Fig 5.2b Block Design Dialogue Box

4.. Right-click on the IP integrator diagram area and choose Add IP.

The catalog for IP integrators opens. As an alternative, you can click the middle of the canvas'
Add IP icon.
To locate the UART LITE core, type uart lite into the search area, choose UART LITE, and
hit Enter.In the block design banner, the Designer Assistance link activates.

5. Click Run Block Automation.

The dialog window for running block automation opens.

In the block design canvas, right-click anywhere and choose Add IP. IP Catalog opens. To
discover the MicroBlaze IP, put micro into the search bar. Once you've chosen MicroBlaze,
hit Enter.
Note: If not displayed by default, the IP Details window can be displayed
by clicking CTRL+Q on the keyboard while searching for IP.

6. Repeat the above steps add IP’s create your design

Step 3: Validate Block Design

To run design rule checks on the design:

1. Click the Validate Design button on the toolbar, or select Tools > Validate Design.
50
 The Validate Design dialog box informs you that there are no critical warnings or errors in
the design.

2. Click OK.
3. Save your design by pressing Ctrl+S, or select File > Save Block Design.

Step 4: Simulate the Design

1 In the Sources window, We can see the Run Implementation command.

.
Click on run implementation
2
. Then It displays the Waveforms then observe the waveforms like
clocl,address,data
Etc…
Step 5: Synthesis the design

1. The Run Synthesis command is seen on the left side of the Source Window in the Sources
window.

2. Click on Run Synthesis

3. Synthesis is the process of translating a gate-level representation that may be implemented

on a programmable logic device (PLD) such as an FPGA or an ASIC from a hardware
description language (HDL) code, such as Verilog or VHDL.

4. This procedure entails optimizing the code for the designer's stated time, area, and power
restrictions. Following synthesis, the design can be implemented and then programmed onto
the intended device for even more refinement.

Step 6: Create a Top-Level Wrapper

1. Under Design Sources, right-click the block design and click Create HDL Wrapper.

2. In the Create HDL Wrapper dialog box, Let Vivado manage wrapper and auto-update
is selected by default.

3. Click OK.
Step 7: Take the Design through Implementation

51
1. In the Flow Navigator, click Generate Bitstream.

The No implementation Results Available dialog box opens.

2. Click Yes.

3. The Launch Runs dialog box opens.

4. Make the appropriate choices and click OK.

5. Bitstream generation can take several minutes to complete. Once it finishes, the
Bitstream Generation Completed dialog box asks you to select what to do next.

6. Keep the default selection of Open Implemented Design and click OK.
7. Verify that all timing constraints have been met by looking at the Timing - Design
Timing Summary window.

Step 8: Export the Design

1. From the Vivado File menu, select File > Export > Export Hardware. The
Export Hardware Platform dialog box opens.
2. Click Next.
3. Select the Include bitstream option using the radio button in the Output view
and click Next.

Step 8: Launch on SDK

From the SDK File menu, select File > Launch on SDK > The SDK Platform opens.
1. From the SDK File menu, select File > New > Application Project. The Project Platform
dialog box opens.
2. Click hello world.
3. Select the Include bitstream option using the radio button in the Output view
and click Next.
4. Which Generates ELF file.
5. Connect PC or Laptop to the FPGA Board(Kc-705 evaluation Board)through J-tag and
Serial Connectors like USB cables
6. Click on Xilinx > Program FPGA
7. Open Tera Term or CRO application for output
52
8. Now we will see the output in Tera Term Window
10. Click ok
Step 9: Associates
11. Click on SourcesELF file to design
>Simulation & Write
Sources >Add Test bench
Sources code
>Add or for design
create
Simulation Sources>Next >Create file >Enter the File Name >Finish
9.
12. From
Click the Vivado
on File File
name menu,
then select
Write Tools
the Test > Associates
Bench code for Elf
Our>design.
Choose the elf path.
13. Run Simulation for output wave forms.
Testbench Code

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity sravan

is end

sravan;

architecture behavioral of sravan is

-- Component declaration for the wrapper

component design_1_wrapper is

port (

reset : in STD_LOGIC;

rs232_uart_rxd : in STD_LOGIC;

rs232_uart_txd : out

STD_LOGIC; 53
 sys_diff_clock_clk_p : in STD_LOGIC

);

end component;

-- Signals declaration

signal reset : STD_LOGIC := '0'; -- Assuming active low reset

signal rs232_uart_rxd : STD_LOGIC := '0';

signal rs232_uart_txd : STD_LOGIC;

signal sys_diff_clock_clk_n : STD_LOGIC := '0';

signal sys_diff_clock_clk_p : STD_LOGIC := '1';

begin

-- Instantiate the wrapper

uut: design_1_wrapper

port map (

reset => reset,

rs232_uart_rxd => rs232_uart_rxd,

rs232_uart_txd => rs232_uart_txd,

sys_diff_clock_clk_n => sys_diff_clock_clk_n,

sys_diff_clock_clk_p => sys_diff_clock_clk_p

);

54
-- Clock generation (100 MHz differential clock)

process

begin

while true loop

sys_diff_clock_clk_p <= not sys_diff_clock_clk_p after 5 ns; -- 100 MHz

period sys_diff_clock_clk_n <= not sys_diff_clock_clk_n after 5 ns;

wait for 2.5 ns;

end loop;

end process;

-- Reset generation

process

begin

reset <= '1';

wait for 100 ns; -- Reset duration

reset <= '0';

wait;

end process;

-- Stimulus process for RS232 UART RX data

Process

55
 begin

rs232_uart_rxd <= '0';

wait for 50 ns;

rs232_uart_rxd <= '1';

wait for 100 ns;

rs232_uart_rxd <= '0';

wait;

end process;

end behavioral;

5.3RESULTS

Figure 4.3.1: Result of the Project

56
 CHAPTER 6

ADVANTAGES & APPLICATIONS

6.1 ADVANTAGES
Microblaze Processor Based Serial Communication System has several
advantages, including:

1. Flexibility: Because MicroBlaze is a soft-core processor, it may be tailored and set up to

satisfy the particular needs of the real-time system's serial communication protocol.
Because of its adaptability, solutions may be customized and optimized for a given use
case.

2. Integration: MicroBlaze can be easily integrated into FPGA designs alongside other IP
cores and peripherals, including UART modules for serial communication. This
integration simplifies the design process and reduces the overall system complexity.

3. Low Latency: Micro-Blaze processors are capable of achieving low-latency

communication with external peripherals, including UARTs. This is crucial for real-time
systems where timely data transmission and reception are essential for system operation.

4. Deterministic Behavior: By carefully designing the firmware running on the

MicroBlaze processor, developers can ensure deterministic behavior in the serial
communication system. This predictability is vital for real-time systems where timing
constraints must be met consistently.

5. Scalability: Scaling MicroBlaze processors to meet real-time system performance needs

is possible. MicroBlaze may be adjusted to meet the needs of the system, whether it calls
for a high-performance CPU or a low-cost, low-power solution.

6. Ease of Development: Development tools such as Xilinx Vivado provide

comprehensive support for designing, debugging, and testing MicroBlaze-based systems.
This ease of development streamlines the process of implementing and verifying the serial
communication functionality in real-time systems.
57
7. Cost-Effectiveness: Utilizing a MicroBlaze processor for serial communication
eliminates the need for external microcontrollers or processors, reducing the overall
hardware cost of the system. Additionally, FPGAs offer reconfigurability, enabling
updates and modifications to be made without requiring new hardware.

8. Reliability: MicroBlaze processors are known for their reliability and robustness,
making them suitable for deployment in mission-critical real-time systems where
reliability is paramount.
6.2 APPLICATIONS

Microprocessor-based serial communication systems find applications in various industries and

devices, including:
Industrial Automation: Used for monitoring and controlling industrial processes, such as
manufacturing assembly lines, conveyor systems, and robotic arms.
Telecommunications: Facilitate communication between devices such as modems, routers, and
switches in networking equipment.
Embedded Systems: Utilized in embedded systems for tasks like data logging, sensor
interfacing, and control in applications such as smart home devices, automotive electronics, and
medical equipment.
Point-of-Sale (POS) Systems: Used for transaction processing, inventory management, and
communication with peripheral devices like barcode scanners, card readers, and receipt printers.
Remote Monitoring and Control: Deployed in systems for monitoring and controlling remote
equipment, such as weather stations, environmental monitoring systems, and remote telemetry
units.
Automotive Systems: Employed in vehicle diagnostic systems, GPS navigation, infotainment
systems, and engine control units (ECUs).
Consumer Electronics: Found in various consumer electronics products like digital cameras,
printers, handheld devices, and home automation systems.

58
Data Acquisition Systems: Used for collecting and transmitting data from sensors, meters, and
instrumentation in scientific research, environmental monitoring, and industrial process control.

59
Healthcare Devices: Applied in medical devices for patient monitoring, diagnostic equipment, and
communication between medical devices and hospital information systems.
Security Systems: Utilized in surveillance cameras, access control systems, and alarm systems
for communication and data transfer.
These applications demonstrate the versatility and importance of microprocessor-based serial
communication systems across different industries and domain

60
 CHAPTER 7
CONCLUSION
For embedded systems, there are several benefits to implementing a Serial Communication
system based on the MicroBlaze CPU. Firstly, the MicroBlaze processor, being a soft processor
core, provides flexibility in its configuration and integration into Field-Programmable Gate
Arrays (FPGAs). This flexibility enables customization of the serial communication system to
meet specific application requirements, such as baud rate, protocol, and interface options.

Secondly, the use of MicroBlaze processor-based systems allows for seamless integration
with other peripheral components within the FPGA, facilitating efficient data processing and
communication tasks. This integration capability simplifies system design and reduces hardware
complexity, ultimately leading to cost-effective solutions.

Moreover, the MicroBlaze processor's scalable architecture enables easy adaptation to

evolving communication standards and protocols. This adaptability ensures the longevity and
compatibility of the serial communication system with future advancements in technology,
enhancing its sustainability and lifespan in various applications.

In conclusion, leveraging the MicroBlaze processor for implementing a Serial

Communication system offers a versatile, cost-effective, and future-proof solution for embedded
systems. Its flexibility, integration capabilities, and scalability make it a compelling choice for
developers seeking efficient and adaptable communication solutions in FPGA-based designs.

61
62
 REFERENCES

[1] "Embedded Systems Design with the Xilinx MicroBlaze Processor" by Peter P. Chu.
[2] "MicroBlaze Processor Reference Guide" from Xilinx documentation.
[3] "MicroBlaze Processor Reference Guide" by Xilinx, UG081 (latest version
available).
[4] "MicroBlaze Processor System Reference Guide" by Xilinx, UG982.
[5] "MicroBlaze Processor IP Core Guide" by Xilinx, PG081.
[6] "Using the AXI UART 16550 IP Core with Xilinx MicroBlaze Processors"
Application Note (XAPP1052) by Xilinx.
[7] Xilinx forums and community discussions for specific application examples
and troubleshooting tips.
[8] These resources should provide detailed information on designing and
implementing serial communication systems using the MicroBlaze processor.

63