Basic Electrical and Electronics Engineering

Laboratory File

DEC1001L

Name of the Student: AMANAT KUMAR

Enrollment Number: No.-210160006001

Program : Diploma

Branch : ECE

Semester 1
 INDEX

S.No. Name of Page No. Date of Date of Remarks

Experiment Performance Submission
1 Verification of 20-10-21
Kirchhoff’s Laws
2 To verify Thevenin’s 27-10-21
Theorem.
3 To verify Norton’s 3-11-21
Theorem.
4 To verify 10-11-21
Superposition
Theorem.
5 To verify 17-11-21
maximum power
transfer theorem on
d.c circuits
6 To Plot Forward and 24-11-21
Reverse
Characteristics of the
P-N Junction Diode.
7 To Plot Forward and 7-12-21
Reverse
Characteristics of the
Zener Diode
8 To verify the Truth 6-12-21
Table for AND, OR,
NOT, NAND,
NOR, Ex-OR, Ex-
NOR
Logic Gates.
9 To verify the truth 22-12-21
table of Half adder
and Full adder by
using Simulator1 and
Simulator
Student’s Name : AMANAT KUMAR Enrollment No.:210160006001

EXPERIMENT No.1

Date of Performance 20-10-21

Aim: Verification of Kirchhoff’s Laws.

Apparatus:

Device Value & Quantity

Resistors 5

Voltage Source 1

Multimeter 1

Connecting wires As required

Theory:

Kirchhoff’s Current Law states that the total current or charge entering a junction or node is equal to
the current or charge leaving the node.

I(entering) = I(exiting)

Kirchhoff’s Voltage Law states that the algebraic sum of all the voltages around any closed
path (loop or mesh) is zero.
Circuit Diagram:

Figure 1

Procedure:

1. Connect the circuit as shown in figure 1.

2. Set the variable supply, E to the required value.
3. Accurately measure all voltages in the circuit using the Digital Multi-Meter (DMM).
4. Calculate current values from the measured voltage values.
5. Record the measurements in a tabular form containing the measured voltage and
calculated current values.
6. Verify KVL and KCL from the obtained values.

Observation Table :

Sr. Resistance Voltage Current

No.

1. R1 =0.974 V1=0.782 v I1 = 0.802

2. R2 =2.16 V2= 1.361v I2 =0.630

3. R3 =3.251 V3=0.562v I3 =0.172

4. R4 =4.60 V4=0.798v I4 =0.173

5. R5 =9.81 V5=7.98v I5 =0.803

 Calculations:

1. Verification of Kirchhoff’s Voltage Law

ABCD
VE = V1+V2+V5
10v = 0.782+1.361+7.857
= 10

ACDF
VE = V1+V3+V4+V5
10 = 0.782+0.562+0.798+7.857
= 10

BCDE
V2 = V3+V4
1.361 = 0.562+0.798
= 1.361

2. Verification of Kirchhoff’s Current Law

I1 = I2+I3
0.802 = 0.630+0.172
= 0.802

I5 = I2+I4
0.803 = 0.630 + 0.173

Precautions:

1. Connections should be neat and clean and as per the circuit diagram.

2. Always connect the Ammeter in series with the component for Current measurement.

3. Always connect the Voltmeter in parallel with the component for Voltage measurement.

4. Always connect the circuit to the ground.

5. Switch off the power supply when not in use

Conclusions: Kirchhoff’s Law has been verified.

Student’s Name : AMANAT KUMAR Enrollment No.: 210160006001

EXPERIMENT No.2

Date of Performance 27-10-21

Aim: To verify Thevenin’s Theorem.

Requirements:

Device Value Quantity

Resistors 4

Voltage Source 10V 1

Connecting wires As required

Theory:

In-circuit theory, Thevenin's theorem states that for linear electrical networks, any combination
of voltage sources, current sources, and resistors with two terminals is electrically equivalent to a
single voltage source ETh and a single series resistor RTh. The Thevenin voltage, ETh is a voltage source
equal to the open-circuit voltage at the terminals whereas the Thevenin resistance, R Th is the
resistance measured at terminals A-B with all voltage sources replaced by short circuits and all
current sources replaced by open circuits.

Circuit Diagram:
Figure 1:Circuit for calculation of IL

Figure 2:Circuit for Open circuit Voltage ETh

Figure: Circuit for Thevenin’s equivalent Resistance

Figure 4: Thevenin’s equivalent circuit

Procedure:
1. Arrange the resistances in the following order R1<R2<R3<RL.

2. Connect the circuit as shown in Figure 1. Measure IL through RL.

3. Measure the voltage across A-B (i.e. potential difference across load resistor).

4. Remove load resistor RL and measure voltage ETh (open circuit voltage) across A-B terminals
(Placing positive terminal of the meter at A and negative at B) as shown in figure 2.

5. Remove voltage sources and replace them with short circuit and remove current sources (if any)
and replace them with the open circuit as shown in figure 3 and Calculate RTh(Thevenin’s resistance
)across A-B.

6. Connect the circuit as shown in figure 4, where ETh and RTh are Thevenin (open circuit)
voltage and Thevenin resistance respectively, as measured in previous steps.

7. Connect the load and measure the voltage V́ L across RL and current ÍL through RL.

8. If IL = ÍL, then Thevenin’s Theorem is verified else repeat the above steps.

Observations and Calculations:

R1 = 1.8 Ω

R2 = 3Ω

R3 = 4.6Ω

RL = 9.8Ω

S.No. IL VTh VL ÍL (A)

1. RTh Measurement and
(A) (V) (V)
Calculation of
(Ω)
Thevenin circuit
1 0.64 9.96 5.72 9.9 0.64 parameters
(Theoretical)
 2. Measurement and Calculation of Thevenin circuit parameters (Experimental)

S.No. IL VTh V́ L ÍL

(A) (V) RTh (V) (A)
(Ω)

2 0.64 9.95 5.72 9.8 0.65

3. Calculate Percent error.

Percent error = |Theoretical − Experimental| / (Theoretical)

= IL-IL’/IL

= 0.64-0.65/0.64

= -0.01/0.64 = -0.01

Precautions:

1. Connections should be neat and clean.

2. Always connect Ammeter in series with the component for Current measurement.

3. Always connect the Voltmeter in parallel with the component for Voltage measurement.

4. Always connect the circuit to the ground.

Conclusions: Thevenin’s Theorem has been verified.

Student’s Name :AMANAT KUMAR Enrollment No. 210160006001

EXPERIMENT No.3

Date of Performance 3-11-21

Aim:To verify Norton’s Theorem.

Requirements:

Device Value Quantity

Resistors 4

Voltage Source 10V 1

Current Source 3

Connecting wires As required

Theory:

Norton's theorem states that:

• Any linear electrical network with voltage and current sources and resistances can be replaced
at terminals A-B by an equivalent current source I NORTAN in parallel connection with an
equivalent resistance RNORTAN.

• This equivalent current INORTAN is the current obtained at terminals A-B of the network with
terminals A-B short-circuited.

• This equivalent resistance RNORTAN is the resistance obtained at terminals A-B of the network
with all its voltage sources replaced by a short circuit and all its current sources replaced by
an open circuit.

In Norton equivalent circuit any network containing resistances, voltage sources, and current sources
can be replaced by an equivalent circuit consisting of an equivalent current source INORTAN in parallel
connection with an equivalent resistance RNORTAN.
Norton's theorem and it's dual, Thevenin's theorem, are widely used for circuit analysis and
simplification of complex circuits.
Norton’s Theorem can be used for two purposes:

1) to calculate the voltage across (or current through) any component in any circuit, or

2) to develop a constant current equivalent circuit which may be used to simplify the analysis of
complex circuits.

Circuit Diagram:

Figure 1
 Figure 2 : Circuit for Norton’s current source

Figure 3:Circuit for Norton’s equivalent Resistance

 Figure 4 : Norton’s equivalent circuit

Procedure:

1. Arrange them in the following order R1<R2<R3<RL.

2. Connect the circuit as shown in Figure 1. Measure current IL through RL.

3. Remove RL and short the load terminals A-B. Measure the short circuit current, INORTAN as shown in
Figure 2.

4. Remove voltage source and replace it with short circuit and remove the current source (if any) and
replace it with an open circuit as shown in Figure 3. Calculate RNORTAN (equivalent resistance) across
A-B.

5. Connect the circuit as shown in Figure 4 using INORTAN in parallel with RNORTAN and RL.

Measure the current ÍL through RL.

6. If IL = ÍL, then Norton’s Theorem is verified else repeat the above steps.
Observations and Calculations:

R1 = 1.4Ω

R2 = 2.3Ω

R3 = 4.2Ω

RL = 9.2Ω

1. Measurement and Calculation of Norton circuit parameters (Theoretical)

S.No. IL INORTON ÍL

(A) (A) RNORTON (A)
(Ω)

1 3.2 1.87 5.07 3.2

2. Measurement and Calculation of Norton circuit parameters (Experimental)

S.No. IL INORTON ÍL

(A) (A) RNORTON (A)
(Ω)

2 3.2 1.88 5.07 3.3

3. Calculate Percent error.

Percent error = |Theoretical − Experimental| / (Theoretical)

Precautions:

1. Connections should be neat and clean.

2. Always connect Ammeter in series with the component for Current measurement.

3. Always connect the Voltmeter in parallel with the component for Voltage measurement.

4. Always connect the circuit to the ground.

Conclusions: Norton’s Theorem has been verified.

Student’s Name :AMANAT KUMAR Enrollment No.: 210160006001

EXPERIMENT No.4

Date of Performance 10-11-21

Aim:To verify Superposition Theorem.

Requirements:

Device Value Quantity

Resistors 3

Voltage Source 5VAND 10V 2

Connecting wires As required

Theory:

Superposition Theorem states that the response (Voltage or Current) in any branch of a bilateral
linear circuit having more than one independent source equals the algebraic sum of the responses
caused by each independent source acting alone, while all other independent sources are replaced by
their internal impedances. To ascertain the contribution of each source, all of the other sources first
must be turned off (set to zero) by:

1) Replacing all other independent voltage sources with a short circuit (thereby eliminating
difference of potential. i.e. V=0, the internal impedance of ideal voltage source is zero
(short circuit)).

2) Replacing all other independent current sources with an open circuit (thereby
eliminating current. i.e. I=0, the internal impedance of the ideal current source is
infinite (open circuit).

3) This procedure is followed for each source in turn, and then the resultant responses are added
to determine the true operation of the circuit. The resultant circuit operation is the
superposition of the various voltage and current sources.
Circuit Diagram:

Figure 1

Figure 2
 Figure 3

Procedure:

1. Arrange them in the following order R1<R2<R3.

2. Connect the circuit as shown in Figure 1.

3. Measure V1 and I1 across R1, V2and I2across R2 and V3 and I3 across R3.
4. Replace E2 with a short circuit as shown in Figure 2. Measure V́ 1 and Í1 across R1,
V́ 2 and, Í2across R2, V́ 3 and Í3 across R3.
5. Connect the circuit as shown in Figure 3 and replace E1 with a short circuit. Measure V́ ́́ 1 and Í 1
across R1, V́ ́́ 2 and Í 2 across R2, V́ ́́ 3and Í 3 across R3.
6. If in the circuit the direction of currents calculated for each source must be taken as per sign
conventions.
 I1 = algebraic sum of Í 1 and Í 1
I2 = algebraic sum of Í 2 and Í 2
I3 = algebraic sum of Í 3 and Í 3
then Superposition Theorem is verified else repeat the above steps.
7. Compare the Voltages and Currents measured in Step 3, Step 4 , Step 5 and deduce the results.

Observations and Calculations:

R1 = 1Ω

R2 = 2 Ω

R3 = 10 Ω

1. When E1 and E2 both sources are present

S.No. V1 V2 V3 I1 I2 I3
5 10 1.16 1.92 0.62
1.Theoretical
5 10 1.16 1.92 0.62
2.Experimenta
l

Table 1
2. When E1 is present and E2 is replaced by a short circuit.

,
́
S.No. V́́́1 V́ 2 V́ 3 Í1 Í2 Í3
5 1.86 1.62 0.32
1.Theoretical
5 1.86 1.62 0.32
2.Experimenta
l

Table 2

3. When E2 is present and E1 is replaced by a short circuit.

S.No. V́́́ 1 V́́́ 2 V́́́ 3 Í 2 Í 2 Í 3

10 0.64 0.325 0.94
1.Theoretical
10 0.64 0.325 0.94
2.Experimenta
l

Table 3
4. Calculate Percent error

Percent error = |Theoretical − Experimental| / (Theoretical)

Precautions:

1. Connections should be neat and clean.

2. Always connect Ammeter in series with the component for Current measurement.

3. Always connect the Voltmeter in parallel with the component for Voltage measurement.

4. Always connect the circuit to the ground.

Conclusions: Superposition Theorem has been verified.

Student’s Name :AMANAT KUMAR Enrollment No.: 210160006001

EXPERIMENT No.5

Date of Performance 17-11-21

Aim: To verify maximum power transfer theorem on d.c circuits

Equipment:

Device Value Quantity

Resistor 2

Dial Resistance Box 1

Multimeter 1

Bread Board - 1

Voltage Source 1

Connecting wires As required

Theory:

It states that, In d.c circuits, maximum power is transferred from a source to load when the
load resistance is equal to the resistance of the network as seen from the output terminals,
with all the energy souces removed leaving behind their internal resistances.
According to Thevenin’s Theorem every Network can be represented by a single voltage
sourceVTh with an series effective resistance RTh

Output Power P = I2RL

P = (VTh / (RTh + RL))2 RL

 Power delivered by the source to the load will be maximum

If dP/d RL = 0

The condition for Maximum Power Theorem is that

RTh (Effective Resistance of the Network) = RL (Load Resistance)

Circuit diagram:

Figure 1

Procedure:
1. Connect the circuit as per the circuit diagram.
2. Adjust the output voltage of the regulated power supply to an appropriate value.
3. Vary the resistance using Dial Resistance Box in steps, and note down the load voltage
for each step.
4. Calculate the power absorbed by the load, PL for each step.
5. Plot the graph by taking RL on X-axis and PL on Y-axis.
6. Get the practical value of the load resistance for which it will gain the maximum
power from the source.
Observation Table & Calculations:

LOAD
RESISTANCE VOLTAGE POWER
SNO. RL
(ohm) VL P
(volt ) ( watt)
1 0.1 0.19 0.38
2 0.2 0.38 0.73

3 0.3 0.56 1.06

4 0.4 0.74 1.36

5 0.5 0.9 1.63

6 0.6 1.07 2.13

7 0.7 1.22 2.14

Graph: Plot graph between PL and RL
 Precautions:

1. Connect the Voltmeter in the right polarity.

2. Do not switch ON the power supply unless all the connections are checked as per the circuit.
3. Always bring the output voltage of the regulated power supply to 0V and switch-off
the supply.

Conclusion:
From the observations, it is evident that the maximum power is delivered at RTh = RL. Thus the
maximum power transfer theorem has been verified.
Student’s Name :AMANAT KUMAR Enrollment No.: 210160006001

EXPERIMENT No.6

Date of Performance 24-11-21

Aim: To Plot Forward and Reverse Characteristics of the P-N Junction Diode.

Equipment:

Device Value Quantity

Resistor 1

Diode IN4001 1

Multimeter 1

Bread Board - 1

Voltage Source 1

Connecting wires As required

Theory:
Donor impurities (pentavalent) are introduced into one side and acceptor impurities into the
other side of a single crystal of an intrinsic semiconductor to form a p-n diode with a junction
called depletion region (this region is depleted of the charge carriers). This region gives rise to a
potential barrier Vγ called Cut- in Voltage. This is the voltage across the diode at which it starts
conducting. The P-N junction can conduct beyond this Potential.

The P-N junction supports uni-directional current flow. If the positive terminal of the
input supply is connected to anode (P-side) and the negative terminal of the input supply is
connected to the cathode (N- side), then the diode is said to be forward biased. In this
condition, the height of the potential barrier at the junction is lowered by an amount equal to the
given forward biasing voltage. Both the holes from the p-side and electrons from the n-side
cross the junction simultaneously and constitute a forward current (injected minority current –
due to
holes crossing the junction and entering N-side of the diode, due to electrons crossing the
junction and entering the P-side of the diode).

Assuming current flowing through the diode to be very large, the diode can be
approximated as the short-circuited switch. If the negative terminal of the input supply is
connected to the anode (p-side) and the positive terminal of the input supply is connected to the
cathode (n-side) then the diode is said to be reverse biased. In this condition, an amount equal
to reverse biasing voltage increases the height of the potential barrier at the junction. Both the
holes on the p-side and electrons on the n-side tend to move away from the junction thereby
increasing the depleted region. However the process cannot continue indefinitely, thus a small
current called reverse saturation current continues to flow in the diode. This small current is due
to thermally generated carriers. Assuming current flowing through the diode to be negligible,
the diode can be approximated as an open-circuited switch.

The volt-ampere characteristics of a diode by following equation: I = Is(Exp(VD/ ηVT)-

1) I= current flowing in the diode

Is = reverse saturation current
VD= voltage applied across the diode
VT=volt-equivalent of temperature=kT/q=T/11,600=26mV(@ room temp).
η= Ideality factor (value ranging from 1 to 2)

Circuit diagram:

Forward Bias
Reverse Bias
Procedure:
Forward Biased Condition:

1. Connect the PN Junction diode in forward bias i.e Anode is connected to the positive of the
power supply and cathode is connected to the negative of the power supply.
2. Use a Regulated power supply of range (0-30)V and a series resistance.
3. For various values of forward voltage (Vf) note down the corresponding values of forward
current(If).

Reverse biased condition:

1. Connect the PN Junction diode in Reverse bias i.e. anode is connected to the negative of the
power supply and the cathode is connected to the positive of the power supply.
2. For various values of reverse voltage (Vr ) note down the corresponding values of
reverse current ( Ir ).

Observation:

Forward
Bias

S. No Vf If
1 0.1 0
2 0.2 0
3 0.3 0.63
4 0.4 0.71
5 0.5 0.9
6 0.6 1.16
7 0.7 10.26
8 0.8 10.27
 Reverse Bias:
S. No Vr Ir
1 -0.1 0
2 -0.2 0
3 -0.3 0.63
4 -0.4 0.71
5 -0.5 0.9
6 -0.6 1.16
7 -0.7 10.26
8 -0.8 10.27

Graph : I-V characteristics of P-N Junction Diode.

Points scored
12

10

0
0.2 0.4 0.6 0.8
 Precautions:
1. Do not exceed the ratings of the diode. This may lead to damage to the diode.
2. Connect voltmeter and Ammeter in the right polarities.
3. Do not switch ON the power supply unless all the connections are checked as per the circuit
diagram.

Conclusion: Plotted the I-V characteristics of P-N Junction diode

Student’s Name :AMANAT KUMAR Enrollment No.: 210160006001

EXPERIMENT No.7

Date of Performance 7-12-21

Aim: To Plot Forward and Reverse Characteristics of the Zener Diode.

Equipment:

Device Value Quantity

Resistor 1

Diode 1

Multimeter 1

Bread Board - 1

Voltage Source 1

Connecting wires As required

Theory:
A Zener diode is a heavily doped diode and conducts excellently even in reverse biased
condition. These diodes operate at a precise value of voltage called the breakdown voltage. A
Zener diode when forward biased behaves like an ordinary P-N junction diode. A Zener diode
when reverse biased can either undergo avalanche breakdown or Zener breakdown.

Avalanche breakdown:-If both p-side and n-side of the diode are lightly doped, the
depletion region at the junction widens. Application of a very large electric field at the junction
may rupture covalent bonding between electrons. Such rupture leads to the generation of a large
number of charge carriers resulting in avalanche multiplication.
 Zener breakdown:-
If both the p-side and n-side of the diode are heavily doped, the depletion region at the
junction reduces. Application of even a small voltage at the junction ruptures covalent bonding
and generates a large number of charge carriers. Such a sudden increase in the number of
charge carriers results in the Zener mechanism.

Circuit diagram:

Forward Bias
Reverse Bias
Procedure:

Forward Biased Condition:

1. Connect the Zener diode in forward bias i.e.the anode is connected to positive of the
power supply and the cathode is connected to the negative of the power supply.
2. Use a Regulated power supply of range (0-30)V and a series resistance.
3. For various values of forward voltage (Vf) note down the corresponding values of
forward current(If)

Reverse Biased condition:

1. Connect the Zener diode in Reverse bias i.e. anode is connected to the negative of the
power supply and the cathode is connected to the positive of the power supply as in
circuit.
2. For various values of reverse voltage(Vr ) note down the corresponding values of
reverse current ( Ir ).

Observation Table:

Forward Bias:

S. No Vf(V) If(mA)
1 0.1 0
2 0.2 0
3 0.3 0.66
4 0.4 0.79
5 0.5 2.34
6 0.6 2.4
7 0.7 4.8
 Reverse Bias:

S. No Vr Ir
1 -0.1 0
2 -0.2 0
3 -0.3 0
4 -0.4 -0.9
5 -0.5 -1.4
6 -0.6 -2.7
7 -0.7 -3.1

Graph: I-V Characteristics of Zener Diode

Precautions:

1. Do not exceed the ratings of the diode. This may lead to damage to the diode.
2. Connect the Voltmeter and Ammeter in the right polarities.

3. Do not switch ON the power supply unless all the connections are checked as per the circuit.

Conclusion: Plotted the I-V characteristics of Zener diode

Student’s Name :AMANAT KUMAR Enrollment No.: 210160006001

EXPERIMENT No.8

Date of Performance 6-10-21

Aim: To verify the Truth Table for AND, OR, NOT, NAND, NOR, Ex-OR, Ex-NOR Logic
Gates.

Software used: Virtual labs.-Digital Electronics IITR (Simulator 2)

Theory:

Logic gates are the basic building blocks of any digital system. Logic gates are electronic circuits
having one or more than one input and only one output. The relationship between the input and
the output is based on a certain logic. Based on this, logic gates are named as

1) AND gate: An AND gate is a logic gate that gives output one only if all inputs are at
logic 1. AND gate follows Boolean rules of multiplication.

Figure 1: IC 7408 AND gate

2) OR gate: An OR gate is a logic gate that gives output 1 if more than one of its inputs are
at logic 1. OR gate follows Boolean rules of addition.
 Figure 2: IC 7432 OR gate

3) NOT gate: NOT gate is a logic gate that produces an inverted version of the input at its
output. It is also known as inverter. If the input variable is A, then output is A’. NOT gate
follows Boolean rules of complementation.

Figure3: IC 7404 NOT gate

4) NAND gate: NAND gate is a Universal gate.It is a NOT-AND gate whose functionality
can be obtained by an AND gate followed by a NOT gate. The output of NAND gates is
1 if any of the input is at logic 0.

Figure 4: IC 7400 NAND gate

5) NOR gate: NAND gate is a Universal gate. It is a NOT-OR gate whose functionality can
be obtained by an OR gate followed by a NOT gate. The outputs of NOR gates is 0 if any
of the input is at logic 1.
 Figure 5: IC 7402 NOR gate

6) Ex-OR gate: The Exclusive-OR gate is a derived gate. The output is at logic 1 if both the
inputs are at different logic otherwise the output is at logic 0.

Figure 6: IC 7486 EXOR gate

7) Ex-NOR: The Exclusive NOR gate is also a derived gate. It is opposite to that of EX-OR
gate. The output is at logic 1 when both the inputs are at the same logic otherwise the
output is at logic 0.
 Figure 7: IC 74266 EXNOR gate

PROCEDURE:

1. Enter the Boolean input “A” and “B”.

2. Enter the Boolean output for corresponding input.
3. Click on “Check” button to verify the output.
4. Click “Print” to get print out of Truth Table.

SIMULATED OUTPUT:

1. VERIFICATION OF AND GATE

A B Output or Y
0 0 0
0 1 0
1 0 0
1 1 1
 2. VERIFICATION OF OR GATE
A B Output Y
0 0 0
0 1 1
1 0 1
1 1 1

3. VERIFICATION OF NOT GATE

A output Y
0 1
1 0

4. VERIFICATION OF NAND GATE

A B Output Y
0 0 1
0 1 1
1 0 1
1 1 0

5. VERIFICATION OF NOR GATE

A B Output Y
0 0 1
0 1 0
1 0 0
1 1 0
 6. VERIFICATION OF Ex-OR GATE
A B Output Y
0 0 0
0 1 1
1 0 1
1 1 0

7. VERIFICATION OF Ex-NOR GATE

A B Output Y
0 0 1
0 1 0
1 0 0
1 1 1

Conclusions: Truth Table of Logic Gates has been verified.

 Student’s Name :AMANAT KUMAR Enrollment No.: 210160006001

EXPERIMENT No.9

Date of Performance 22-12-21

AIM: To verify the truth table of Half adder and Full adder by using Simulator1 and Simulator 2.

Software used: Virtual labs.-Digital Electronics IITR (Simulator 1 and Simulator 2)

Theory: Adders are combinational circuits that carry out the addition of binary numbers. The
task performed by this digital circuit is binary addition.

Some basic rules of binary additions are shown below:

Rules of Binary Addition

1. Half adder – Half adder is a combinational circuit that adds two binary bits. Block
diagram of the Half adder is shown in figure 1 and the functionality of the Half adder is
shown by Truth Table in Table 1.

Figure 1: Block Diagram of Half Adder

 Table 1: Truth Table of Half Adder
Based on the truth table the K-maps for both sum and carry can be derived along with its
implementation using logic gates.

K- Maps for Half Adder: K-Maps for Sum is shown in figure 2 and K-Map for Carry is shown
in figure 3

Figure2:K-Map for Sum Figure3:K-Map for Carry

Output Logic Expression: Sum = A’B’ + A’B Carry = AB

Implementation of Half Adder: Implementation of Half Adder is shown in figure 4

 Figure4:Implementation of Half Adder

2. Full Adder: Full Adder is a digital circuit used to calculate the sum of three binary bits. Two
of the three inputs are A and B. The third bit is a carry bit from the previous stage and is called
“carry-in”or CIN. The block diagram for Full Adder is shown in figure 5 and the functionality of
Full Adder is shown by a Truth Table in table 2.

Figure 5: Block Diagram of Full Adder

 Table 2: Truth Table of Full Adder

Based on the truth table the K-maps for both sum and carry can be derived.

K- Maps for Full Adder :K-Maps for Sum is shown in figure and K-Map for Carry is shown in
figure 6 and figure 7

Figure6: K-Map for Sum

Figure7: K-Map for Carry

Output Logic Expression: Sum = A’B’CIN + A’BC’IN + A’BCIN + ABCIN

Carry = AB + BCIN + ACIN

Imlementation/Logic Diagram : Implementation of Full Adder is shown in the figure 8

Figure 8: Implementation of Full Adder

PROCEDURE:

For Simulator 1

1. Connect the supply (+5V) to the ICs.

2. Press the input switches to ON position (Logic 1) and OFF position (Logic 0).
3. Apply the input combinations as mentioned in the Truth Table one at a time.
4. Note the corresponding outputs for each applied input combination. (If LED glows
consider it as Logic 1 and if LED does not glow consider it as Logic 0).
5. Repeat the above steps and verify the Truth Table for Half Adder and Full Adder.
For Simulator 2

1. Enter the Boolean value of Inputs as Logic 1 or Logic 0.

2. Enter the Boolean value of Output as Logic 0 or Logic 1 based on the entered inputs
in Step 1.
3. Click on check button to verify the output obtained in step 2.
 4. Repeat the above steps and verify the Truth table for Half Adder and Full Adder.

Simulated Output:

1. Simulated Output of Half Adder using Simulator 1

s.n A B Carry sum
o
1 off off LED does not LED does not
glow glow
2 off on LED does not LED glow
glow
3 on off LED does not LED glow
glow
4 on on LED glow LED does not
glow

2. Simulated Output of Half Adder using Simulator 2

s.n A B Carry Sum
o
1 0 0 0 0
2 0 1 0 1
3 1 0 0 1
4 1 1 1 0
3. Simulated Output of Full Adder using Simulator 1
4. s.no A B Cin Sum Cout
1 off off off LED does LED does
not glow not glow
2 off off on LED glow LED does
not glow
3 off on off LED glow LED does
not glow
4 off on on LED does LED glow
not glow
5 on off off LED glow LED does
not glow
6 on off on LED does LED glow
not glow
7 on on off LED does LED glow
not glow
8 on on on LED glow LED glow

5. Simulated Output of Full Adder using Simulator 2

 s.no A B Cin Sum Cout
1 0 0 0 0 0
2 0 0 1 1 0
3 0 1 0 1 0
4 0 1 1 0 1
5 1 0 0 1 0
6 1 0 1 0 1
7 1 1 0 0 1
8 1 1 1 1 1

Conclusion: Truth Tables of Half Adder and Full Adder have been verified.