Macroblock: 16-Bit Constant Current LED Sink Driver
Macroblock: 16-Bit Constant Current LED Sink Driver
Macroblock: 16-Bit Constant Current LED Sink Driver
Macroblock
16-bit Constant Current LED Sink Driver
Features MBI5026CN\CNS
MBI5016CNS
MBI5016CNS
l 16 constant-current output channels
l Constant output current invariant to load voltage change
l Excellent output current accuracy:
between channels: <±3% (max.), and
CN: P-DIP24-300-2.54
between ICs: <±6% (max.) CNS: SP-DIP24-300-1.78
MBI5026CP\CPA
MBI5016CP
CP\CPA: SSOP24-150-0.64
Current Accuracy
Conditions
Between Channels Between ICs
Product Description
MBI5026 is designed for LED displays. As an enhancement of its predecessor, MBI5016, MBI5026 exploits
PrecisionDrive™ technology to enhance its output characteristics. MBI5026 contains a serial buffer and data
latches which convert serial input data into parallel output format. At MBI5026 output stage, sixteen regulated
current ports are designed to provide uniform and constant current sinks for driving LEDs within a large range of Vf
variations.
MBI5026 provides users with great flexibility and device performance while using MBI5026 in their system design
for LED display applications, e.g. LED panels. Users may adjust the output current from 5 mA to 90 mA through an
external resistor, Rext, which gives users flexibility in controlling the light intensity of LEDs. MBI5026 guarantees to
endure maximum 17V at the output port. The high clock frequency, 25 MHz, also satisfies the system requirements
of high volume data transmission.
R-EXT IO Regulator
VDD
16
GND 16
CLK
OE terminal LE terminal
VDD VDD
IN IN
IN OUT
N=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK
SDI
LE
OE
OFF
OUT0 ON
OFF
OUT1
ON
OFF
OUT2
ON
OFF
OUT3 ON
OFF
OUT15 ON
SDO
: don’t care
Truth Table
H L Dn Dn ….. Dn - 7 …. Dn - 15 Dn-15
H L Dn+2 Dn + 2 …. Dn - 5 …. Dn - 13 Dn-13
X L Dn+3 Dn + 2 …. Dn - 5 …. Dn - 13 Dn-13
IOL=26.25mA
Current Skew dIOUT1 Rext=720 Ω - ±1 ±3 %
VDS=0.6V
IOL=52.5mA
Current Skew dIOUT2 Rext=360 Ω - ±1 ±3 %
VDS=0.8V
Output Current vs.
%/dVDS VDS within 1.0V and 3.0V - ±0.1 - %/V
Output Voltage Regulation
Output Current vs.
%/dVDD VDD within 4.5V and 5.5V - ±1 - %/V
Supply Voltage Regulation
Pull-up Resistor RIN(up) OE 250 500 800 KΩ
Pull-down Resistor RIN(down) LE 250 500 800 KΩ
IDD(off) 1 Rext=Open, OUT0 ~ OUT15 =Off - 7 12
“OFF” IDD(off) 2 Rext=720 Ω, OUT0 ~ OUT15 =Off - 10 12
Supply
IDD(off) 3 Rext=360 Ω, OUT0 ~ OUT15 =Off - 12 15 mA
Current
IDD(on) 1 Rext=720 Ω, OUT0 ~ OUT15 =On - 10 18
“ON”
IDD(on) 2 Rext=360 Ω, OUT0 ~ OUT15 =On - 12 20
IOUT
VDD
OE
..
OUT0
IIH,IIL
CLK ..
LE OUT15
SDI
SDO
R - EXT GND
VIH, VIL
Iref
OE tw(OE) 200 - - ns
Hold Time for LE th(L) 5 - - ns
Setup Time for LE tsu(L) 5 - - ns
Hold Time for SDI th(D) 10 - - ns
Setup Time for SDI tsu(D) 5 - - ns
Cascade
Clock Frequency FCLK - - 25.0 MHz
Operation
Maximum CLK Rise Time tr** - - 500 ns
Maximum CLK Fall Time tf** - - 500 ns
Output Rise Time of Vout (turn off) tor - 70 200 ns
Output Fall Time of Vout (turn on) tof - 40 120 ns
**If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for
data transfer between two cascaded devices.
IDD
IOUT
VDD
VIH, VIL
OE
..
OUT0
Function CLK
.
Generator LE OUT15
RL
SDI
SDO CL
R - EXT GND
Logic input
waveform VL
VIH = 5V CL
Iref
VIL = 0V
tr = tf = 10 ns
tW(CLK)
50%
CLK 50% 50%
tsu(D) th(D)
SDO 50%
LE 50% 50%
th(L) tsu(L)
OUTn 50%
LOW = OUTPUT ON
tpLH1, tpHL1
tpLH2, tpHL2
tW(OE)
OE 50% 50%
tpHL3 tpLH3
90% 90%
OUTn 50% 50%
10% 10%
tof tor
100.00
90.00
80.00
70.00
60.00
Iout (mA)
50.00
40.00
30.00
20.00
10.00
0.00
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 2 2.5
VDS (V)
100
90
80
70
IOUT (mA)
60
50
40 VDS = 1.0V
30
20
10
0
0 500 1000 1500 2000 2500 3000 3500
Rext
Iout(mA)
Iout(mA)
60 60
50 50
40 40
30 30
20 20
10 10
0 0 5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
55%
60%
65%
70%
75%
80%
85%
90%
95%
100%
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
55%
60%
65%
70%
75%
80%
85%
90%
95%
100%
Iout vs. Duty Cycle at Rth = 66.74 (°C/W) Iout vs. Duty Cycle at Rth = 72.43 (°C/W)
100 100
90 90
80 80
Iout(mA)
70 70
Iout(mA)
60 60
50 50
40 40
30 30
20 20
10 10
0 0
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
55%
60%
65%
70%
75%
80%
85%
90%
95%
100%
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
55%
60%
65%
70%
75%
80%
85%
90%
95%
100%
100
90
80 Condition:Iout = 90mA,VDS = 1.0V,16 output
70
channels active
Iout(mA)
60
50
Device Type Rth(j-a)(°C/W) Note
40 CN 53.82
30 CNS 66.74 Ta = 25℃
20 Ta = 55℃
CD 49.81
10 Ta = 85℃
0
CF 59.01
CP\CPA 72.43
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
55%
60%
65%
70%
75%
80%
85%
90%
95%
100%
Duty Cycle
CD type package
The maximum power dissipation, PD(max) = (Tj – Ta) / Rth(j-a), decreases as the ambient temperature increases.
2.50
2.25
2.00
Power Dissipation
0.75
0.50
10 20 30 40 50 60 70 80 90
Ambient Temperature
VLED VLED
VDROP VDROP
Vf
Vf
VDS VDS
MBI5026 MBI5026
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