Vlsi 1

1.
Write a verilog code for a full adder using data flow

abstruction and verify the testbench
module full_adder(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign sum=a^b^cin;
assign cout=(a&b)|(b&cin)|(cin&a);
endmodule
module full_adder_tb();
reg a,b,cin;
wire sum,cout;
integer i;
full_adder dut(a,b,cin,sum,cout);
initial
begin
a=1'b0;
b=1'b0;
cin=1'b0;
end
initial
begin
for(i=0;i<8;i=i+1)
begin
{a,b,cin}=i;
#10;
end
end
initial
$monitor ("input
a=%b,b=%d,cin=%d,sum=%d,cout=%d",a,b,cin,sum,cout);
initial #100 $finish();
endmodule
2. Write a verilog for a 1bit full adder using 2 half adder
and 1 or gate and verify using testbench
module full_adder(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire w1,w2,w3;
half_adder ha1(.a(a),.b(b),.sum(sum),.carry(carry));
half_adder ha2(.a(w1),.b(c),.sum(sum),.carry(w3));
or or1(carry,w2,w3);
endmodule
module half_adder(a,b,sum,carry);
input a,b;
output sum,carry;
assign sum=a^b;
assign carry=a&b;
endmodule
module full_adder_tb();
reg a,b,c;
wire sum,carry;
integer i;
full_adder dut(a,b,c,sum,carry);
initial
begin
a=1'b0;
b=1'b0;
c=1'b0;
end
initial
begin
for(i=0;i<8;i=i+1)
begin
{a,b,c}=i;
#10;
end
end
initial
$monitor("Input
a=%b,b=%b,c=%b,sum=%b,carry=%b",a,b,c,sum,carry);
initial #100 $finish;
endmodule
3. write a verilog code for a half adder using data flow of
abstruction and verify using testbench
RTL Code:
module Half_adder(a,b,sum,cout);
input a,b;
output sum,cout;
assign sum=a^b;
assign cout=a&b;
endmodule
module Half_adder_tb();
reg a,b;
wire sum,cout;
integer i;
Half_adder dut (a,b,sum,cout);
initial
begin
a=1'b0;
b=1'b0;
end
initial
begin
for(i=0;i<4;i=i+1)
begin
{a,b}=i;
#10;
end
end
endmodule
4. Write an rtl and testbench for 2:4 decoder using data
flow abstruction
module decoder_2x4(a,b,en,d0,d1,d2,d3);
input a,b,en;
output d0,d1,d2,d3;
assign d0=~a&~b&en;
assign d1=~a&b&en;
assign d2=a&~b&en;
assign d3=a&b&en;
endmodule
module decoder_2x4_tb();
reg a,b,en;
wire d0,d1,d2,d3;
integer i;
decoder_2x4 dut(a,b,en,d0,d1,d2,d3);
initial
begin
a=1'b0;
b=1'b0;
en=1'b1;
end
initial
begin
for(i=0;i<4;i=i+1)
begin
{a,b}=i;
#10;
end
end
endmodule
5. Write an Rtl and Testbench for a 4:1 mux using 2:1
mux
module mux_4x1(S0,S1,I0,I1,I2,I3,out);
input S0,S1,I0,I1,I2,I3;
output out;
wire W1,W2;
mux_2x1 m1(.s(S0),.i0(I0),.i1(I1),.y(W1));
mux_2x1 m2(.s(S0),.i0(I2),.i1(I3),.y(W2));
mux_2x1 m3(.s(S1),.i0(W1),.i1(W2),.y(out));
endmodule
module mux_2x1(s,i0,i1,y);
input s,i0,i1;
output y;
assign y=(~s&i0)|(s&i1);
endmodule
Testbench:
module mux_4x1_tb();
reg S0,S1,I0,I1,I2,I3;
wire out;
integer i;
mux_4x1 dut (S0,S1,I0,I1,I2,I3,out);
initial
begin
S0=1'b0;S1=1'b0;I0=1'b0;I1=1'b0;I2=1'b0;I3=1'b0;
end
initial
begin
for(i=0;i<64;i=i+1)
begin
{S1,S0,I0,I1,I2,I3}=i;
#10;
end
end
Endmodule
Simulation Result:
Synthesis results:
6. write an Rtl code for a bidirectional buffer and verify
the same using testbench
RTL Code:
module bi_buff(a,b,ctrl);
inout a,b;
input ctrl;
bufif1 b1(b,a,ctrl);
bufif0 b2 (a,b,ctrl);
endmodule
Testbench:
module bi_buff_tb();
wire a,b;
reg ctrl;
reg tempa,tempb;
integer i;
bi_buff dut (a,b,ctrl);
assign a=ctrl?tempa:1'bz;
assign b=~ctrl?tempb:1'bz;
initial
begin
for(i=0;i<8;i=i+1)
begin
{tempa,tempb,ctrl}=i;
#10;
end
end
initial
$monitor("a=%b,b=%b,ctrl=%b",a,b,ctrl);
endmodule
Simulation result:
7. write an rtl and testbench and testbench for a 4 bit
ripple carry adder using 1bit full adder
Rtl Code:
module full_adder(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign sum=a^b^cin;
assign carry=a&b/b&cin/cin&a;
endmodule
module ripple_carry_adder(a,b,cin,s,carry);
output [3:0]s;
output carry;
input[3:0]a,b;
input cin;
wire c1,c2,c3;
full_adder f1(a[0],b[0],cin,s[0],c1);
full_adder f2(a[1],b[1],c1,s[1],c2);
full_adder f3(a[2],b[2],c2,s[2],c3);
full_adder f4(a[3],b[3],c3,s[3],carry);
endmodule
Testbench:
module ripple_carry_adder_tb();
wire [3:0]s;
wire carry;
reg [3:0]a,b;
reg cin;
integer i;
ripple_carry_adder dut
(.a(a),.b(b),.cin(cin),.s(s),.carry(carry));
initial
begin
a=4'b0;b=4'b0;cin=1'b0;
end
initial
begin
for(i=0;i<256;i=i+1)
begin
{a,b}=i;
#10;
end
end
initial
$monitor ("input
a=%b,b=%b,cin=%b,sum=%b,cout=%b",a,b,cin,s,carry);
endmodule
Simulation results:
Synthesis results:
9.write 8:3 priority encoder using structural model
RTL Code:
module pr_encoder(in,idle,y);
input [7:0]in;
output[2:0]y;
output idle;
wire [7:0]h;
pr_circuit c1(in,h,idle);
encoder c2(h,y);
endmodule
module pr_circuit(i,h,idle);
input [7:0]i;
output [7:0]h;
output idle;
assign h[7]=i[7];
assign h[6]=i[6]&~i[7];
assign h[5]=i[5]&~i[6]&~i[7];
assign h[4]=i[4]&~i[5]&~i[6]&~i[7];
assign h[3]=i[3]&~i[4]&~i[5]&~i[6]&~i[7];
assign h[2]=i[2]&~i[3]&~i[4]&~i[5]&~i[6]&~i[7];
assign h[1]=i[1]&~i[2]&~i[3]&~i[4]&~i[5]&~i[6]&~i[7];
assign
h[0]=i[0]&~i[1]&~i[2]&~i[3]&~i[4]&~i[5]&~i[6]&~i[7];
assign
idle=~i[0]&~i[1]&~i[2]&~i[3]&~i[4]&~i[5]&~i[6]&~i[7];
endmodule
module encoder(in,y);
input [7:0]in;
output [2:0]y;
assign y[2]=in[4]+in[5]+in[6]+in[7];
Endmodule
Testbench:
module pr_encoder_tb();
reg [7:0]in;
wire [2:0]y;
wire idle;
integer i,chanel_1;
pr_encoder dut(in,idle,y);
initial
begin
chanel_1=$fopen("fileoutpr1");
$fmonitor(chanel_1,$time,"input=%b,y=%b",in,y);
end
initial
begin
in=8'd0;
end
initial
begin
for(i=0;i<256;i=i+1)
begin
in=i;#10;
end
end
initial
$monitor("input=%b,y=%b",in,y);initial #3000 $finish;
endmodule
simulation result:
Synthesis result:

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Write a verilog code for a full adder using data flow

9.write 8:3 priority encoder using structural model

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