PIC24FJ64GA104 39951c

PIC24FJ64GA104 Family
Data Sheet
28/44-Pin, 16-Bit General Purpose
Flash Microcontrollers
with nanoWatt XLP Technology
 2010 Microchip Technology Inc. DS39951C

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Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
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Printed on recycled paper.
ISBN:978-1-60932-440-7
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39951C-page 2  2010 Microchip Technology Inc.

PIC24FJ64GA104 FAMILY
28/44-Pin, 16-Bit General Purpose Flash Microcontrollers
with nanoWatt XLP Technology
Power Management Modes: Special Microcontroller Features
• Selectable Power Management modes with nanoWatt (continued):
XLP Technology for Extremely Low Power: • Flash Program Memory:
- Deep Sleep mode allows near total power-down - 10,000 erase/write cycle endurance (minimum)
(20 nA typical and 500 nA with RTCC or WDT), - 20-year data retention minimum
along with the ability to wake-up on external triggers, - Selectable write protection boundary
or self-wake on programmable WDT or RTCC alarm • Fail-Safe Clock Monitor Operation:
- Extreme low-power DSBOR for Deep Sleep, - Detects clock failure and switches to on-chip
LPBOR for all other modes FRC Oscillator
- Sleep mode shuts down peripherals and core for • On-Chip 2.5V Regulator
substantial power reduction, fast wake-up
• Power-on Reset (POR), Power-up Timer (PWRT)
- Idle mode shuts down the CPU and peripherals for
and Oscillator Start-up Timer (OST)
significant power reduction, down to 4.5 A typical • Two Flexible Watchdog Timers (WDT) for Reliable
- Doze mode enables CPU clock to run slower than Operation:
peripherals - Standard programmable WDT for normal operation
- Alternate Clock modes allow on-the-fly switching to - Extreme low-power WDT with programmable
a lower clock speed for selective power reduction
period of 2 ms to 26 days for Deep Sleep mode
during Run mode, down to 15 A typical
• In-Circuit Serial Programming™ (ICSP™) and
High-Performance CPU: In-Circuit Debug (ICD) via 2 Pins
• JTAG Boundary Scan Support
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator with: Analog Features:
- 4x PLL option
- Multiple divide options • 10-Bit, up to 13-Channel Analog-to-Digital (A/D)
• 17-Bit x 17-Bit Single-Cycle Hardware Converter:
Fractional/integer Multiplier - 500 ksps conversion rate
• 32-Bit by 16-Bit Hardware Divider - Conversion available during Sleep and Idle
• 16 x 16-Bit Working Register Array • Three Analog Comparators with Programmable
• C Compiler Optimized Instruction Set Architecture: Input/Output Configuration
- 76 base instructions • Charge Time Measurement Unit (CTMU):
- Flexible addressing modes - Supports capacitive touch sensing for touch
• Linear Program Memory Addressing, up to 12 Mbytes screens and capacitive switches
• Linear Data Memory Addressing, up to 64 Kbytes - Provides high-resolution time measurement and
• Two Address Generation Units for Separate Read and simple temperature sensing
Write Addressing of Data Memory
Special Microcontroller Features:

• Operating Voltage Range of 2.0V to 3.6V
• Self-Reprogrammable under Software Control
• 5.5V Tolerant Input (digital pins only)
• High-Current Sink/Source (18 mA/18 mA) on All I/O pins
Remappable Peripherals
Program Memory
Comparators
Compare/PWM
10-Bit A/D
PMP/PSP
Remappable
(Bytes)
(Bytes)
SRAM
CTMU
RTCC
I2C™
UART w/
PIC24FJ
Pins
Capture
(ch)
Output
Timers
16-Bit
IrDA®
Input
Pins
SPI
Device
32GA102 28 32K 8K 16 5 5 5 2 2 2 10 3 Y Y Y
64GA102 28 64K 8K 16 5 5 5 2 2 2 10 3 Y Y Y
32GA104 44 32K 8K 26 5 5 5 2 2 2 13 3 Y Y Y
64GA104 44 64K 8K 26 5 5 5 2 2 2 13 3 Y Y Y
 2010 Microchip Technology Inc. DS39951C-page 3

Peripheral Features: • Two UART modules:
- Supports RS-485, RS-232 and LIN/J2602
• Peripheral Pin Select: - On-chip hardware encoder/decoder for IrDA®
- Allows independent I/O mapping of many peripherals - Auto-wake-up on Start bit
- Up to 26 available pins (44-pin devices) - Auto-Baud Detect (ABD)
- Continuous hardware integrity checking and safety - 4-level deep FIFO buffer
interlocks prevent unintentional configuration changes • Five 16-Bit Timers/Counters with Programmable
• 8-Bit Parallel Master Port (PMP/PSP): Prescaler
- Up to 16-bit multiplexed addressing, with up to • Five 16-Bit Capture Inputs, each with a Dedicated Time
11 dedicated address pins on 44-pin devices Base
- Programmable polarity on control lines • Five 16-Bit Compare/PWM Outputs, each with a
- Supports legacy Parallel Slave Port Dedicated Time Base
• Hardware Real-Time Clock/Calendar (RTCC): • Programmable, 32-Bit Cyclic Redundancy Check (CRC)
- Provides clock, calendar and alarm functions Generator
- Functions even in Deep Sleep mode • Configurable Open-Drain Outputs on Digital I/O Pins
• Two 3-Wire/4-Wire SPI modules (support 4 Frame • Up to 3 External Interrupt Sources
modes) with 8-Level FIFO Buffer
• Two I2C™ modules support Multi-Master/Slave mode
and 7-Bit/10-Bit Addressing
Pin Diagrams
28-Pin SPDIP, SOIC, SSOP(1)
MCLR 1 28 VDD
AN0/C3INC/VREF+/CN2/CTED1/RA0 2 27 VSS
AN1/C3IND/VREF-/CN3/CTED2/RA1 3 26 AN9/C3INA/RP15/CN11/PMCS1/RB15
PIC24FJXXGA102
PGED1/AN2/C2INB/RP0/CN4/RB0 4 25 AN10/C3INB/CVREF/RTCC/RP14/CN12/PMWR/RB14
PGEC1/AN3/C2INA/RP1/CN5/RB1 5 24 AN11/C1INC/RP13/CN13/PMRD/REFO/RB13
AN4/C1INB/RP2/SDA2/CN6/RB2 6 23 AN12/RP12/CN14/PMD0/RB12
AN5/C1INA/RP3/SCL2/CN7/RB3 7 22 PGEC2/TMS/RP11/CN15/PMD1/RB11
VSS 8 21 PGED2/TDI/RP10/CN16/PMD2/RB10
OSCI/CLKI/C1IND/CN30/RA2 9 20 VCAP/VDDCORE
OSCO/CLKO/PMA0/CN29/RA3 10 19 DISVREG
SOSCI/C2IND/RP4/PMBE/CN1/RB4 11 18 TDO/RP9/SDA1/CN21/PMD3/RB9
SOSCO/SCLKI/T1CK/C2INC/CN0/PMA1/RA4 12 17 TCK/RP8/SCL1/CN22/PMD4/RB8
VDD 13 16 RP7/INT0/CN23/PMD5/RB7
PGED3/RP5/ASDA1(2)/CN27/PMD7/RB5 14 15 PGC3/EMUC3/RP6/ASCL1(2)/CN24/PMD6/RB6
Legend: RPn represents remappable peripheral pins.

Note 1: Gray shading indicates 5.5V tolerant input pins.
2: Alternative multiplexing for SDA1 and SCL1 when the I2C1SEL bit is set.

Pin Diagrams
AN10/C3INB/CVREF/RTCC/RP14/CN12/PMWR/RB14
28-Pin QFN(1,3)
AN9/C3INA/RP15/CN11/PMCS1/RB15
AN0/C3INC/VREF+/CN2/CTED1/RA0
AN1/C3IND/VREF-/CN3/CTED2/RA1
MCLR
VDD
VSS
28 27 26 25 24 23 22
PGED1/AN2/C2INB/RP0/CN4/RB0 1 21 AN11/C1INC/RP13/CN13/PMRD/REFO/RB13
PGEC1/AN3/C2INA/RP1/CN5/RB1 2 20 AN12/RP12/CN14/PMD0/RB12
AN4/C1INB/SDA2/RP2/CN6/RB2 3 19 PGEC2/TMS/RP11/CN15/PMD1/RB11
AN5/C1INA/SCL2/RP3/CN7/RB3 4 PIC24FJXXGA102 18 PGED2/TDI/RP10/CN16/PMD2/RB10
VSS 5 17 VCAP/VDDCORE
OSCI/CLKI/C1IND/CN30/RA2 6 16 DISVREG
OSCO/CLKO/CN29/PMA0/RA3 7 15 TDO/RP9/SDA1/CN21/PMD3/RB9
8 9 10 11 12 13 14
PGED3/RP5/ASDA1(2)/CN27/PMD7/RB5
PGEC3/RP6/ASCL1(2)/CN24/PMD6/RB6
SOSCI/C2IND/RP4/PMBE/CN1/RB4
RP7/INT0/CN23/PMD5/RB7
SOSCO/SCLKI/T1CK/C2INC/CN0/PMA1/RA4
VDD
TCK/RP8/SCL1/CN22/PMD4/RB8

3: The back pad on QFN devices should be connected to VSS.

Pin Diagrams
PGED3/RP5/ASDA1(2)/CN27/PMD7/RB5
PGEC3/RP6/ASCL1(2)/CN24/PMD6/RB6
SOSCO/SCLKI/T1CK/C2INC/CN0/RA4
44-PIN TQFP,
44-Pin QFN(1,3)
RP8/SCL1/CN22/PMD4/RB8
RP7/INT0/CN23/PMD5/RB7
RP19/CN28/PMBE/RC3
RP21/CN26/PMA3/RC5
RP20/CN25/PMA4/RC4
TDI/PMA9/RA9
VDD
VSS
42
41
39
38
37
35
44
43
40
36
34
RP9/SDA1/CN21/PMD3/RB9 1 33 SOSCI/C1IND/RP4/CN1/RB4
RP22/CN18/PMA1/RC6 2 32 TDO/PMA8/RA8
RP23/CN17/PMA0/RC7 3 31 OSCO/CLKO/CN29/RA3
RP24/CN20/PMA5/RC8 4 30 OSCI/CLKI/C1IND/CN30/RA2
RP25/CN19/PMA6/RC9 5 29 VSS
DISVREG 6 PIC24FJXXGA104 28 VDD
VCAP/VDDCORE 7 27 AN8/RP18/PMA2/CN10/RC2
PGED2/RP10/CN16/PMD2/RB10 8 26 AN7/RP17/CN9/RC1
PGEC2/RP11/CN15/PMD1/RB11 9 25 AN6/RP16/CN8/RC0
AN12/RP12/CN14/PMD0/RB12 10 24 AN5/C1INA/RP3/SCL2/CN7/RB3
AN11/C1INC/RP13/PMRD/REFO/CN13/RB13 11 23 AN4/C1INB/RP2/SDA2/CN6/RB2
15
17
22
12
13
14
16
18
19
20
21
MCLR
AN10/C3INB/CVREF/RTCC/RP14/CN12/PMWR/RB14
AN0/C3INC/VREF+/CN2/CTED1/RA0
AN1/C3IND/VREF-/CN3/CTED2/RA1
TMS/PMA10/RA10
PGED1/AN2/C2INB/RP0/CN4/RB0
PGEC1/AN3/C2INA/RP1/CN5/RB1
TCK/PMA7/RA7
AN9/C3INA/RP15/CN11/RB15
AVDD
AVSS

3: The back pad on QFN devices should be connected to VSS.

Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 19
3.0 CPU ........................................................................................................................................................................................... 25
4.0 Memory Organization ................................................................................................................................................................. 31
5.0 Flash Program Memory.............................................................................................................................................................. 51
6.0 Resets ........................................................................................................................................................................................ 59
7.0 Interrupt Controller ..................................................................................................................................................................... 65
8.0 Oscillator Configuration ............................................................................................................................................................ 101
9.0 Power-Saving Features............................................................................................................................................................ 111
10.0 I/O Ports ................................................................................................................................................................................... 121
11.0 Timer1 ...................................................................................................................................................................................... 143
12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 145
13.0 Input Capture with Dedicated Timers ....................................................................................................................................... 151
14.0 Output Compare with Dedicated Timers .................................................................................................................................. 155
15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 165
16.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 175
17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 183
18.0 Parallel Master Port (PMP)....................................................................................................................................................... 191
19.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 201
20.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator ........................................................................................ 213
21.0 10-Bit High-Speed A/D Converter ............................................................................................................................................ 219
22.0 Triple Comparator Module........................................................................................................................................................ 229
23.0 Comparator Voltage Reference................................................................................................................................................ 233
24.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 235
25.0 Special Features ...................................................................................................................................................................... 239
26.0 Development Support............................................................................................................................................................... 251
27.0 Instruction Set Summary .......................................................................................................................................................... 255
28.0 Electrical Characteristics .......................................................................................................................................................... 263
29.0 Packaging Information.............................................................................................................................................................. 283
Appendix A: Revision History............................................................................................................................................................. 297
Index ................................................................................................................................................................................................. 299
The Microchip Web Site ..................................................................................................................................................................... 305
Customer Change Notification Service .............................................................................................................................................. 305
Customer Support .............................................................................................................................................................................. 305
Reader Response .............................................................................................................................................................................. 306
Product Identification System ............................................................................................................................................................ 307

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1.0 DEVICE OVERVIEW • Instruction-Based Power-Saving Modes: There
are three instruction-based power-saving modes:
This document contains device-specific information for - Idle Mode – The core is shut down while leaving
the following devices: the peripherals active.
• PIC24FJ32GA102 • PIC24FJ32GA104 - Sleep Mode – The core and peripherals that
• PIC24FJ64GA102 • PIC24FJ64GA104 require the system clock are shut down, leaving
the peripherals active that use their own clock or
The PIC24FJ64GA104 family provides an expanded the clock from other devices.
peripheral feature set and a new option for
- Deep Sleep Mode – The core, peripherals
high-performance applications which may need more
(except RTCC and DSWDT), Flash and SRAM
than an 8-bit platform, but do not require the power of a
are shut down for optimal current savings to
digital signal processor.
extend battery life for portable applications.
1.1 Core Features 1.1.3 OSCILLATOR OPTIONS AND

FEATURES
1.1.1 16-BIT ARCHITECTURE
All of the devices in the PIC24FJ64GA104 family offer
Central to all PIC24F devices is the 16-bit modified five different oscillator options, allowing users a range
Harvard architecture, first introduced with Microchip’s of choices in developing application hardware. These
dsPIC® digital signal controllers. The PIC24F CPU core include:
offers a wide range of enhancements, such as:
• Two Crystal modes using crystals or ceramic
• 16-bit data and 24-bit address paths with the resonators.
ability to move information between data and
• Two External Clock modes offering the option of a
memory spaces
divide-by-2 clock output.
• Linear addressing of up to 12 Mbytes (program
• A Fast Internal Oscillator (FRC) with a nominal
space) and 64 Kbytes (data)
8 MHz output, which can also be divided under
• A 16-element working register array with built-in software control to provide clock speeds as low as
software stack support 31 kHz.
• A 17 x 17 hardware multiplier with support for • A Phase Lock Loop (PLL) frequency multiplier
integer math available to the external oscillator modes and the
• Hardware support for 32 by 16-bit division FRC Oscillator, which allows clock speeds of up
• An instruction set that supports multiple to 32 MHz.
addressing modes and is optimized for high-level • A separate Low-Power Internal RC Oscillator
languages, such as ‘C’ (LPRC) with a fixed 31 kHz output, which pro-
• Operational performance up to 16 MIPS vides a low-power option for timing-insensitive
applications.
1.1.2 POWER-SAVING TECHNOLOGY The internal oscillator block also provides a stable
All of the devices in the PIC24FJ64GA104 family reference source for the Fail-Safe Clock Monitor. This
incorporate a range of features that can significantly option constantly monitors the main clock source
reduce power consumption during operation. Key against a reference signal provided by the internal
items include: oscillator and enables the controller to switch to the
• On-the-Fly Clock Switching: The device clock internal oscillator, allowing for continued low-speed
can be changed under software control to the operation or a safe application shutdown.
Timer1 source or the internal, Low-Power Internal
1.1.4 EASY MIGRATION
RC Oscillator during operation, allowing the user
to incorporate power-saving ideas into their Regardless of the memory size, all devices share the
software designs. same rich set of peripherals, allowing for a smooth
• Doze Mode Operation: When timing-sensitive migration path as applications grow and evolve. The
applications, such as serial communications, consistent pinout scheme used throughout the entire
require the uninterrupted operation of peripherals, family also aids in migrating from one device to the next
the CPU clock speed can be selectively reduced, larger device.
allowing incremental power savings without The PIC24F family is pin-compatible with devices in the
missing a beat. dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30 devices. This
extends the ability of applications to grow from the
relatively simple, to the powerful and complex, yet still
selecting a Microchip device.

1.2 Other Special Features 1.3 Details on Individual Family
• Peripheral Pin Select: The Peripheral Pin Select
Members
feature allows most digital peripherals to be Devices in the PIC24FJ64GA104 family are available
mapped over a fixed set of digital I/O pins. Users in 28-pin and 44-pin packages. The general block
may independently map the input and/or output of diagram for all devices is shown in Figure 1-1.
any one of the many digital peripherals to any one
The devices are differentiated from each other in
of the I/O pins.
several ways:
• Communications: The PIC24FJ64GA104 family
incorporates a range of serial communication • Flash Program Memory:
peripherals to handle a range of application - PIC24FJ32GA1 devices – 32 Kbytes
requirements. There are two independent I2C™ - PIC24FJ64GA1 devices – 64 Kbytes
modules that support both Master and Slave • Available I/O Pins and Ports:
modes of operation. Devices also have, through
- 28-pin devices – 21 pins on two ports
the Peripheral Pin Select (PPS) feature, two
independent UARTs with built-in IrDA® - 44-pin devices – 35 pins on three ports
encoder/decoders and two SPI modules. • Available Interrupt-on-Change Notification (ICN)
• Analog Features: All members of the Inputs:
PIC24FJ64GA104 family include a 10-bit A/D - 28-pin devices – 21
Converter module and a triple comparator - 44-pin devices – 31
module. The A/D module incorporates program- • Available Remappable Pins:
mable acquisition time, allowing for a channel to - 28-pin devices – 16 pins
be selected and a conversion to be initiated
- 44-pin devices – 26 pins
without waiting for a sampling period, as well as
faster sampling speeds. The comparator module • Available PMP Address Pins:
includes three analog comparators that are - 28-pin devices – 3 pins
configurable for a wide range of operations. - 44-pin devices – 12 pins
• CTMU Interface: This module provides a • Available A/D Input Channels:
convenient method for precision time measure- - 28-pin devices – 10 pins
ment and pulse generation, and can serve as an
- 44-pin devices – 13 pins
interface for capacitive sensors.
• Parallel Master/Enhanced Parallel Slave Port: All other features for devices in this family are identical.
One of the general purpose I/O ports can be These are summarized in Table 1-1.
reconfigured for enhanced parallel data communi- A list of the pin features available on the
cations. In this mode, the port can be configured PIC24FJ64GA104 family devices, sorted by function, is
for both master and slave operations, and shown in Table 1-2. Note that this table shows the pin
supports 8-bit and 16-bit data transfers with up to location of individual peripheral features and not how
12 external address lines in Master modes. they are multiplexed on the same pin. This information
• Real-Time Clock/Calendar: This module is provided in the pinout diagrams in the beginning of
implements a full-featured clock and calendar with this data sheet. Multiplexed features are sorted by the
alarm functions in hardware, freeing up timer priority given to a feature, with the highest priority
resources and program memory space for the use peripheral being listed first.
of the core application.

TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ64GA104 FAMILY
Features PIC24FJ32GA102 PIC24FJ64GA102 PIC24FJ32GA104 PIC24FJ64GA104
Operating Frequency DC – 32 MHz
Program Memory (bytes) 32K 64K 32K 64K
Program Memory (instructions) 11,008 22,016 11,008 22,016
Data Memory (bytes) 8,192
Interrupt Sources (soft vectors/ 45 (41/4)
NMI traps)
I/O Ports Ports A and B Ports A, B, C
Total I/O Pins 21 35
Remappable Pins 16 26
Timers:
Total Number (16-bit) 5(1)
32-Bit (from paired 16-bit timers) 2
Input Capture Channels 5(1)
Output Compare/PWM Channels 5(1)
Input Change Notification Interrupt 21 31
Serial Communications:
UART 2(1)
SPI (3-wire/4-wire) 2(1)
I2C™ 2
Parallel Communications (PMP/PSP) Yes
JTAG Boundary Scan Yes
10-Bit Analog-to-Digital Module 10 13
(input channels)
Analog Comparators 3
CTMU Interface Yes
Resets (and delays) POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode,
REPEAT Instruction, Hardware Traps, Configuration Word Mismatch
(PWRT, OST, PLL Lock)
Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations
Packages 28-Pin QFN, SOIC, SSOP and SPDIP 44-Pin QFN and TQFP
Note 1: Peripherals are accessible through remappable pins.

FIGURE 1-1: PIC24FJ64GA104 FAMILY GENERAL BLOCK DIAGRAM
Interrupt Data Bus

Controller
PORTA(1)
16
8 16 16 (9 I/O)
PSV & Table Data Latch

Data Access
Control Block PCH PCL Data RAM
23
Program Counter Address PORTB
Stack Repeat Latch
Control Control
Logic Logic (16 I/O)
16
23
16
Address Latch Read AGU

Write AGU
PORTC(1)
Program Memory
(10 I/O)
Data Latch
EA MUX 16
Address Bus
Literal Data
24 16 16
Inst Latch
RP(1)
Inst Register
RP0:RP25
Instruction
Decode &
Control
Divide
Control Signals Support
OSCO/CLKO 16 x 16
OSCI/CLKI W Reg Array
17 x 17
Timing Power-up Multiplier
Generation Timer
Oscillator
FRC/LPRC Start-up Timer
REFO
Oscillators 16-Bit ALU
Power-on
Reset
16
Precision
Band Gap Watchdog
Reference Timer
DISVREG BOR and
Voltage
Regulator LVD(2)
VDDCORE/VCAP VDD, VSS MCLR
10-Bit
Timer1 Timer2/3(3) Timer4/5(3) RTCC Comparators(3)
ADC
PMP/PSP
IC PWM/OC SPI I2C UART

ICNs(1) 1/2(3) CTMU
1-5(3) 1-5(3) 1/2 1/2(3)
Note 1: Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-2 for specific implementations by pin count.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
3: These peripheral I/Os are only accessible through remappable pins.

TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS
Pin Number
28-Pin 44-Pin Input

Function 28-Pin I/O Description
SPDIP/ QFN/ Buffer
QFN
SOIC/SSOP TQFP
AN0 2 27 19 I ANA A/D Analog Inputs.

AN1 3 28 20 I ANA
AN2 4 1 21 I ANA
AN3 5 2 22 I ANA
AN4 6 3 23 I ANA
AN5 7 4 24 I ANA
AN6 — — 25 I ANA
AN7 — — 26 I ANA
AN8 — — 27 I ANA
AN9 26 23 15 I ANA
AN10 25 22 14 I ANA
AN11 24 21 11 I ANA
AN12 23 20 10 I ANA
ASCL1 15 12 42 I/O I2C Alternate I2C1 Synchronous Serial Clock Input/Output.
2
ASDA1 14 11 41 I/O I C Alternate I2C1 Synchronous Serial Data Input/Output.
AVDD — — 17 P — Positive Supply for Analog modules.
AVSS — — 16 P — Ground Reference for Analog modules.
C1INA 7 4 24 I ANA Comparator 1 Input A.
C1INB 6 3 23 I ANA Comparator 1 Input B.
C1INC 24 21 11 I ANA Comparator 1 Input C.
C1IND 9 6 30 I ANA Comparator 1 Input D.
CLKI 9 6 30 I ANA Main Clock Input Connection.
CLKO 10 7 31 O — System Clock Output.
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C™ = I2C/SMBus input buffer

TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
28-Pin 44-Pin Input

SPDIP/ QFN/ Buffer
QFN
SOIC/SSOP TQFP
CN0 12 9 34 I ST Interrupt-on-Change Inputs.

CN1 11 8 33 I ST
CN2 2 27 19 I ST
CN3 3 28 20 I ST
CN4 4 1 21 I ST
CN5 5 2 22 I ST
CN6 6 3 23 I ST
CN7 7 4 24 I ST
CN8 — — 25 I ST
CN9 — — 26 I ST
CN10 — — 27 I ST
CN11 26 23 15 I ST
CN12 25 22 14 I ST
CN13 24 21 11 I ST
CN14 23 20 10 I ST
CN15 22 19 9 I ST
CN16 21 18 8 I ST
CN17 — — 3 I ST
CN18 — — 2 I ST
CN19 — — 5 I ST
CN20 — — 4 I ST
CN21 18 15 1 I ST
CN22 17 14 44 I ST
CN23 16 13 43 I ST
CN24 15 12 42 I ST
CN25 — — 37 I ST
CN26 — — 38 I ST
CN27 14 11 41 I ST
CN28 — — 36 I ST
CN29 10 7 31 I ST
CN30 9 6 30 I ST
CTED1 2 27 19 I ANA CTMU External Edge Input 1.
CTED2 3 28 20 I ANA CTMU External Edge Input 2.
CVREF 25 22 14 O — Comparator Voltage Reference Output.
DISVREG 19 16 6 I ST Voltage Regulator Disable.

Pin Number
28-Pin 44-Pin Input

SPDIP/ QFN/ Buffer
QFN
SOIC/SSOP TQFP
INT0 16 13 43 I ST External Interrupt Input.

MCLR 1 26 18 I ST Master Clear (device Reset) Input. This line is brought low to
cause a Reset.
OSCI 9 6 30 I ANA Main Oscillator Input Connection.
OSCO 10 7 31 O ANA Main Oscillator Output Connection.
PGEC1 5 2 22 I/O ST In-Circuit Debugger/Emulator/ICSP™ Programming Clock.
PGED1 4 1 21 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data.
PGEC2 22 19 9 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock.
PGEC3 15 12 42 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock.
PMA0 10 7 3 I/O ST Parallel Master Port Address Bit 0 Input (Buffered Slave
modes) and Output (Master modes).
PMA1 12 9 2 I/O ST Parallel Master Port Address Bit 1 Input (Buffered Slave
modes) and Output (Master modes).
PMA2 — — 27 O — Parallel Master Port Address (Demultiplexed Master modes).
PMA3 — — 38 O —
PMA4 — — 37 O —
PMA5 — — 4 O —
PMA6 — — 5 O —
PMA7 — — 13 O —
PMA8 — — 32 O —
PMA9 — — 35 O —
PMA10 — — 12 O —
PMCS1 26 23 15 I/O ST/TTL Parallel Master Port Chip Select 1 Strobe/Address Bit 15.
PMBE 11 8 36 O — Parallel Master Port Byte Enable Strobe.
PMD0 23 20 10 I/O ST/TTL Parallel Master Port Data (Demultiplexed Master mode) or
PMD1 22 19 9 I/O ST/TTL Address/Data (Multiplexed Master modes).
PMD2 21 18 8 I/O ST/TTL
PMRD 24 21 11 O — Parallel Master Port Read Strobe.
PMWR 25 22 14 O — Parallel Master Port Write Strobe.

Pin Number
28-Pin 44-Pin Input

SPDIP/ QFN/ Buffer
QFN
SOIC/SSOP TQFP
RA0 2 27 19 I/O ST PORTA Digital I/O.

RA1 3 28 20 I/O ST
RA2 9 6 30 I/O ST
RA3 10 7 31 I/O ST
RA4 12 9 34 I/O ST
RA7 — — 13 I/O ST
RA8 — — 32 I/O ST
RA9 — — 35 I/O ST
RA10 — — 12 I/O ST
RB0 4 1 21 I/O ST PORTB Digital I/O.
RB1 5 2 22 I/O ST
RB2 6 3 23 I/O ST
RB3 7 4 24 I/O ST
RB4 11 8 33 I/O ST
RB5 14 11 41 I/O ST
RB6 15 12 42 I/O ST
RB7 16 13 43 I/O ST
RB8 17 14 44 I/O ST
RB9 18 15 1 I/O ST
RB10 21 18 8 I/O ST
RB11 22 19 9 I/O ST
RB12 23 20 10 I/O ST
RB13 24 21 11 I/O ST
RB14 25 22 14 I/O ST
RB15 26 23 15 I/O ST
RC0 — — 25 I/O ST PORTC Digital I/O.
RC1 — — 26 I/O ST
RC2 — — 27 I/O ST
RC3 — — 36 I/O ST
RC4 — — 37 I/O ST
RC5 — — 38 I/O ST
RC6 — — 2 I/O ST
RC7 — — 3 I/O ST
RC8 — — 4 I/O ST
RC9 — — 5 I/O ST
REFO 24 21 11 O — Reference Clock Output.

Pin Number
28-Pin 44-Pin Input

SPDIP/ QFN/ Buffer
QFN
SOIC/SSOP TQFP
RP0 4 1 21 I/O ST Remappable Peripheral (input or output).

RP1 5 2 22 I/O ST
RP2 6 3 23 I/O ST
RP3 7 4 24 I/O ST
RP4 11 8 33 I/O ST
RP5 14 11 41 I/O ST
RP6 15 12 42 I/O ST
RP7 16 13 43 I/O ST
RP8 17 14 44 I/O ST
RP9 18 15 1 I/O ST
RP10 21 18 8 I/O ST
RP11 22 19 9 I/O ST
RP12 23 20 10 I/O ST
RP13 24 21 11 I/O ST
RP14 25 22 14 I/O ST
RP15 26 23 15 I/O ST
RP16 — — 25 I/O ST
RP17 — — 26 I/O ST
RP18 — — 27 I/O ST
RP19 — — 36 I/O ST
RP20 — — 37 I/O ST
RP21 — — 38 I/O ST
RP22 — — 2 I/O ST
RP23 — — 3 I/O ST
RP24 — — 4 I/O ST
RP25 — — 5 I/O ST
RTCC 25 22 14 O — Real-Time Clock Alarm/Seconds Pulse Output.
SCL1 17 14 44 I/O I2C I2C1 Synchronous Serial Clock Input/Output.
SCL2 7 4 24 I/O I2C I2C2 Synchronous Serial Clock Input/Output.
SDA1 18 15 1 I/O I2C I2C1 Data Input/Output.
SDA2 6 3 23 I/O I2C I2C2 Data Input/Output.
SOSCI 11 8 33 I ANA Secondary Oscillator/Timer1 Clock Input.
SOSCO 12 9 34 O ANA Secondary Oscillator/Timer1 Clock Output.
T1CK 12 9 34 I ST Timer1 Clock Input.
TCK 17 14 13 I ST JTAG Test Clock Input.
TDI 21 18 35 I ST JTAG Test Data Input.
TDO 18 15 32 O — JTAG Test Data Output.
TMS 22 19 12 I ST JTAG Test Mode Select Input.

Pin Number
28-Pin 44-Pin Input

SPDIP/ QFN/ Buffer
QFN
SOIC/SSOP TQFP
VCAP 20 17 7 P — External Filter Capacitor Connection (regulator enabled).

VDD 13, 28 10, 25 28, 40 P — Positive Supply for Peripheral Digital Logic and I/O Pins.
VDDCORE 20 17 7 P — Positive Supply for Microcontroller Core Logic (regulator
disabled).
VREF- 3 28 20 I ANA A/D and Comparator Reference Voltage (low) Input.
VREF+ 2 27 19 I ANA A/D and Comparator Reference Voltage (high) Input.
VSS 8, 27 5, 24 29, 39 P — Ground Reference for Logic and I/O Pins.

2.0 GUIDELINES FOR GETTING FIGURE 2-1: RECOMMENDED
STARTED WITH 16-BIT MINIMUM CONNECTIONS
MICROCONTROLLERS
C2(2)
2.1 Basic Connection Requirements VDD
Getting started with the PIC24FJ64GA104 family of
VDD
VSS
R1 (1) (1)
16-bit microcontrollers requires attention to a minimal R2
set of device pin connections before proceeding with (EN/DIS)VREG
MCLR
development. VCAP/VDDCORE
C1
The following pins must always be connected: C7
PIC24FXXXX
• All VDD and VSS pins
VDD
(see Section 2.2 “Power Supply Pins”) VSS
C6(2) C3(2)
• All AVDD and AVSS pins, regardless of whether or VSS
VDD
not the analog device features are used
AVDD
AVSS
VDD
VSS
(see Section 2.2 “Power Supply Pins”)
• MCLR pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
C5(2) C4(2)
• ENVREG/DISVREG and VCAP/VDDCORE pins
(PIC24FJ devices only)
(see Section 2.4 “Voltage Regulator Pins
Key (all values are recommendations):
(ENVREG/DISVREG and VCAP/VDDCORE)”)
C1 through C6: 0.1 F, 20V ceramic
These pins must also be connected if they are being
C7: 10 F, 6.3V or greater, tantalum or ceramic
used in the end application:
R1: 10 kΩ
• PGECx/PGEDx pins used for In-Circuit Serial
R2: 100Ω to 470Ω
Programming™ (ICSP™) and debugging purposes
Note 1: See Section 2.4 “Voltage Regulator Pins
(see Section 2.5 “ICSP Pins”)
(ENVREG/DISVREG and VCAP/VDDCORE)”
• OSCI and OSCO pins when an external oscillator for explanation of ENVREG/DISVREG pin
source is used connections.
(see Section 2.6 “External Oscillator Pins”) 2: The example shown is for a PIC24F device
Additionally, the following pins may be required: with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
• VREF+/VREF- pins used when external voltage adjust the number of decoupling capacitors
reference for analog modules is implemented appropriately.
Note: The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
The minimum mandatory connections are shown in
Figure 2-1.

2.2 Power Supply Pins 2.3 Master Clear (MCLR) Pin
2.2.1 DECOUPLING CAPACITORS The MCLR pin provides two specific device
functions: device Reset, and device programming
The use of decoupling capacitors on every pair of and debugging. If programming and debugging are
power supply pins, such as VDD, VSS, AVDD and not required in the end application, a direct
AVSS is required. connection to VDD may be all that is required. The
Consider the following criteria when using decoupling addition of other components, to help increase the
capacitors: application’s resistance to spurious Resets from
voltage sags, may be beneficial. A typical
• Value and type of capacitor: A 0.1 F (100 nF),
configuration is shown in Figure 2-1. Other circuit
10-20V capacitor is recommended. The capacitor
designs may be implemented, depending on the
should be a low-ESR device with a resonance
application’s requirements.
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended. During programming and debugging, the resistance
• Placement on the printed circuit board: The and capacitance that can be added to the pin must
decoupling capacitors should be placed as close be considered. Device programmers and debuggers
to the pins as possible. It is recommended to drive the MCLR pin. Consequently, specific voltage
place the capacitors on the same side of the levels (VIH and VIL) and fast signal transitions must
board as the device. If space is constricted, the not be adversely affected. Therefore, specific values
capacitor can be placed on another layer on the of R1 and C1 will need to be adjusted based on the
PCB using a via; however, ensure that the trace application and PCB requirements. For example, it is
length from the pin to the capacitor is no greater recommended that the capacitor, C1, be isolated
than 0.25 inch (6 mm). from the MCLR pin during programming and
debugging operations by using a jumper (Figure 2-2).
• Handling high-frequency noise: If the board is
The jumper is replaced for normal run-time
experiencing high-frequency noise (upward of
operations.
tens of MHz), add a second ceramic type capaci-
tor in parallel to the above described decoupling Any components associated with the MCLR pin
capacitor. The value of the second capacitor can should be placed within 0.25 inch (6 mm) of the pin.
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling FIGURE 2-2: EXAMPLE OF MCLR PIN
capacitor. In high-speed circuit designs, consider CONNECTIONS
implementing a decade pair of capacitances as
close to the power and ground pins as possible VDD
(e.g., 0.1 F in parallel with 0.001 F).
• Maximizing performance: On the board layout R1
from the power supply circuit, run the power and R2
return traces to the decoupling capacitors first, MCLR
and then to the device pins. This ensures that the PIC24FXXXX
JP
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length C1
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
Note 1: R1  10 k is recommended. A suggested
2.2.2 TANK CAPACITORS starting value is 10 k. Ensure that the
On boards with power traces running longer than six MCLR pin VIH and VIL specifications are met.
inches in length, it is suggested to use a tank capacitor 2: R2  470 will limit any current flowing into
for integrated circuits including microcontrollers to MCLR from the external capacitor, C, in the
supply a local power source. The value of the tank event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
capacitor should be determined based on the trace
Overstress (EOS). Ensure that the MCLR pin
resistance that connects the power supply source to
VIH and VIL specifications are met.
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.

2.4 Voltage Regulator Pins FIGURE 2-3: FREQUENCY vs. ESR
(ENVREG/DISVREG and PERFORMANCE FOR
VCAP/VDDCORE) SUGGESTED VCAP
10
Note: This section applies only to PIC24FJ
devices with an on-chip voltage regulator.
1
The on-chip voltage regulator enable/disable pin
(ENVREG or DISVREG, depending on the device
ESR ()
family) must always be connected directly to either a 0.1
supply voltage or to ground. The particular connection

is determined by whether or not the regulator is to be
0.01
used:
• For ENVREG, tie to VDD to enable the regulator,
0.001
or to ground to disable the regulator 0.01 0.1 1 10 100 1000 10,000
• For DISVREG, tie to ground to enable the Frequency (MHz)
regulator or to VDD to disable the regulator Note: Data for Murata GRM21BF50J106ZE01 shown.
Measurements at 25°C, 0V DC bias.
Refer to Section 25.2 “On-Chip Voltage Regulator”
for details on connecting and using the on-chip
regulator. 2.5 ICSP Pins
When the regulator is enabled, a low-ESR (<5Ω)
The PGECx and PGEDx pins are used for In-Circuit
capacitor is required on the VCAP/VDDCORE pin to
Serial Programming (ICSP) and debugging purposes.
stabilize the voltage regulator output voltage. The
It is recommended to keep the trace length between
VCAP/VDDCORE pin must not be connected to VDD, and
the ICSP connector and the ICSP pins on the device as
must use a capacitor of 10 F connected to ground. The
short as possible. If the ICSP connector is expected to
type can be ceramic or tantalum. A suitable example is
experience an ESD event, a series resistor is recom-
the Murata GRM21BF50J106ZE01 (10 F, 6.3V) or
mended, with the value in the range of a few tens of
equivalent. Designers may use Figure 2-3 to evaluate
ohms, not to exceed 100Ω.
ESR equivalence of candidate devices.
Pull-up resistors, series diodes and capacitors on the
The placement of this capacitor should be close to
PGECx and PGEDx pins are not recommended as they
VCAP/VDDCORE. It is recommended that the trace
will interfere with the programmer/debugger communi-
length not exceed 0.25 inch (6 mm). Refer to
cations to the device. If such discrete components are
Section 28.0 “Electrical Characteristics” for
an application requirement, they should be removed
additional information.
from the circuit during programming and debugging.
When the regulator is disabled, the VCAP/VDDCORE pin Alternatively, refer to the AC/DC characteristics and
must be tied to a voltage supply at the VDDCORE level. timing requirements information in the respective
Refer to Section 28.0 “Electrical Characteristics” for device Flash programming specification for information
information on VDD and VDDCORE. on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
For device emulation, ensure that the “Communication
Channel Select” (i.e., PGECx/PGEDx pins) programmed
into the device matches the physical connections for the
ICSP to the Microchip debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 26.0 “Development Support”.

2.6 External Oscillator Pins FIGURE 2-4: SUGGESTED PLACEMENT
OF THE OSCILLATOR
Many microcontrollers have options for at least two
CIRCUIT
oscillators: a high-frequency primary oscillator and a
low-frequency Secondary Oscillator (refer to Single-Sided and In-line Layouts:
Section 8.0 “Oscillator Configuration” for details).
Copper Pour Primary Oscillator
The oscillator circuit should be placed on the same (tied to ground) Crystal
side of the board as the device. Place the oscillator
DEVICE PINS
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side Primary OSCI
Oscillator
of the board.
C1 ` OSCO
Use a grounded copper pour around the oscillator cir-
cuit to isolate it from surrounding circuits. The C2 GND
grounded copper pour should be routed directly to the `
MCU ground. Do not run any signal traces or power SOSCO
traces inside the ground pour. Also, if using a two-sided
SOSC I
board, avoid any traces on the other side of the board Secondary
where the crystal is placed. Oscillator
Crystal `
Layout suggestions are shown in Figure 2-4. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With Sec Oscillator: C1 Sec Oscillator: C2
fine-pitch packages, it is not always possible to com-
pletely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored Fine-Pitch (Dual-Sided) Layouts:
ground layer. In all cases, the guard trace(s) must be
returned to ground. Top Layer Copper Pour
(tied to ground)
In planning the application’s routing and I/O assign-
ments, ensure that adjacent port pins and other signals Bottom Layer
in close proximity to the oscillator are benign (i.e., free Copper Pour
of high frequencies, short rise and fall times and other (tied to ground)
similar noise).
OSCO
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
C2
Application Notes, available at the corporate web site
Oscillator
(www.microchip.com): GND Crystal
• AN826, “Crystal Oscillator Basics and Crystal C1
Selection for rfPIC™ and PICmicro® Devices”
• AN849, “Basic PICmicro® Oscillator Design” OSCI
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
• AN949, “Making Your Oscillator Work”
DEVICE PINS

2.7 Configuration of Analog and If your application needs to use certain A/D pins as
Digital Pins During ICSP analog input pins during the debug session, the user
application must modify the appropriate bits during
Operations
initialization of the ADC module, as follows:
If an ICSP compliant emulator is selected as a debug- • For devices with an ADnPCFG register, clear the
ger, it automatically initializes all of the A/D input pins bits corresponding to the pin(s) to be configured
(ANx) as “digital” pins. Depending on the particular as analog. Do not change any other bits, particu-
device, this is done by setting all bits in the ADnPCFG larly those corresponding to the PGECx/PGEDx
register(s), or clearing all bit in the ANSx registers. pair, at any time.
All PIC24F devices will have either one or more • For devices with ANSx registers, set the bits
ADnPCFG registers or several ANSx registers (one for corresponding to the pin(s) to be configured as
each port); no device will have both. Refer to analog. Do not change any other bits, particularly
Section 21.0 “10-Bit High-Speed A/D Converter”) those corresponding to the PGECx/PGEDx pair,
for more specific information. at any time.
The bits in these registers that correspond to the A/D When a Microchip debugger/emulator is used as a
pins that initialized the emulator must not be changed programmer, the user application firmware must
by the user application firmware; otherwise, correctly configure the ADnPCFG or ANSx registers.
communication errors will result between the debugger Automatic initialization of this register is only done
and the device. during debugger operation. Failure to correctly
configure the register(s) will result in all A/D pins being
recognized as analog input pins, resulting in the port
value being read as a logic '0', which may affect user
application functionality.
2.8 Unused I/Os

Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.

NOTES:

3.0 CPU For most instructions, the core is capable of executing
a data (or program data) memory read, a working reg-
Note: This data sheet summarizes the features ister (data) read, a data memory write and a program
of this group of PIC24F devices. It is not (instruction) memory read per instruction cycle. As a
intended to be a comprehensive reference result, three parameter instructions can be supported,
source. For more information, refer to the allowing trinary operations (that is, A + B = C) to be
“PIC24F Family Reference Manual”, executed in a single cycle.
Section 2. “CPU” (DS39703). A high-speed, 17-bit by 17-bit multiplier has been
The PIC24F CPU has a 16-bit (data), modified Harvard included to significantly enhance the core arithmetic
architecture with an enhanced instruction set and a capability and throughput. The multiplier supports
24-bit instruction word with a variable length opcode Signed, Unsigned and Mixed mode, 16-bit by 16-bit or
field. The Program Counter (PC) is 23 bits wide and 8-bit by 8-bit integer multiplication. All multiply
addresses up to 4M instructions of user program instructions execute in a single cycle.
memory space. A single-cycle instruction prefetch The 16-bit ALU has been enhanced with integer divide
mechanism is used to help maintain throughput and assist hardware that supports an iterative non-restoring
provides predictable execution. All instructions execute divide algorithm. It operates in conjunction with the
in a single cycle, with the exception of instructions that REPEAT instruction looping mechanism and a selection
change the program flow, the double-word move of iterative divide instructions to support 32-bit (or
(MOV.D) instruction and the table instructions. 16-bit), divided by 16-bit, integer signed and unsigned
Overhead-free program loop constructs are supported division. All divide operations require 19 cycles to
using the REPEAT instructions, which are interruptible at complete, but are interruptible at any cycle boundary.
any point.
The PIC24F has a vectored exception scheme with up
PIC24F devices have sixteen, 16-bit working registers to 8 sources of non-maskable traps and up to 118 inter-
in the programmer’s model. Each of the working rupt sources. Each interrupt source can be assigned to
registers can act as a data, address or address offset one of seven priority levels.
register. The 16th working register (W15) operates as
A block diagram of the CPU is shown in Figure 3-1.
a Software Stack Pointer for interrupts and calls.
The upper 32 Kbytes of the data space memory map 3.1 Programmer’s Model
can optionally be mapped into program space at any
16K word boundary defined by the 8-bit Program Space The programmer’s model for the PIC24F is shown in
Visibility Page Address (PSVPAG) register. The program Figure 3-2. All registers in the programmer’s model are
to data space mapping feature lets any instruction memory mapped and can be manipulated directly by
access program space as if it were data space. instructions. A description of each register is provided
in Table 3-1. All registers associated with the
The Instruction Set Architecture (ISA) has been
programmer’s model are memory mapped.
significantly enhanced beyond that of the PIC18, but
maintains an acceptable level of backward compatibility.
All PIC18 instructions and addressing modes are
supported either directly or through simple macros.
Many of the ISA enhancements have been driven by
compiler efficiency needs.
The core supports Inherent (no operand), Relative,
Literal, Memory Direct and three groups of addressing
modes. All modes support Register Direct and various
Register Indirect modes. Each group offers up to seven
addressing modes. Instructions are associated with
predefined addressing modes depending upon their
functional requirements.

FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM
PSV & Table

Data Access
Control Block
Data Bus
Interrupt
Controller
16
8 16 16
Data Latch
23
PCH PCL Data RAM 16
23
Program Counter
Stack Loop Address
Control Control Latch
Logic Logic
23 16
RAGU
Address Latch WAGU
Program Memory
Address Bus EA MUX
Data Latch ROM Latch

24 16 16
Instruction Literal Data

Decode &
Control Instruction Reg
Control Signals
to Various Blocks Hardware
Multiplier 16 x 16
W Register Array
Divide
Support 16
16-Bit ALU
16
To Peripheral Modules

TABLE 3-1: CPU CORE REGISTERS
Register(s) Name Description
W0 through W15 Working Register Array
PC 23-Bit Program Counter
SR ALU STATUS Register
SPLIM Stack Pointer Limit Value Register
TBLPAG Table Memory Page Address Register
PSVPAG Program Space Visibility Page Address Register
RCOUNT Repeat Loop Counter Register
CORCON CPU Control Register
FIGURE 3-2: PROGRAMMER’S MODEL

15 0
W0 (WREG)
Divider Working Registers
W1
W2
Multiplier Registers
W3
W4
W5
W6
W7 Working/Address
W8 Registers
W9
W10
W11
W12
W13
W14 Frame Pointer
W15 Stack Pointer 0
SPLIM 0 Stack Pointer Limit

Value Register
22 0
PC 0 Program Counter
7 0
Table Memory Page
TBLPAG
Address Register
7 0
Program Space Visibility
PSVPAG Page Address Register
15 0
Repeat Loop Counter
RCOUNT
Register
15 SRH SRL 0
IPL
— — — — — — — DC
2 1 0 RA N OV Z C
ALU STATUS Register (SR)
15 0
— — — — — — — — — — — — IPL3 PSV — — CPU Control Register (CORCON)
Registers or bits shaded for PUSH.S and POP.S instructions.

3.2 CPU Control Registers
REGISTER 3-1: SR: ALU STATUS REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — DC
bit 15 bit 8
R/W-0(1) R/W-0(1) R/W-0(1) R-0 R/W-0 R/W-0 R/W-0 R/W-0

(2) (2)
IPL2 IPL1 IPL0(2) RA N OV Z C
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as ‘0’

bit 8 DC: ALU Half Carry/Borrow bit
1 = A carry out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry out from the 4th or 8th low-order bit of the result has occurred
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(1,2)
111 = CPU interrupt priority level is 7 (15); user interrupts disabled
110 = CPU interrupt priority level is 6 (14)
bit 4 RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3 N: ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2 OV: ALU Overflow bit
1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation
0 = No overflow has occurred
bit 1 Z: ALU Zero bit
1 = An operation which effects the Z bit has set it at some time in the past
0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result)
bit 0 C: ALU Carry/Borrow bit
1 = A carry out from the Most Significant bit of the result occurred
0 = No carry out from the Most Significant bit of the result occurred
Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
2: The IPL Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.

REGISTER 3-2: CORCON: CPU CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0

(1)
— — — — IPL3 PSV — —
bit 7 bit 0
Legend: C = Clearable bit


bit 3 IPL3: CPU Interrupt Priority Level Status bit(1)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
bit 2 PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
Note 1: User interrupts are disabled when IPL3 = 1.
3.3 Arithmetic Logic Unit (ALU) The PIC24F CPU incorporates hardware support for
both multiplication and division. This includes a
The PIC24F ALU is 16 bits wide and is capable of addi- dedicated hardware multiplier and support hardware
tion, subtraction, bit shifts and logic operations. Unless for 16-bit divisor division.
otherwise mentioned, arithmetic operations are 2’s
complement in nature. Depending on the operation, the 3.3.1 MULTIPLIER
ALU may affect the values of the Carry (C), Zero (Z),
The ALU contains a high-speed, 17-bit x 17-bit
Negative (N), Overflow (OV) and Digit Carry (DC)
multiplier. It supports unsigned, signed or mixed sign
Status bits in the SR register. The C and DC Status bits
operation in several multiplication modes:
operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations. 1. 16-bit x 16-bit signed
The ALU can perform 8-bit or 16-bit operations, 2. 16-bit x 16-bit unsigned
depending on the mode of the instruction that is used. 3. 16-bit signed x 5-bit (literal) unsigned
Data for the ALU operation can come from the W 4. 16-bit unsigned x 16-bit unsigned
register array, or data memory, depending on the 5. 16-bit unsigned x 5-bit (literal) unsigned
addressing mode of the instruction. Likewise, output
6. 16-bit unsigned x 16-bit signed
data from the ALU can be written to the W register array
or a data memory location. 7. 8-bit unsigned x 8-bit unsigned

3.3.2 DIVIDER 3.3.3 MULTI-BIT SHIFT SUPPORT
The divide block supports signed and unsigned integer The PIC24F ALU supports both single bit and
divide operations with the following data sizes: single-cycle, multi-bit arithmetic and logic shifts.
1. 32-bit signed/16-bit signed divide Multi-bit shifts are implemented using a shifter block,
capable of performing up to a 15-bit arithmetic right
2. 32-bit unsigned/16-bit unsigned divide
shift, or up to a 15-bit left shift, in a single cycle. All
3. 16-bit signed/16-bit signed divide multi-bit shift instructions only support Register Direct
4. 16-bit unsigned/16-bit unsigned divide Addressing for both the operand source and result
The quotient for all divide instructions ends up in W0 destination.
and the remainder in W1. Sixteen-bit signed and A full summary of instructions that use the shift
unsigned DIV instructions can specify any W register operation is provided below in Table 3-2.
for both the 16-bit divisor (Wn), and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
TABLE 3-2: INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION
Instruction Description
ASR Arithmetic shift right source register by one or more bits.
SL Shift left source register by one or more bits.
LSR Logical shift right source register by one or more bits.

4.0 MEMORY ORGANIZATION from either the 23-bit Program Counter (PC) during pro-
gram execution, or from table operation or data space
As Harvard architecture devices, PIC24F micro- remapping, as described in Section 4.3 “Interfacing
controllers feature separate program and data memory Program and Data Memory Spaces”.
spaces and busses. This architecture also allows the
User access to the program memory space is restricted
direct access of program memory from the data space
to the lower half of the address range (000000h to
during code execution.
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations which use TBLPAG<7> to permit access to
4.1 Program Address Space the Configuration bits and Device ID sections of the
The program address memory space of the configuration memory space.
PIC24FJ64GA104 family devices is 4M instructions. Memory maps for the PIC24FJ64GA104 family of
The space is addressable by a 24-bit value derived devices are shown in Figure 4-1.
FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ64GA104 FAMILY DEVICES
PIC24FJ32GA10X PIC24FJ64GA10X
GOTO Instruction GOTO Instruction 000000h

Reset Address Reset Address 000002h
000004h
Interrupt Vector Table Interrupt Vector Table
0000FEh
Reserved Reserved 000100h
000104h
Alternate Vector Table Alternate Vector Table
0001FEh
000200h
User Flash
Program Memory
(11K instructions)
User Flash
Program Memory
User Memory Space
Flash Config Words (22K instructions) 0057FEh

005800h
Flash Config Words 00ABFEh

Unimplemented 00AC00h
Read ‘0’
Unimplemented
Read ‘0’
7FFFFFh
800000h
Reserved Reserved
Configuration Memory Space
F7FFFEh
F80000h
Device Config Registers Device Config Registers
F8000Eh
F80010h
Reserved Reserved
FEFFFEh
FF0000h
DEVID (2) DEVID (2)
FFFFFFh
Note: Memory areas are not shown to scale.

4.1.1 PROGRAM MEMORY 4.1.3 FLASH CONFIGURATION WORDS
ORGANIZATION In PIC24FJ64GA104 family devices, the top four words
The program memory space is organized in of on-chip program memory are reserved for configura-
word-addressable blocks. Although it is treated as tion information. On device Reset, the configuration
24 bits wide, it is more appropriate to think of each information is copied into the appropriate Configuration
address of the program memory as a lower and upper registers. The addresses of the Flash Configuration
word, with the upper byte of the upper word being Word for devices in the PIC24FJ64GA104 family are
unimplemented. The lower word always has an even shown in Table 4-1. Their location in the memory map
address, while the upper word has an odd address is shown with the other memory vectors in Figure 4-1.
(Figure 4-2). The Configuration Words in program memory are a
Program memory addresses are always word-aligned compact format. The actual Configuration bits are
on the lower word and addresses are incremented or mapped in several different registers in the configuration
decremented by two during code execution. This memory space. Their order in the Flash Configuration
arrangement also provides compatibility with data Words do not reflect a corresponding arrangement in the
memory space addressing and makes it possible to configuration space. Additional details on the device
access data in the program memory space. Configuration Words are provided in Section 25.1
“Configuration Bits”.
4.1.2 HARD MEMORY VECTORS
All PIC24F devices reserve the addresses between TABLE 4-1: FLASH CONFIGURATION
00000h and 000200h for hard coded program execu- WORDS FOR PIC24FJ64GA104
tion vectors. A hardware Reset vector is provided to FAMILY DEVICES
redirect code execution from the default value of the
Program Configuration
PC on device Reset to the actual start of code. A GOTO
Device Memory Word
instruction is programmed by the user at 000000h with
(Words) Addresses
the actual address for the start of code at 000002h.
PIC24F devices also have two interrupt vector tables, 0057F8h:
PIC24FJ32GA1 11,008
located from 000004h to 0000FFh and 000100h to 0057FEh
0001FFh. These vector tables allow each of the many 00ABF8h:
PIC24FJ64GA1 22,016
device interrupt sources to be handled by separate 00ABFEh
ISRs. A more detailed discussion of the interrupt vector
tables is provided in Section 7.1 “Interrupt Vector
Table”.
FIGURE 4-2: PROGRAM MEMORY ORGANIZATION
MSW most significant word least significant word PC Address

Address (LSW Address)
23 16 8 0
000001h 00000000 000000h
000003h 00000000 000002h
000005h 00000000 000004h
000007h 00000000 000006h
Program Memory Instruction Width

‘Phantom’ Byte
(read as ‘0’)

4.2 Data Address Space PIC24FJ64GA104 family devices implement a total of
16 Kbytes of data memory. Should an EA point to a
The PIC24F core has a separate, 16-bit wide data mem- location outside of this area, an all zero word or byte will
ory space, addressable as a single linear range. The be returned.
data space is accessed using two Address Generation
Units (AGUs), one each for read and write operations. 4.2.1 DATA SPACE WIDTH
The data space memory map is shown in Figure 4-3.
The data memory space is organized in
All Effective Addresses (EAs) in the data memory space byte-addressable, 16-bit wide blocks. Data is aligned
are 16 bits wide and point to bytes within the data space. in data memory and registers as 16-bit words, but all
This gives a data space address range of 64 Kbytes or data space EAs resolve to bytes. The Least Significant
32K words. The lower half of the data memory space Bytes (LSBs) of each word have even addresses, while
(that is, when EA<15> = 0) is used for implemented the Most Significant Bytes (MSBs) have odd
memory addresses, while the upper half (EA<15> = 1) is addresses.
reserved for the program space visibility area (see
Section 4.3.3 “Reading Data from Program Memory
Using Program Space Visibility”).
FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24FJ64GA104 FAMILY DEVICES
MSB LSB
Address MSB LSB Address
0001h 0000h SFR
SFR Space
07FFh 07FEh Space
Near
0801h 0800h Data Space
1FFFh Data RAM 1FFEh
Implemented
2001h 2000h
Data RAM
27FFh 27FEh
2801h 2800h
Unimplemented
Read as ‘0’
7FFFh 7FFFh
8001h 8000h
Program Space
Visibility Area
FFFFh FFFEh
Note: Data memory areas are not shown to scale.

4.2.2 DATA MEMORY ORGANIZATION A Sign-Extend (SE) instruction is provided to allow
AND ALIGNMENT users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
To maintain backward compatibility with PIC® devices
can clear the MSB of any W register by executing a
and improve data space memory usage efficiency, the
Zero-Extend (ZE) instruction on the appropriate
PIC24F instruction set supports both word and byte
address.
operations. As a consequence of byte accessibility, all
Effective Address calculations are internally scaled to Although most instructions are capable of operating on
step through word-aligned memory. For example, the word or byte data sizes, it should be noted that some
core recognizes that Post-Modified Register Indirect instructions operate only on words.
Addressing mode [Ws++] will result in a value of Ws + 1
for byte operations and Ws + 2 for word operations. 4.2.3 NEAR DATA SPACE
Data byte reads will read the complete word which con- The 8-Kbyte area between 0000h and 1FFFh is
tains the byte using the LSb of any EA to determine referred to as the near data space. Locations in this
which byte to select. The selected byte is placed onto space are directly addressable via a 13-bit absolute
the LSB of the data path. That is, data memory and reg- address field within all memory direct instructions. The
isters are organized as two parallel, byte-wide entities remainder of the data space is indirectly addressable.
with shared (word) address decode, but separate write Additionally, the whole data space is addressable using
lines. Data byte writes only write to the corresponding MOV instructions, which support Memory Direct
side of the array or register which matches the byte Addressing with a 16-bit address field.
address.
4.2.4 SFR SPACE
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so The first 2 Kbytes of the near data space, from 0000h
care must be taken when mixing byte and word to 07FFh, are primarily occupied with Special Function
operations or translating from 8-bit MCU code. If a Registers (SFRs). These are used by the PIC24F core
misaligned read or write is attempted, an address error and peripheral modules for controlling the operation of
trap will be generated. If the error occurred on a read, the device.
the instruction underway is completed; if it occurred on SFRs are distributed among the modules that they
a write, the instruction will be executed but the write will control and are generally grouped together by module.
not occur. In either case, a trap is then executed, allow- Much of the SFR space contains unused addresses;
ing the system and/or user to examine the machine these are read as ‘0’. A diagram of the SFR space,
state prior to execution of the address Fault. showing where SFRs are actually implemented, is
All byte loads into any W register are loaded into the shown in Table 4-2. Each implemented area indicates
Least Significant Byte. The Most Significant Byte is not a 32-byte region where at least one address is
modified. implemented as an SFR. A complete listing of
implemented SFRs, including their addresses, is
shown in Tables 4-3 through 4-26.
TABLE 4-2: IMPLEMENTED REGIONS OF SFR DATA SPACE

SFR Space Address
xx00 xx20 xx40 xx60 xx80 xxA0 xxC0 xxE0

000h Core ICN Interrupts —
100h Timers Capture Compare —
200h I2C™ UART SPI — — — I/O
300h A/D A/D/CTMU — — — — — —
400h — — — — — — — —
500h — — — — — — — —
600h PMP RTCC CRC/Comp Comparators PPS —
700h — — System/DS NVM/PMD — — — —
Legend: — = No implemented SFRs in this block

TABLE 4-3: CPU CORE REGISTERS MAP
 2010 Microchip Technology Inc.
File All
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
WREG0 0000 Working Register 0 0000

WREG5 000A Working Register 5 0000
WREG6 000C Working Register 6 0000
WREG7 000E Working Register 7 0000
WREG13 001A Working Register 13 0000
WREG14 001C Working Register 14 0000
WREG15 001E Working Register 15 0800
SPLIM 0020 Stack Pointer Limit Value Register xxxx
PCL 002E Program Counter Low Word Register 0000
PCH 0030 — — — — — — — — Program Counter Register High Byte 0000
TBLPAG 0032 — — — — — — — — Table Memory Page Address Register 0000
PSVPAG 0034 — — — — — — — — Program Space Visibility Page Address Register 0000
RCOUNT 0036 Repeat Loop Counter Register xxxx
SR 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C 0000
CORCON 0044 — — — — — — — — — — — — IPL3 PSV — — 0000
DISICNT 0052 — — Disable Interrupts Counter Register xxxx
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS39951C-page 35
TABLE 4-4: ICN REGISTER MAP
DS39951C-page 36
File All
Name Resets
CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE(1) CN9IE(1) CN8IE(1) CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000
(1) (1) (1)
CNEN2 0062 — CN30IE CN29IE CN28IE CN27IE CN26IE CN25IE CN24IE CN23IE CN22IE CN21IE CN20IE(1) CN19IE(1) CN18IE(1) CN17IE(1) CN16IE 0000
CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE(1) CN9PUE(1) CN8PUE(1) CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000
CNPU2 006A — CN30PUE CN29PUE CN28PUE(1) CN27PUE CN26PUE(1) CN25PUE(1) CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE(1) CN19PUE(1) CN18PUE(1) CN17PUE(1) CN16PUE 0000
Note 1: Unimplemented in 28-pin devices; read as ‘0’.
TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP
All
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Resets
INTCON1 0080 NSTDIS — — — — — — — — — — MATHERR ADDRERR STKERR OSCFAIL — 0000

INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000
IFS0 0084 — — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000
IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF — — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000
IFS2 0088 — — PMPIF — — — OC5IF — IC5IF IC4IF IC3IF — — — SPI2IF SPF2IF 0000
IFS3 008A — RTCIF — — — — — — — — — — — MI2C2IF SI2C2IF — 0000
IFS4 008C — — CTMUIF — — — — LVDIF — — — — CRCIF U2ERIF U1ERIF — 0000
IEC0 0094 — — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000
IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE — — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000
IEC2 0098 — — PMPIE — — — OC5IE — IC5IE IC4IE IC3IE — — — SPI2IE SPF2IE 0000
IEC3 009A — RTCIE — — — — — — — — — — — MI2C2IE SI2C2IE — 0000
IEC4 009C — — CTMUIE — — — — LVDIE — — — — CRCIE U2ERIE U1ERIE — 0000
IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444
IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — — 4440
IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 4444
IPC3 00AA — — — — — — — — — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 0044
IPC4 00AC — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4444
IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004
IPC6 00B0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0 — — — — 4440
IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 4444
IPC8 00B4 — — — — — — — — — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 0044
IPC9 00B6 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0 — — — — 4440
IPC10 00B8 — — — — — — — — — OC5IP2 OC5IP1 OC5IP0 — — — — 0040
IPC11 00BA — — — — — — — — — PMPIP2 PMPIP1 PMPIP0 — — — — 0040
IPC12 00BC — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — 0440
IPC15 00C2 — — — — — RTCIP2 RTCIP1 RTCIP0 — — — — — — — — 0400
IPC16 00C4 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — 4440
IPC18 00C8 — — — — — — — — — — — — — LVDIP2 LVDIP1 LVDIP0 0004
IPC19 00CA — — — — — — — — — CTMUIP2 CTMUIP1 CTMUIP0 — — — — 0040
INTTREG 00E0 CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000
DS39951C-page 37
TABLE 4-6: TIMER REGISTER MAP
DS39951C-page 38
All
Resets
TMR1 0100 Timer1 Register 0000

PR1 0102 Timer1 Period Register FFFF
T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000
TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) 0000
TMR3 010A Timer3 Register 0000
PR2 010C Timer2 Period Register FFFF
PR3 010E Timer3 Period Register FFFF
T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000
T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000
TMR5HLD 0116 Timer5 Holding Register (for 32-bit operations only) 0000
PR4 011A Timer4 Period Register FFFF
PR5 011C Timer5 Period Register FFFF
T4CON 011E TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000
T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000
TABLE 4-7: INPUT CAPTURE REGISTER MAP
File All
Name Resets
IC1CON1 0140 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
IC1CON2 0142 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC1BUF 0144 Input Capture 1 Buffer Register 0000
IC1TMR 0146 Timer Value 1 Register xxxx
IC2CON2 014A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC2BUF 014C Input Capture 2 Buffer Register 0000
IC2TMR 014E Timer Value 2 Register xxxx
IC4CON2 015A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC4BUF 015C Input Capture 4 Buffer Register 0000
IC4TMR 015E Timer Value 4 Register xxxx
DS39951C-page 39
TABLE 4-8: OUTPUT COMPARE REGISTER MAP
DS39951C-page 40
All
Resets
OC1CON1 0190 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000
OC1CON2 0192 FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC1RS 0194 Output Compare 1 Secondary Register 0000
OC1R 0196 Output Compare 1 Register 0000
OC1TMR 0198 Timer Value 1 Register xxxx
OC2CON1 019A — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000
OC2CON2 019C FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC2RS 019E Output Compare 2 Secondary Register 0000
OC2R 01A0 Output Compare 2 Register 0000
OC2TMR 01A2 Timer Value 2 Register xxxx
OC3CON1 01A4 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000
OC3CON2 01A6 FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC3RS 01A8 Output Compare 3 Secondary Register 0000
OC3R 01AA Output Compare 3 Register 0000
OC3TMR 01AC Timer Value 3 Register xxxx
OC4CON1 01AE — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000
OC4CON2 01B0 FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC4RS 01B2 Output Compare 4 Secondary Register 0000
OC4R 01B4 Output Compare 4 Register 0000
OC4TMR 01B6 Timer Value 4 Register xxxx
OC5CON1 01B8 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000
OC5CON2 01BA FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC5RS 01BC Output Compare 5 Secondary Register 0000
OC5R 01BE Output Compare 5 Register 0000
OC5TMR 01C0 Timer Value 5 Register xxxx
TABLE 4-9: I2C™ REGISTER MAP
All
Resets
I2C1RCV 0200 — — — — — — — — Receive Register 0000

I2C1TRN 0202 — — — — — — — — Transmit Register 00FF
I2C1BRG 0204 — — — — — — — Baud Rate Generator Register 0000
I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000
I2C1ADD 020A — — — — — — Address Register 0000
I2C1MSK 020C — — — — — — Address Mask Register 0000
I2C2RCV 0210 — — — — — — — — Receive Register 0000
I2C2TRN 0212 — — — — — — — — Transmit Register 00FF
I2C2BRG 0214 — — — — — — — Baud Rate Generator Register 0000
I2C2CON 0216 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
I2C2STAT 0218 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000
I2C2ADD 021A — — — — — — Address Register 0000
I2C2MSK 021C — — — — — — Address Mask Register 0000
TABLE 4-10: UART REGISTER MAPS
All
Resets
U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000
U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110
U1TXREG 0224 — — — — — — — Transmit Register xxxx
U1RXREG 0226 — — — — — — — Receive Register 0000
U1BRG 0228 Baud Rate Generator Prescaler Register 0000
U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000
U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110
U2TXREG 0234 — — — — — — — Transmit Register xxxx
U2RXREG 0236 — — — — — — — Receive Register 0000
U2BRG 0238 Baud Rate Generator Prescaler Register 0000
DS39951C-page 41
TABLE 4-11: SPI REGISTER MAPS
DS39951C-page 42
All
Resets
SPI1STAT 0240 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000
SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000
SPI1CON2 0244 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN 0000
SPI1BUF 0248 Transmit and Receive Buffer 0000
SPI2STAT 0260 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000
SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000
SPI2CON2 0264 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN 0000
SPI2BUF 0268 Transmit and Receive Buffer 0000
TABLE 4-12: PORTA REGISTER MAP

File All
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10(1) Bit 9(1) Bit 8(1) Bit 7(1) Bit 6 Bit 5 Bit 4 Bit 3 Bit2 Bit 1 Bit 0
Name Resets
TRISA 02C0 — — — — — TRISA10 TRISA9 TRISA8 TRISA7 — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 079F
PORTA 02C2 — — — — — RA10 RA9 RA8 RA7 — — RA4 RA3 RA2 RA1 RA0 xxxx
LATA 02C4 — — — — — LATA10 LATA9 LATA8 LATA7 — — LATA4 LATA3 LATA2 LATA1 LATA0 xxxx
ODCA 02C6 — — — — — ODA10 ODA9 ODA8 ODA7 — — ODA4 ODA3 ODA2 ODA1 ODA0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 44-pin devices.
Note 1: Bits are unimplemented in 28-pin devices; read as ‘0’.
TABLE 4-13: PORTB REGISTER MAP

File All
Name Resets
TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 EFBF
PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx
LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx
ODCB 02CE ODB15 ODB14 ODB13 ODB12 ODB11 ODB10 ODB9 ODB8 ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 0000
TABLE 4-14: PORTC REGISTER MAP

File All
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9(1) Bit 8(1) Bit 7(1) Bit 6(1) Bit 5(1) Bit 4(1) Bit 3(1) Bit 2(1) Bit 1(2(1) Bit 0(1)
Name Resets
TRISC 02D0 — — — — — — TRISC9 TRISC8 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 03FF
PORTC 02D2 — — — — — — RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx
LATC 02D4 — — — — — — LATC9 LATC8 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx
ODCC 02D6 — — — — — — ODC9 ODC8 ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 44-pin devices.
Note 1: Bits are unimplemented in 28-pin devices; read as ‘0’.
TABLE 4-15: PAD CONFIGURATION REGISTER MAP
All
Resets
PADCFG1 02FC — — — — — — — — — — — — — RTSECSEL1 RTSECSEL0 PMPTTL 0000

TABLE 4-16: ADC REGISTER MAP

All
Resets
ADC1BUF0 0300 ADC Data Buffer 0 xxxx

ADC1BUF5 030A ADC Data Buffer 5 xxxx
ADC1BUF6 030C ADC Data Buffer 6 xxxx
ADC1BUF7 030E ADC Data Buffer 7 xxxx
ADC1BUFA 0314 ADC Data Buffer 10 xxxx
ADC1BUFB 0316 ADC Data Buffer 11 xxxx
ADC1BUFC 0318 ADC Data Buffer 12 xxxx
ADC1BUFD 031A ADC Data Buffer 13 xxxx
ADC1BUFE 031C ADC Data Buffer 14 xxxx
ADC1BUFF 031E ADC Data Buffer 15 xxxx
AD1CON1 0320 ADON — ADSIDL — — — FORM1 FORM0 SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE 0000
AD1CON2 0322 VCFG2 VCFG1 VCFG0 r — CSCNA — — BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS 0000
AD1CON3 0324 ADRC r r SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000
AD1CHS 0328 CH0NB — — CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA — — CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 0000
AD1PCFG 032C PCFG15 PCFG14 PCFG13 PCFG12(1) PCFG11 PCFG10 PCFG9 PCFG8(1) PCFG7(1) PCFG6(1) PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000
(1) CSSL8(1) CSSL7(1) CSSL6(1)
AD1CSSL 0330 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000
Legend: — = unimplemented, read as ‘0’, r = reserved, maintain as ‘0’. Reset values are shown in hexadecimal.
Note 1: Bits are not available on 28-pin devices; read as ‘0’.
TABLE 4-17: CTMU REGISTER MAP

DS39951C-page 43
All
Resets
CTMUCON 033C CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 0000
CTMUICON 033E ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 — — — — — — — — 0000
DS39951C-page 44
TABLE 4-18: PARALLEL MASTER/SLAVE PORT REGISTER MAP
All
Resets
PMCON 0600 PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN CSF1 CSF0 ALP — CS1P BEP WRSP RDSP 0000
PMMODE 0602 BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0 0000
PMADDR 0604 — CS1 — — — ADDR10(1) ADDR9(1) ADDR8(1) ADDR7(1) ADDR6(1) ADDR5(1) ADDR4(1) ADDR3(1) ADDR2(1) ADDR1 ADDR0 0000
PMDOUT1 Parallel Port Data Out Register 1 (Buffers 0 and 1) 0000
PMDOUT2 0606 Parallel Port Data Out Register 2 (Buffers 2 and 3) 0000
PMDIN1 0608 Parallel Port Data In Register 1 (Buffers 0 and 1) 0000
PMDIN2 060A Parallel Port Data In Register 2 (Buffers 2 and 3) 0000
PMAEN 060C — PTEN14 — — — PTEN10(1) PTEN9(1) PTEN8(1) PTEN7(1) PTEN6(1) PTEN5(1) PTEN4(1) PTEN3(1) PTEN2(1) PTEN1 PTEN0 0000
PMSTAT 060E IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E OB1E OB0E 0000
Note 1: Bits are not available on 28-pin devices; read as ‘0’.
TABLE 4-19: REAL-TIME CLOCK AND CALENDAR REGISTER MAP

All
Resets
ALRMVAL 0620 Alarm Value Register Window Based on ALRMPTR<1:0> xxxx

ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000
RTCVAL 0624 RTCC Value Register Window Based on RTCPTR<1:0> xxxx
RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 xxxx
TABLE 4-20: CRC REGISTER MAP

All
Resets
CRCCON1 0640 CRCEN — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — 0000
CRCCON2 0642 — — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 — — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0 0000
CRCXORL 0644 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 — 0000

CRCXORH 0646 X31 X30 X29 X28 X27 X26 X25 X24 X23 X22 X21 X20 X19 X19 X17 X16 0000
CRCDATL 0648 CRC Data Input Register Low Word xxxx
CRCDATH 064A CRC Data Input Register High Word xxxx
CRCWDATL 064C CRC Result Register Low Word xxxx
CRCWDATH 064E CRC Result Register High Word xxxx
TABLE 4-21: COMPARATORS REGISTER MAP
All
Resets
CMSTAT 0650 CMIDL — — — — C3EVT C2EVT C1EVT — — — — — C3OUT C2OUT C1OUT 0000
CVRCON 0652 — — — — — CVREFP CVREFM1 CVREFM0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000
CM1CON 0654 CEN COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000
CM2CON 065C CEN COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000
CM3CON 0664 CEN COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000
TABLE 4-22: PERIPHERAL PIN SELECT REGISTER MAP

All
Resets
RPINR0 0680 — — — INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 — — — — — — — — 1F00

RPINR1 0682 — — — — — — — — — — — INT2R4 INT2R3 INT2R2 INT2R1 INT2R0 001F
RPINR3 0686 — — — T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 — — — T2CKR4 T2CKR3 T2CKR2 T2CKR1 T2CKR0 1F1F
RPINR4 0688 — — — T5CKR4 T5CKR3 T5CKR2 T5CKR1 T5CKR0 — — — T4CKR4 T4CKR3 T4CKR2 T4CKR1 T4CKR0 1F1F
RPINR7 068E — — — IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 — — — IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 1F1F
RPINR8 0690 — — — IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 — — — IC3R4 IC3R3 IC3R2 IC3R1 IC3R0 1F1F
RPINR9 0692 — — — — — — — — — — — IC5R4 IC5R3 IC5R2 IC5R1 IC5R0 001F
RPINR11 0696 — — — OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0 — — — OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0 1F1F
RPINR18 06A4 — — — U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 — — — U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 1F1F
RPINR19 06A6 — — — U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 — — — U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0 1F1F
RPINR20 06A8 — — — SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 — — — SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 1F1F
RPINR21 06AA — — — — — — — — — — — SS1R4 SS1R3 SS1R2 SS1R1 SS1R0 001F
RPINR22 06AC — — — SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 — — — SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 1F1F
RPINR23 06AE — — — — — — — — — — — SS2R4 SS2R3 SS2R2 SS2R1 SS2R0 001F
RPOR0 06C0 — — — RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 — — — RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 0000
RPOR5 06CA — — — RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 — — — RP10R4 RP10R3 RP10R2 RP10R1 RP10R0 0000
RPOR6 06CC — — — RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 — — — RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 0000
RPOR7 06CE — — — RP15R4 RP15R3 RP15R2 RP15R1 RP15R0 — — — RP14R4 RP14R3 RP14R2 RP14R1 RP14R0 0000
RPOR8(1) 06D0 — — — RP17R4 RP17R3 RP17R2 RP17R1 RP17R0 — — — RP16R4 RP16R3 RP16R2 RP16R1 RP16R0
DS39951C-page 45
0000
RPOR9(1) 06D2 — — — RP19R4 RP19R3 RP19R2 RP19R1 RP19R0 — — — RP18R4 RP18R3 RP18R2 RP18R1 RP18R0 0000
Note 1: Registers are unimplemented in 28-pin devices; read as ‘0’.
TABLE 4-23: SYSTEM REGISTER MAP
DS39951C-page 46
All
Resets
RCON 0740 TRAPR IOPUWR — — — DPSLP CM PMSLP EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Note 1
OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK — CF POSCEN SOSCEN OSWEN Note 2
CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 — — — — — — — — 0100
OSCTUN 0748 — — — — — — — — — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000
REFOCON 074E ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 — — — — — — — — 0000
Note 1: The Reset value of the RCON register is dependent on the type of Reset event. See Section 6.0 “Resets” for more information.
2: The Reset value of the OSCCON register is dependent on both the type of Reset event and the device configuration. See Section 8.0 “Oscillator Configuration” for more information.
TABLE 4-24: DEEP SLEEP REGISTER MAP

All
Resets(1)
DSCON 758 DSEN — — — — — — — — — — — — — DSBOR RELEASE 0000

DSWAKE 075A — — — — — — — DSINT0 DSFLT — — DSWDT DSRTC DSMCLR — DSPOR 0001
DSGPR0 075C Deep Sleep General Purpose Register 0 0000
DSGPR1 075E Deep Sleep General Purpose Register 1 0000
Note 1: The Deep Sleep registers are only reset on a VDD POR event.
TABLE 4-25: NVM REGISTER MAP

All
Resets
NVMCON 0760 WR WREN WRERR — — — — — — ERASE — — NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1)
NVMKEY 0766 — — — — — — — — NVMKEY Register<7:0> 0000
Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-26: PMD REGISTER MAP

All
Resets
PMD1 0770 T5MD T4MD T3MD T2MD T1MD — — — I2C1MD U2MD U1MD SPI2MD SPI1MD — — ADC1MD 0000
PMD2 0772 — — — IC5MD IC4MD IC3MD IC2MD IC1MD — — — OC5MD OC4MD OC3MD OC2MD OC1MD 0000
PMD3 0774 — — — — — CMPMD RTCCMD PMPMD CRCMD — — — — — I2C2MD — 0000
PMD4 0776 — — — — — — — — — — — — REFOMD CTMUMD LVDMD — 0000
4.2.5 SOFTWARE STACK 4.3 Interfacing Program and Data
In addition to its use as a working register, the W15 Memory Spaces
register in PIC24F devices is also used as a Software The PIC24F architecture uses a 24-bit wide program
Stack Pointer. The pointer always points to the first space and a 16-bit wide data space. The architecture is
available free word and grows from lower to higher also a modified Harvard scheme, meaning that data
addresses. It predecrements for stack pops and can also be present in the program space. To use this
post-increments for stack pushes, as shown in data successfully, it must be accessed in a way that
Figure 4-4. Note that for a PC push during any CALL preserves the alignment of information in both spaces.
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear. Aside from normal execution, the PIC24F architecture
provides two methods by which program space can be
Note: A PC push during exception processing accessed during operation:
will concatenate the SRL register to the
• Using table instructions to access individual bytes
MSB of the PC prior to the push.
or words anywhere in the program space
The Stack Pointer Limit Value (SPLIM) register, associ- • Remapping a portion of the program space into
ated with the Stack Pointer, sets an upper address the data space (program space visibility)
boundary for the stack. SPLIM is uninitialized at Reset.
As is the case for the Stack Pointer, SPLIM<0> is Table instructions allow an application to read or write
forced to ‘0’ because all stack operations must be to small areas of the program memory. This makes the
word-aligned. Whenever an EA is generated using method ideal for accessing data tables that need to be
W15 as a source or destination pointer, the resulting updated from time to time. It also allows access to all
address is compared with the value in SPLIM. If the bytes of the program word. The remapping method
contents of the Stack Pointer (W15) and the SPLIM allows an application to access a large block of data on
register are equal, and a push operation is performed, a read-only basis, which is ideal for look-ups from a
a stack error trap will not occur. The stack error trap will large table of static data; it can only access the least
occur on a subsequent push operation. Thus, for significant word of the program word.
example, if it is desirable to cause a stack error trap
4.3.1 ADDRESSING PROGRAM SPACE
when the stack grows beyond address 2000h in RAM,
initialize the SPLIM with the value, 1FFEh. Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
Similarly, a Stack Pointer underflow (stack error) trap is
needed to create a 23-bit or 24-bit program address
generated when the Stack Pointer address is found to
from 16-bit data registers. The solution depends on the
be less than 0800h. This prevents the stack from
interface method to be used.
interfering with the Special Function Register (SFR)
space. For table operations, the 8-bit Table Memory Page
Address (TBLPAG) register is used to define a 32K word
A write to the SPLIM register should not be immediately
region within the program space. This is concatenated
followed by an indirect read operation using W15.
with a 16-bit EA to arrive at a full 24-bit program space
address. In this format, the Most Significant bit of
FIGURE 4-4: CALL STACK FRAME TBLPAG is used to determine if the operation occurs in
0000h the user memory (TBLPAG<7> = 0) or the configuration
15 0
memory (TBLPAG<7> = 1).
For remapping operations, the 8-bit Program Space
Visibility Page Address (PSVPAG) register is used to
Stack Grows Towards
Higher Address
define a 16K word page in the program space. When

the Most Significant bit of the EA is ‘1’, PSVPAG is con-
PC<15:0> W15 (before CALL) catenated with the lower 15 bits of the EA to form a
000000000 PC<22:16> 23-bit program space address. Unlike table operations,
<Free Word> W15 (after CALL) this limits remapping operations strictly to the user
memory area.
POP : [--W15]
PUSH : [W15++] Table 4-27 and Figure 4-5 show how the program EA is
created for table operations and remapping accesses
from the data EA. Here, P<23:0> refers to a program
space word, whereas D<15:0> refers to a data space
word.

TABLE 4-27: PROGRAM SPACE ADDRESS CONSTRUCTION
Access Program Space Address
Access Type
Space <23> <22:16> <15> <14:1> <0>
Instruction Access User 0 PC<22:1> 0
(Code Execution) 0xx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0>
(Byte/Word Read/Write) 0xxx xxxx xxxx xxxx xxxx xxxx
Configuration TBLPAG<7:0> Data EA<15:0>
1xxx xxxx xxxx xxxx xxxx xxxx
Program Space Visibility User 0 PSVPAG<7:0> Data EA<14:0>(1)
(Block Remap/Read) 0 xxxx xxxx xxx xxxx xxxx xxxx
Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG<0>.
FIGURE 4-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1) 0 Program Counter 0
23 Bits
EA 1/0
Table Operations(2) 1/0 TBLPAG
8 Bits 16 Bits
24 Bits
Select
1 EA 0
Program Space Visibility(1)
(Remapping)
0 PSVPAG
8 Bits 15 Bits
23 Bits
User/Configuration Byte Select

Space Select
Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of
data in the program and data spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted in the
configuration memory space.

4.3.2 DATA ACCESS FROM PROGRAM 2. TBLRDH (Table Read High): In Word mode, it
MEMORY USING TABLE maps the entire upper word of a program address
INSTRUCTIONS (P<23:16>) to a data address. Note that
D<15:8>, the ‘phantom’ byte, will always be ‘0’.
The TBLRDL and TBLWTL instructions offer a direct
In Byte mode, it maps the upper or lower byte of
method of reading or writing the lower word of any
the program word to D<7:0> of the data
address within the program space without going through
address, as above. Note that the data will
data space. The TBLRDH and TBLWTH instructions are
always be ‘0’ when the upper ‘phantom’ byte is
the only method to read or write the upper 8 bits of a
selected (byte select = 1).
program space word as data.
In a similar fashion, two table instructions, TBLWTH
The PC is incremented by two for each successive
and TBLWTL, are used to write individual bytes or
24-bit program word. This allows program memory
words to a program space address. The details of
addresses to directly map to data space addresses.
their operation are explained in Section 5.0 “Flash
Program memory can thus be regarded as two, 16-bit
Program Memory”.
word-wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL For all table operations, the area of program memory
access the space which contains the least significant space to be accessed is determined by the Table
data word, and TBLRDH and TBLWTH access the space Memory Page Address register (TBLPAG). TBLPAG
which contains the upper data byte. covers the entire program memory space of the
device, including user and configuration spaces. When
Two table instructions are provided to move byte or
TBLPAG<7> = 0, the table page is located in the user
word-sized (16-bit) data to and from program space.
memory space. When TBLPAG<7> = 1, the page is
Both function as either byte or word operations.
located in configuration space.
1. TBLRDL (Table Read Low): In Word mode, it
maps the lower word of the program space Note: Only table read operations will execute in
location (P<15:0>) to a data address (D<15:0>). the configuration memory space, and only
then, in implemented areas, such as the
In Byte mode, either the upper or lower byte of
Device ID. Table write operations are not
the lower program word is mapped to the lower
allowed.
byte of a data address. The upper byte is
selected when the byte select is ‘1’; the lower
byte is selected when it is ‘0’.
FIGURE 4-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

Program Space
TBLPAG
Data EA<15:0>
02
23 15 0
000000h 23 16 8 0
00000000
00000000
020000h
00000000
030000h
00000000
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
The address for the table operation is determined by the data EA

within the page defined by the TBLPAG register.
800000h
Only read operations are shown; write operations are also valid in
the user memory area.

4.3.3 READING DATA FROM PROGRAM 24-bit program word are used to contain the data. The
MEMORY USING PROGRAM SPACE upper 8 bits of any program space locations used as
VISIBILITY data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
The upper 32 Kbytes of data space may optionally be issues should the area of code ever be accidentally
mapped into any 16K word page of the program space. executed.
This provides transparent access of stored constant
data from the data space without the need to use Note: PSV access is temporarily disabled during
special instructions (i.e., TBLRDL/H). table reads/writes.
Program space access through the data space occurs if For operations that use PSV and are executed outside
the Most Significant bit (MSb) of the data space EA is ‘1’ a REPEAT loop, the MOV and MOV.D instructions will
and program space visibility is enabled by setting the require one instruction cycle in addition to the specified
PSV bit in the CPU Control register (CORCON<2>). The execution time. All other instructions will require two
location of the program memory space to be mapped instruction cycles in addition to the specified execution
into the data space is determined by the Program Space time.
Visibility Page Address register (PSVPAG). This 8-bit For operations that use PSV which are executed inside
register defines any one of 256 possible pages of a REPEAT loop, there will be some instances that
16K words in program space. In effect, PSVPAG func- require two instruction cycles in addition to the
tions as the upper 8 bits of the program memory specified execution time of the instruction:
address, with the 15 bits of the EA functioning as the
lower bits. Note that by incrementing the PC by 2 for • Execution in the first iteration
each program memory word, the lower 15 bits of data • Execution in the last iteration
space addresses directly map to the lower 15 bits in the • Execution prior to exiting the loop due to an
corresponding program space addresses. interrupt
Data reads to this area add an additional cycle to the • Execution upon re-entering the loop after an
instruction being executed, since two program memory interrupt is serviced
fetches are required. Any other iteration of the REPEAT loop will allow the
Although each data space address, 8000h and higher, instruction accessing data, using PSV, to execute in a
maps directly into a corresponding program memory single cycle.
address (see Figure 4-7), only the lower 16 bits of the
FIGURE 4-7: PROGRAM SPACE VISIBILITY OPERATION

When CORCON<2> = 1 and EA<15> = 1:
Program Space Data Space

PSVPAG 23 15 0
000000h 0000h
02 Data EA<14:0>
010000h
018000h
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory 8000h
space....
PSV Area
...while the lower
15 bits of the EA
specify an exact
FFFFh address within the
PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
800000h
space address.

5.0 FLASH PROGRAM MEMORY RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
Note: This data sheet summarizes the features may write program memory data in blocks of 64 instruc-
of this group of PIC24F devices. It is not tions (192 bytes) at a time and erase program memory
intended to be a comprehensive reference in blocks of 512 instructions (1536 bytes) at a time.
source. For more information, refer to the
“PIC24F Family Reference Manual”, 5.1 Table Instructions and Flash
Section 4. “Program Memory” Programming
(DS39715).
Regardless of the method used, all programming of
The PIC24FJ64GA104 family of devices contains inter-
Flash memory is done with the table read and table
nal Flash program memory for storing and executing
write instructions. These allow direct read and write
application code. The memory is readable, writable and
access to the program memory space from the data
erasable when operating with VDD over 2.35V. (If the
memory while the device is in normal operating mode.
regulator is disabled, VDDCORE must be over 2.25V.)
The 24-bit target address in the program memory is
It can be programmed in four ways: formed using the TBLPAG<7:0> bits and the Effective
• In-Circuit Serial Programming™ (ICSP™) Address (EA) from a W register specified in the table
instruction, as shown in Figure 5-1.
• Run-Time Self-Programming (RTSP)
• Enhanced In-Circuit Serial Programming The TBLRDL and the TBLWTL instructions are used to
(Enhanced ICSP) read or write to bits<15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
ICSP allows a PIC24FJ64GA104 family device to be both Word and Byte modes.
serially programmed while in the end application circuit.
This is simply done with two lines for the programming The TBLRDH and TBLWTH instructions are used to read
clock and programming data (which are named PGECx or write to bits<23:16> of program memory. TBLRDH
and PGEDx, respectively), and three other lines for and TBLWTH can also access program memory in Word
power (VDD), ground (VSS) and Master Clear (MCLR). or Byte mode.
This allows customers to manufacture boards with
unprogrammed devices and then program the micro-
controller just before shipping the product. This also
allows the most recent firmware or a custom firmware
to be programmed.
FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS
24 Bits
Using
Program 0 Program Counter 0
Counter
Working Reg EA
Using 1/0 TBLPAG Reg

Table
Instruction
8 Bits 16 Bits
User/Configuration Byte
Space Select 24-Bit EA Select

5.2 RTSP Operation 5.3 JTAG Operation
The PIC24F Flash program memory array is organized The PIC24F family supports JTAG boundary scan.
into rows of 64 instructions or 192 bytes. RTSP allows Boundary scan can improve the manufacturing
the user to erase blocks of eight rows (512 instructions) process by verifying pin to PCB connectivity.
at a time and to program one row at a time. It is also
possible to program single words. 5.4 Enhanced In-Circuit Serial
The 8-row erase blocks and single row write blocks are Programming
edge-aligned, from the beginning of program memory, on
boundaries of 1536 bytes and 192 bytes, respectively. Enhanced In-Circuit Serial Programming uses an
on-board bootloader, known as the program executive,
When data is written to program memory using TBLWT to manage the programming process. Using an SPI
instructions, the data is not written directly to memory. data frame format, the program executive can erase,
Instead, data written using table writes is stored in program and verify program memory. For more
holding latches until the programming sequence is information on Enhanced ICSP, see the device
executed. programming specification.
Any number of TBLWT instructions can be executed
and a write will be successfully performed. However, 5.5 Control Registers
64 TBLWT instructions are required to write the full row
of memory. There are two SFRs used to read and write the
program Flash memory: NVMCON and NVMKEY.
To ensure that no data is corrupted during a write, any
unused addresses should be programmed with The NVMCON register (Register 5-1) controls which
FFFFFFh. This is because the holding latches reset to blocks are to be erased, which memory type is to be
an unknown state, so if the addresses are left in the programmed and when the programming cycle starts.
Reset state, they may overwrite the locations on rows NVMKEY is a write-only register that is used for write
which were not rewritten. protection. To start a programming or erase sequence,
The basic sequence for RTSP programming is to set up the user must consecutively write 55h and AAh to the
a Table Pointer, then do a series of TBLWT instructions NVMKEY register. Refer to Section 5.6 “Programming
to load the buffers. Programming is performed by Operations” for further details.
setting the control bits in the NVMCON register.
Data can be loaded in any order and the holding
5.6 Programming Operations
registers can be written to multiple times before A complete programming sequence is necessary for
performing a write operation. Subsequent writes, programming or erasing the internal Flash in RTSP
however, will wipe out any previous writes. mode. During a programming or erase operation, the
Note: Writing to a location multiple times without processor stalls (waits) until the operation is finished.
erasing is not recommended. Setting the WR bit (NVMCON<15>) starts the
operation and the WR bit is automatically cleared when
All of the table write operations are single-word writes the operation is finished.
(2 instruction cycles), because only the buffers are writ-
ten. A programming cycle is required for programming
each row.

REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0, HC(1) R/W-0(1) R/W-0, HS(1) U-0 U-0 U-0 U-0 U-0
WR WREN WRERR — — — — —
bit 15 bit 8
U-0 R/W-0(1) U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1)

— ERASE — — NVMOP3(2) NVMOP2(2) NVMOP1(2) NVMOP0(2)
bit 7 bit 0
Legend: SO = Settable Only bit HC = Hardware Clearable bit HS = Hardware Settable bit
bit 15 WR: Write Control bit(1)

1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once the operation is complete.
0 = Program or erase operation is complete and inactive
bit 14 WREN: Write Enable bit(1)
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
bit 13 WRERR: Write Sequence Error Flag bit(1)
1 = An improper program or erase sequence attempt, or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 6 ERASE: Erase/Program Enable bit(1)
1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command
0 = Perform the program operation specified by NVMOP<3:0> on the next WR command
bit 3-0 NVMOP<3:0>: NVM Operation Select bits(1,2)
1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)(3)
0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1)
0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)
0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1)
Note 1: These bits can only be reset on POR.

2: All other combinations of NVMOP<3:0> are unimplemented.
3: Available in ICSP™ mode only. Refer to device programming specification.

5.6.1 PROGRAMMING ALGORITHM FOR 4. Write the first 64 instructions from data RAM into
FLASH PROGRAM MEMORY the program memory buffers (see Example 5-1).
The user can program one row of Flash program memory 5. Write the program block to Flash memory:
at a time. To do this, it is necessary to erase the 8-row a) Set the NVMOP bits to ‘0001’ to configure
erase block containing the desired row. The general for row programming. Clear the ERASE bit
process is as follows: and set the WREN bit.
1. Read eight rows of program memory b) Write 55h to NVMKEY.
(512 instructions) and store in data RAM. c) Write AAh to NVMKEY.
2. Update the program data in RAM with the d) Set the WR bit. The programming cycle
desired new data. begins and the CPU stalls for the duration
3. Erase the block (see Example 5-1): of the write cycle. When the write to Flash
memory is done, the WR bit is cleared
a) Set the NVMOP bits (NVMCON<3:0>) to
automatically.
‘0010’ to configure for block erase. Set the
ERASE (NVMCON<6>) and WREN 6. Repeat steps 4 and 5, using the next available
(NVMCON<14>) bits. 64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
b) Write the starting address of the block to be
512 instructions are written back to Flash
erased into the TBLPAG and W registers.
memory.
c) Write 55h to NVMKEY.
For protection against accidental operations, the write
d) Write AAh to NVMKEY.
initiate sequence for NVMKEY must be used to allow
e) Set the WR bit (NVMCON<15>). The erase any erase or program operation to proceed. After the
cycle begins and the CPU stalls for the dura- programming command has been executed, the user
tion of the erase cycle. When the erase is must wait for the programming time until programming
done, the WR bit is cleared automatically. is complete. The two instructions following the start of
the programming sequence should be NOPs, as shown
in Example 5-5.
EXAMPLE 5-1: ERASING A PROGRAM MEMORY BLOCK (ASSEMBLY LANGUAGE CODE)

; Set up NVMCON for block erase operation
MOV #0x4042, W0 ;
MOV W0, NVMCON ; Initialize NVMCON
; Init pointer to row to be ERASED
MOV #tblpage(PROG_ADDR), W0 ;
MOV W0, TBLPAG ; Initialize PM Page Boundary SFR
MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA[15:0] pointer
TBLWTL W0, [W0] ; Set base address of erase block
DISI #5 ; Block all interrupts with priority <7
; for next 5 instructions
MOV #0x55, W0
MOV W0, NVMKEY ; Write the 55 key
MOV #0xAA, W1 ;
MOV W1, NVMKEY ; Write the AA key
BSET NVMCON, #WR ; Start the erase sequence
NOP ; Insert two NOPs after the erase
NOP ; command is asserted

EXAMPLE 5-2: ERASING A PROGRAM MEMORY BLOCK (C LANGUAGE CODE)
// C example using MPLAB C30
unsigned long progAddr = 0xXXXXXX; // Address of row to write
unsigned int offset;
//Set up pointer to the first memory location to be written

TBLPAG = progAddr>>16; // Initialize PM Page Boundary SFR
offset = progAddr & 0xFFFF; // Initialize lower word of address
__builtin_tblwtl(offset, 0x0000); // Set base address of erase block

// with dummy latch write
NVMCON = 0x4042; // Initialize NVMCON
asm("DISI #5"); // Block all interrupts with priority <7

// for next 5 instructions
__builtin_write_NVM(); // C30 function to perform unlock
// sequence and set WR
EXAMPLE 5-3: LOADING THE WRITE BUFFERS (ASSEMBLY LANGUAGE CODE)

; Set up NVMCON for row programming operations
MOV #0x4001, W0 ;
MOV W0, NVMCON ; Initialize NVMCON
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV #0x0000, W0 ;
MOV W0, TBLPAG ; Initialize PM Page Boundary SFR
MOV #0x6000, W0 ; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV #LOW_WORD_0, W2 ;
MOV #HIGH_BYTE_0, W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
; 1st_program_word
; 2nd_program_word
•
•
•
; 63rd_program_word
TBLWTH W3, [W0] ; Write PM high byte into program latch

EXAMPLE 5-4: LOADING THE WRITE BUFFERS (C LANGUAGE CODE)
#define NUM_INSTRUCTION_PER_ROW 64
unsigned int i;
unsigned long progAddr = 0xXXXXXX; // Address of row to write
unsigned int progData[2*NUM_INSTRUCTION_PER_ROW]; // Buffer of data to write
//Set up NVMCON for row programming


//Perform TBLWT instructions to write necessary number of latches

for(i=0; i < 2*NUM_INSTRUCTION_PER_ROW; i++)
{
__builtin_tblwtl(offset, progData[i++]); // Write to address low word
__builtin_tblwth(offset, progData[i]); // Write to upper byte
offset = offset + 2; // Increment address
}
EXAMPLE 5-5: INITIATING A PROGRAMMING SEQUENCE (ASSEMBLY LANGUAGE CODE)

DISI #5 ; Block all interrupts with priority <7
; for next 5 instructions
MOV #0x55, W0
MOV W0, NVMKEY ; Write the 55 key
MOV #0xAA, W1 ;
MOV W1, NVMKEY ; Write the AA key
BSET NVMCON, #WR ; Start the erase sequence
NOP ;
NOP ;
BTSC NVMCON, #15 ; and wait for it to be
BRA $-2 ; completed
EXAMPLE 5-6: INITIATING A PROGRAMMING SEQUENCE (C LANGUAGE CODE)

asm("DISI #5"); // Block all interrupts with priority < 7

__builtin_write_NVM(); // Perform unlock sequence and set WR

5.6.2 PROGRAMMING A SINGLE WORD instructions write the desired data into the write latches
OF FLASH PROGRAM MEMORY and specify the lower 16 bits of the program memory
address to write to. To configure the NVMCON register
If a Flash location has been erased, it can be pro-
for a word write, set the NVMOP bits (NVMCON<3:0>)
grammed using table write instructions to write an
to ‘0011’. The write is performed by executing the
instruction word (24-bit) into the write latch. The
unlock sequence and setting the WR bit (see
TBLPAG register is loaded with the 8 Most Significant
Example 5-7).
Bytes of the Flash address. The TBLWTL and TBLWTH
EXAMPLE 5-7: PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY

(ASSEMBLY LANGUAGE CODE)
; Setup a pointer to data Program Memory
MOV #tblpage(PROG_ADDR), W0 ;
MOV W0, TBLPAG ;Initialize PM Page Boundary SFR
MOV #tbloffset(PROG_ADDR), W0 ;Initialize a register with program memory address
MOV #LOW_WORD, W2 ;
MOV #HIGH_BYTE, W3 ;
; Setup NVMCON for programming one word to data Program Memory

MOV #0x4003, W0 ;
MOV W0, NVMCON ; Set NVMOP bits to 0011
DISI #5 ; Disable interrupts while the KEY sequence is written

MOV #0x55, W0 ; Write the key sequence
MOV W0, NVMKEY
MOV #0xAA, W0
MOV W0, NVMKEY
BSET NVMCON, #WR ; Start the write cycle
NOP ; Insert two NOPs after the erase
NOP ; Command is asserted
EXAMPLE 5-8: PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY

(C LANGUAGE CODE)

unsigned long progAddr = 0xXXXXXX; // Address of word to program
unsigned int progDataL = 0xXXXX; // Data to program lower word
unsigned char progDataH = 0xXX; // Data to program upper byte
//Set up NVMCON for word programming


//Perform TBLWT instructions to write latches

__builtin_tblwtl(offset, progDataL); // Write to address low word
__builtin_tblwth(offset, progDataH); // Write to upper byte
asm(“DISI #5”); // Block interrupts with priority < 7
__builtin_write_NVM(); // C30 function to perform unlock
// sequence and set WR

NOTES:

6.0 RESETS Any active source of Reset will make the SYSRST
signal active. Many registers associated with the CPU
Note: This data sheet summarizes the features and peripherals are forced to a known Reset state.
of this group of PIC24F devices. It is not Most registers are unaffected by a Reset; their status is
intended to be a comprehensive reference unknown on POR and unchanged by all other Resets.
“PIC24F Family Reference Manual”, Note: Refer to the specific peripheral or CPU
Section 7. “Reset” (DS39712). section of this manual for register Reset
states.
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The All types of device Reset will set a corresponding status
following is a list of device Reset sources: bit in the RCON register to indicate the type of Reset
(see Register 6-1). A Power-on Reset will clear all bits,
• POR: Power-on Reset except for the BOR and POR bits (RCON<1:0>), which
• MCLR: Pin Reset are set. The user may set or clear any bit at any time
• SWR: RESET Instruction during code execution. The RCON bits only serve as
• WDT: Watchdog Timer Reset status bits. Setting a particular Reset status bit in
software will not cause a device Reset to occur.
• BOR: Brown-out Reset
• CM: Configuration Mismatch Reset The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
• TRAPR: Trap Conflict Reset
The function of these bits is discussed in other sections
• IOPUWR: Illegal Opcode Reset of this data sheet.
• UWR: Uninitialized W Register Reset
Note: The status bits in the RCON register
A simplified block diagram of the Reset module is
should be cleared after they are read so
shown in Figure 6-1.
that the next RCON register value after a
device Reset will be meaningful.
FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM
RESET
Instruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
VDD Rise POR

Detect SYSRST
VDD
Brown-out BOR
Reset
Enable Voltage Regulator
Trap Conflict
Illegal Opcode
Configuration Mismatch
Uninitialized W Register

REGISTER 6-1: RCON: RESET CONTROL REGISTER(1)
R/W-0 R/W-0 U-0 U-0 U-0 R/CO-0, HS R/W-0 R/W-0
TRAPR IOPUWR — — — DPSLP CM PMSLP
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, R/W-0 R/W-1 R/W-1

EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR
bit 7 bit 0
Legend: CO = Clearable Only bit HS = Hardware Settable bit

bit 15 TRAPR: Trap Reset Flag bit

1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address
Pointer caused a Reset
0 = An illegal opcode or uninitialized W Reset has not occurred
bit 10 DPSLP: Deep Sleep Mode Flag bit
1 = Deep Sleep has occurred
0 = Deep Sleep has not occurred
bit 9 CM: Configuration Word Mismatch Reset Flag bit
1 = A Configuration Word Mismatch Reset has occurred
0 = A Configuration Word Mismatch Reset has not occurred
bit 8 PMSLP: Program Memory Power During Sleep bit
1 = Program memory bias voltage remains powered during Sleep
0 = Program memory bias voltage is powered down during Sleep and voltage regulator enters Standby mode
bit 7 EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6 SWR: Software Reset (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
bit 5 SWDTEN: Software Enable/Disable of WDT bit(2)
1 = WDT is enabled
0 = WDT is disabled
bit 4 WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
bit 3 SLEEP: Wake From Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
bit 2 IDLE: Wake-up From Idle Flag bit
1 = Device has been in Idle mode
0 = Device has not been in Idle mode
Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.

REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED)
bit 1 BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred. Note that BOR is also set after a Power-on Reset.
0 = A Brown-out Reset has not occurred
bit 0 POR: Power-on Reset Flag bit
1 = A Power-on Reset has occurred
0 = A Power-on Reset has not occurred
Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
TABLE 6-1: RESET FLAG BIT OPERATION

Flag Bit Setting Event Clearing Event
TRAPR (RCON<15>) Trap Conflict Event POR
IOPUWR (RCON<14>) Illegal Opcode or Uninitialized W Register Access POR
CM (RCON<9>) Configuration Mismatch Reset POR
EXTR (RCON<7>) MCLR Reset POR
SWR (RCON<6>) RESET Instruction POR
WDTO (RCON<4>) WDT Time-out PWRSAV Instruction, POR
SLEEP (RCON<3>) PWRSAV #SLEEP Instruction POR
IDLE (RCON<2>) PWRSAV #IDLE Instruction POR
BOR (RCON<1>) POR, BOR —
POR (RCON<0>) POR —
DPSLP (RCON<10>) PWRSAV #SLEEP instruction with DSCON <DSEN> set POR
Note: All Reset flag bits may be set or cleared by the user software.
6.1 Clock Source Selection at Reset 6.2 Device Reset Times

If clock switching is enabled, the system clock source at The Reset times for various types of device Reset are
device Reset is chosen as shown in Table 6-2. If clock summarized in Table 6-3. Note that the System Reset
switching is disabled, the system clock source is always signal, SYSRST, is released after the POR and PWRT
selected according to the oscillator Configuration bits. delay times expire.
Refer to Section 8.0 “Oscillator Configuration” for The time at which the device actually begins to execute
further details. code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
TABLE 6-2: OSCILLATOR SELECTION vs. the PLL lock time. The OST and PLL lock times occur
TYPE OF RESET (CLOCK in parallel with the applicable SYSRST delay times.
SWITCHING ENABLED) The FSCM delay determines the time at which the
Reset Type Clock Source Determinant FSCM begins to monitor the system clock source after
the SYSRST signal is released.
POR FNOSC Configuration bits
BOR (CW2<10:8>)
MCLR COSC Control bits

WDTO (OSCCON<14:12>)
SWR

TABLE 6-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
System Clock
Reset Type Clock Source SYSRST Delay Notes
Delay
POR(6) EC TPOR + TRST + TPWRT — 1, 2, 3, 8
FRC, FRCDIV TPOR + TRST + TPWRT TFRC 1, 2, 3, 4, 7, 8
LPRC TPOR + TRST + TPWRT TLPRC 1, 2, 3, 4, 8
ECPLL TPOR + TRST + TPWRT TLOCK 1, 2, 3, 5, 8
FRCPLL TPOR + TRST + TPWRT TFRC + TLOCK 1, 2, 3, 4, 5, 7, 8
XT, HS, SOSC TPOR+ TRST + TPWRT TOST 1, 2, 3, 6, 8
XTPLL, HSPLL TPOR + TRST + TPWRT TOST + TLOCK 1, 2, 3, 5, 6, 8
BOR EC TRST + TPWRT — 2, 3, 8
FRC, FRCDIV TRST + TPWRT TFRC 2, 3, 4, 7, 8
LPRC TRST + TPWRT TLPRC 2, 3, 4, 8
ECPLL TRST + TPWRT TLOCK 2, 3, 5, 8
FRCPLL TRST + TPWRT TFRC + TLOCK 2, 3, 4, 5, 7, 8
XT, HS, SOSC TRST + TPWRT TOST 2, 3, 6, 8
XTPLL, HSPLL TRST + TPWRT TFRC + TLOCK 2, 3, 4, 5, 8
All Others Any Clock TRST — 2, 8
Note 1: TPOR = Power-on Reset delay.
2: TRST = Internal State Reset time.
3: TPWRT = 64 ms nominal if regulator is disabled (DISVREG tied to VDD).
4: TFRC and TLPRC = RC Oscillator start-up times.
5: TLOCK = PLL lock time.
6: TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the
oscillator clock to the system.
7: If Two-Speed Start-up is enabled, regardless of the Primary Oscillator selected, the device starts with
FRC, and in such cases, FRC start-up time is valid.
8: TRST = Configuration setup time.
Note: For detailed operating frequency and timing specifications, see Section 28.0 “Electrical Characteristics”.

6.2.1 POR AND LONG OSCILLATOR 6.3 Special Function Register Reset
START-UP TIMES States
The oscillator start-up circuitry and its associated delay Most of the Special Function Registers (SFRs) associ-
timers are not linked to the device Reset delays that ated with the PIC24F CPU and peripherals are reset to a
occur at power-up. Some crystal circuits (especially particular value at a device Reset. The SFRs are
low-frequency crystals) will have a relatively long grouped by their peripheral or CPU function and their
start-up time. Therefore, one or more of the following Reset values are specified in each section of this manual.
conditions is possible after SYSRST is released:
The Reset value for each SFR does not depend on the
• The oscillator circuit has not begun to oscillate. type of Reset with the exception of four registers. The
• The Oscillator Start-up Timer has not expired (if a Reset value for the Reset Control register, RCON, will
crystal oscillator is used). depend on the type of device Reset. The Reset value
• The PLL has not achieved a lock (if PLL is used). for the Oscillator Control register, OSCCON, will
depend on the type of Reset and the programmed
The device will not begin to execute code until a valid
values of the FNOSC bits in Flash Configuration
clock source has been released to the system. There-
Word 2 (CW2); see Table 6-2. The RCFGCAL and
fore, the oscillator and PLL start-up delays must be
NVMCON registers are only affected by a POR.
considered when the Reset delay time must be known.
6.2.2 FAIL-SAFE CLOCK MONITOR 6.4 Deep Sleep BOR (DSBOR)

(FSCM) AND DEVICE RESETS Deep Sleep BOR is a very low-power BOR circuitry,
If the FSCM is enabled, it will begin to monitor the used when the device is in Deep Sleep mode. Due to
system clock source when SYSRST is released. If a low-current consumption, accuracy may vary.
valid clock source is not available at this time, the The DSBOR trip point is around 2.0V. DSBOR is
device will automatically switch to the FRC Oscillator enabled by configuring CW4 (DSBOREN) = 1. DSBOR
and the user can switch to the desired crystal oscillator will re-arm the POR to ensure the device will reset if VDD
in the Trap Service Routine (TSR). drops below the POR threshold.

NOTES:

7.0 INTERRUPT CONTROLLER 7.1.1 ALTERNATE INTERRUPT VECTOR
TABLE
Note: This data sheet summarizes the features
The Alternate Interrupt Vector Table (AIVT) is located
of this group of PIC24F devices. It is not
after the IVT, as shown in Figure 7-1. Access to the
intended to be a comprehensive reference
AIVT is provided by the ALTIVT control bit
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
“PIC24F Family Reference Manual”,
and exception processes will use the alternate vectors
Section 8. “Interrupts” (DS39707).
instead of the default vectors. The alternate vectors are
The PIC24F interrupt controller reduces the numerous organized in the same manner as the default vectors.
peripheral interrupt request signals to a single interrupt The AIVT supports emulation and debugging efforts by
request signal to the PIC24F CPU. It has the following providing a means to switch between an application
features: and a support environment without requiring the inter-
• Up to 8 processor exceptions and software traps rupt vectors to be reprogrammed. This feature also
• 7 user-selectable priority levels enables switching between applications for evaluation
of different software algorithms at run time. If the AIVT
• Interrupt Vector Table (IVT) with up to 118 vectors
is not needed, the AIVT should be programmed with
• A unique vector for each interrupt or exception the same addresses used in the IVT.
source
• Fixed priority within a specified user priority level 7.2 Reset Sequence
• Alternate Interrupt Vector Table (AIVT) for debug
support A device Reset is not a true exception because the
• Fixed interrupt entry and return latencies interrupt controller is not involved in the Reset process.
The PIC24F devices clear their registers in response to
a Reset which forces the PC to zero. The micro-
7.1 Interrupt Vector Table controller then begins program execution at location
The Interrupt Vector Table (IVT) is shown in Figure 7-1. 000000h. The user programs a GOTO instruction at the
The IVT resides in program memory, starting at location Reset address, which redirects program execution to
000004h. The IVT contains 126 vectors, consisting of the appropriate start-up routine.
8 non-maskable trap vectors, plus up to 118 sources of
Note: Any unimplemented or unused vector
interrupt. In general, each interrupt source has its own
locations in the IVT and AIVT should be
vector. Each interrupt vector contains a 24-bit wide
programmed with the address of a default
address. The value programmed into each interrupt
interrupt handler routine that contains a
vector location is the starting address of the associated
RESET instruction.
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority; this is linked to their position in the vector table.
All other things being equal, lower addresses have a
higher natural priority. For example, the interrupt
associated with vector 0 will take priority over interrupts
at any other vector address.
PIC24FJ64GA104 family devices implement
non-maskable traps and unique interrupts. These are
summarized in Table 7-1 and Table 7-2.

FIGURE 7-1: PIC24F INTERRUPT VECTOR TABLE
Reset – GOTO Instruction 000000h

Reset – GOTO Address 000002h
Reserved 000004h
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0 000014h
Interrupt Vector 1
—
—
—
Interrupt Vector 52 00007Ch
Interrupt Vector Table (IVT)(1)
Decreasing Natural Order Priority
Interrupt Vector 53 00007Eh

—
—
—
Interrupt Vector 116 0000FCh
Interrupt Vector 117 0000FEh
Reserved 000100h
Reserved 000102h
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 1
—
—
— Alternate Interrupt Vector Table (AIVT)(1)
Interrupt Vector 52 00017Ch
Interrupt Vector 53 00017Eh
—
—
—
Interrupt Vector 116
Interrupt Vector 117 0001FEh
Start of Code 000200h
Note 1: See Table 7-2 for the interrupt vector list.
TABLE 7-1: TRAP VECTOR DETAILS

Vector Number IVT Address AIVT Address Trap Source
0 000004h 000104h Reserved
1 000006h 000106h Oscillator Failure
2 000008h 000108h Address Error
3 00000Ah 00010Ah Stack Error
4 00000Ch 00010Ch Math Error
5 00000Eh 00010Eh Reserved
6 000010h 000110h Reserved
7 000012h 000112h Reserved

TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS
Vector AIVT Interrupt Bit Locations
Interrupt Source IVT Address
Number Address Flag Enable Priority
ADC1 Conversion Done 13 00002Eh 00012Eh IFS0<13> IEC0<13> IPC3<6:4>

Comparator Event 18 000038h 000138h IFS1<2> IEC1<2> IPC4<10:8>
CRC Generator 67 00009Ah 00019Ah IFS4<3> IEC4<3> IPC16<14:12>
CTMU Event 77 0000AEh 0001AEh IFS4<13> IEC4<13> IPC19<6:4>
External Interrupt 0 0 000014h 000114h IFS0<0> IEC0<0> IPC0<2:0>
External Interrupt 1 20 00003Ch 00013Ch IFS1<4> IEC1<4> IPC5<2:0>
External Interrupt 2 29 00004Eh 00014Eh IFS1<13> IEC1<13> IPC7<6:4>
I2C1 Master Event 17 000036h 000136h IFS1<1> IEC1<1> IPC4<6:4>
I2C1 Slave Event 16 000034h 000134h IFS1<0> IEC1<0> IPC4<2:0>
I2C2 Master Event 50 000078h 000178h IFS3<2> IEC3<2> IPC12<10:8>
I2C2 Slave Event 49 000076h 000176h IFS3<1> IEC3<1> IPC12<6:4>
Input Capture 1 1 000016h 000116h IFS0<1> IEC0<1> IPC0<6:4>
Input Capture 2 5 00001Eh 00011Eh IFS0<5> IEC0<5> IPC1<6:4>
Input Capture 3 37 00005Eh 00015Eh IFS2<5> IEC2<5> IPC9<6:4>
Input Change Notification 19 00003Ah 00013Ah IFS1<3> IEC1<3> IPC4<14:12>
LVD Low-Voltage Detect 72 0000A4h 0001A4h IFS4<8> IEC4<8> IPC18<2:0>
Output Compare 1 2 000018h 000118h IFS0<2> IEC0<2> IPC0<10:8>
Parallel Master Port 45 00006Eh 00016Eh IFS2<13> IEC2<13> IPC11<6:4>
Real-Time Clock/Calendar 62 000090h 000190h IFS3<14> IEC3<14> IPC15<10:8>
SPI1 Error 9 000026h 000126h IFS0<9> IEC0<9> IPC2<6:4>
SPI1 Event 10 000028h 000128h IFS0<10> IEC0<10> IPC2<10:8>
SPI2 Error 32 000054h 000154h IFS2<0> IEC2<0> IPC8<2:0>
SPI2 Event 33 000056h 000156h IFS2<1> IEC2<1> IPC8<6:4>
Timer1 3 00001Ah 00011Ah IFS0<3> IEC0<3> IPC0<14:12>
Timer2 7 000022h 000122h IFS0<7> IEC0<7> IPC1<14:12>
Timer3 8 000024h 000124h IFS0<8> IEC0<8> IPC2<2:0>
Timer4 27 00004Ah 00014Ah IFS1<11> IEC1<11> IPC6<14:12>
Timer5 28 00004Ch 00014Ch IFS1<12> IEC1<12> IPC7<2:0>
UART1 Error 65 000096h 000196h IFS4<1> IEC4<1> IPC16<6:4>
UART1 Receiver 11 00002Ah 00012Ah IFS0<11> IEC0<11> IPC2<14:12>
UART1 Transmitter 12 00002Ch 00012Ch IFS0<12> IEC0<12> IPC3<2:0>
UART2 Error 66 000098h 000198h IFS4<2> IEC4<2> IPC16<10:8>
UART2 Receiver 30 000050h 000150h IFS1<14> IEC1<14> IPC7<10:8>
UART2 Transmitter 31 000052h 000152h IFS1<15> IEC1<15> IPC7<14:12>

7.3 Interrupt Control and Status The interrupt sources are assigned to the IFSx, IECx
Registers and IPCx registers in the order of their vector numbers,
as shown in Table 7-2. For example, the INT0 (External
The PIC24FJ64GA104 family of devices implements Interrupt 0) is shown as having a vector number and a
the following registers for the interrupt controller: natural order priority of 0. Thus, the INT0IF status bit is
• INTCON1 found in IFS0<0>, the INT0IE enable bit in IEC0<0>
and the INT0IP<2:0> priority bits in the first position of
• INTCON2
IPC0 (IPC0<2:0>).
• IFS0 through IFS4
Although they are not specifically part of the interrupt
• IEC0 through IEC4
control hardware, two of the CPU control registers con-
• IPC0 through IPC20 (except IPC13, IPC14 and tain bits that control interrupt functionality. The ALU
IPC17) STATUS Register (SR) contains the IPL<2:0> bits
• INTTREG (SR<7:5>); these indicate the current CPU interrupt
Global interrupt control functions are controlled from priority level. The user may change the current CPU
INTCON1 and INTCON2. INTCON1 contains the Inter- priority level by writing to the IPL bits.
rupt Nesting Disable (NSTDIS) bit, as well as the The CORCON register contains the IPL3 bit, which,
control and status flags for the processor trap sources. together with IPL<2:0>, indicates the current CPU
The INTCON2 register controls the external interrupt priority level. IPL3 is a read-only bit so that trap events
request signal behavior and the use of the Alternate cannot be masked by the user software.
Interrupt Vector Table.
The interrupt controller has the Interrupt Controller Test
The IFSx registers maintain all of the interrupt request Register (INTTREG) that displays the status of the
flags. Each source of interrupt has a status bit which is interrupt controller. When an interrupt request occurs,
set by the respective peripherals, or an external signal, its associated vector number and the new interrupt
and is cleared via software. priority level are latched into INTTREG.
The IECx registers maintain all of the interrupt enable This information can be used to determine a specific
bits. These control bits are used to individually enable interrupt source if a generic ISR is used for multiple
interrupts from the peripherals or external signals. vectors – such as when ISR remapping is used in boot-
The IPCx registers are used to set the interrupt priority loader applications. It also could be used to check if
level for each source of interrupt. Each user interrupt another interrupt is pending while in an ISR.
source can be assigned to one of eight priority levels. All interrupt registers are described in Register 7-1
through Register 7-32, on the following pages.

REGISTER 7-1: SR: ALU STATUS REGISTER (IN CPU)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0
— — — — — — — DC(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

(2,3) IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1)
IPL2
bit 7 bit 0
Legend:
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)

111 = CPU interrupt priority level is 7 (15). User interrupts are disabled.
Note 1: See Register 3-1 for the description of the remaining bit(s) that are not dedicated to interrupt control
functions.
2: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level.
The value in parentheses indicates the interrupt priority level if IPL3 = 1.
3: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
REGISTER 7-2: CORCON: CPU CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0

— — — — IPL3(2) PSV(1) — —
bit 7 bit 0
Legend: C = Clearable bit

bit 3 IPL3: CPU Interrupt Priority Level Status bit(2)

1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
Note 1: See Register 3-2 for the description of the remaining bit(s) that are not dedicated to interrupt control
functions.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.

REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

NSTDIS — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

— — — MATHERR ADDRERR STKERR OSCFAIL —
bit 7 bit 0
Legend:
bit 15 NSTDIS: Interrupt Nesting Disable bit

1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
bit 4 MATHERR: Arithmetic Error Trap Status bit
1 = Overflow trap has occurred
0 = Overflow trap has not occurred
bit 3 ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
bit 2 STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
bit 1 OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred
bit 0 Unimplemented: Read as ‘0’

REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

ALTIVT DISI — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — INT2EP INT1EP INT0EP
bit 7 bit 0
Legend:
bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit

1 = Use Alternate Interrupt Vector Table
0 = Use standard (default) vector table
bit 14 DISI: DISI Instruction Status bit
1 = DISI instruction is active
0 = DISI instruction is not active
bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge

REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF
bit 7 bit 0
Legend:

bit 13 AD1IF: A/D Conversion Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit
bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit
bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit
bit 9 SPF1IF: SPI1 Fault Interrupt Flag Status bit
bit 8 T3IF: Timer3 Interrupt Flag Status bit
bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit
bit 0 INT0IF: External Interrupt 0 Flag Status bit

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — INT1IF CNIF CMIF MI2C1IF SI2C1IF
bit 7 bit 0
Legend:
bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit

bit 14 U2RXIF: UART2 Receiver Interrupt Flag Status bit
bit 3 CNIF: Input Change Notification Interrupt Flag Status bit
bit 2 CMIF: Comparator Interrupt Flag Status bit
bit 1 MI2C1IF: Master I2C1 Event Interrupt Flag Status bit
bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit

U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0

— — PMPIF — — — OC5IF —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0

IC5IF IC4IF IC3IF — — — SPI2IF SPF2IF
bit 7 bit 0
Legend:

bit 13 PMPIF: Parallel Master Port Interrupt Flag Status bit
bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit
bit 0 SPF2IF: SPI2 Fault Interrupt Flag Status bit

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

— RTCIF — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0, R/W-0 U-0

— — — — — MI2C2IF SI2C2IF —
bit 7 bit 0
Legend:

bit 14 RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit
bit 2 MI2C2IF: Master I2C2 Event Interrupt Flag Status bit
bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0

— — CTMUIF — — — — LVDIF
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0

— — — — CRCIF U2ERIF U1ERIF —
bit 7 bit 0
Legend:

bit 13 CTMUIF: CTMU Interrupt Flag Status bit
bit 8 LVDIF: Low-Voltage Detect Interrupt Flag Status bit
bit 3 CRCIF: CRC Generator Interrupt Flag Status bit
bit 2 U2ERIF: UART2 Error Interrupt Flag Status bit
bit 1 U1ERIF: UART1 Error Interrupt Flag Status bit

REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE
bit 7 bit 0
Legend:

bit 13 AD1IE: A/D Conversion Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit
bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit
bit 10 SPI1IE: SPI1 Transfer Complete Interrupt Enable bit
bit 9 SPF1IE: SPI1 Fault Interrupt Enable bit
bit 8 T3IE: Timer3 Interrupt Enable bit
bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit
bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit
bit 0 INT0IE: External Interrupt 0 Enable bit


U2TXIE U2RXIE INT2IE(1) T5IE T4IE OC4IE OC3IE —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — INT1IE(1) CNIE CMIE MI2C1IE SI2C1IE
bit 7 bit 0
Legend:
bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit

bit 14 U2RXIE: UART2 Receiver Interrupt Enable bit
bit 13 INT2IE: External Interrupt 2 Enable bit(1)
bit 4 INT1IE: External Interrupt 1 Enable bit(1)
bit 3 CNIE: Input Change Notification Interrupt Enable bit
bit 2 CMIE: Comparator Interrupt Enable bit
bit 1 MI2C1IE: Master I2C1 Event Interrupt Enable bit
bit 0 SI2C1IE: Slave I2C1 Event Interrupt Enable bit
Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or PRIx
pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information.

U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0

— — PMPIE — — — OC5IE —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0

IC5IE IC4IE IC3IE — — — SPI2IE SPF2IE
bit 7 bit 0
Legend:

bit 13 PMPIE: Parallel Master Port Interrupt Enable bit
bit 1 SPI2IE: SPI2 Event Interrupt Enable bit
bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

— RTCIE — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0

— — — — — MI2C2IE SI2C2IE —
bit 7 bit 0
Legend:

bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit
bit 2 MI2C2IE: Master I2C2 Event Interrupt Enable bit
bit 1 SI2C2IE: Slave I2C2 Event Interrupt Enable bit

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0
— — CTMUIE — — — — LVDIE
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0

— — — — CRCIE U2ERIE U1ERIE —
bit 7 bit 0
Legend:

bit 13 CTMUIE: CTMU Interrupt Enable bit
bit 8 LVDIE: Low-Voltage Detect Interrupt Enable bit
bit 3 CRCIE: CRC Generator Interrupt Enable bit
bit 2 U2ERIE: UART2 Error Interrupt Enable bit
bit 1 U1ERIE: UART1 Error Interrupt Enable bit

REGISTER 7-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0
bit 7 bit 0
Legend:

bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits
•
•
•
bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits
•
•
•
bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits
•
•
•

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— IC2IP2 IC2IP1 IC2IP0 — — — —
bit 7 bit 0
Legend:

•
•
•
•
•
•
•
•
•

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0
bit 7 bit 0
Legend:

bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits
•
•
•
bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits
•
•
•
bit 6-4 SPF1IP<2:0>: SPI1 Fault Interrupt Priority bits
•
•
•
•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0
bit 7 bit 0
Legend:

bit 6-4 AD1IP<2:0>: A/D Conversion Complete Interrupt Priority bits
•
•
•
bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits
•
•
•

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0
bit 7 bit 0
Legend:

bit 14-12 CNIP<2:0>: Input Change Notification Interrupt Priority bits
•
•
•
bit 10-8 CMIP<2:0>: Comparator Interrupt Priority bits
•
•
•
bit 6-4 MI2C1IP<2:0>: Master I2C1 Event Interrupt Priority bits
•
•
•
bit 2-0 SI2C1IP<2:0>: Slave I2C1 Event Interrupt Priority bits
•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — INT1IP2 INT1IP1 INT1IP0
bit 7 bit 0
Legend:

•
•
•

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— OC3IP2 OC3IP1 OC3IP0 — — — —
bit 7 bit 0
Legend:

•
•
•
•
•
•
•
•
•

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0
bit 7 bit 0
Legend:

bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits
•
•
•
bit 10-8 U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits
•
•
•
•
•
•
•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0
bit 7 bit 0
Legend:

bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Priority bits
•
•
•
bit 2-0 SPF2IP<2:0>: SPI2 Fault Interrupt Priority bits
•
•
•

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— IC3IP2 IC3IP1 IC3IP0 — — — —
bit 7 bit 0
Legend:

•
•
•
•
•
•
•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— OC5IP2 OC5IP1 OC5IP0 — — — —
bit 7 bit 0
Legend:

•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— PMPIP2 PMPIP1 PMPIP0 — — — —
bit 7 bit 0
Legend:

bit 6-4 PMPIP<2:0>: Parallel Master Port Interrupt Priority bits
•
•
•

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — —
bit 7 bit 0
Legend:

bit 10-8 MI2C2IP<2:0>: Master I2C2 Event Interrupt Priority bits
•
•
•
bit 6-4 SI2C2IP<2:0>: Slave I2C2 Event Interrupt Priority bits
•
•
•

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — RTCIP2 RTCIP1 RTCIP0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:

bit 10-8 RTCIP<2:0>: Real-Time Clock/Calendar Interrupt Priority bits
•
•
•

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— U1ERIP2 U1ERIP1 U1ERIP0 — — — —
bit 7 bit 0
Legend:

bit 14-12 CRCIP<2:0>: CRC Generator Error Interrupt Priority bits
•
•
•
bit 10-8 U2ERIP<2:0>: UART2 Error Interrupt Priority bits
•
•
•
bit 6-4 U1ERIP<2:0>: UART1 Error Interrupt Priority bits
•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — LVDIP2 LVDIP1 LVDIP0
bit 7 bit 0
Legend:

bit 2-0 LVDIP<2:0>: Low-Voltage Detect Interrupt Priority bits
•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— CTMUIP2 CTMUIP1 CTMUIP0 — — — —
bit 7 bit 0
Legend:

bit 6-4 CTMUIP<2:0>: CTMU Interrupt Priority bits
•
•
•

REGISTER 7-32: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
R-0 U-0 R/W-0 U-0 R-0 R-0 R-0 R-0
CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0
bit 15 bit 8
U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

— VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
bit 7 bit 0
Legend:
bit 15 CPUIRQ: Interrupt Request from Interrupt Controller CPU bit

1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU; this happens
when the CPU priority is higher than the interrupt priority
0 = No interrupt request is unacknowledged
bit 13 VHOLD: Vector Number Capture Configuration bit
1 = The VECNUM bits contain the value of the highest priority pending interrupt
0 = The VECNUM bits contain the value of the last Acknowledged interrupt (i.e., the last interrupt that
has occurred with higher priority than the CPU, even if other interrupts are pending)
bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits
1111 = CPU Interrupt Priority Level is 15
•
•
•
bit 6-0 VECNUM<6:0>: Pending Interrupt Vector ID bits (pending vector number is VECNUM + 8)
0111111 = Interrupt Vector pending is number 135
•
•
•

7.4 Interrupt Setup Procedures 7.4.3 TRAP SERVICE ROUTINE
A Trap Service Routine (TSR) is coded like an ISR,
7.4.1 INITIALIZATION except that the appropriate trap status flag in the
To configure an interrupt source: INTCON1 register must be cleared to avoid re-entry
1. Set the NSTDIS control bit (INTCON1<15>) if into the TSR.
nested interrupts are not desired.
7.4.4 INTERRUPT DISABLE
2. Select the user-assigned priority level for the
interrupt source by writing the control bits in the All user interrupts can be disabled using the following
appropriate IPCx register. The priority level will procedure:
depend on the specific application and type of 1. Push the current SR value onto the software
interrupt source. If multiple priority levels are not stack using the PUSH instruction.
desired, the IPCx register control bits for all 2. Force the CPU to priority level 7 by inclusive
enabled interrupt sources may be programmed ORing the value OEh with SRL.
to the same non-zero value.
To enable user interrupts, the POP instruction may be
Note: At a device Reset, the IPCx registers are used to restore the previous SR value.
initialized, such that all user interrupt
Note that only user interrupts with a priority level of 7 or
sources are assigned to priority level 4.
less can be disabled. Trap sources (level 8-15) cannot
3. Clear the interrupt flag status bit associated with be disabled.
the peripheral in the associated IFSx register. The DISI instruction provides a convenient way to
4. Enable the interrupt source by setting the disable interrupts of priority levels 1-6 for a fixed period
interrupt enable control bit associated with the of time. Level 7 interrupt sources are not disabled by
source in the appropriate IECx register. the DISI instruction.
7.4.2 INTERRUPT SERVICE ROUTINE

The method that is used to declare an ISR and initialize
the IVT with the correct vector address will depend on
the programming language (i.e., ‘C’ or assembler) and
the language development toolsuite that is used to
develop the application. In general, the user must clear
the interrupt flag in the appropriate IFSx register for the
source of the interrupt that the ISR handles. Otherwise,
the ISR will be re-entered immediately after exiting the
routine. If the ISR is coded in assembly language, it
must be terminated using a RETFIE instruction to
unstack the saved PC value, SRL value and old CPU
priority level.

NOTES:

8.0 OSCILLATOR • Software-controllable switching between various
clock sources
CONFIGURATION
• Software-controllable postscaler for selective
Note: This data sheet summarizes the features clocking of CPU for system power savings
of this group of PIC24F devices. It is not • A Fail-Safe Clock Monitor (FSCM) that detects
intended to be a comprehensive reference clock failure and permits safe application recovery
source. For more information, refer to the or shutdown
“PIC24F Family Reference Manual”, • A separate and independently configurable system
“Section 6. Oscillator” (DS39700). clock output for synchronizing external hardware
The oscillator system for PIC24FJ64GA104 family A simplified diagram of the oscillator system is shown
devices has the following features: in Figure 8-1.
• A total of four external and internal oscillator options
as clock sources, providing 11 different clock modes
• On-chip 4x PLL to boost internal operating frequency
on select internal and external oscillator sources
FIGURE 8-1: PIC24FJ64GA104 FAMILY CLOCK DIAGRAM
Primary Oscillator
REFOCON<15:8>
XT, HS, EC
OSCO
Reference Clock
Generator
XTPLL, HSPLL
OSCI ECPLL,FRCPLL
4 x PLL
REFO
8 MHz
Postscaler
4 MHz
FRC FRCDIV
Oscillator 8 MHz
(nominal)
Peripherals
CLKDIV<10:8> FRC
CLKO
LPRC LPRC
Postscaler
Oscillator 31 kHz (nominal) CPU
Secondary Oscillator
SOSC
SOSCO
CLKDIV<14:12>
SOSCEN
Enable
SOSCI Oscillator Clock Control Logic
Fail-Safe
Clock
Monitor
WDT, PWRT
Clock Source Option

for Other Modules

8.1 CPU Clocking Scheme 8.2 Initial Configuration on POR
The system clock source can be provided by one of The oscillator source (and operating mode) that is
four sources: used at a device Power-on Reset event is selected
• Primary Oscillator (POSC) on the OSCI and using Configuration bit settings. The oscillator Config-
OSCO pins uration bit settings are located in the Configuration
registers in the program memory (refer to
• Secondary Oscillator (SOSC) on the SOSCI and
Section 25.1 “Configuration Bits” for further details).
SOSCO pins
The Primary Oscillator Configuration bits,
• Fast Internal RC (FRC) Oscillator POSCMD<1:0> (Configuration Word 2<1:0>), and
• Low-Power Internal RC (LPRC) Oscillator the Initial Oscillator Select Configuration bits,
The Primary Oscillator and FRC sources have the FNOSC<2:0> (Configuration Word 2<10:8>), select
option of using the internal 4x PLL. The frequency of the oscillator source that is used at a Power-on Reset.
the FRC clock source can optionally be reduced by the The FRC Primary Oscillator with postscaler (FRCDIV)
programmable clock divider. The selected clock source is the default (unprogrammed) selection. The Second-
generates the processor and peripheral clock sources. ary Oscillator, or one of the internal oscillators, may be
chosen by programming these bit locations.
The processor clock source is divided by two to pro-
duce the internal instruction cycle clock, FCY. In this The Configuration bits allow users to choose between
document, the instruction cycle clock is also denoted the various clock modes, shown in Table 8-1.
by FOSC/2. The internal instruction cycle clock, FOSC/2,
can be provided on the OSCO I/O pin for some 8.2.1 CLOCK SWITCHING MODE
operating modes of the Primary Oscillator. CONFIGURATION BITS
The FCKSM Configuration bits (Configuration
Word 2<7:6>) are used to jointly configure device clock
switching and the Fail-Safe Clock Monitor (FSCM).
Clock switching is enabled only when FCKSM1 is
programmed (‘0’). The FSCM is enabled only when the
FCKSM<1:0> bits are both programmed (‘00’).
TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION

Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> Note
Fast RC Oscillator with Postscaler Internal 11 111 1, 2
(FRCDIV)
(Reserved) Internal xx 110 1
Low-Power RC Oscillator (LPRC) Internal 11 101 1
Secondary (Timer1) Oscillator Secondary 11 100 1
(SOSC)
Primary Oscillator (XT) with PLL Primary 01 011
Module (XTPLL)
Primary Oscillator (EC) with PLL Primary 00 011
Module (ECPLL)
Primary Oscillator (HS) Primary 10 010
Primary Oscillator (XT) Primary 01 010
Primary Oscillator (EC) Primary 00 010
Fast RC Oscillator with PLL Module Internal 11 001 1
(FRCPLL)
Fast RC Oscillator (FRC) Internal 11 000 1
Note 1: OSCO pin function is determined by the OSCIOFCN Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.

8.3 Control Registers The CLKDIV register (Register 8-2) controls the
features associated with Doze mode, as well as the
The operation of the oscillator is controlled by three postscaler for the FRC Oscillator.
Special Function Registers:
The OSCTUN register (Register 8-3) allows the user to
• OSCCON fine tune the FRC Oscillator over a range of approxi-
• CLKDIV mately ±12%. Each bit increment or decrement
• OSCTUN changes the factory calibrated frequency of the FRC
Oscillator by a fixed amount.
The OSCCON register (Register 8-1) is the main con-
trol register for the oscillator. It controls clock source
switching and allows the monitoring of clock sources.
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER

U-0 R-0 R-0 R-0 U-0 R/W-x(1) R/W-x(1) R/W-x(1)
— COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0
bit 15 bit 8
R/SO-0 R/W-0 R-0(3) U-0 R/CO-0 R/W-0 R/W-0 R/W-0

CLKLOCK IOLOCK(2) LOCK — CF POSCEN SOSCEN OSWEN
bit 7 bit 0
Legend: CO = Clearable Only bit SO = Settable Only bit


bit 14-12 COSC<2:0>: Current Oscillator Selection bits
111 = Fast RC Oscillator with Postscaler (FRCDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 10-8 NOSC<2:0>: New Oscillator Selection bits(1)
110 = Reserved
Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.
2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared.
3: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL clock mode is selected.

REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 7 CLKLOCK: Clock Selection Lock Enabled bit
If FSCM is enabled (FCKSM1 = 1):
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit
If FSCM is disabled (FCKSM1 = 0):
Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
bit 6 IOLOCK: I/O Lock Enable bit(2)
1 = I/O lock is active
0 = I/O lock is not active
bit 5 LOCK: PLL Lock Status bit(3)
1 = PLL module is in lock or PLL module start-up timer is satisfied
0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled
bit 3 CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
bit 2 POSCEN: Primary Oscillator Sleep Enable bit
1 = Primary Oscillator continues to operate during Sleep mode
0 = Primary Oscillator disabled during Sleep mode
bit 1 SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit
1 = Enable Secondary Oscillator
0 = Disable Secondary Oscillator
bit 0 OSWEN: Oscillator Switch Enable bit
1 = Initiate an oscillator switch to clock source specified by NOSC<2:0> bits
0 = Oscillator switch is complete
Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.
2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared.
3: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL clock mode is selected.

REGISTER 8-2: CLKDIV: CLOCK DIVIDER REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1

ROI DOZE2 DOZE1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15 ROI: Recover on Interrupt bit

1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1
0 = Interrupts have no effect on the DOZEN bit
bit 14-12 DOZE<2:0>: CPU Peripheral Clock Ratio Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
bit 11 DOZEN: DOZE Enable bit(1)
1 = DOZE<2:0> bits specify the CPU peripheral clock ratio
0 = CPU peripheral clock ratio set to 1:1
bit 10-8 RCDIV<2:0>: FRC Postscaler Select bits
111 = 31.25 kHz (divide-by-256)
110 = 125 kHz (divide-by-64)
101 = 250 kHz (divide-by-32)
100 = 500 kHz (divide-by-16)
011 = 1 MHz (divide-by-8)
Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.

REGISTER 8-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — TUN5(1) TUN4(1) TUN3(1) TUN2(1) TUN1(1) TUN0(1)
bit 7 bit 0
Legend:

bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1)
011111 = Maximum frequency deviation
011110 =



000001 =
000000 = Center frequency, oscillator is running at factory calibrated frequency
111111 =



100001 =
100000 = Minimum frequency deviation
Note 1: Increments or decrements of TUN<5:0> may not change the FRC frequency in equal steps over the FRC
tuning range and may not be monotonic.
8.4 Clock Switching Operation 8.4.1 ENABLING CLOCK SWITCHING

With few limitations, applications are free to switch To enable clock switching, the FCKSM Configuration bits
between any of the four clock sources (POSC, SOSC, in CW2 must be programmed to ‘00’. (Refer to
FRC and LPRC) under software control and at any Section 25.1 “Configuration Bits” for further details.)
time. To limit the possible side effects that could result If the FCKSM Configuration bits are unprogrammed
from this flexibility, PIC24F devices have a safeguard (‘1x’), the clock switching function and Fail-Safe Clock
lock built into the switching process. Monitor function are disabled. This is the default setting.
The NOSCx control bits (OSCCON<10:8>) do not
Note: The Primary Oscillator mode has three
control the clock selection when clock switching is dis-
different submodes (XT, HS and EC)
abled. However, the COSCx bits (OSCCON<14:12>)
which are determined by the POSCMDx
will reflect the clock source selected by the FNOSCx
Configuration bits. While an application
Configuration bits.
can switch to and from Primary Oscillator
mode in software, it cannot switch The OSWEN control bit (OSCCON<0>) has no effect
between the different primary submodes when clock switching is disabled. It is held at ‘0’ at all
without reprogramming the device. times.

8.4.2 OSCILLATOR SWITCHING A recommended code sequence for a clock switch
SEQUENCE includes the following:
At a minimum, performing a clock switch requires this 1. Disable interrupts during the OSCCON register
basic sequence: unlock and write sequence.
1. If desired, read the COSCx bits 2. Execute the unlock sequence for the OSCCON
(OSCCON<14:12>), to determine the current high byte by writing 78h and 9Ah to
oscillator source. OSCCON<15:8> in two back-to-back
instructions.
2. Perform the unlock sequence to allow a write to
the OSCCON register high byte. 3. Write new oscillator source to the NOSCx bits in
the instruction immediately following the unlock
3. Write the appropriate value to the NOSCx bits
sequence.
(OSCCON<10:8>) for the new oscillator source.
4. Execute the unlock sequence for the OSCCON
4. Perform the unlock sequence to allow a write to
low byte by writing 46h and 57h to
the OSCCON register low byte.
OSCCON<7:0> in two back-to-back instructions.
5. Set the OSWEN bit to initiate the oscillator
5. Set the OSWEN bit in the instruction immediately
switch.
following the unlock sequence.
Once the basic sequence is completed, the system 6. Continue to execute code that is not clock
clock hardware responds automatically as follows: sensitive (optional).
1. The clock switching hardware compares the 7. Invoke an appropriate amount of software delay
COSCx bits with the new value of the NOSCx (cycle counting) to allow the selected oscillator
bits. If they are the same, then the clock switch and/or PLL to start and stabilize.
is a redundant operation. In this case, the 8. Check to see if OSWEN is ‘0’. If it is, the switch
OSWEN bit is cleared automatically and the was successful. If OSWEN is still set, then
clock switch is aborted. check the LOCK bit to determine the cause of
2. If a valid clock switch has been initiated, the failure.
LOCK (OSCCON<5>) and CF (OSCCON<3>)
The core sequence for unlocking the OSCCON register
bits are cleared.
and initiating a clock switch is shown in Example 8-1.
3. The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
EXAMPLE 8-1: BASIC CODE SEQUENCE
must be turned on, the hardware will wait until
FOR CLOCK SWITCHING
the OST expires. If the new source is using the
PLL, then the hardware waits until a PLL lock is ;Place the new oscillator selection in W0
detected (LOCK = 1). ;OSCCONH (high byte) Unlock Sequence
MOV #OSCCONH, w1
4. The hardware waits for 10 clock cycles from the MOV #0x78, w2
new clock source and then performs the clock MOV #0x9A, w3
switch. MOV.b w2, [w1]
5. The hardware clears the OSWEN bit to indicate a MOV.b w3, [w1]
successful clock transition. In addition, the ;Set new oscillator selection
NOSCx bit values are transferred to the COSCx MOV.b WREG, OSCCONH
;OSCCONL (low byte) unlock sequence
bits.
MOV #OSCCONL, w1
6. The old clock source is turned off at this time, with MOV #0x46, w2
the exception of LPRC (if WDT or FSCM are MOV #0x57, w3
enabled) or SOSC (if SOSCEN remains set). MOV.b w2, [w1]
MOV.b w3, [w1]
Note 1: The processor will continue to execute ;Start oscillator switch operation
code throughout the clock switching BSET OSCCON,#0
sequence. Timing sensitive code should
not be executed during this time.
2: Direct clock switches between any
Primary Oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direc-
tion. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL
modes.

8.5 Secondary Oscillator (SOSC) In general, the crystal circuit connections should be as
short as possible. It is also good practice to surround
8.5.1 BASIC SOSC OPERATION the crystal circuit with a ground loop or ground plane.
For more information on crystal circuit design, please
PIC24FJ64GA104 family devices do not have to set the
refer to Section 6 “Oscillator” (DS39700) of the
SOSCEN bit to use the Secondary Oscillator. Any
“PIC24F Family Reference Manual”. Additional infor-
module requiring the SOSC (such as RTCC, Timer1 or
mation is also available in these Microchip Application
DSWDT) will automatically turn on the SOSC when the
Notes:
clock signal is needed. The SOSC, however, has a long
start-up time. To avoid delays for peripheral start-up, the • AN826, “Crystal Oscillator Basics and Crystal
SOSC can be manually started using the SOSCEN bit. Selection for rfPIC® and PICmicro® Devices”
(DS00826)
To use the Secondary Oscillator, the SOSCSEL<1:0>
bits (CW3<9:8>) must be configured in an oscillator • AN849, “Basic PICmicro® Oscillator Design”
mode – either ‘11’ or ‘01’. Setting SOSCSEL to ‘00’ (DS00849).
configures the SOSC pins for Digital mode, enabling
digital I/O functionality on the pins. Digital functionality 8.6 Reference Clock Output
will not be available if the SOSC is configured in either In addition to the CLKO output (FOSC/2) available in
of the oscillator modes. certain oscillator modes, the device clock in the
PIC24FJ64GA104 family devices can also be config-
8.5.2 LOW-POWER SOSC OPERATION ured to provide a reference clock output signal to a port
The Secondary Oscillator can operate in two distinct pin. This feature is available in all oscillator configura-
levels of power consumption based on device configu- tions and allows the user to select a greater range of
ration. In Low-Power mode, the oscillator operates in a clock submultiples to drive external devices in the
low drive strength, low-power state. By default, the application.
oscillator uses a higher drive strength, and therefore, This reference clock output is controlled by the
requires more power. The Secondary Oscillator Mode REFOCON register (Register 8-4). Setting the ROEN
Configuration bits, SOSCSEL<1:0> (CW3<9:8>), bit (REFOCON<15>) makes the clock signal available
determine the oscillator’s power mode. Programming on the REFO pin. The RODIV bits (REFOCON<11:8>)
the SOSCSEL bits to ‘01’ selects low-power operation. enable the selection of 16 different clock divider
The lower drive strength of this mode makes the SOSC options.
more sensitive to noise and requires a longer start-up The ROSSLP and ROSEL bits (REFOCON<13:12>)
time. When Low-Power mode is used, care must be control the availability of the reference output during
taken in the design and layout of the SOSC circuit to Sleep mode. The ROSEL bit determines if the oscillator
ensure that the oscillator starts up and oscillates on OSC1 and OSC2, or the current system clock source,
properly. is used for the reference clock output. The ROSSLP bit
determines if the reference source is available on REFO
8.5.3 EXTERNAL (DIGITAL) CLOCK
when the device is in Sleep mode.
MODE (SCLKI)
To use the reference clock output in Sleep mode, both
The SOSC can also be configured to run from an the ROSSLP and ROSEL bits must be set. The device
external 32 kHz clock source, rather than the internal clock must also be configured for one of the primary
oscillator. In this mode, also referred to as Digital mode, modes (EC, HS or XT); otherwise, if the POSCEN bit is
the clock source provided on the SCLKI pin is used to not also set, the oscillator on OSC1 and OSC2 will be
clock any modules that are configured to use the powered down when the device enters Sleep mode.
Secondary Oscillator. In this mode, the crystal driving Clearing the ROSEL bit allows the reference output
circuit is disabled and the SOSCEN bit (OSCCON<1>) frequency to change as the system clock changes
has no effect. during any clock switches.
8.5.4 SOSC LAYOUT CONSIDERATIONS
The pinout limitations on low pin count devices, such as
those in the PIC24FJ64GA104 family, may make the
SOSC more susceptible to noise than other PIC24F
devices. Unless proper care is taken in the design and
layout of the SOSC circuit, this external noise may
introduce inaccuracies into the oscillator’s period.

REGISTER 8-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15 ROEN: Reference Oscillator Output Enable bit

1 = Reference oscillator is enabled on REFO pin
0 = Reference oscillator is disabled
bit 13 ROSSLP: Reference Oscillator Output Stop in Sleep bit
1 = Reference oscillator continues to run in Sleep
0 = Reference oscillator is disabled in Sleep
bit 12 ROSEL: Reference Oscillator Source Select bit
1 = Primary Oscillator is used as the base clock. Note that the crystal oscillator must be enabled using
the FOSC<2:0> bits; the crystal maintains the operation in Sleep mode.
0 = System clock is used as the base clock; base clock reflects any clock switching of the device
bit 11-8 RODIV<3:0>: Reference Oscillator Divisor Select bits
1111 = Base clock value divided by 32,768
1001 = Base clock value divided by 512
0000 = Base clock value

NOTES:

9.0 POWER-SAVING FEATURES The assembly syntax of the PWRSAV instruction is
shown in Example 9-1.
Note: SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
“PIC24F Family Reference Manual”, Sleep and Idle modes can be exited as a result of an
Section 39. “Power-Saving Features enabled interrupt, WDT time-out or a device Reset.
with Deep Sleep” (DS39727). When the device exits these modes, it is said to
“wake-up”.
The PIC24FJ64GA104 family of devices provides the
ability to manage power consumption by selectively 9.2.1 SLEEP MODE
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the Sleep mode has these features:
number of circuits being clocked constitutes lower • The system clock source is shut down. If an
consumed power. All PIC24F devices manage power on-chip oscillator is used, it is turned off.
consumption in four different ways: • The device current consumption will be reduced
• Clock Frequency to a minimum provided that no I/O pin is sourcing
• Instruction-Based Sleep, Idle and Deep Sleep current.
modes • The I/O pin directions and states are frozen.
• Software Controlled Doze mode • The Fail-Safe Clock Monitor does not operate
• Selective Peripheral Control in Software during Sleep mode since the system clock source
is disabled.
Combinations of these methods can be used to
• The LPRC clock will continue to run in Sleep
selectively tailor an application’s power consumption,
mode if the WDT or RTCC with LPRC as clock
while still maintaining critical application features, such
source is enabled.
as timing-sensitive communications.
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
9.1 Clock Frequency and Clock
• Some device features or peripherals may
Switching continue to operate in Sleep mode. This includes
PIC24F devices allow for a wide range of clock items, such as the input change notification on the
frequencies to be selected under application control. If I/O ports, or peripherals that use an external clock
the system clock configuration is not locked, users can input. Any peripheral that requires the system
choose low-power or high-precision oscillators by simply clock source for its operation will be disabled in
changing the NOSC bits. The process of changing a Sleep mode.
system clock during operation, as well as limitations to The device will wake-up from Sleep mode on any of
the process, are discussed in more detail in Section 8.0 these events:
“Oscillator Configuration”.
• On any interrupt source that is individually
enabled
9.2 Instruction-Based Power-Saving
• On any form of device Reset
Modes
• On a WDT time-out
PIC24F devices have two special power-saving modes On wake-up from Sleep, the processor will restart with
that are entered through the execution of a special the same clock source that was active when Sleep
PWRSAV instruction. Sleep mode stops clock operation mode was entered.
and halts all code execution; Idle mode halts the CPU
and code execution, but allows peripheral modules to
continue operation. Deep Sleep mode stops clock
operation, code execution and all peripherals except
RTCC and DSWDT. It also freezes I/O states and
removes power to SRAM and Flash memory.
EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX

PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode
PWRSAV #IDLE_MODE ; Put the device into IDLE mode
BSET DSCON, #DSEN ; Enable Deep Sleep
PWRSAV #SLEEP_MODE ; Put the device into Deep SLEEP mode

9.2.2 IDLE MODE Note: Since Deep Sleep mode powers down the
Idle mode has these features: microcontroller by turning off the on-chip
• The CPU will stop executing instructions. VDDCORE voltage regulator, Deep Sleep
capability is available only when operating
• The WDT is automatically cleared.
with the internal regulator enabled.
• The system clock source remains active. By
default, all peripheral modules continue to operate 9.2.4.1 Entering Deep Sleep Mode
normally from the system clock source, but can
Deep Sleep mode is entered by setting the DSEN bit in
also be selectively disabled (see Section 9.4
the DSCON register, and then executing a SLEEP
“Selective Peripheral Module Control”). instruction (PWRSAV #SLEEP_MODE) within one to three
• If the WDT or FSCM is enabled, the LPRC will instruction cycles to minimize the chance that Deep
also remain active. Sleep will be spuriously entered.
The device will wake from Idle mode on any of these If the PWRSAV command is not given within three
events: instruction cycles, the DSEN bit will be cleared by the
• Any interrupt that is individually enabled hardware and must be set again by the software before
entering Deep Sleep mode. The DSEN bit is also
• Any device Reset
automatically cleared when exiting the Deep Sleep
• A WDT time-out mode.
On wake-up from Idle, the clock is reapplied to the CPU
Note: To re-enter Deep Sleep after a Deep Sleep
and instruction execution begins immediately, starting
wake-up, allow a delay of at least 3 TCY
with the instruction following the PWRSAV instruction or
after clearing the RELEASE bit.
the first instruction in the ISR.
The sequence to enter Deep Sleep mode is:
9.2.3 INTERRUPTS COINCIDENT WITH 1. If the application requires the Deep Sleep WDT,
POWER SAVE INSTRUCTIONS enable it and configure its clock source (see
Any interrupt that coincides with the execution of a Section 9.2.4.7 “Deep Sleep WDT” for
PWRSAV instruction (except for Deep Sleep) will be held details).
off until entry into Sleep or Idle mode has completed. 2. If the application requires Deep Sleep BOR,
The device will then wake-up from Sleep or Idle mode. enable it by programming the DSBOREN
Configuration bit (CW4<6>).
9.2.4 DEEP SLEEP MODE
3. If the application requires wake-up from Deep
In PIC24FJ64GA104 family devices, Deep Sleep mode Sleep on RTCC alarm, enable and configure the
is intended to provide the lowest levels of power RTCC module (see Section 19.0 “Real-Time
consumption available, without requiring the use of
Clock and Calendar (RTCC)” for more
external switches to completely remove all power from
information).
the device. Entry into Deep Sleep mode is completely
under software control. Exit from Deep Sleep mode can 4. If needed, save any critical application context
be triggered from any of the following events: data by writing it to the DSGPR0 and DSGPR1
registers (optional).
• POR event
5. Enable Deep Sleep mode by setting the DSEN
• MCLR event bit (DSCON<15>).
• RTCC alarm (If the RTCC is present) 6. Enter Deep Sleep mode by immediately issuing
• External Interrupt 0 a PWRSAV #0 instruction.
• Deep Sleep Watchdog Timer (DSWDT) time-out Any time the DSEN bit is set, all bits in the DSWAKE
In Deep Sleep mode, it is possible to keep the device register will be automatically cleared.
Real-Time Clock and Calendar (RTCC) running without
the loss of clock cycles.
The device has a dedicated Deep Sleep Brown-out
Reset (DSBOR) and a Deep Sleep Watchdog Timer
Reset (DSWDT) for monitoring voltage and time-out
events. The DSBOR and DSWDT are independent of
the standard BOR and WDT used with other
power-managed modes (Sleep, Idle and Doze).

9.2.4.2 Special Cases when Entering Deep Examples for implementing these cases are shown in
Sleep Mode Example 9-2. It is recommended that an assembler, or
in-line C routine be used in these cases, to ensure that
When entering Deep Sleep mode, there are certain
the code executes in the number of cycles required.
circumstances that require a delay between setting the
DSEN bit and executing the PWRSAV instruction. These
can be generally reduced to three scenarios: EXAMPLE 9-2: IMPLEMENTING THE
SPECIAL CASES FOR
1. Scenario (1): use an external wake-up source
ENTERING DEEP SLEEP
(INT0) or the RTCC is used
2. Scenario (2): with application-level interrupts // Case 1: simplest delay scenario
that can be temporarily disabled //
asm("bset DSCON, #15");
3. Scenario (3): with interrupts that must be
asm("nop");
monitored
asm("nop");
In the first scenario, the application requires a wake-up asm("nop");
from Deep Sleep on the assertion of the INT0 pin or the asm("pwrsav #0");
RTCC interrupt. In this case, three NOP instructions //
must be inserted to properly synchronize the detection // Case 2: interrupts disabled
of an asynchronous INT0 interrupt after the device //
enters Deep Sleep mode. If the application does not asm("disi #4");
use wake-up on INT0 or RTCC, the NOP instructions asm("bset DSCON, #15");
are optional. asm("nop");
In the second scenario, the application also uses asm("nop");
interrupts which can be briefly ignored. With these asm("nop");
applications, an interrupt event during the execution of asm("pwrsav #0");
the NOP instructions may cause an ISR to be executed. //
This means that more than three instruction cycles will // Case 3: interrupts disabled with
elapse before returning to the code and that the DSEN // interrupt testing
bit will be cleared. To prevent the missed entry into //
Deep Sleep, temporarily disable interrupts prior to asm("disi #4");
entering Deep Sleep mode. Invoking the DISI instruc- asm("bset DSCON, #15");
tion for four cycles is sufficient to prevent interrupts asm("nop");
from disrupting Deep Sleep entry. asm("nop");
asm("btss INTTREG, #15");
In the third scenario, interrupts cannot be ignored even
asm("pwrsav #0");
briefly; constant interrupt detection is required, even
// continue with application code here
during the interval between setting DSEN and
//
executing the PWRSAV instruction. For these cases, it is
possible to disable interrupts and test for an interrupt
condition, skipping the PWRSAV instruction if necessary.
Testing for interrupts can be accomplished by checking
the status of the CPUIRQ bit (INTTREG<15>). If an
unserviced interrupt is pending, this bit will be set. If
CPUIRQ is set prior to executing the PWRSAV instruc-
tion, the instruction is skipped. At this point, the DISI
instruction has expired (being more than 4 instructions
from when it was executed) and the application vectors
to the appropriate ISR. When the application returns, it
can either attempt to re-enter Deep Sleep mode or per-
form some other system function. In either case, the
application must have some functional code located,
following the PWRSAV instruction, in the event that the
PWRSAV instruction is skipped and the device does not
enter Deep Sleep mode.

9.2.4.3 Exiting Deep Sleep Mode 9.2.4.4 Deep Sleep Wake-up Time
Deep Sleep mode exits on any one of the following events: Since wake-up from Deep Sleep results in a POR, the
• POR event on VDD supply. If there is no DSBOR wake-up time from Deep Sleep is the same as the
circuit to re-arm the VDD supply POR circuit, the device POR time. Also, because the internal regulator
external VDD supply must be lowered to the is turned off, the voltage on VCAP may drop depending
natural arming voltage of the POR circuit. on how long the device is asleep. If VCAP has dropped
below 2V, then there will be additional wake-up time
• DSWDT time-out. When the DSWDT timer times
while the regulator charges VCAP.
out, the device exits Deep Sleep.
• RTCC alarm (if RTCEN = 1). Deep Sleep wake-up time is specified in Section 28.0
• Assertion (‘0’) of the MCLR pin. “Electrical Characteristics” as TDSWU. This specifi-
cation indicates the worst-case wake-up time, including
• Assertion of the INT0 pin (if the interrupt was
the full POR Reset time (including TPOR and TRST), as
enabled before Deep Sleep mode was entered).
well as the time to fully charge a 10 F capacitor on
The polarity configuration is used to determine the
VCAP which has discharged to 0V. Wake-up may be
assertion level (‘0’ or ‘1’) of the pin that will cause
significantly faster if VCAP has not discharged.
an exit from Deep Sleep mode. Exiting from Deep
Sleep mode requires a change on the INT0 pin
9.2.4.5 Saving Context Data with the
while in Deep Sleep mode.
DSGPR0/DSGPR1 Registers
Note: Any interrupt pending when entering Deep
As exiting Deep Sleep mode causes a POR, most
Sleep mode is cleared.
Special Function Registers reset to their default POR
Exiting Deep Sleep mode generally does not retain the values. In addition, because VDDCORE power is not
state of the device and is equivalent to a Power-on supplied in Deep Sleep mode, information in data RAM
Reset (POR) of the device. Exceptions to this include may be lost when exiting this mode.
the RTCC (if present), which remains operational
Applications which require critical data to be saved
through the wake-up, the DSGPRx registers and the
prior to Deep Sleep may use the Deep Sleep General
DSWDT bit.
Purpose registers, DSGPR0 and DSGPR1, or data
Wake-up events that occur from the time Deep Sleep EEPROM (if available). Unlike other SFRs, the con-
exits, until the time that the POR sequence completes, tents of these registers are preserved while the device
are ignored, and are not captured in the DSWAKE is in Deep Sleep mode. After exiting Deep Sleep,
register. software can restore the data by reading the registers
The sequence for exiting Deep Sleep mode is: and clearing the RELEASE bit (DSCON<0>).
1. After a wake-up event, the device exits Deep 9.2.4.6 I/O Pins During Deep Sleep
Sleep and performs a POR. The DSEN bit is
cleared automatically. Code execution resumes During Deep Sleep, the general purpose I/O pins retain
at the Reset vector. their previous states and the Secondary Oscillator
(SOSC) will remain running, if enabled. Pins that are
2. To determine if the device exited Deep Sleep,
configured as inputs (TRIS bit is set) prior to entry into
read the Deep Sleep bit, DPSLP (RCON<10>).
Deep Sleep remain high-impedance during Deep
This bit will be set if there was an exit from Deep
Sleep. Pins that are configured as outputs (TRIS bit is
Sleep mode. If the bit is set, clear it.
clear) prior to entry into Deep Sleep remain as output
3. Determine the wake-up source by reading the pins during Deep Sleep. While in this mode, they
DSWAKE register. continue to drive the output level determined by their
4. Determine if a DSBOR event occurred during corresponding LAT bit at the time of entry into Deep
Deep Sleep mode by reading the DSBOR bit Sleep.
(DSCON<1>).
5. If application context data has been saved, read
it back from the DSGPR0 and DSGPR1
registers.
6. Clear the RELEASE bit (DSCON<0>).

Once the device wakes back up, all I/O pins continue to 9.2.4.8 Switching Clocks in Deep Sleep Mode
maintain their previous states, even after the device
Both the RTCC and the DSWDT may run from either
has finished the POR sequence and is executing appli-
SOSC or the LPRC clock source. This allows both the
cation code again. Pins configured as inputs during
RTCC and DSWDT to run without requiring both the
Deep Sleep remain high-impedance and pins config-
LPRC and SOSC to be enabled together, reducing
ured as outputs continue to drive their previous value.
power consumption.
After waking up, the TRIS and LAT registers, and the
SOSCEN bit (OSCCON<1>) are reset. If firmware Running the RTCC from LPRC will result in a loss of
modifies any of these bits or registers, the I/O will not accuracy in the RTCC of approximately 5 to 10%. If an
immediately go to the newly configured states. Once accurate RTCC is required, it must be run from the
the firmware clears the RELEASE bit (DSCON<0>) the SOSC clock source. The RTCC clock source is selected
I/O pins are “released”. This causes the I/O pins to take with the RTCOSC Configuration bit (CW4<5>).
the states configured by their respective TRIS and LAT Under certain circumstances, it is possible for the
bit values. DSWDT clock source to be off when entering Deep
This means that keeping the SOSC running after Sleep mode. In this case, the clock source is turned on
waking up requires the SOSCEN bit to be set before automatically (if DSWDT is enabled), without the need
clearing RELEASE. for software intervention. However, this can cause a
delay in the start of the DSWDT counters. In order to
If the Deep Sleep BOR (DSBOR) is enabled, and a
avoid this delay when using SOSC as a clock source,
DSBOR or a true POR event occurs during Deep
the application can activate SOSC prior to entering
Sleep, the I/O pins will be immediately released similar
Deep Sleep mode.
to clearing the RELEASE bit. All previous state infor-
mation will be lost, including the general purpose 9.2.4.9 Checking and Clearing the Status of
DSGPR0 and DSGPR1 contents.
Deep Sleep
If a MCLR Reset event occurs during Deep Sleep, the
Upon entry into Deep Sleep mode, the status bit,
DSGPRx, DSCON and DSWAKE registers will remain
DPSLP (RCON<10>), becomes set and must be
valid and the RELEASE bit will remain set. The state of
cleared by software.
the SOSC will also be retained. The I/O pins, however,
will be reset to their MCLR Reset state. Since On power-up, the software should read this status bit to
RELEASE is still set, changes to the SOSCEN bit determine if the Reset was due to an exit from Deep
(OSCCON<1>) cannot take effect until the RELEASE Sleep mode and clear the bit if it is set. Of the four
bit is cleared. possible combinations of DPSLP and POR bit states,
three cases can be considered:
In all other Deep Sleep wake-up cases, application
firmware must clear the RELEASE bit in order to • Both the DPSLP and POR bits are cleared. In this
reconfigure the I/O pins. case, the Reset was due to some event other
than a Deep Sleep mode exit.
9.2.4.7 Deep Sleep WDT • The DPSLP bit is clear, but the POR bit is set.
To enable the DSWDT in Deep Sleep mode, program This is a normal Power-on Reset.
the Configuration bit, DSWDTEN (CW4<7>). The • Both the DPSLP and POR bits are set. This
device Watchdog Timer (WDT) need not be enabled for means that Deep Sleep mode was entered, the
the DSWDT to function. Entry into Deep Sleep mode device was powered down and Deep Sleep mode
automatically resets the DSWDT. was exited.
The DSWDT clock source is selected by the
DSWDTOSC Configuration bit (CW4<4>). The
postscaler options are programmed by the
DSWDTPS<3:0> Configuration bits (CW4<3:0>). The
minimum time-out period that can be achieved is
2.1 ms and the maximum is 25.7 days. For more
details on the CW4 Configuration register and DSWDT
configuration options, refer to Section 25.0 “Special
Features”.

9.2.4.10 Power-on Resets (PORs) 9.2.4.11 Summary of Deep Sleep Sequence
VDD voltage is monitored to produce PORs. Since exit- To review, these are the necessary steps involved in
ing from Deep Sleep functionally looks like a POR, the invoking and exiting Deep Sleep mode:
technique described in Section 9.2.4.9 “Checking 1. Device exits Reset and begins to execute its
and Clearing the Status of Deep Sleep” should be application code.
used to distinguish between Deep Sleep and a true
2. If DSWDT functionality is required, program the
POR event.
appropriate Configuration bit.
When a true POR occurs, the entire device, including 3. Select the appropriate clock(s) for the DSWDT
all Deep Sleep logic (Deep Sleep registers, RTCC, and RTCC (optional).
DSWDT, etc.) is reset.
4. Enable and configure the RTCC (optional).
5. Write context data to the DSGPRx registers
(optional).
6. Enable the INT0 interrupt (optional).
7. Set the DSEN bit in the DSCON register.
8. Enter Deep Sleep by issuing a PWRSV
#SLEEP_MODE command.
9. Device exits Deep Sleep when a wake-up event
occurs.
10. The DSEN bit is automatically cleared.
11. Read and clear the DPSLP status bit in RCON,
and the DSWAKE status bits.
12. Read the DSGPRx registers (optional).
13. Once all state related configurations are
complete, clear the RELEASE bit.
14. Application resumes normal operation.

REGISTER 9-1: DSCON: DEEP SLEEP CONTROL REGISTER
R/W-0, HC U-0 U-0 U-0 U-0 U-0 U-0 U-0
DSEN(1) — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HCS R/C-0, HS

(1,2,3)
— — — — — — DSBOR RELEASE(1,2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit C = Clearable bit U = Unimplemented, read as ‘0’
HC = Hardware Clearable bit HS = Hardware Settable bit HCS = Hardware Clearable/Settable bit
bit 15 DSEN: Deep Sleep Enable bit(1)

1 = Device enters Deep Sleep when PWRSAV #0 is executed in the next instruction
0 = Device enters normal Sleep when PWRSAV #0 is executed
bit 1 DSBOR: Deep Sleep BOR Event Status bit(1,2,3)
1 = The DSBOR was active and a BOR event was detected during Deep Sleep
0 = The DSBOR was disabled or was active and did not detect a BOR event during Deep Sleep
bit 0 RELEASE: I/O Pin State Deep Sleep Release bit(1,2)
1 = I/O pins and SOSC maintain their states following exit from Deep Sleep, regardless of their LAT
and TRIS configuration
0 = I/O pins and SOSC are released from their Deep Sleep states. The pin state is controlled by the
LAT and TRIS configurations, and the SOSCEN bit.
Note 1: These bits are reset only in the case of a POR event outside of Deep Sleep mode.
2: Reset value is ‘0’ for initial power-on POR only and ‘1’ for Deep Sleep POR.
3: This is a status bit only; a DSBOR event will NOT cause a wake-up from Deep Sleep.

REGISTER 9-2: DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS
— — — — — — — DSINT0(1)
bit 15 bit 8
R/W-0, HS U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS U-0 R/W-0, HS

(1) (1) (1) (1)
DSFLT — — DSWDT DSRTC DSMCLR — DSPOR(2)
bit 7 bit 0
Legend: HS = Hardware Settable bit


bit 8 DSINT0: Interrupt-on-Change bit(1)
1 = External Interrupt 0 was asserted during Deep Sleep
0 = External Interrupt 0 was not asserted during Deep Sleep
bit 7 DSFLT: Deep Sleep Fault Detected bit(1)
1 = A Fault occurred during Deep Sleep and some Deep Sleep configuration settings may have been
corrupted
0 = No Fault was detected during Deep Sleep
bit 4 DSWDT: Deep Sleep Watchdog Timer Time-out bit(1)
1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep
0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep
bit 3 DSRTC: Real-Time Clock and Calendar Alarm bit(1)
1 = The Real-Time Clock and Calendar triggered an alarm during Deep Sleep
0 = The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep
bit 2 DSMCLR: Deep Sleep MCLR Event bit(1)
1 = The MCLR pin was asserted during Deep Sleep
0 = The MCLR pin was not asserted during Deep Sleep
bit 0 DSPOR: Power-on Reset Event bit(2)
1 = The VDD supply POR circuit was active and a POR event was detected
0 = The VDD supply POR circuit was not active, or was active, but did not detect a POR event
Note 1: This bit can only be set while the device is in Deep Sleep mode.
2: This bit can be set outside of Deep Sleep.

9.3 Doze Mode 9.4 Selective Peripheral Module
Generally, changing clock speed and invoking one of
Control
the power-saving modes are the preferred strategies Idle and Doze modes allow users to substantially
for reducing power consumption. There may be reduce power consumption by slowing or stopping the
circumstances, however, where this is not practical. For CPU clock. Even so, peripheral modules still remain
example, it may be necessary for an application to clocked, and thus, consume power. There may be
maintain uninterrupted synchronous communication, cases where the application needs what these modes
even while it is doing nothing else. Reducing system do not provide: the allocation of power resources to
clock speed may introduce communication errors, CPU processing with minimal power consumption from
while using a power-saving mode may stop the peripherals.
communications completely.
PIC24F devices address this requirement by allowing
Doze mode is a simple and effective alternative method peripheral modules to be selectively disabled, reducing
to reduce power consumption while the device is still or eliminating their power consumption. This can be
executing code. In this mode, the system clock contin- done with two control bits:
ues to operate from the same source and at the same
• The Peripheral Enable bit, generically named
speed. Peripheral modules continue to be clocked at
“XXXEN”, located in the module’s main control
the same speed while the CPU clock speed is reduced.
SFR.
Synchronization between the two clock domains is
maintained, allowing the peripherals to access the • The Peripheral Module Disable (PMD) bit,
SFRs while the CPU executes code at a slower rate. generically named “XXXMD”, located in one of the
PMD Control registers.
Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core Both bits have similar functions in enabling or disabling
clock speed is determined by the DOZE<2:0> bits its associated module. Setting the PMD bit for a module
(CLKDIV<14:12>). There are eight possible disables all clock sources to that module, reducing its
configurations, from 1:1 to 1:128, with 1:1 being the power consumption to an absolute minimum. In this
default. state, the control and status registers associated with
the peripheral will also be disabled, so writes to those
It is also possible to use Doze mode to selectively registers will have no effect and read values will be
reduce power consumption in event driven applica- invalid. Many peripheral modules have a corresponding
tions. This allows clock-sensitive functions, such as PMD bit.
synchronous communications, to continue without
interruption while the CPU Idles, waiting for something In contrast, disabling a module by clearing its XXXEN bit
to invoke an interrupt routine. Enabling the automatic disables its functionality, but leaves its registers available
return to full-speed CPU operation on interrupts is to be read and written to. This reduces power consump-
enabled by setting the ROI bit (CLKDIV<15>). By tion, but not by as much as setting the PMD bit does.
default, interrupt events have no effect on Doze mode Most peripheral modules have an enable bit; exceptions
operation. include input capture, output compare and RTCC.
To achieve more selective power savings, peripheral
modules can also be selectively disabled when the
device enters Idle mode. This is done through the
control bit of the generic name format, “XXXIDL”. By
default, all modules that can operate during Idle mode
will do so. Using the disable on Idle feature allows
further reduction of power consumption during Idle
mode, enhancing power savings for extremely critical
power applications.

NOTES:

10.0 I/O PORTS When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
Note: This data sheet summarizes the features a general purpose output pin is disabled. The I/O pin
of this group of PIC24F devices. It is not may be read, but the output driver for the parallel port
intended to be a comprehensive reference bit will be disabled. If a peripheral is enabled, but the
source. For more information, refer to the peripheral is not actively driving a pin, that pin may be
“PIC24F Family Reference Manual”, driven by a port.
Section 12. “I/O Ports with Peripheral All port pins have three registers directly associated
Pin Select (PPS)” (DS39711). with their operation as digital I/Os. The Data Direction
All of the device pins (except VDD, VSS, MCLR and register (TRIS) determines whether the pin is an input
OSCI/CLKI) are shared between the peripherals and or an output. If the data direction bit is a ‘1’, then the pin
the parallel I/O ports. All I/O input ports feature Schmitt is an input. All port pins are defined as inputs after a
Trigger inputs for improved noise immunity. Reset. Reads from the Output Latch register (LAT),
read the latch. Writes to the Output Latch register, write
the latch. Reads from the port (PORT), read the port
10.1 Parallel I/O (PIO) Ports
pins, while writes to the port pins, write the latch.
A parallel I/O port that shares a pin with a peripheral is, in Any bit and its associated data and control registers
general, subservient to the peripheral. The peripheral’s that are not valid for a particular device will be
output buffer data and control signals are provided to a disabled. That means the corresponding LAT and
pair of multiplexers. The multiplexers select whether the TRIS registers, and the port pin will read as zeros.
peripheral or the associated port has ownership of the
output data and control signals of the I/O pin. The logic When a pin is shared with another peripheral or func-
also prevents “loop through”, in which a port’s digital out- tion that is defined as an input only, it is regarded as a
put can drive the input of a peripheral that shares the dedicated port because there is no other competing
same pin. Figure 10-1 shows how ports are shared with source of outputs.
other peripherals and the associated I/O pin to which
they are connected.
FIGURE 10-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module Output Multiplexers

Peripheral Input Data
Peripheral Module Enable

I/O
Peripheral Output Enable
1 Output Enable
Peripheral Output Data
0
PIO Module 1
Output Data
Read TRIS 0
Data Bus D Q I/O Pin
WR TRIS CK
TRIS Latch
D Q
WR LAT +
CK
WR PORT
Data Latch
Read LAT
Input Data
Read PORT

10.1.1 OPEN-DRAIN CONFIGURATION 10.2.2 ANALOG INPUT PINS AND
In addition to the PORT, LAT and TRIS registers for VOLTAGE CONSIDERATIONS
data control, each port pin can also be individually The voltage tolerance of pins used as device inputs is
configured for either digital or open-drain output. This is dependent on the pin’s input function. Pins that are
controlled by the Open-Drain Control register, ODCx, used as digital only inputs are able to handle DC
associated with each port. Setting any of the bits con- voltages up to 5.5V, a level typical for digital logic
figures the corresponding pin to act as an open-drain circuits. In contrast, pins that also have analog input
output. functions of any kind can only tolerate voltages up to
The open-drain feature allows the generation of VDD. Voltage excursions beyond VDD on these pins
outputs higher than VDD (e.g., 5V) on any desired should be avoided.
digital only pins by using external pull-up resistors. The Table 10-1 summarizes the input voltage capabilities.
maximum open-drain voltage allowed is the same as Refer to Section 28.0 “Electrical Characteristics” for
the maximum VIH specification. more details.
10.2 Configuring Analog Port Pins TABLE 10-1: INPUT VOLTAGE TOLERANCE
The AD1PCFGL and TRIS registers control the opera- Tolerated
Port or Pin Description
tion of the A/D port pins. Setting a port pin as an analog Input
input also requires that the corresponding TRIS bit be
PORTA<4:0> VDD Only VDD input levels
set. If the TRIS bit is cleared (output), the digital output
PORTB<15:12> tolerated.
level (VOH or VOL) will be converted.
When reading the PORT register, all pins configured as PORTB<4:0>
analog input channels will read as cleared (a low level). PORTC<3:0>(1)
Pins configured as digital inputs will not convert an PORTA<10:7>(1) 5.5V Tolerates input levels
analog input. Analog levels on any pin that is defined as PORTB<11:7> above VDD, useful for
a digital input (including the ANx pins) may cause the most standard logic.
PORTB<6:5>
input buffer to consume current that exceeds the
device specifications. PORTC<9:4>(1)
Note 1: Not available on 28-pin devices.
10.2.1 I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP (Example 10-1).
EXAMPLE 10-1: PORT WRITE/READ EXAMPLE

MOV 0xFF00, W0 ; Configure PORTB<15:8> as inputs
MOV W0, TRISB ; and PORTB<7:0> as outputs
NOP ; Delay 1 cycle
BTSS PORTB, #13 ; Next Instruction

10.3 Input Change Notification 10.4.1 AVAILABLE PINS
The input change notification function of the I/O ports The Peripheral Pin Select feature is used with a range
allows the PIC24FJ64GA104 family of devices to gen- of up to 25 pins, depending on the particular device and
erate interrupt requests to the processor in response to its pin count. Pins that support the Peripheral Pin
a Change-of-State (COS) on selected input pins. This Select feature include the designation “RPn” in their full
feature is capable of detecting input Change-of-States pin designation, where “n” is the remappable pin
even in Sleep mode, when the clocks are disabled. number.
Depending on the device pin count, there are up to See Table 1-2 for a summary of pinout options in each
31 external inputs that may be selected (enabled) for package offering.
generating an interrupt request on a Change-of-State.
Registers, CNEN1 and CNEN2, contain the interrupt 10.4.2 AVAILABLE PERIPHERALS
enable control bits for each of the CN input pins. Setting The peripherals managed by the Peripheral Pin Select
any of these bits enables a CN interrupt for the are all digital only peripherals. These include general
corresponding pins. serial communications (UART and SPI), general
Each CN pin has a weak pull-up connected to it. The purpose timer clock inputs, timer related peripherals
pull-up acts as a current source that is connected to the (input capture and output compare) and external
pin. This eliminates the need for external resistors interrupt inputs. Also included are the outputs of the
when push button or keypad devices are connected. comparator module, since these are discrete digital
The pull-ups are separately enabled using the CNPU1 signals.
and CNPU2 registers (for pull-ups). Each CN pin has Peripheral Pin Select is not available for I2C™ change
individual control bits for its pull-up. Setting a control bit notification inputs, RTCC alarm outputs or peripherals
enables the weak pull-up for the corresponding pin. with analog inputs.
When the internal pull-up is selected, the pin pulls up to A key difference between pin select and non pin select
VDD – 0.7V (typical). Make sure that there is no external peripherals is that pin select peripherals are not asso-
pull-up source when the internal pull-ups are enabled, ciated with a default I/O pin. The peripheral must
as the voltage difference can cause a current path. always be assigned to a specific I/O pin before it can be
used. In contrast, non pin select peripherals are always
Note: Pull-ups on change notification pins
available on a default pin, assuming that the peripheral
should always be disabled whenever the
is active and not conflicting with another peripheral.
port pin is configured as a digital output.
10.4.2.1 Peripheral Pin Select Function
10.4 Peripheral Pin Select (PPS) Priority
A major challenge in general purpose devices is provid- Pin-selectable peripheral outputs (for example, OC and
ing the largest possible set of peripheral features while UART transmit) take priority over any general purpose
minimizing the conflict of features on I/O pins. In an digital functions permanently tied to that pin, such as
application that needs to use more than one peripheral PMP and port I/O. Specialized digital outputs, such as
multiplexed on a single pin, inconvenient work arounds USB functionality, take priority over PPS outputs on the
in application code or a complete redesign may be the same pin. The pin diagrams at the beginning of this
only option. data sheet list peripheral outputs in order of priority.
Refer to them for priority concerns on a particular pin.
The Peripheral Pin Select feature provides an alternative
to these choices by enabling the user’s peripheral set Unlike devices with fixed peripherals, pin-selectable
selection and their placement on a wide range of I/O peripheral inputs never take ownership of a pin. The
pins. By increasing the pinout options available on a par- pin’s output buffer is controlled by the pin’s TRIS bit
ticular device, users can better tailor the microcontroller setting, or by a fixed peripheral on the pin. If the pin is
to their entire application, rather than trimming the configured in Digital mode, then the PPS input will
application to fit the device. operate correctly, reading the input. If an analog func-
tion is enabled on the same pin, the pin-selectable
The Peripheral Pin Select feature operates over a fixed
input will be disabled.
subset of digital I/O pins. Users may independently
map the input and/or output of any one of many digital
peripherals to any one of these I/O pins. Peripheral Pin
Select is performed in software and generally does not
require the device to be reprogrammed. Hardware
safeguards are included that prevent accidental or
spurious changes to the peripheral mapping once it has
been established.

10.4.3 CONTROLLING PERIPHERAL PIN 10.4.3.1 Input Mapping
SELECT The inputs of the Peripheral Pin Select options are
Peripheral Pin Select features are controlled through mapped on the basis of the peripheral; that is, a control
two sets of Special Function Registers: one to map register associated with a peripheral dictates the pin it
peripheral inputs and one to map outputs. Because will be mapped to. The RPINRx registers are used to
they are separately controlled, a particular peripheral’s configure peripheral input mapping (see Register 10-1
input and output (if the peripheral has both) can be through Register 10-14). Each register contains up to
placed on any selectable function pin without two sets of 5-bit fields, with each set associated with
constraint. one of the pin-selectable peripherals. Programming a
given peripheral’s bit field with an appropriate 6-bit
The association of a peripheral to a
value maps the RPn pin with that value to that
peripheral-selectable pin is handled in two different
peripheral. For any given device, the valid range of
ways, depending on if an input or an output is being
values for any of the bit fields corresponds to the
mapped.
maximum number of Peripheral Pin Select options
supported by the device.
TABLE 10-2: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1)

Function Mapping
Input Name Function Name Register
Bits
External Interrupt 1 INT1 RPINR0 INT1R<5:0>
External Interrupt 2 INT2 RPINR1 INT2R<5:0>
Input Capture 1 IC1 RPINR7 IC1R<5:0>
Output Compare Fault A OCFA RPINR11 OCFAR<5:0>
Output Compare Fault B OCFB RPINR11 OCFBR<5:0>
SPI1 Clock Input SCK1IN RPINR20 SCK1R<5:0>
SPI1 Data Input SDI1 RPINR20 SDI1R<5:0>
SPI1 Slave Select Input SS1IN RPINR21 SS1R<5:0>
SPI2 Clock Input SCK2IN RPINR22 SCK2R<5:0>
SPI2 Data Input SDI2 RPINR22 SDI2R<5:0>
SPI2 Slave Select Input SS2IN RPINR23 SS2R<5:0>
Timer2 External Clock T2CK RPINR3 T2CKR<5:0>
UART1 Clear To Send U1CTS RPINR18 U1CTSR<5:0>
UART1 Receive U1RX RPINR18 U1RXR<5:0>
UART2 Clear To Send U2CTS RPINR19 U2CTSR<5:0>
UART2 Receive U2RX RPINR19 U2RXR<5:0>
Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.

10.4.3.2 Output Mapping the bit field corresponds to one of the peripherals and
that peripheral’s output is mapped to the pin (see
In contrast to inputs, the outputs of the Peripheral Pin
Table 10-3).
Select options are mapped on the basis of the pin. In
this case, a control register associated with a particular Because of the mapping technique, the list of peripherals
pin dictates the peripheral output to be mapped. The for output mapping also includes a null value of ‘000000’.
RPORx registers are used to control output mapping. This permits any given pin to remain disconnected from
Each register contains up to two 5-bit fields, with each the output of any of the pin-selectable peripherals.
field being associated with one RPn pin (see
Register 10-15 through Register 10-27). The value of
TABLE 10-3: SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT)

Output Function Number(1) Function Output Name
0 NULL(2) Null
1 C1OUT Comparator 1 Output
3 U1TX UART1 Transmit
(3)
4 U1RTS UART1 Request To Send
5 U2TX UART2 Transmit
(3)
6 U2RTS UART2 Request To Send
7 SDO1 SPI1 Data Output
8 SCK1OUT SPI1 Clock Output
9 SS1OUT SPI1 Slave Select Output
10 SDO2 SPI2 Data Output
11 SCK2OUT SPI2 Clock Output
12 SS2OUT SPI2 Slave Select Output
18 OC1 Output Compare 1
23-28 (unused) NC
29 CTPLS CTMU Output Pulse
31 (unused) NC
Note 1: Setting the RPORx register with the listed value assigns that output function to the associated RPn pin.
2: The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function.
3: IrDA® BCLK functionality uses this output.

10.4.3.3 Mapping Limitations Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
The control schema of the Peripheral Pin Select is
allows all of the Peripheral Pin Selects to be configured
extremely flexible. Other than systematic blocks that
with a single unlock sequence, followed by an update
prevent signal contention caused by two physical pins
to all control registers, then locked with a second lock
being configured as the same functional input, or two
sequence.
functional outputs configured as the same pin, there
are no hardware enforced lock outs. The flexibility
10.4.4.2 Continuous State Monitoring
extends to the point of allowing a single input to drive
multiple peripherals or a single functional output to In addition to being protected from direct writes, the
drive multiple output pins. contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
10.4.3.4 PPS Mapping Exceptions for If an unexpected change in any of the registers occurs
PIC24FJ64GA1 Family Devices (such as cell disturbances caused by ESD or other
external events), a Configuration Mismatch Reset will
Although the PPS registers allow for up to 32 remappable
be triggered.
pins, a maximum of 26 pins are implemented in 44-pin
devices (RP0 through RP25). In 28-pin devices, none of 10.4.4.3 Configuration Bit Pin Select Lock
the remappable pins above RP15 are implemented.
As an additional level of safety, the device can be
10.4.4 CONTROLLING CONFIGURATION configured to prevent more than one write session to
CHANGES the RPINRx and RPORx registers. The IOL1WAY
(CW2<4>) Configuration bit blocks the IOLOCK bit
Because peripheral remapping can be changed during from being cleared after it has been set once. If
run time, some restrictions on peripheral remapping IOLOCK remains set, the register unlock procedure will
are needed to prevent accidental configuration not execute and the Peripheral Pin Select Control
changes. PIC24F devices include three features to registers cannot be written to. The only way to clear the
prevent alterations to the peripheral map: bit and re-enable peripheral remapping is to perform a
• Control register lock sequence device Reset.
• Continuous state monitoring In the default (unprogrammed) state, IOL1WAY is set,
• Configuration bit remapping lock restricting users to one write session. Programming
IOL1WAY allows users unlimited access (with the
10.4.4.1 Control Register Lock proper use of the unlock sequence) to the Peripheral
Under normal operation, writes to the RPINRx and Pin Select registers.
RPORx registers are not allowed. Attempted writes will
appear to execute normally, but the contents of the
registers will remain unchanged. To change these reg-
isters, they must be unlocked in hardware. The register
lock is controlled by the IOLOCK bit (OSCCON<6>).
Setting IOLOCK prevents writes to the control
registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
1. Write 46h to OSCCON<7:0>.
2. Write 57h to OSCCON<7:0>.
3. Clear (or set) IOLOCK as a single operation.

10.4.5 CONSIDERATIONS FOR The assignment of a peripheral to a particular pin does
PERIPHERAL PIN SELECTION not automatically perform any other configuration of the
pin’s I/O circuitry. In theory, this means adding a
The ability to control Peripheral Pin Selection intro-
pin-selectable output to a pin may mean inadvertently
duces several considerations into application design
driving an existing peripheral input when the output is
that could be overlooked. This is particularly true for
driven. Users must be familiar with the behavior of
several common peripherals that are available only as
other fixed peripherals that share a remappable pin and
remappable peripherals.
know when to enable or disable them. To be safe, fixed
The main consideration is that the Peripheral Pin digital peripherals that share the same pin should be
Selects are not available on default pins in the device’s disabled when not in use.
default (Reset) state. Since all RPINRx registers reset
Along these lines, configuring a remappable pin for a
to ‘11111’ and all RPORx registers reset to ‘00000’, all
specific peripheral does not automatically turn that
Peripheral Pin Select inputs are tied to VSS and all
feature on. The peripheral must be specifically
Peripheral Pin Select outputs are disconnected.
configured for operation and enabled, as if it were tied to
Note: RP31 does not have to exist on a device a fixed pin. Where this happens in the application code
for the registers to be reset to it, or for (immediately following device Reset and peripheral
peripheral pin outputs to be tied to it. configuration or inside the main application routine)
depends on the peripheral and its use in the application.
This situation requires the user to initialize the device
with the proper peripheral configuration before any A final consideration is that Peripheral Pin Select func-
other application code is executed. Since the IOLOCK tions neither override analog inputs, nor reconfigure
bit resets in the unlocked state, it is not necessary to pins with analog functions for digital I/O. If a pin is
execute the unlock sequence after the device has configured as an analog input on device Reset, it must
come out of Reset. For application safety, however, it is be explicitly reconfigured as digital I/O when used with
best to set IOLOCK and lock the configuration after a Peripheral Pin Select.
writing to the control registers. Example 10-2 shows a configuration for bidirectional
Because the unlock sequence is timing-critical, it must communication with flow control using UART1. The
be executed as an assembly language routine in the following input and output functions are used:
same manner as changes to the oscillator configura- • Input Functions: U1RX, U1CTS
tion. If the bulk of the application is written in C or • Output Functions: U1TX, U1RTS
another high-level language, the unlock sequence
should be performed by writing in-line assembly.
Choosing the configuration requires the review of all
Peripheral Pin Selects and their pin assignments,
especially those that will not be used in the application.
In all cases, unused pin-selectable peripherals should
be disabled completely. Unused peripherals should
have their inputs assigned to an unused RPn pin
function. I/O pins with unused RPn functions should be
configured with the null peripheral output.

EXAMPLE 10-2: CONFIGURING UART1 INPUT AND OUTPUT FUNCTIONS IN ASSEMBLY CODE
;unlock registers
push w1;
push w2;
push w3;
mov #OSCCON, w1;
mov #0x46, w2;
mov #0x57, w3;
mov.b w2, [w1];
mov.b w3, [w1];
bclr OSCCON, #6;
; Configure Input Functions (Table10-2)

; Assign U1CTS To Pin RP1, U1RX To Pin RP0
mov #0x0100, w1;
mov w1,RPINR18;
; Configure Output Functions (Table 10-3)

; Assign U1RTS To Pin RP3, U1TX To Pin RP2
mov #0x0403, w1;
mov w1, RPOR1;
;lock registers
mov #OSCCON, w1;
mov #0x46, w2;
mov #0x57, w3;
mov.b w2, [w1];
mov.b w3, [w1];
bset OSCCON, #6;
pop w3;
pop w2;
pop w1;
EXAMPLE 10-3: CONFIGURING UART1 INPUT AND OUTPUT FUNCTIONS IN C

//unlock registers
__builtin_write_OSCCONL(OSCCON & 0xBF);
// Configure Input Functions (Table 9-1)

// Assign U1RX To Pin RP0
RPINR18bits.U1RXR = 0;
// Assign U1CTS To Pin RP1

RPINR18bits.U1CTSR = 1;
// Configure Output Functions (Table 9-2)

// Assign U1TX To Pin RP2
RPOR1bits.RP2R = 3;
// Assign U1RTS To Pin RP3

RPOR1bits.RP3R = 4;
//lock registers
__builtin_write_OSCCONL(OSCCON | 0x40);

10.4.6 PERIPHERAL PIN SELECT Note: Input and output register values can only be
REGISTERS changed if IOLOCK (OSCCON<6>) = 0.
The PIC24FJ64GA104 family of devices implements a See Section 10.4.4.1 “Control Register
total of 27 registers for remappable peripheral Lock” for a specific command sequence.
configuration:
• Input Remappable Peripheral Registers (14)
• Output Remappable Peripheral Registers (13)
REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — INT1R4 INT1R3 INT1R2 INT1R1 INT1R0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:

bit 12-8 INT1R<4:0>: Assign External Interrupt 1 (INT1) to Corresponding RPn or RPIn Pin bits

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — INT2R4 INT2R3 INT2R2 INT2R1 INT2R0
bit 7 bit 0
Legend:

bit 4-0 INT2R<4:0>: Assign External Interrupt 2 (INT2) to Corresponding RPn or RPIn pin bits

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

bit 7 bit 0
Legend:

bit 12-8 T3CKR<4:0>: Assign Timer3 External Clock (T3CK) to Corresponding RPn or RPIn Pin bits
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — IC2R4 IC2R3 IC2R2 IC2R1 IC2R0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

bit 7 bit 0
Legend:

bit 12-8 IC2R<4:0>: Assign Input Capture 2 (IC2) to Corresponding RPn or RPIn Pin bits

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

bit 7 bit 0
Legend:


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

bit 7 bit 0
Legend:

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0
bit 7 bit 0
Legend:

bit 12-8 OCFBR<4:0>: Assign Output Compare Fault B (OCFB) to Corresponding RPn or RPIn Pin bits
bit 4-0 OCFAR<4:0>: Assign Output Compare Fault A (OCFA) to Corresponding RPn or RPIn Pin bits

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0
bit 7 bit 0
Legend:

bit 12-8 U1CTSR<4:0>: Assign UART1 Clear to Send (U1CTS) to Corresponding RPn or RPIn Pin bits
bit 4-0 U1RXR<4:0>: Assign UART1 Receive (U1RX) to Corresponding RPn or RPIn Pin bits
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0
bit 7 bit 0
Legend:

bit 12-8 U2CTSR<4:0>: Assign UART2 Clear to Send (U2CTS) to Corresponding RPn or RPIn Pin bits
bit 4-0 U2RXR<4:0>: Assign UART2 Receive (U2RX) to Corresponding RPn or RPIn Pin bits

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0
bit 7 bit 0
Legend:

bit 12-8 SCK1R<4:0>: Assign SPI1 Clock Input (SCK1IN) to Corresponding RPn or RPIn Pin bits
bit 4-0 SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to Corresponding RPn or RPIn Pin bits
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — SS1R4 SS1R3 SS1R2 SS1R1 SS1R0
bit 7 bit 0
Legend:

bit 4-0 SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to Corresponding RPn or RPIn Pin bits

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0
bit 7 bit 0
Legend:

bit 12-8 SCK2R<4:0>: Assign SPI2 Clock Input (SCK2IN) to Corresponding RPn or RPIn Pin bits
bit 4-0 SDI2R<4:0>: Assign SPI2 Data Input (SDI2) to Corresponding RPn or RPIn Pin bits

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — SS2R4 SS2R3 SS2R2 SS2R1 SS2R0
bit 7 bit 0
Legend:

bit 4-0 SS2R<4:0>: Assign SPI2 Slave Select Input (SS2IN) to Corresponding RPn or RPIn Pin bits

REGISTER 10-15: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP1R4 RP1R3 RP1R2 RP1R1 RP1R0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:

bit 12-8 RP1R<4:0<: RP1 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP1 (see Table 10-3 for peripheral function numbers).
bit 4-0 RP0R<4:0>: RP0 Output Pin Mapping bits
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


REGISTER 10-23: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8(1)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:

Note 1: This register is unimplemented in 28-pin devices; all bits read as ‘0’.
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


11.0 TIMER1 Figure 11-1 presents a block diagram of the 16-bit timer
module.
Note: This data sheet summarizes the features To configure Timer1 for operation:
intended to be a comprehensive reference 1. Set the TON bit (= 1).
source. For more information, refer to the 2. Select the timer prescaler ratio using the
“PIC24F Family Reference Manual”, TCKPS<1:0> bits.
Section 14. “Timers” (DS39704). 3. Set the Clock and Gating modes using the TCS
and TGATE bits.
The Timer1 module is a 16-bit timer which can serve as
the time counter for the Real-Time Clock (RTC) or 4. Set or clear the TSYNC bit to configure
operate as a free-running, interval timer/counter. synchronous or asynchronous operation.
Timer1 can operate in three modes: 5. Load the timer period value into the PR1
register.
• 16-Bit Timer
6. If interrupts are required, set the interrupt enable
• 16-Bit Synchronous Counter
bit, T1IE. Use the priority bits, T1IP<2:0>, to set
• 16-Bit Asynchronous Counter the interrupt priority.
Timer1 also supports these features:
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation during CPU Idle and Sleep
modes
• Interrupt on 16-Bit Period Register Match or
Falling Edge of External Gate Signal
FIGURE 11-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM
TCKPS<1:0>
SOSCO/ TON 2
1x
T1CK
Gate Prescaler
SOSCEN Sync 01 1, 8, 64, 256
SOSCI
TCY 00
TGATE
TGATE TCS
1 Q D
Set T1IF
0 Q CK
0
Reset
TMR1
1 Sync
Comparator TSYNC
Equal
PR1

REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER(1)
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

TON — TSIDL — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0

— TGATE TCKPS1 TCKPS0 — TSYNC TCS —
bit 7 bit 0
Legend:
bit 15 TON: Timer1 On bit

1 = Starts 16-bit Timer1
0 = Stops 16-bit Timer1
bit 13 TSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation enabled
0 = Gated time accumulation disabled
bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1:
1 = Synchronize external clock input
0 = Do not synchronize external clock input
When TCS = 0:
bit 1 TCS: Timer1 Clock Source Select bit
1 = External clock from T1CK pin (on the rising edge)
0 = Internal clock (FOSC/2)
Note 1: Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.

12.0 TIMER2/3 AND TIMER4/5 To configure Timer2/3 or Timer4/5 for 32-bit operation:
1. Set the T32 bit (T2CON<3> or T4CON<3> = 1).
2. Select the prescaler ratio for Timer2 or Timer4
using the TCKPS<1:0> bits.
source. For more information, refer to the 3. Set the Clock and Gating modes using the TCS
“PIC24F Family Reference Manual”, and TGATE bits. If TCS is set to an external
Section 14. “Timers” (DS39704). clock, RPINRx (TxCK) must be configured to an
available RPn pin. See Section
The Timer2/3 and Timer4/5 modules are 32-bit timers, 10.4 “Peripheral Pin Select (PPS)” for more
which can also be configured as four independent 16-bit information.
timers with selectable operating modes. 4. Load the timer period value. PR3 (or PR5) will
As 32-bit timers, Timer2/3 and Timer4/5 can each contain the most significant word of the value
operate in three modes: while PR2 (or PR4) contains the least significant
word.
• Two Independent 16-Bit Timers with All 16-Bit
Operating modes (except Asynchronous Counter 5. If interrupts are required, set the interrupt enable
mode) bit, T3IE or T5IE; use the priority bits, T3IP<2:0>
or T5IP<2:0>, to set the interrupt priority. Note
• Single 32-Bit Timer
that while Timer2 or Timer4 controls the timer,
• Single 32-Bit Synchronous Counter the interrupt appears as a Timer3 or Timer5
They also support these features: interrupt.
• Timer Gate Operation 6. Set the TON bit (= 1).
• Selectable Prescaler Settings The timer value, at any point, is stored in the register
• Timer Operation during Idle and Sleep modes pair, TMR3:TMR2 (or TMR5:TMR4). TMR3 (TMR5)
• Interrupt on a 32-Bit Period Register Match always contains the most significant word of the count,
while TMR2 (TMR4) contains the least significant word.
• ADC Event Trigger (Timer4/5 only)
To configure any of the timers for individual 16-bit
Individually, all four of the 16-bit timers can function as
operation:
synchronous timers or counters. They also offer the
features listed above, except for the ADC event trigger; 1. Clear the T32 bit corresponding to that timer
this is implemented only with Timer5. The operating (T2CON<3> for Timer2 and Timer3 or
modes and enabled features are determined by setting T4CON<3> for Timer4 and Timer5).
the appropriate bit(s) in the T2CON, T3CON, T4CON 2. Select the timer prescaler ratio using the
and T5CON registers. T2CON and T4CON are shown TCKPS<1:0> bits.
in generic form in Register 12-1; T3CON and T5CON 3. Set the Clock and Gating modes using the TCS
are shown in Register 12-2. and TGATE bits. See Section 10.4 “Peripheral
For 32-bit timer/counter operation, Timer2 and Timer4 Pin Select (PPS)” for more information.
are the least significant word; Timer3 and Timer4 are 4. Load the timer period value into the PRx register.
the most significant word of the 32-bit timers. 5. If interrupts are required, set the interrupt enable
Note: For 32-bit operation, T3CON and T5CON bit, TxIE; use the priority bits, TxIP<2:0>, to set
control bits are ignored. Only T2CON and the interrupt priority.
T4CON control bits are used for setup and 6. Set the TON bit (TxCON<15> = 1).
control. Timer2 and Timer4 clock and gate
inputs are utilized for the 32-bit timer
modules, but an interrupt is generated with
the Timer3 or Timer5 interrupt flags.

FIGURE 12-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM
TCKPS<1:0>
T2CK TON 2
1x
(T4CK)
Gate Prescaler
Sync 01 1, 8, 64, 256
TCY 00
TGATE TGATE(2)
TCS(2)
1 Q D
Set T3IF (T5IF)
Q CK
0
PR3 PR2
(PR5) (PR4)
ADC Event Trigger(3)

Equal
Comparator
MSB LSB
TMR3 TMR2
Sync
Reset (TMR5) (TMR4)
16
(1)
Read TMR2 (TMR4)
Write TMR2 (TMR4)(1)
16
TMR3HLD 16
(TMR5HLD)
Data Bus<15:0>
Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are
respective to the T2CON and T4CON registers.
2: The timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral
Pin Select (PPS)” for more information.
3: The ADC event trigger is available only on Timer 2/3 in 32-bit mode and Timer 3 in 16-bit mode.

FIGURE 12-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
TCKPS<1:0>
TON 2
T2CK 1x
(T4CK)
Gate Prescaler
Sync 01 1, 8, 64, 256
TGATE 00
TCY TCS(1)
1 Q D TGATE(1)
Set T2IF (T4IF) Q CK
0
Reset
TMR2 (TMR4) Sync
Comparator
Equal
PR2 (PR4)
Note 1: The timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral
FIGURE 12-3: TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM
TCKPS<1:0>
T3CK TON 2
Sync 1x
(T5CK)
Prescaler
01 1, 8, 64, 256
TGATE 00
TCY TCS(1)
1 Q D TGATE(1)
Set T3IF (T5IF) Q CK
0
Reset
TMR3 (TMR5)
ADC Event Trigger(2)

Comparator
Equal
PR3 (PR5)
Note 1: The timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral
2: The ADC event trigger is available only on Timer3.

REGISTER 12-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(3)
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

TON — TSIDL — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0

— TGATE TCKPS1 TCKPS0 T32(1) — TCS(2) —
bit 7 bit 0
Legend:
bit 15 TON: Timerx On bit

When TxCON<3> = 1:
1 = Starts 32-bit Timerx/y
0 = Stops 32-bit Timerx/y
When TxCON<3> = 0:
1 = Starts 16-bit Timerx
0 = Stops 16-bit Timerx
bit 13 TSIDL: Stop in Idle Mode bit
bit 6 TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3 T32: 32-Bit Timer Mode Select bit(1)
1 = Timerx and Timery form a single 32-bit timer
0 = Timerx and Timery act as two 16-bit timers
In 32-bit mode, T3CON control bits do not affect 32-bit timer operation.
bit 1 TCS: Timerx Clock Source Select bit(2)
1 = External clock from pin, TxCK (on the rising edge)
Note 1: In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation.
2: If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. For more information, see
Section 10.4 “Peripheral Pin Select (PPS)”.
3: Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to

REGISTER 12-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER(3)
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

TON(1) — TSIDL(1) — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0

— TGATE(1) TCKPS1(1) TCKPS0(1) — — TCS(1,2) —
bit 7 bit 0
Legend:
bit 15 TON: Timery On bit(1)

1 = Starts 16-bit Timery
0 = Stops 16-bit Timery
bit 13 TSIDL: Stop in Idle Mode bit(1)
bit 6 TGATE: Timery Gated Time Accumulation Enable bit(1)
When TCS = 1:
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timery Input Clock Prescale Select bits(1)
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 1 TCS: Timery Clock Source Select bit(1,2)
1 = External clock from pin TyCK (on the rising edge)
Note 1: When 32-bit operation is enabled (T2CON<3> or T4CON<3> = 1), these bits have no effect on Timery
operation; all timer functions are set through T2CON and T4CON.
2: If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 10.4 “Peripheral
3: Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to

NOTES:

13.0 INPUT CAPTURE WITH 13.1 General Operating Modes
DEDICATED TIMERS
13.1.1 SYNCHRONOUS AND TRIGGER
Note: This data sheet summarizes the features MODES
of this group of PIC24F devices. It is not By default, the input capture module operates in a
intended to be a comprehensive reference free-running mode. The internal 16-bit counter ICxTMR
source. For more information, refer to the counts up continuously, wrapping around from FFFFh
“PIC24F Family Reference Manual”, to 0000h on each overflow, with its period synchronized
Section 34. “Input Capture with to the selected external clock source. When a capture
Dedicated Timer” (DS39722). event occurs, the current 16-bit value of the internal
Devices in the PIC24FJ64GA104 family all feature 5 counter is written to the FIFO buffer.
independent input capture modules. Each of the In Synchronous mode, the module begins capturing
modules offers a wide range of configuration and events on the ICx pin as soon as its selected clock
operating options for capturing external pulse events source is enabled. Whenever an event occurs on the
and generating interrupts. selected sync source, the internal counter is reset. In
Key features of the input capture module include: Trigger mode, the module waits for a Sync event from
another internal module to occur before allowing the
• Hardware-configurable for 32-bit operation in all internal counter to run.
modes by cascading two adjacent modules
Standard, free-running operation is selected by setting
• Synchronous and Trigger modes of output
the SYNCSEL bits to ‘00000’ and clearing the ICTRIG
compare operation, with up to 20 user-selectable
bit (ICxCON2<7>). Synchronous and Trigger modes
trigger/sync sources available
are selected any time the SYNCSEL bits are set to any
• A 4-level FIFO buffer for capturing and holding value except ‘00000’. The ICTRIG bit selects either
timer values for several events Synchronous or Trigger mode; setting the bit selects
• Configurable interrupt generation Trigger mode operation. In both modes, the SYNCSEL
• Up to 6 clock sources available for each module, bits determine the sync/trigger source.
driving a separate internal 16-bit counter When the SYNCSEL bits are set to ‘00000’ and
The module is controlled through two registers: ICxCON1 ICTRIG is set, the module operates in Software Trigger
(Register 13-1) and ICxCON2 (Register 13-2). A general mode. In this case, capture operations are started by
block diagram of the module is shown in Figure 13-1. manually setting the TRIGSTAT bit (ICxCON2<6>).
FIGURE 13-1: INPUT CAPTURE BLOCK DIAGRAM

ICM<2:0>
ICI<1:0>
Prescaler Edge Detect Logic Event and Set ICxIF

Counter and Interrupt
1:1/4/16 Clock Synchronizer Logic
ICx Pin(1)
ICTSEL<2:0>
Clock Increment 16
IC Clock Select ICxTMR 4-Level FIFO Buffer
Sources 16
Trigger and
Sync Logic 16
Reset
Trigger and ICxBUF
Sync Sources
SYNCSEL<4:0>
Trigger
ICOV, ICBNE System Bus
Note 1: The ICx inputs must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral

13.1.2 CASCADED (32-BIT) MODE For 32-bit cascaded operations, the setup procedure is
slightly different:
By default, each module operates independently with
its own 16-bit timer. To increase resolution, adjacent 1. Set the IC32 bits for both modules
even and odd modules can be configured to function as (ICyCON2<8> and (ICxCON2<8>), enabling the
a single 32-bit module. (For example, modules 1 and 2 even-numbered module first. This ensures the
are paired, as are modules 3 and 4, and so on.) The modules will start functioning in unison.
odd-numbered module (ICx) provides the Least Signif- 2. Set the ICTSEL and SYNCSEL bits for both
icant 16 bits of the 32-bit register pairs, and the even modules to select the same sync/trigger and
module (ICy) provides the Most Significant 16 bits. time base source. Set the even module first,
Wrap-arounds of the ICx registers cause an increment then the odd module. Both modules must use
of their corresponding ICy registers. the same ICTSEL and SYNCSEL settings.
Cascaded operation is configured in hardware by 3. Clear the ICTRIG bit of the even module
setting the IC32 bits (ICxCON2<8>) for both modules. (ICyCON2<7>); this forces the module to run in
Synchronous mode with the odd module,
13.2 Capture Operations regardless of its trigger setting.
The input capture module can be configured to capture 4. Use the odd module’s ICI bits (ICxCON1<6:5>)
timer values and generate interrupts on rising edges on to the desired interrupt frequency.
ICx, or all transitions on ICx. Captures can be configured 5. Use the ICTRIG bit of the odd module
to occur on all rising edges or just some (every 4th or (ICxCON2<7>) to configure Trigger or
16th). Interrupts can be independently configured to Synchronous mode operation.
generate on each event or a subset of events. Note: For Synchronous mode operation, enable
To set up the module for capture operations: the sync source as the last step. Both
1. Configure the ICx input for one of the available input capture modules are held in Reset
Peripheral Pin Select pins. until the sync source is enabled.
2. If Synchronous mode is to be used, disable the 6. Use the ICM bits of the odd module
sync source before proceeding. (ICxCON1<2:0>) to set the desired capture
mode.
3. Make sure that any previous data has been
removed from the FIFO by reading ICxBUF until The module is ready to capture events when the time
the ICBNE bit (ICxCON1<3>) is cleared. base and the trigger/sync source are enabled. When
4. Set the SYNCSEL bits (ICxCON2<4:0>) to the the ICBNE bit (ICxCON1<3>) becomes set, at least
desired sync/trigger source. one capture value is available in the FIFO. Read input
capture values from the FIFO until the ICBNE clears to
5. Set the ICTSEL bits (ICxCON1<12:10>) for the
‘0’.
desired clock source. If the desired clock source
is running, set the ICTSEL bits before the Input For 32-bit operation, read both the ICxBUF and
Capture module is enabled for proper ICyBUF for the full 32-bit timer value (ICxBUF for the
synchronization with the desired clock source. lsw, ICyBUF for the msw). At least one capture value is
6. Set the ICI bits (ICxCON1<6:5>) to the desired available in the FIFO buffer when the odd module’s
interrupt frequency. ICBNE bit (ICxCON1<3>) becomes set. Continue to
read the buffer registers until ICBNE is cleared
7. Select Synchronous or Trigger mode operation:
(perform automatically by hardware).
a) Check that the SYNCSEL bits are not set to
‘00000’.
b) For Synchronous mode, clear the ICTRIG
bit (ICxCON2<7>).
c) For Trigger mode, set ICTRIG and clear the
TRIGSTAT bit (ICxCON2<6>).
8. Set the ICM bits (ICxCON1<2:0>) to the desired
operational mode.
9. Enable the selected trigger/sync source.

REGISTER 13-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0

— — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R-0, HCS R-0, HCS R/W-0 R/W-0 R/W-0
— ICI1 ICI0 ICOV ICBNE ICM2(1) ICM1(1) ICM0(1)
bit 7 bit 0
Legend: HCS = Hardware Clearable/Settable bit


bit 13 ICSIDL: Input Capture x Module Stop in Idle Control bit
1 = Input capture module halts in CPU Idle mode
0 = Input capture module continues to operate in CPU Idle mode
bit 12-10 ICTSEL<2:0>: Input Capture Timer Select bits
111 = System clock (FOSC/2)
110 = Reserved
101 = Reserved
100 = Timer1
011 = Timer5
010 = Timer4
001 = Timer2
000 = Timer3
bit 6-5 ICI<1:0>: Select Number of Captures per Interrupt bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4 ICOV: Input Capture x Overflow Status Flag bit (read-only)
1 = Input capture overflow occurred
0 = No input capture overflow occurred
bit 3 ICBNE: Input Capture x Buffer Empty Status bit (read-only)
1 = Input capture buffer is not empty, at least one more capture value can be read
0 = Input capture buffer is empty
bit 2-0 ICM<2:0>: Input Capture Mode Select bits(1)
111 = Interrupt mode: input capture functions as interrupt pin only when device is in Sleep or Idle mode
(rising edge detect only, all other control bits are not applicable)
110 = Unused (module disabled)
101 = Prescaler Capture mode: capture on every 16th rising edge
100 = Prescaler Capture mode: capture on every 4th rising edge
011 = Simple Capture mode: capture on every rising edge
010 = Simple Capture mode: capture on every falling edge
001 = Edge Detect Capture mode: capture on every edge (rising and falling); ICI<1:0 bits do not control
interrupt generation for this mode
000 = Input capture module turned off
Note 1: The ICx input must also be configured to an available RPn pin. For more information, see Section 10.4
“Peripheral Pin Select (PPS)”.

REGISTER 13-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — IC32
bit 15 bit 8
R/W-0 R/W-0, HS U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1

ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
bit 7 bit 0


bit 8 IC32: Cascade Two IC Modules Enable bit (32-bit operation)
1 = ICx and ICy operate in cascade as a 32-bit module (this bit must be set in both modules)
0 = ICx functions independently as a 16-bit module
bit 7 ICTRIG: ICx Trigger/Sync Select bit
1 = Trigger ICx from source designated by SYNCSELx bits
0 = Synchronize ICx with source designated by SYNCSELx bits
bit 6 TRIGSTAT: Timer Trigger Status bit
1 = Timer source has been triggered and is running (set in hardware, can be set in software)
0 = Timer source has not been triggered and is being held clear
bit 4-0 SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits
11111 = Reserved
11110 = Reserved
11101 = Reserved
11100 = CTMU(1)
11011 = A/D(1)
11010 = Comparator 3(1)
10111 = Input Capture 4
10011 = Reserved
10010 = Reserved
1000x = Reserved
01111 = Timer5
01110 = Timer4
01101 = Timer3
01100 = Timer2
01011 = Timer1
01001 = Reserved
01000 = Reserved
00111 = Reserved
00110 = Reserved
00101 = Output Compare 5
00000 = Not synchronized to any other module
Note 1: Use these inputs as trigger sources only and never as sync sources.

14.0 OUTPUT COMPARE WITH In Synchronous mode, the module begins performing
its compare or PWM operation as soon as its selected
DEDICATED TIMERS
clock source is enabled. Whenever an event occurs on
Note: This data sheet summarizes the features the selected sync source, the module’s internal counter
of this group of PIC24F devices. It is not is reset. In Trigger mode, the module waits for a sync
intended to be a comprehensive reference event from another internal module to occur before
source. For more information, refer to the allowing the counter to run.
“PIC24F Family Reference Manual”, Free-Running mode is selected by default or any time
Section 35. “Output Capture with that the SYNCSEL bits (OCxCON2<4:0>) are set to
Dedicated Timer” (DS39723). ‘00000’. Synchronous or Trigger modes are selected
All devices in the PIC24FJ64GA104 family features any time the SYNCSEL bits are set to any value except
5 independent output compare modules. Each of these ‘00000’. The OCTRIG bit (OCxCON2<7>) selects
modules offers a wide range of configuration and oper- either Synchronous or Trigger mode; setting the bit
ating options for generating pulse trains on internal selects Trigger mode operation. In both modes, the
device events, and can produce Pulse-Width Modulated SYNCSEL bits determine the sync/trigger source.
(PWM) waveforms for driving power applications.
14.1.2 CASCADED (32-BIT) MODE
Key features of the output compare module include:
By default, each module operates independently with
• Hardware-configurable for 32-bit operation in all
its own set of 16-bit Timer and Duty Cycle registers. To
modes by cascading two adjacent modules
increase the range, adjacent even and odd modules
• Synchronous and Trigger modes of output can be configured to function as a single 32-bit module.
compare operation, with up to 21 user-selectable (For example, Modules 1 and 2 are paired, as are
trigger/sync sources available Modules 3 and 4, and so on.) The odd-numbered
• Two separate Period registers (a main register, module (OCx) provides the Least Significant 16 bits of
OCxR, and a secondary register, OCxRS) for the 32-bit register pairs and the even-numbered
greater flexibility in generating pulses of varying module (OCy) provides the Most Significant 16 bits.
widths Wrap-arounds of the OCx registers cause an increment
• Configurable for single pulse or continuous pulse of their corresponding OCy registers.
generation on an output event or continuous Cascaded operation is configured in hardware by setting
PWM waveform generation the OC32 bit (OCxCON2<8>) for both modules.
• Up to 6 clock sources available for each module,
driving a separate internal 16-bit counter
14.1 General Operating Modes

14.1.1 SYNCHRONOUS AND TRIGGER
MODES
By default, the output compare module operates in a
Free-Running mode. The internal 16-bit counter,
OCxTMR, runs counts up continuously, wrapping
around from FFFFh to 0000h on each overflow with its
period synchronized to the selected external clock
source. Compare or PWM events are generated each
time a match between the internal counter and one of
the Period registers occurs.

FIGURE 14-1: OUTPUT COMPARE BLOCK DIAGRAM (16-BIT MODE)
DCBx
OCMx
OCxCON1 OCINV
OCTRIS
OCTSELx
OCxCON2 FLTOUT
SYNCSELx
FLTTRIEN
TRIGSTAT
FLTMD
TRIGMODE
ENFLTx
OCTRIG OCxR OCFLTx
Match Event OCx Pin(1)

Comparator
Clock Increment
OC Clock
Sources Select
OCxTMR OC Output and
Reset Fault Logic OCFA/
OCFB/
Match Event CxOUT
Comparator
Match Event
Trigger and Trigger and
Sync Sources Sync Logic OCxRS
Reset
OCx Interrupt
Note 1: The OCx outputs must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral

14.2 Compare Operations For 32-bit cascaded operation, these steps are also
necessary:
In Compare mode (Figure 14-1), the output compare
module can be configured for single-shot or continuous 1. Set the OC32 bits for both registers
pulse generation; it can also repeatedly toggle an (OCyCON2<8> and (OCxCON2<8>). Enable
output pin on each timer event. the even-numbered module first to ensure the
modules will start functioning in unison.
To set up the module for compare operations:
2. Clear the OCTRIG bit of the even module
1. Configure the OCx output for one of the (OCyCON2), so the module will run in
available Peripheral Pin Select pins. Synchronous mode.
2. Calculate the required values for the OCxR and 3. Configure the desired output and Fault settings
(for Double Compare modes) OCxRS Duty Cycle for OCy.
registers:
4. Force the output pin for OCx to the output state
a) Determine the instruction clock cycle time. by clearing the OCTRIS bit.
Take into account the frequency of the
5. If Trigger mode operation is required, configure
external clock to the timer source (if one is
the trigger options in OCx by using the OCTRIG
used) and the timer prescaler settings. (OCxCON2<7>), TRIGSTAT (OCxCON2<6>)
b) Calculate time to the rising edge of the and SYNCSEL (OCxCON2<4:0>) bits.
output pulse relative to the timer start value 6. Configure the desired Compare or PWM mode
(0000h). of operation (OCM<2:0>) for OCy first, then for
c) Calculate the time to the falling edge of the OCx.
pulse based on the desired pulse width and Depending on the output mode selected, the module
the time to the rising edge of the pulse. holds the OCx pin in its default state and forces a
3. Write the rising edge value to OCxR and the transition to the opposite state when OCxR matches
falling edge value to OCxRS. the timer. In Double Compare modes, OCx is forced
4. For Trigger mode operations, set OCTRIG to back to its default state when a match with OCxRS
enable Trigger mode. Set or clear TRIGMODE to occurs. The OCxIF interrupt flag is set after an OCxR
configure trigger operation and TRIGSTAT to match in Single Compare modes and after each
select a hardware or software trigger. For OCxRS match in Double Compare modes.
Synchronous mode, clear OCTRIG. Single-shot pulse events only occur once, but may be
5. Set the SYNCSEL<4:0> bits to configure the repeated by simply rewriting the value of the
trigger or synchronization source. If free-running OCxCON1 register. Continuous pulse events continue
timer operation is required, set the SYNCSEL indefinitely until terminated.
bits to ‘00000’ (no sync/trigger source).
6. Select the time base source with the
OCTSEL<2:0> bits. If the desired clock source is
running, set the OCTSEL<2:0> bits before the
output compare module is enabled for proper
synchronization with the desired clock source. If
necessary, set the TON bit for the selected timer
which enables the compare time base to count.
Synchronous mode operation starts as soon as
the synchronization source is enabled. Trigger
mode operation starts after a trigger source event
occurs.
7. Set the OCM<2:0> bits for the appropriate
compare operation (= 0xx).

14.3 Pulse-Width Modulation (PWM) 5. Select a clock source by writing to the
Mode OCTSEL2<2:0> (OCxCON1<12:10>) bits.
6. Enable interrupts, if required, for the timer and
In PWM mode, the output compare module can be output compare modules. The output compare
configured for edge-aligned or center-aligned pulse interrupt is required for PWM Fault pin utilization.
waveform generation. All PWM operations are 7. Select the desired PWM mode in the OCM<2:0>
double-buffered (buffer registers are internal to the (OCxCON1<2:0>) bits.
module and are not mapped into SFR space). 8. If a timer is selected as a clock source, set the
To configure the output compare module for TMRy prescale value and enable the time base by
edge-aligned PWM operation: setting the TON (TxCON<15>) bit.
1. Configure the OCx output for one of the Note: This peripheral contains input and output
available Peripheral Pin Select pins. functions that may need to be configured
2. Calculate the desired on-time and load it into the by the Peripheral Pin Select. See
OCxR register. Section 10.4 “Peripheral Pin Select
(PPS)” for more information.
3. Calculate the desired period and load it into the
OCxRS register.
4. Select the current OCx as the synchronization
source by writing 0x1F to SYNCSEL<4:0>
(OCxCON2<4:0>) and ‘0’ to OCTRIG
(OCxCON2<7>).
FIGURE 14-2: OUTPUT COMPARE BLOCK DIAGRAM

(DOUBLE-BUFFERED, 16-BIT PWM MODE)
OCxCON1
OCMx
OCxCON2 OCINV
OCTSELx OCTRIS
SYNCSELx OCxR and DCB<1:0> FLTOUT
TRIGSTAT FLTTRIEN
TRIGMODE FLTMD
OCTRIG Rollover/Reset ENFLTx
OCFLTx
OCxR and DCB<1:0> Buffers DCB<1:0>
OCx Pin(1)
Comparator Match
Clock Increment
OC Clock Event
Select
Sources
OC Output Timing
OCxTMR
Rollover and Fault Logic
Reset
Comparator OCFA/OCFB/CxOUT
Match Event Match
Trigger and Event
Trigger and
Sync Sources Sync Logic
OCxRS Buffer
Rollover/Reset
OCxRS
OCx Interrupt
Reset
Note 1: The OCx outputs must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Pin
Select (PPS)” for more information.

14.3.1 PWM PERIOD 14.3.2 PWM DUTY CYCLE
In edge aligned PWM mode, the period is specified by The PWM duty cycle is specified by writing to the
the value of OCxRS register. In center aligned PWM OCxRS and OCxR registers. The OCxRS and OCxR
mode, the period of the synchronization source such as registers can be written to at any time, but the duty
Timer's PRy specifies the period. The period in both cycle value is not latched until a period is complete.
cases can be calculated using Equation 14-1. This provides a double buffer for the PWM duty cycle
and is essential for glitchless PWM operation.
EQUATION 14-1: CALCULATING THE PWM Some important boundary parameters of the PWM duty
PERIOD(1) cycle include:
PWM Period = [Value + 1] x TCY x (Prescaler Value) • Edge-Aligned PWM
- If OCxR and OCxRS are loaded with 0000h,
Where: Value = OCxRS in Edge-Aligned PWM mode
and can be PRy in Center-Aligned PWM mode the OCx pin will remain low (0% duty cycle).
(If TMRy is the sync source). - If OCxRS is greater than OCxR, the pin will
remain high (100% duty cycle).
Note 1: Based on TCY = TOSC * 2; Doze mode
• Center-Aligned PWM (with TMRy as the sync
and PLL are disabled.
source)
- If OCxR, OCxRS and PRy are all loaded with
0000h, the OCx pin will remain low (0% duty
cycle).
- If OCxRS is greater than PRy, the pin will go
high (100% duty cycle).
See Example 14-1 for PWM mode timing details.
Table 14-1 and Table 14-2 show example PWM
frequencies and resolutions for a device operating at
4 MIPS and 10 MIPS, respectively.
EQUATION 14-2: CALCULATION FOR MAXIMUM PWM RESOLUTION(1)
Maximum PWM Resolution (bits) =

log10 (F
PWM
FCY
• (Prescale Value) ) bits
log10(2)
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
EXAMPLE 14-1: PWM PERIOD AND DUTY CYCLE CALCULATIONS(1)

1. Find the OCxRS register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device
clock rate) and a prescaler setting of 1:1 using Edge-Aligned PWM mode.
TCY = 2 * TOSC = 62.5 ns
PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 s
PWM Period = (OCxRS + 1) • TCY • (OCx Prescale Value)
19.2 s = (OCxRS + 1) • 62.5 ns • 1
OCxRS = 306
2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate:
PWM Resolution = log10 (FCY/FPWM)/log102) bits
= (log10 (16 MHz/52.08 kHz)/log102) bits
= 8.3 bits
Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.

14.4 Subcycle Resolution The DCB bits are intended for use with a clock source
identical to the system clock. When an OCx module
The DCB bits (OCxCON2<10:9>) provide for resolution with enabled prescaler is used, the falling edge delay
better than one instruction cycle. When used, they caused by the DCB bits will be referenced to the
delay the falling edge generated by a match event by a system clock period, rather than the OCx module's
portion of an instruction cycle. period.
For example, setting DCB<1:0> = 10 causes the falling
edge to occur half way through the instruction cycle in
which the match event occurs, instead of at the
beginning. These bits cannot be used when
OCM<2:0> = 001. When operating the module in PWM
mode (OCM<2:0> = 110 or 111), the DCB bits will be
double-buffered.
TABLE 14-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)(1)
PWM Frequency 7.6 Hz 61 Hz 122 Hz 977 Hz 3.9 kHz 31.3 kHz 125 kHz
Prescaler Ratio 8 1 1 1 1 1 1
Period Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh
Resolution (bits) 16 16 15 12 10 7 5
TABLE 14-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)(1)
PWM Frequency 30.5 Hz 244 Hz 488 Hz 3.9 kHz 15.6 kHz 125 kHz 500 kHz
Prescaler Ratio 8 1 1 1 1 1 1
Period Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh
Resolution (bits) 16 16 15 12 10 7 5

REGISTER 14-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(2)
— — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1
bit 15 bit 8
R/W-0 R/W-0, HCS R/W-0, HCS R/W-0, HCS R/W-0 R/W-0 R/W-0 R/W-0
ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2(1) OCM1(1) OCM0(1)
bit 7 bit 0
Legend: HCS = Hardware Clearable/Settable bit


bit 13 OCSIDL: Stop Output Compare x in Idle Mode Control bit
1 = Output compare x halts in CPU Idle mode
0 = Output compare x continues to operate in CPU Idle mode
bit 12-10 OCTSEL<2:0>: Output Compare x Timer Select bits
111 = System clock
110 = Reserved
101 = Reserved
100 = Timer1
011 = Timer5
010 = Timer4
001 = Timer3
000 = Timer2
bit 9 ENFLT2: Comparator Fault Input Enable bit(2)
1 = Comparator Fault input is enabled
0 = Comparator Fault input is disabled
bit 8 ENFLT1: OCFB Fault Input Enable bit
1 = OCFB Fault input is enabled
0 = OCFB Fault input is disabled
bit 7 ENFLT0: OCFA Fault Input Enable bit
1 = OCFA Fault input is enabled
0 = OCFA Fault input is disabled
bit 6 OCFLT2: PWM Comparator Fault Condition Status bit(2)
1 = PWM comparator Fault condition has occurred (this is cleared in hardware only)
0 = PWM comparator Fault condition has not occurred (this bit is used only when OCM<2:0> = 111)
bit 5 OCFLT1: PWM OCFB Fault Input Enable bit
1 = PWM OCFB Fault condition has occurred (this is cleared in hardware only)
0 = PWM OCFB Fault condition has not occurred (this bit is used only when OCM<2:0> = 111)
bit 4 OCFLT0: PWM OCFA Fault Condition Status bit
1 = PWM OCFA Fault condition has occurred (this is cleared in hardware only)
0 = PWM OCFA Fault condition has not occurred (this bit is used only when OCM<2:0> = 111)
bit 3 TRIGMODE: Trigger Status Mode Select bit
1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software
0 = TRIGSTAT is only cleared by software
Note 1: The OCx output must also be configured to an available RPn pin. For more information, see Section 10.4
2: The comparator module used for Fault input varies with the OCx module. OC1 and OC2 use Comparator 1;
OC3 and OC4 use Comparator 2; OC5 uses Comparator 3.

REGISTER 14-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED)
bit 2-0 OCM<2:0>: Output Compare x Mode Select bits(1)
111 = Center-Aligned PWM mode on OCx
110 = Edge-Aligned PWM mode on OCx
101 = Double Compare Continuous Pulse mode: initialize OCx pin low, toggle OCx state continuously
on alternate matches of OCxR and OCxRS
100 = Double Compare Single-Shot mode: initialize OCx pin low, toggle OCx state on matches of
OCxR and OCxRS for one cycle
011 = Single Compare Continuous Pulse mode: compare events continuously toggle OCx pin
010 = Single Compare Single-Shot mode: initialize OCx pin high, compare event forces OCx pin low
001 = Single Compare Single-Shot mode: initialize OCx pin low, compare event forces OCx pin high
000 = Output compare channel is disabled
Note 1: The OCx output must also be configured to an available RPn pin. For more information, see Section 10.4
2: The comparator module used for Fault input varies with the OCx module. OC1 and OC2 use Comparator 1;
OC3 and OC4 use Comparator 2; OC5 uses Comparator 3.

REGISTER 14-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
(3) (3)
FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32
bit 15 bit 8
R/W-0 R/W-0, HS R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0

OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
bit 7 bit 0

bit 15 FLTMD: Fault Mode Select bit

1 = Fault mode is maintained until the Fault source is removed and the corresponding OCFLT0 bit is
cleared in software
0 = Fault mode is maintained until the Fault source is removed and a new PWM period starts
bit 14 FLTOUT: Fault Out bit
1 = PWM output is driven high on a Fault
0 = PWM output is driven low on a Fault
bit 13 FLTTRIEN: Fault Output State Select bit
1 = Pin is forced to an output on a Fault condition
0 = Pin I/O condition is unaffected by a Fault
bit 12 OCINV: OCMP Invert bit
1 = OCx output is inverted
0 = OCx output is not inverted
bit 10-9 DCB<1:0>: OC Pulse-Width Least Significant bits(3)
11 = Delay OCx falling edge by 3/4 of the instruction cycle
00 = OCx falling edge occurs at start of the instruction cycle
bit 8 OC32: Cascade Two OC Modules Enable bit (32-bit operation)
1 = Cascade module operation enabled
0 = Cascade module operation disabled
bit 7 OCTRIG: OCx Trigger/Sync Select bit
1 = Trigger OCx from source designated by SYNCSELx bits
0 = Synchronize OCx with source designated by SYNCSELx bits
bit 6 TRIGSTAT: Timer Trigger Status bit
1 = Timer source has been triggered and is running
0 = Timer source has not been triggered and is being held clear
bit 5 OCTRIS: OCx Output Pin Direction Select bit
1 = OCx pin is tri-stated
0 = Output compare peripheral x connected to OCx pin
Note 1: Do not use an OC module as its own trigger source, either by selecting this mode or another equivalent
SYNCSEL setting.
2: Use these inputs as trigger sources only and never as sync sources.
3: These bits affect the rising edge when OCINV = 1. The bits have no effect when the
OCM bits (OCxCON1<1:0>) = 001.

REGISTER 14-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED)
bit 4-0 SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits
11111 = This OC module(1)
11110 = Reserved
11101 = Reserved
11100 = CTMU(2)
11011 = A/D(2)
10111 = Input Capture 4(2)
100xx = Reserved
01111 = Timer5
01110 = Timer4
01101 = Timer3
01100 = Timer2
01011 = Timer1
01001 = Reserved
01000 = Reserved
00111 = Reserved
00110 = Reserved
00101 = Output Compare 5(1)
00000 = Not synchronized to any other module
Note 1: Do not use an OC module as its own trigger source, either by selecting this mode or another equivalent
SYNCSEL setting.
2: Use these inputs as trigger sources only and never as sync sources.
3: These bits affect the rising edge when OCINV = 1. The bits have no effect when the
OCM bits (OCxCON1<1:0>) = 001.

15.0 SERIAL PERIPHERAL The SPI serial interface consists of four pins:
INTERFACE (SPI) • SDIx: Serial Data Input
• SDOx: Serial Data Output
• SCKx: Shift Clock Input or Output
intended to be a comprehensive reference • SSx: Active-Low Slave Select or Frame
source. For more information, refer to the Synchronization I/O Pulse
“PIC24F Family Reference Manual”, The SPI module can be configured to operate using
Section 23. “Serial Peripheral Interface 2, 3 or 4 pins. In the 3-pin mode, SSx is not used. In the
(SPI)” (DS39699). 2-pin mode, both SDOx and SSx are not used.
The Serial Peripheral Interface (SPI) module is a Block diagrams of the module in Standard and
synchronous serial interface useful for communicating Enhanced modes are shown in Figure 15-1 and
with other peripheral or microcontroller devices. These Figure 15-2.
peripheral devices may be serial EEPROMs, shift Note: In this section, the SPI modules are
registers, display drivers, A/D Converters, etc. The SPI referred to together as SPIx or separately
module is compatible with Motorola® SPI and SIOP as SPI1, SPI2 or SPI3. Special Function
interfaces. All devices of the PIC24FJ64GA104 family Registers will follow a similar notation. For
include three SPI modules example, SPIxCON1 and SPIxCON2 refer
The module supports operation in two buffer modes. In to the control registers for any of the 3 SPI
Standard mode, data is shifted through a single serial modules.
buffer. In Enhanced Buffer mode, data is shifted
through an 8-level FIFO buffer.
Note: Do not perform read-modify-write opera-
tions (such as bit-oriented instructions) on
the SPIxBUF register in either Standard or
Enhanced Buffer mode.
The module also supports a basic framed SPI protocol
while operating in either Master or Slave mode. A total
of four framed SPI configurations are supported.

To set up the SPI module for the Standard Master mode To set up the SPI module for the Standard Slave mode
of operation: of operation:
1. If using interrupts: 1. Clear the SPIxBUF register.
a) Clear the SPIxIF bit in the respective IFS 2. If using interrupts:
register. a) Clear the SPIxIF bit in the respective IFS
b) Set the SPIxIE bit in the respective IEC register.
register. b) Set the SPIxIE bit in the respective IEC
c) Write the SPIxIP bits in the respective IPC register.
register to set the interrupt priority. c) Write the SPIxIP bits in the respective IPC
2. Write the desired settings to the SPIxCON1 register to set the interrupt priority.
and SPIxCON2 registers with MSTEN 3. Write the desired settings to the SPIxCON1
(SPIxCON1<5>) = 1. and SPIxCON2 registers with MSTEN
3. Clear the SPIROV bit (SPIxSTAT<6>). (SPIxCON1<5>) = 0.
4. Enable SPI operation by setting the SPIEN bit 4. Clear the SMP bit.
(SPIxSTAT<15>). 5. If the CKE bit (SPIxCON1<8>) is set, then the
5. Write the data to be transmitted to the SPIxBUF SSEN bit (SPIxCON1<7>) must be set to enable
register. Transmission (and reception) will start the SSx pin.
as soon as data is written to the SPIxBUF 6. Clear the SPIROV bit (SPIxSTAT<6>).
register. 7. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
FIGURE 15-1: SPIx MODULE BLOCK DIAGRAM (STANDARD MODE)
SCKx 1:1 to 1:8 1:1/4/16/64

Secondary Primary FCY
Prescaler Prescaler
SSx/FSYNCx
Sync Control Select
Control Clock Edge SPIxCON1<1:0>
Shift Control SPIxCON1<4:2>

SDOx
Enable
SDIx bit 0 Master Clock
SPIxSR
Transfer Transfer
SPIxBUF
Read SPIxBUF Write SPIxBUF
16
Internal Data Bus

To set up the SPI module for the Enhanced Buffer To set up the SPI module for the Enhanced Buffer
Master mode of operation: Slave mode of operation:
1. If using interrupts: 1. Clear the SPIxBUF register.
a) Clear the SPIxIF bit in the respective IFS 2. If using interrupts:
register. a) Clear the SPIxIF bit in the respective IFS
b) Set the SPIxIE bit in the respective IEC register.
register. b) Set the SPIxIE bit in the respective IEC
c) Write the SPIxIP bits in the respective IPC register.
register. c) Write the SPIxIP bits in the respective IPC
2. Write the desired settings to the SPIxCON1 register to set the interrupt priority.
and SPIxCON2 registers with MSTEN 3. Write the desired settings to the SPIxCON1
(SPIxCON1<5>) = 1. and SPIxCON2 registers with MSTEN
3. Clear the SPIROV bit (SPIxSTAT<6>). (SPIxCON1<5>) = 0.
4. Select Enhanced Buffer mode by setting the 4. Clear the SMP bit.
SPIBEN bit (SPIxCON2<0>). 5. If the CKE bit is set, then the SSEN bit must be
5. Enable SPI operation by setting the SPIEN bit set, thus enabling the SSx pin.
(SPIxSTAT<15>). 6. Clear the SPIROV bit (SPIxSTAT<6>).
6. Write the data to be transmitted to the SPIxBUF 7. Select Enhanced Buffer mode by setting the
register. Transmission (and reception) will start SPIBEN bit (SPIxCON2<0>).
as soon as data is written to the SPIxBUF 8. Enable SPI operation by setting the SPIEN bit
register. (SPIxSTAT<15>).
FIGURE 15-2: SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)

SCKx 1:1/4/16/64
1:1 to 1:8
Secondary Primary FCY
Prescaler Prescaler
SSx/FSYNCx
Sync Control Select
Control Clock Edge SPIxCON1<1:0>
Shift Control SPIxCON1<4:2>

SDOx
Enable
SDIx bit 0 Master Clock
SPIxSR
Transfer Transfer
8-Level FIFO 8-Level FIFO

Receive Buffer Transmit Buffer
SPIxBUF
Read SPIxBUF Write SPIxBUF
16
Internal Data Bus

REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 R-0 R-0 R-0
(1)
SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0
bit 15 bit 8
R-0 R/C-0, HS R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0

SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF
bit 7 bit 0
Legend: C = Clearable bit HS = Hardware Settable bit

bit 15 SPIEN: SPIx Enable bit(1)

1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables module
bit 13 SPISIDL: Stop in Idle Mode bit
bit 10-8 SPIBEC<2:0>: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)
Master mode:
Number of SPI transfers that are pending.
Slave mode:
Number of SPI transfers that are unread.
bit 7 SRMPT: Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)
1 = SPIx Shift register is empty and ready to send or receive
0 = SPIx Shift register is not empty
bit 6 SPIROV: Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded. The user software has not read the previous
data in the SPIxBUF register.
0 = No overflow has occurred
bit 5 SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = Receive FIFO is empty
0 = Receive FIFO is not empty
bit 4-2 SISEL<2:0>: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111 = Interrupt when SPIx transmit buffer is full (SPITBF bit is set)
110 = Interrupt when last bit is shifted into SPIxSR; as a result, the TX FIFO is empty
101 = Interrupt when the last bit is shifted out of SPIxSR; now the transmit is complete
100 = Interrupt when one data is shifted into the SPIxSR; as a result, the TX FIFO has one open spot
011 = Interrupt when SPIx receive buffer is full (SPIRBF bit is set)
010 = Interrupt when SPIx receive buffer is 3/4 or more full
001 = Interrupt when data is available in the receive buffer (SRMPT bit is set)
000 = Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty
(SRXMPT bit set)
Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 10.4
“Peripheral Pin Select (PPS)” for more information.

REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)
bit 1 SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit not yet started; SPIxTXB is full
0 = Transmit started; SPIxTXB is empty
In Standard Buffer mode:
Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB. Automatically
cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.
In Enhanced Buffer mode:
Automatically set in hardware when CPU writes SPIxBUF location, loading the last available buffer location.
Automatically cleared in hardware when a buffer location is available for a CPU write.
bit 0 SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive is complete, SPIxRXB is full
0 = Receive is not complete, SPIxRXB is empty
In Standard Buffer mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically
cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.
In Enhanced Buffer mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unread
buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from
SPIxSR.
Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 10.4
“Peripheral Pin Select (PPS)” for more information.

REGISTER 15-2: SPIXCON1: SPIx CONTROL REGISTER 1
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — DISSCK(1) DISSDO(2) MODE16 SMP CKE(3)
bit 15 bit 8

(4)
SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0
bit 7 bit 0
Legend:

bit 12 DISSCK: Disable SCKx pin bit (SPI Master modes only)(1)
1 = Internal SPI clock is disabled; pin functions as I/O
0 = Internal SPI clock is enabled
bit 11 DISSDO: Disable SDOx pin bit(2)
1 = SDOx pin is not used by module; pin functions as I/O
0 = SDOx pin is controlled by the module
bit 10 MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
bit 9 SMP: SPIx Data Input Sample Phase bit
Master mode:
1 = Input data is sampled at the end of data output time
0 = Input data is sampled at the middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8 CKE: SPIx Clock Edge Select bit(3)
1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
bit 7 SSEN: Slave Select Enable (Slave mode) bit(4)
1 = SSx pin is used for Slave mode
0 = SSx pin is not used by module; pin is controlled by port function
bit 6 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5 MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
Note 1: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin
2: If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin
3: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
4: If SSEN = 1, SSx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select

REGISTER 15-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)
111 = Secondary prescale 1:1
...
bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)
11 = Primary prescale 1:1
Note 1: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin
2: If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin
3: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
4: If SSEN = 1, SSx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select
REGISTER 15-3: SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0

FRMEN SPIFSD SPIFPOL — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — SPIFE SPIBEN
bit 7 bit 0
Legend:
bit 15 FRMEN: Framed SPIx Support bit

1 = Framed SPIx support is enabled
0 = Framed SPIx support is disabled
bit 14 SPIFSD: Frame Sync Pulse Direction Control on SSx Pin bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
bit 13 SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only)
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
bit 1 SPIFE: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with the first bit clock
0 = Frame sync pulse precedes the first bit clock
bit 0 SPIBEN: Enhanced Buffer Enable bit
1 = Enhanced buffer is enabled
0 = Enhanced buffer is disabled (Legacy mode)

FIGURE 15-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE)
PROCESSOR 1 (SPI Master) PROCESSOR 2 (SPI Slave)
SDOx SDIx
Serial Receive Buffer Serial Receive Buffer

(SPIxRXB) (SPIxRXB)
Shift Register SDIx SDOx Shift Register

(SPIxSR) (SPIxSR)
MSb LSb MSb LSb
Serial Transmit Buffer Serial Transmit Buffer

(SPIxTXB) (SPIxTXB)
Serial Clock
SCKx SCKx SPIx Buffer
SPIx Buffer
(SPIxBUF)(2) (SPIxBUF)(2)
SSx(1)
MSTEN (SPIxCON1<5>) = 1) SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0
Note 1: Using the SSx pin in Slave mode of operation is optional.

2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory
mapped to SPIxBUF.
FIGURE 15-4: SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)
PROCESSOR 1 (SPI Enhanced Buffer Master) PROCESSOR 2 (SPI Enhanced Buffer Slave)
SDOx SDIx
Shift Register SDIx SDOx Shift Register

(SPIxSR) (SPIxSR)
MSb LSb MSb LSb
8-Level FIFO Buffer 8-Level FIFO Buffer
SPIx Buffer Serial Clock SPIx Buffer

(SPIxBUF)(2) SCKx SCKx (SPIxBUF)(2)
SSx SSx(1)
MSTEN (SPIxCON1<5>) = 1 and SSEN (SPIxCON1<7>) = 1,

SPIBEN (SPIxCON2<0>) = 1 MSTEN (SPIxCON1<5>) = 0 and
SPIBEN (SPIxCON2<0>) = 1
Note 1: Using the SSx pin in Slave mode of operation is optional.
2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory
mapped to SPIxBUF.

FIGURE 15-5: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM
PIC24F PROCESSOR 2
(SPI Master, Frame Master)
SDOx SDIx
SDIx SDOx
Serial Clock
SCKx SCKx
SSx SSx
Frame Sync
Pulse
FIGURE 15-6: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM
PIC24F PROCESSOR 2
SPI Master, Frame Slave)
SDOx SDIx
SDIx SDOx
Serial Clock
SCKx SCKx
SSx SSx
Frame Sync
Pulse
FIGURE 15-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM
PIC24F PROCESSOR 2
(SPI Slave, Frame Master)
SDOx SDIx
SDIx SDOx
Serial Clock
SCKx SCKx
SSx SSx
Frame Sync.
Pulse
FIGURE 15-8: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM
PIC24F PROCESSOR 2
(SPI Slave, Frame Slave)
SDOx SDIx
SDIx SDOx
Serial Clock
SCKx SCKx
SSx SSx
Frame Sync
Pulse

EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1)
FCY
FSCK =
Primary Prescaler * Secondary Prescaler
Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
TABLE 15-1: SAMPLE SCK FREQUENCIES(1,2)

Secondary Prescaler Settings
FCY = 16 MHz
1:1 2:1 4:1 6:1 8:1
Primary Prescaler Settings 1:1 Invalid 8000 4000 2667 2000
4:1 4000 2000 1000 667 500
16:1 1000 500 250 167 125
64:1 250 125 63 42 31
FCY = 5 MHz
Primary Prescaler Settings 1:1 5000 2500 1250 833 625
4:1 1250 625 313 208 156
16:1 313 156 78 52 39
64:1 78 39 20 13 10
2: SCKx frequencies are shown in kHz.

16.0 INTER-INTEGRATED CIRCUIT 16.1 Communicating as a Master in a
(I2C™) Single Master Environment
Note: This data sheet summarizes the features The details of sending a message in Master mode
of this group of PIC24F devices. It is not depends on the communications protocol for the device
intended to be a comprehensive reference being communicated with. Typically, the sequence of
source. For more information, refer to the events is as follows:
“PIC24F Family Reference Manual”, 1. Assert a Start condition on SDAx and SCLx.
Section 24. “Inter-Integrated Circuit™ 2. Send the I 2C device address byte to the slave
(I2C™)” (DS39702). with a write indication.
The Inter-Integrated Circuit (I2C) module is a serial 3. Wait for and verify an Acknowledge from the
interface useful for communicating with other peripheral slave.
or microcontroller devices. These peripheral devices 4. Send the first data byte (sometimes known as
may be serial EEPROMs, display drivers, A/D the command) to the slave.
Converters, etc. 5. Wait for and verify an Acknowledge from the
The I 2C
module supports these features: slave.
6. Send the serial memory address low byte to the
• Independent master and slave logic
slave.
• 7-bit and 10-bit device addresses
7. Repeat steps 4 and 5 until all data bytes are
• General call address as defined in the I2C protocol sent.
• Clock stretching to provide delays for the 8. Assert a Repeated Start condition on SDAx and
processor to respond to a slave data request SCLx.
• Both 100 kHz and 400 kHz bus specifications. 9. Send the device address byte to the slave with
• Configurable address masking a read indication.
• Multi-Master modes to prevent loss of messages 10. Wait for and verify an Acknowledge from the
in arbitration slave.
• Bus Repeater mode, allowing the acceptance of 11. Enable master reception to receive serial
all messages as a slave regardless of the address memory data.
• Automatic SCL 12. Generate an ACK or NACK condition at the end
A block diagram of the module is shown in Figure 16-1. of a received byte of data.
13. Generate a Stop condition on SDAx and SCLx.

FIGURE 16-1: I2C™ BLOCK DIAGRAM
Internal
Data Bus
I2CxRCV
Read
Shift
SCLx Clock
I2CxRSR
LSB
SDAx Address Match

Match Detect Write
I2CxMSK
Write Read
I2CxADD
Read
Start and Stop

Bit Detect
Write
Start and Stop

Bit Generation I2CxSTAT
Control Logic
Read
Collision Write
Detect
I2CxCON
Acknowledge
Generation Read
Clock
Stretching
Write
I2CxTRN
LSB
Read
Shift Clock
Reload
Control
Write
BRG Down Counter I2CxBRG
Read
TCY/2

16.2 Setting Baud Rate When 16.3 Slave Address Masking
Operating as a Bus Master The I2CxMSK register (Register 16-3) designates
To compute the Baud Rate Generator (BRG) reload address bit positions as “don’t care” for both 7-Bit and
value, use Equation 16-1. 10-Bit Addressing modes. Setting a particular bit loca-
tion (= 1) in the I2CxMSK register causes the slave
EQUATION 16-1: COMPUTING BAUD RATE module to respond whether the corresponding address
RELOAD VALUE(1,2) bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK
FCY is set to ‘00100000’, the slave module will detect both
FSCL = ----------------------------------------------------------------------
FCY addresses: ‘0000000’ and ‘0100000’.
I2CxBRG + 1 + ------------------------------
10 000 000 To enable address masking, the IPMI (Intelligent
or
FCY FCY Peripheral Management Interface) must be disabled by
I2CxBRG =  ------------ – ------------------------------ – 1 clearing the IPMIEN bit (I2CxCON<11>).
FSCL 10 000 000
Note 1: Based on FCY = FOSC/2, Doze mode and Note: As a result of changes in the I2C™ proto-
PLL are disabled. col, the addresses in Table 16-2 are
2: These clock rate values are for guidance reserved and will not be Acknowledged in
only. The actual clock rate can be affected Slave mode. This includes any address
by various system level parameters. The mask settings that include any of these
actual clock rate should be measured in addresses.
its intended application.
TABLE 16-1: I2C™ CLOCK RATES(1,2)

I2CxBRG Value
Required System FSCL FCY Actual FSCL
(Decimal) (Hexadecimal)
100 kHz 16 MHz 157 9D 100 kHz
100 kHz 8 MHz 78 4E 100 kHz
100 kHz 4 MHz 39 27 99 kHz
400 kHz 16 MHz 37 25 404 kHz
400 kHz 8 MHz 18 12 404 kHz
400 kHz 4 MHz 9 9 385 kHz
400 kHz 2 MHz 4 4 385 kHz
1 MHz 16 MHz 13 D 1.026 MHz
1 MHz 8 MHz 6 6 1.026 MHz
1 MHz 4 MHz 3 3 0.909 MHz
2: These clock rate values are for guidance only. The actual clock rate can be affected by various system
level parameters. The actual clock rate should be measured in its intended application.
TABLE 16-2: I2C™ RESERVED ADDRESSES(1)

Slave Address R/W Bit Description
0000 000 0 General Call Address(2)
0000 000 1 Start Byte
0000 001 x Cbus Address
0000 010 x Reserved
0000 011 x Reserved
0000 1xx x HS Mode Master Code
1111 1xx x Reserved
1111 0xx x 10-Bit Slave Upper Byte(3)
Note 1: The address bits listed here will never cause an address match, independent of address mask settings.
2: The address will be Acknowledged only if GCEN = 1.
3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.

REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0

I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC

GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend: HC = Hardware Clearable bit

bit 15 I2CEN: I2Cx Enable bit

1 = Enables the I2Cx module, and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module. All I2C pins are controlled by port functions.
bit 13 I2CSIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters an Idle mode
0 = Continues module operation in Idle mode
bit 12 SCLREL: SCLx Release Control bit (when operating as I2C Slave)
1 = Releases SCLx clock
0 = Holds SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear
at beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware clear at beginning of slave
transmission.
bit 11 IPMIEN: Intelligent Platform Management Interface (IPMI) Enable bit
1 = IPMI Support mode is enabled; all addresses Acknowledged
0 = IPMI mode is disabled
bit 10 A10M: 10-Bit Slave Addressing bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9 DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
bit 8 SMEN: SMBus Input Levels bit
1 = Enables I/O pin thresholds compliant with the SMBus specification
0 = Disables the SMBus input thresholds
bit 7 GCEN: General Call Enable bit (when operating as I2C slave)
1 = Enables interrupt when a general call address is received in the I2CxRSR
(module is enabled for reception)
0 = General call address is disabled
bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with the SCLREL bit.
1 = Enables software or receive clock stretching
0 = Disables software or receive clock stretching

REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
bit 5 ACKDT: Acknowledge Data bit (When operating as I2C master. Applicable during master receive.)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Sends NACK during Acknowledge
0 = Sends ACK during Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit
(When operating as I2C master. Applicable during master receive.)
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit. Hardware
clear at end of master Acknowledge sequence.
0 = Acknowledge sequence is not in progress
bit 3 RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.
0 = Receive sequence is not in progress
bit 2 PEN: Stop Condition Enable bit (when operating as I2C master)
1 = Initiates Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
0 = Stop condition is not in progress
bit 1 RSEN: Repeated Start Condition Enabled bit (when operating as I2C master)
1 = Initiates Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master
Repeated Start sequence.
0 = Repeated Start condition is not in progress
bit 0 SEN: Start Condition Enabled bit (when operating as I2C master)
1 = Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.
0 = Start condition is not in progress

REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER
R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC
ACKSTAT TRSTAT — — — BCL GCSTAT ADD10
bit 15 bit 8
R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC
IWCOL I2COV D/A P S R/W RBF TBF
bit 7 bit 0
Legend: C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit
bit 15 ACKSTAT: Acknowledge Status bit

1 = NACK was detected last
0 = ACK was detected last
Hardware set or clear at end of Acknowledge.
bit 14 TRSTAT: Transmit Status bit
(When operating as I2C master. Applicable to master transmit operation.)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware set at the beginning of master transmission. Hardware clear at the end of slave Acknowledge.
bit 10 BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware set at detection of bus collision.
bit 9 GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware set when the address matches the general call address. Hardware clear at Stop detection.
bit 8 ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware set at the match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.
bit 7 IWCOL: Write Collision Detect bit
1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy
0 = No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
bit 6 I2COV: Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register was still holding the previous byte
0 = No overflow
Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
bit 5 D/A: Data/Address bit (when operating as I2C slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was the the device address
Hardware clear occurs at device address match. Hardware set after a transmission finishes or at reception
of a slave byte.

REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
bit 4 P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop is detected.
bit 3 S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop is detected.
bit 2 R/W: Read/Write Information bit (when operating as I2C slave)
1 = Read – indicates data transfer is output from the slave
0 = Write – indicates data transfer is input to the slave
Hardware set or clear after reception of I 2C device address byte.
bit 1 RBF: Receive Buffer Full Status bit
1 = Receive is complete, I2CxRCV is full
0 = Receive is not complete, I2CxRCV is empty
Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV.
bit 0 TBF: Transmit Buffer Full Status bit
1 = Transmit is in progress, I2CxTRN is full
0 = Transmit is complete, I2CxTRN is empty
Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.

REGISTER 16-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — AMSK9 AMSK8
bit 15 bit 8

AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0
bit 7 bit 0
Legend:

bit 9-0 AMSK<9:0>: Mask for Address Bit x Select bits
1 = Enable masking for bit x of incoming message address; bit match is not required in this position
0 = Disable masking for bit x; bit match is required in this position

17.0 UNIVERSAL ASYNCHRONOUS • Fully Integrated Baud Rate Generator with 16-Bit
Prescaler
RECEIVER TRANSMITTER
• Baud Rates Ranging from 1 Mbps to 15 bps at
(UART) 16 MIPS
Note: This data sheet summarizes the features • 4-Deep, First-In-First-Out (FIFO) Transmit Data
of this group of PIC24F devices. It is not Buffer
intended to be a comprehensive reference • 4-Deep FIFO Receive Data Buffer
source. For more information, refer to the • Parity, Framing and Buffer Overrun Error Detection
“PIC24F Family Reference Manual”, • Support for 9-Bit mode with Address Detect
Section 21. “UART” (DS39708). (9th bit = 1)
The Universal Asynchronous Receiver Transmitter • Transmit and Receive Interrupts
(UART) module is one of the serial I/O modules available • Loopback mode for Diagnostic Support
in the PIC24F device family. The UART is a full-duplex, • Support for Sync and Break Characters
asynchronous system that can communicate with
• Supports Automatic Baud Rate Detection
peripheral devices, such as personal computers,
LIN/J2602, RS-232 and RS-485 interfaces. The module • IrDA Encoder and Decoder Logic
also supports a hardware flow control option with the • 16x Baud Clock Output for IrDA Support
UxCTS and UxRTS pins, and also includes an IrDA® A simplified block diagram of the UART is shown in
encoder and decoder. Figure 17-1. The UART module consists of these key
The primary features of the UART module are: important hardware elements:
• Full-Duplex, 8 or 9-Bit Data Transmission through • Baud Rate Generator
the UxTX and UxRX pins • Asynchronous Transmitter
• Even, Odd or No Parity Options (for 8-bit data) • Asynchronous Receiver
• One or Two Stop bits
• Hardware Flow Control Option with UxCTS and
UxRTS pins
FIGURE 17-1: UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
Hardware Flow Control UxRTS/BCLKx

UxCTS
UARTx Receiver UxRX
UARTx Transmitter UxTX
Note: The UART inputs and outputs must all be assigned to available RPn pins before use. Please see
Section 10.4 “Peripheral Pin Select (PPS)” for more information.

17.1 UART Baud Rate Generator (BRG) The maximum baud rate (BRGH = 0) possible is
FCY/16 (for UxBRG = 0) and the minimum baud rate
The UART module includes a dedicated 16-bit Baud possible is FCY/(16 * 65536).
Rate Generator. The UxBRG register controls the
period of a free-running, 16-bit timer. Equation 17-1 Equation 17-2 shows the formula for computation of
shows the formula for computation of the baud rate the baud rate with BRGH = 1.
with BRGH = 0.
EQUATION 17-2: UART BAUD RATE WITH
EQUATION 17-1: UART BAUD RATE WITH BRGH = 1(1,2)
BRGH = 0(1,2) FCY
Baud Rate =
FCY 4 • (UxBRG + 1)
Baud Rate =
16 • (UxBRG + 1)
FCY
UxBRG = –1
4 • Baud Rate
UxBRG = FCY –1
16 • Baud Rate Note 1: FCY denotes the instruction cycle clock
frequency.
Note 1: FCY denotes the instruction cycle clock 2: Based on FCY = FOSC/2, Doze mode
frequency (FOSC/2). and PLL are disabled.
2: Based on FCY = FOSC/2, Doze mode
and PLL are disabled. The maximum baud rate (BRGH = 1) possible is FCY/4
(for UxBRG = 0) and the minimum baud rate possible
Example 17-1 shows the calculation of the baud rate is FCY/(4 * 65536).
error for the following conditions: Writing a new value to the UxBRG register causes the
• FCY = 4 MHz BRG timer to be reset (cleared). This ensures the BRG
does not wait for a timer overflow before generating the
• Desired Baud Rate = 9600
new baud rate.
EXAMPLE 17-1: BAUD RATE ERROR CALCULATION (BRGH = 0)(1)

Desired Baud Rate = FCY/(16 (UxBRG + 1))
Solving for UxBRG Value:
UxBRG = ((FCY/Desired Baud Rate)/16) – 1
UxBRG = ((4000000/9600)/16) – 1
UxBRG = 25
Calculated Baud Rate = 4000000/(16 (25 + 1))
= 9615
Error = (Calculated Baud Rate – Desired Baud Rate)
Desired Baud Rate
= (9615 – 9600)/9600
= 0.16%

17.2 Transmitting in 8-Bit Data Mode 17.5 Receiving in 8-Bit or 9-Bit Data
1. Set up the UART:
Mode
a) Write appropriate values for data, parity and 1. Set up the UART (as described in Section 17.2
Stop bits. “Transmitting in 8-Bit Data Mode”).
b) Write appropriate baud rate value to the 2. Enable the UART.
UxBRG register. 3. A receive interrupt will be generated when one
c) Set up transmit and receive interrupt enable or more data characters have been received as
and priority bits. per interrupt control bit, URXISELx.
2. Enable the UART. 4. Read the OERR bit to determine if an overrun
3. Set the UTXEN bit (causes a transmit interrupt error has occurred. The OERR bit must be reset
two cycles after being set). in software.
4. Write data byte to the lower byte of the 5. Read UxRXREG.
UxTXREG word. The value will be immediately The act of reading the UxRXREG character will move
transferred to the Transmit Shift Register (TSR) the next character to the top of the receive FIFO,
and the serial bit stream will start shifting out including a new set of PERR and FERR values.
with the next rising edge of the baud clock.
5. Alternately, the data byte may be transferred 17.6 Operation of UxCTS and UxRTS
while UTXEN = 0, and then the user may set Control Pins
UTXEN. This will cause the serial bit stream to
begin immediately because the baud clock will UARTx Clear to Send (UxCTS) and Request to Send
start from a cleared state. (UxRTS) are the two hardware-controlled pins that are
6. A transmit interrupt will be generated as per associated with the UART module. These two pins
interrupt control bit, UTXISELx. allow the UART to operate in Simplex and Flow Control
modes. They are implemented to control the transmis-
17.3 Transmitting in 9-Bit Data Mode sion and reception between the Data Terminal
Equipment (DTE). The UEN<1:0> bits in the UxMODE
1. Set up the UART (as described in Section 17.2 register configure these pins.
“Transmitting in 8-Bit Data Mode”).
2. Enable the UART. 17.7 Infrared Support
3. Set the UTXEN bit (causes a transmit interrupt).
The UART module provides two types of infrared UART
4. Write UxTXREG as a 16-bit value only. support: one is the IrDA clock output to support the
5. A word write to UxTXREG triggers the transfer external IrDA encoder and decoder device (legacy
of the 9-bit data to the TSR. The serial bit stream module support), and the other is the full implementa-
will start shifting out with the first rising edge of tion of the IrDA encoder and decoder. Note that
the baud clock. because the IrDA modes require a 16x baud clock, they
6. A transmit interrupt will be generated as per the will only work when the BRGH bit (UxMODE<3>) is ‘0’.
setting of control bit, UTXISELx.
17.7.1 IRDA CLOCK OUTPUT FOR
17.4 Break and Sync Transmit EXTERNAL IRDA SUPPORT
Sequence To support external IrDA encoder and decoder devices,
the BCLKx pin (same as the UxRTS pin) can be
The following sequence will send a message frame configured to generate the 16x baud clock. When
header made up of a Break, followed by an Auto-Baud UEN<1:0> = 11, the BCLKx pin will output the 16x
Sync byte. baud clock if the UART module is enabled. It can be
1. Configure the UART for the desired mode. used to support the IrDA codec chip.
2. Set UTXEN and UTXBRK to set up the Break
character. 17.7.2 BUILT-IN IRDA ENCODER AND
DECODER
3. Load the UxTXREG with a dummy character to
initiate transmission (value is ignored). The UART has full implementation of the IrDA encoder
4. Write ‘55h’ to UxTXREG; this loads the Sync and decoder as part of the UART module. The built-in
character into the transmit FIFO. IrDA encoder and decoder functionality is enabled
using the IREN bit (UxMODE<12>). When enabled
5. After the Break has been sent, the UTXBRK bit
(IREN = 1), the receive pin (UxRX) acts as the input
is reset by hardware. The Sync character now
from the infrared receiver. The transmit pin (UxTX) acts
transmits.
as the output to the infrared transmitter.

REGISTER 17-1: UxMODE: UARTx MODE REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

(1) (2)
UARTEN — USIDL IREN RTSMD — UEN1 UEN0
bit 15 bit 8
R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL
bit 7 bit 0
Legend: HC = Hardware Clearable bit

bit 15 UARTEN: UARTx Enable bit(1)

1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption is minimal
bit 13 USIDL: Stop in Idle Mode bit
1 = Discontinue module operation when the device enters Idle mode
bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2)
1 = IrDA encoder and decoder are enabled
0 = IrDA encoder and decoder are disabled
bit 11 RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
bit 9-8 UEN<1:0>: UARTx Enable bits
11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by port latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by
port latches
bit 7 WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit
1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared in
hardware on following rising edge
0 = No wake-up is enabled
bit 6 LPBACK: UARTx Loopback Mode Select bit
1 = Enable Loopback mode
0 = Loopback mode is disabled
bit 5 ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h);
cleared in hardware upon completion
0 = Baud rate measurement is disabled or completed
bit 4 RXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See
2: This feature is only available for the 16x BRG mode (BRGH = 0).

REGISTER 17-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 3 BRGH: High Baud Rate Enable bit
1 = High-Speed mode (four BRG clock cycles per bit)
0 = Standard mode (16 BRG clock cycles per bit)
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0 STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See
2: This feature is only available for the 16x BRG mode (BRGH = 0).

REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0 R-1

UTXISEL1 UTXINV(1) UTXISEL0 — UTXBRK UTXEN(2) UTXBF TRMT
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0

URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA
bit 7 bit 0
Legend: C = Clearable bit HC = Hardware Clearable bit

bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits

11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result,
the transmit buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
least one character open in the transmit buffer)
bit 14 UTXINV: IrDA® Encoder Transmit Polarity Inversion bit(1)
IREN = 0:
1 = UxTX Idle ‘0’
IREN = 1:
bit 11 UTXBRK: Transmit Break bit
1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0 = Sync Break transmission is disabled or completed
bit 10 UTXEN: Transmit Enable bit(2)
1 = Transmit is enabled, UxTX pin is controlled by UARTx
0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is
controlled by port
bit 9 UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full; at least one more character can be written
bit 8 TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bits
11 = Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer;
receive buffer has one or more characters
Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1).
2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See

REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled. If 9-bit mode is not selected, this does not take effect.
0 = Address Detect mode is disabled
bit 4 RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Receiver is active
bit 3 PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character (character at the top of the receive FIFO)
0 = Parity error has not been detected
bit 2 FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character (character at the top of the receive FIFO)
0 = Framing error has not been detected
bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed (clearing a previously set OERR bit (1  0 transition) will reset
the receiver buffer and the RSR to the empty state
bit 0 URXDA: Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1).
2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See

NOTES:

18.0 PARALLEL MASTER PORT Key features of the PMP module include:
(PMP) • Up to 16 Programmable Address Lines
• One Chip Select Line
• Programmable Strobe Options:
intended to be a comprehensive reference - Individual Read and Write Strobes or;
source. For more information, refer to the - Read/Write Strobe with Enable Strobe
“PIC24F Family Reference Manual”, • Address Auto-Increment/Auto-Decrement
Section 13. “Parallel Master Port • Programmable Address/Data Multiplexing
(PMP)” (DS39713). • Programmable Polarity on Control Signals
The Parallel Master Port (PMP) module is a parallel, • Legacy Parallel Slave Port Support
8-bit I/O module, specifically designed to communicate • Enhanced Parallel Slave Support:
with a wide variety of parallel devices, such as commu- - Address Support
nication peripherals, LCDs, external memory devices
- 4-Byte Deep Auto-Incrementing Buffer
and microcontrollers. Because the interface to parallel
peripherals varies significantly, the PMP is highly • Programmable Wait States
configurable. • Selectable Input Voltage Levels
Note: A number of the pins for the PMP are not

present on PIC24FJ64GA1 family devices.
Refer to the specific device’s pinout to
determine which pins are available.
FIGURE 18-1: PMP MODULE OVERVIEW

Address Bus
Data Bus
Control Lines
PIC24F
PMA<0>
Parallel Master Port PMALL
PMA<1>
PMALH
(1) Up to 11-Bit Address

PMA<10:2> EEPROM
PMCS1
PMBE
PMRD FIFO
PMRD/PMWR Microcontroller LCD
Buffer
PMWR
PMENB
PMD<7:0>
PMA<7:0>
PMA<15:8>
8-Bit Data
Note 1: PMA<10:2> bits are not available on 28-pin devices.

REGISTER 18-1: PMCON: PARALLEL PORT CONTROL REGISTER

PMPEN — PSIDL ADRMUX1(1) ADRMUX0(1) PTBEEN PTWREN PTRDEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0(2) U-0 R/W-0(2) R/W-0 R/W-0 R/W-0

CSF1 CSF0 ALP — CS1P BEP WRSP RDSP
bit 7 bit 0
Legend:
bit 15 PMPEN: Parallel Master Port Enable bit

1 = PMP is enabled
0 = PMP is disabled, no off-chip access performed
bit 13 PSIDL: Stop in Idle Mode bit
bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits(1)
11 = Reserved
10 = All 16 bits of address are multiplexed on PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins; upper 3 bits are multiplexed on
PMA<10:8>
00 = Address and data appear on separate pins
bit 10 PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode)
1 = PMBE port is enabled
0 = PMBE port is disabled
bit 9 PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port is enabled
0 = PMWR/PMENB port is disabled
bit 8 PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port is enabled
0 = PMRD/PMWR port is disabled
bit 7-6 CSF<1:0>: Chip Select Function bits
11 = Reserved
10 = PMCS1 functions as chip set
01 = Reserved
00 = Reserved
bit 5 ALP: Address Latch Polarity bit(2)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
bit 3 CS1P: Chip Select 1 Polarity bit(2)
1 = Active-high (PMCS1/PMCS1)
0 = Active-low (PMCS1/PMCS1)

2: These bits have no effect when their corresponding pins are used as address lines.

REGISTER 18-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
bit 2 BEP: Byte Enable Polarity bit
1 = Byte enable active-high (PMBE)
0 = Byte enable active-low (PMBE)
bit 1 WRSP: Write Strobe Polarity bit
For Slave modes and Master Mode 2 (PMMODE<9:8> = 00,01,10):
1 = Write strobe active-high (PMWR)
0 = Write strobe active-low (PMWR)
For Master Mode 1 (PMMODE<9:8> = 11):
1 = Enable strobe active-high (PMENB)
0 = Enable strobe active-low (PMENB)
bit 0 RDSP: Read Strobe Polarity bit
For Slave modes and Master Mode 2 (PMMODE<9:8> = 00,01,10):
1 = Read strobe active-high (PMRD)
0 = Read strobe active-low (PMRD)
For Master Mode 1 (PMMODE<9:8> = 11):
1 = Read/write strobe active-high (PMRD/PMWR)
0 = Read/write strobe active-low (PMRD/PMWR)

2: These bits have no effect when their corresponding pins are used as address lines.

REGISTER 18-2: PMMODE: PARALLEL PORT MODE REGISTER
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0
bit 15 bit 8

WAITB1(1) WAITB0(1) WAITM3 WAITM2 WAITM1 WAITM0 WAITE1(1) WAITE0(1)
bit 7 bit 0
Legend:
bit 15 BUSY: Busy bit (Master mode only)

1 = Port is busy (not useful when the processor stall is active)
0 = Port is not busy
bit 14-13 IRQM<1:0>: Interrupt Request Mode bits
11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode),
or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only)
10 = No interrupt is generated, processor stall activated
01 = Interrupt is generated at the end of the read/write cycle
00 = No interrupt is generated
bit 12-11 INCM<1:0>: Increment Mode bits
11 = PSP read and write buffers auto-increment (Legacy PSP mode only)
10 = Decrement ADDR<10:0> by 1 every read/write cycle
01 = Increment ADDR<10:0> by 1 every read/write cycle
00 = No increment or decrement of address
bit 10 MODE16: 8/16-Bit Mode bit
1 = 16-bit mode: Data register is 16 bits; a read or write to the Data register invokes two 8-bit transfers
0 = 8-bit mode: Data register is 8 bits; a read or write to the Data register invokes one 8-bit transfer
bit 9-8 MODE<1:0>: Parallel Port Mode Select bits
11 = Master Mode 1 (PMCS1, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)
10 = Master Mode 2 (PMCS1, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)
01 = Enhanced PSP control signals (PMRD, PMWR, PMCS1, PMD<7:0> and PMA<1:0>)
00 = Legacy Parallel Slave Port control signals (PMRD, PMWR, PMCS1 and PMD<7:0>)
bit 7-6 WAITB<1:0>: Data Setup to Read/Write Wait State Configuration bits(1)
11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY
bit 5-2 WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits
1111 = Wait of additional 15 TCY
...
0001 = Wait of additional 1 TCY
0000 = No additional wait cycles (operation forced into one TCY)
bit 1-0 WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits(1)
11 = Wait of 4 TCY
10 = Wait of 3 TCY
01 = Wait of 2 TCY
00 = Wait of 1 TCY
Note 1: WAITB and WAITE bits are ignored whenever WAITM<3:0> = 0000.

REGISTER 18-3: PMADDR: PARALLEL PORT ADDRESS REGISTER
U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— CS1 — — — ADDR10(1) ADDR9(1) ADDR8(1)
bit 15 bit 8

(1) ADDR6(1) ADDR5(1) ADDR4(1) ADDR3(1) ADDR2(1) ADDR1(1) ADDR0(1)
ADDR7
bit 7 bit 0
Legend:

bit 14 CS1: Chip Select 1 bit
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive
bit 10-0 ADDR<10:0>: Parallel Port Destination Address bits(1)
REGISTER 18-4: PMAEN: PARALLEL PORT ENABLE REGISTER
U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— PTEN14 — — — PTEN10(1) PTEN9(1) PTEN8(1)
bit 15 bit 8

PTEN7(1) PTEN6(1) PTEN5(1) PTEN4(1) PTEN3(1) PTEN2(1) PTEN1 PTEN0
bit 7 bit 0
Legend:

bit 14 PTEN14: PMCS1 Strobe Enable bit
1 = PMCS1 functions as chip select
0 = PMCS1 pin functions as port I/O
bit 10-2 PTEN<10:2>: PMP Address Port Enable bits(1)
1 = PMA<10:2> function as PMP address lines
0 = PMA<10:2> function as port I/O
bit 1-0 PTEN<1:0>: PMALH/PMALL Strobe Enable bits
1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL
0 = PMA1 and PMA0 pads function as port I/O

REGISTER 18-5: PMSTAT: PARALLEL PORT STATUS REGISTER
R-0 R/W-0, HS U-0 U-0 R-0 R-0 R-0 R-0

IBF IBOV — — IB3F IB2F IB1F IB0F
bit 15 bit 8
R-1 R/W-0, HS U-0 U-0 R-1 R-1 R-1 R-1

OBE OBUF — — OB3E OB2E OB1E OB0E
bit 7 bit 0

bit 15 IBF: Input Buffer Full Status bit

1 = All writable input buffer registers are full
0 = Some or all of the writable input buffer registers are empty
bit 14 IBOV: Input Buffer Overflow Status bit
1 = A write attempt to a full input byte register occurred (must be cleared in software)
0 = No overflow occurred
bit 11-8 IB3F:IB0F Input Buffer x Status Full bits
1 = Input buffer contains data that has not been read (reading buffer will clear this bit)
0 = Input buffer does not contain any unread data
bit 7 OBE: Output Buffer Empty Status bit
1 = All readable output buffer registers are empty
0 = Some or all of the readable output buffer registers are full
bit 6 OBUF: Output Buffer Underflow Status bits
1 = A read occurred from an empty output byte register (must be cleared in software)
0 = No underflow occurred
bit 3-0 OB3E:OB0E Output Buffer x Status Empty bits
1 = Output buffer is empty (writing data to the buffer will clear this bit)
0 = Output buffer contains data that has not been transmitted

REGISTER 18-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — RTSECSEL1(1) RTSECSEL0(1) PMPTTL
bit 7 bit 0
Legend:

bit 2-1 RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits(1)
10 = RTCC source clock is selected for the RTCC pin (clock can be LPRC or SOSC, depending on the
setting of the Flash Configuration bit, RTCOSC (CW4<5>))
01 = RTCC seconds clock is selected for the RTCC pin
00 = RTCC alarm pulse is selected for the RTCC pin
bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffers
Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit needs to be set.

FIGURE 18-2: LEGACY PARALLEL SLAVE PORT EXAMPLE
Address Bus
Master PIC24F Slave
Data Bus
PMD<7:0> PMD<7:0> Control Lines
PMCS1 PMCS1
PMRD PMRD
PMWR PMWR
FIGURE 18-3: ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE
Master PIC24F Slave

PMA<1:0>
PMA<1:0>
PMD<7:0> Write Read
PMD<7:0> Address Address
Decode Decode
PMDOUT1L (0) PMDIN1L (0)

PMCS1 PMCS1 PMDOUT1H (1) PMDIN1H (1)
PMRD PMRD PMDOUT2L (2) PMDIN2L (2)
PMWR PMWR PMDOUT2H (3) PMDIN2H (3)
Address Bus
Data Bus
Control Lines
TABLE 18-1: SLAVE MODE ADDRESS RESOLUTION

PMA<1:0> Output Register (Buffer) Input Register (Buffer)
00 PMDOUT1<7:0> (0) PMDIN1<7:0> (0)
01 PMDOUT1<15:8> (1) PMDIN1<15:8> (1)
10 PMDOUT2<7:0> (2) PMDIN2<7:0> (2)
11 PMDOUT2<15:8> (3) PMDIN2<15:8> (3)
FIGURE 18-4: MASTER MODE, DEMULTIPLEXED ADDRESSING (SEPARATE READ AND

WRITE STROBES, SINGLE CHIP SELECT)
PIC24F PMA<10:0>
PMD<7:0>
PMCS1
PMRD Address Bus

Data Bus
PMWR Control Lines

FIGURE 18-5: MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READ
AND WRITE STROBES, SINGLE CHIP SELECT)
PIC24F PMA<10:8>
PMD<7:0>
PMA<7:0>
PMCS1
PMALL
Address Bus
Multiplexed
PMRD Data and
Address Bus
PMWR Control Lines
FIGURE 18-6: MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND
WRITE STROBES, SINGLE CHIP SELECT)
PMD<7:0>
PIC24F PMA<7:0>
PMA<15:8>
PMCS1
PMALL
PMALH
Multiplexed
PMRD Data and
Address Bus
PMWR Control Lines
FIGURE 18-7: EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION

PIC24F
PMD<7:0> 373 A<7:0>
A<15:0>
PMALL
D<7:0>
D<7:0>
CE
A<15:8>
373 OE WR
PMALH
PMCS1 Address Bus

PMRD Data Bus
PMWR Control Lines
FIGURE 18-8: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION

PIC24F
PMD<7:0> 373 A<7:0>
A<10:0>
PMALL
D<7:0>
D<7:0>
A<10:8> CE
PMA<10:8>
OE WR Address Bus
PMCS1
Data Bus
PMRD
Control Lines
PMWR

FIGURE 18-9: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION
PIC24F Parallel Peripheral

PMD<7:0> AD<7:0>
PMALL ALE
PMCS1 CS Address Bus
PMRD RD Data Bus
PMWR WR Control Lines
FIGURE 18-10: PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 8-BIT DATA)
PIC24F Parallel EEPROM

PMA<n:0> A<n:0>
PMD<7:0> D<7:0>
PMCS1 CE
Address Bus
PMRD OE
Data Bus
PMWR WR
Control Lines
FIGURE 18-11: PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 16-BIT DATA)
PIC24F Parallel EEPROM

PMA<n:0> A<n:1>
PMD<7:0> D<7:0>
PMBE A0
PMCS1 CE
Address Bus
PMRD OE
Data Bus
PMWR WR
Control Lines
FIGURE 18-12: LCD CONTROL EXAMPLE (BYTE MODE OPERATION)
PIC24F LCD Controller

PMD<7:0> D<7:0>
PMA0 RS
PMRD/PMWR R/W Address Bus
PMCS1 E
Data Bus
Control Lines

19.0 REAL-TIME CLOCK AND • Alarm-configurable for half a second, one second,
10 seconds, one minute, 10 minutes, one hour,
CALENDAR (RTCC)
one day, one week, one month or one year
Note: This data sheet summarizes the features • Alarm repeat with decrementing counter
of this group of PIC24F devices. It is not • Alarm with indefinite repeat chime
intended to be a comprehensive reference • Year 2000 to 2099 leap year correction
• BCD format for smaller software overhead
“PIC24F Family Reference Manual”,
Section 29. “Real-Time Clock and • Optimized for long-term battery operation
Calendar (RTCC)” (DS39696). • User calibration of the 32.768 kHz clock
crystal/32K INTRC frequency with periodic
The RTCC provides the user with a Real-Time Clock auto-adjust
and Calendar (RTCC) function that can be calibrated.
Key features of the RTCC module are: 19.1 RTCC Source Clock
• Operates in Deep Sleep mode The user can select between the SOSC crystal
• Selectable clock source oscillator or the LPRC Low-Power Internal Oscillator as
• Provides hours, minutes and seconds using the clock reference for the RTCC module. This is con-
24-hour format figured using the RTCOSC (CW4<5>) Configuration
• Visibility of one half second period bit. This gives the user an option to trade off system
cost, accuracy and power consumption, based on the
• Provides calendar – weekday, date, month and
overall system needs.
year
The SOSC and RTCC will both remain running while
the device is held in Reset with MCLR and will continue
running after MCLR is released.
FIGURE 19-1: RTCC BLOCK DIAGRAM
RTCC Clock Domain CPU Clock Domain

Input from
SOSC/LPRC RCFGCAL
Oscillator
RTCC Prescalers ALCFGRPT
0.5 Sec YEAR
MTHDY
RTCC Timer RTCVAL
WKDYHR
1 Sec MINSEC
Alarm
Event
Comparator
ALMTHDY
Alarm Registers with Masks ALRMVAL ALWDHR
ALMINSEC
Repeat Counter RTSECSEL<1:0>
01
RTCC
RTCC Interrupt Logic Interrupt
Alarm Pulse
00
RTCC
Pin
10
Clock Source
RTCOE

19.2 RTCC Module Registers TABLE 19-2: ALRMVAL REGISTER
MAPPING
The RTCC module registers are organized into three
categories: ALRMPTR Alarm Value Register Window
• RTCC Control Registers <1:0> ALRMVAL<15:8> ALRMVAL<7:0>
• RTCC Value Registers
00 ALRMMIN ALRMSEC
• Alarm Value Registers
01 ALRMWD ALRMHR
19.2.1 REGISTER MAPPING 10 ALRMMNTH ALRMDAY
To limit the register interface, the RTCC Timer and 11 — —
Alarm Time registers are accessed through Considering that the 16-bit core does not distinguish
corresponding register pointers. The RTCC Value between 8-bit and 16-bit read operations, the user must
register window (RTCVALH and RTCVALL) uses the be aware that when reading either the ALRMVALH or
RTCPTR bits (RCFGCAL<9:8>) to select the desired ALRMVALL bytes, the ALRMPTR<1:0> value will be
Timer register pair (see Table 19-1). decremented. The same applies to the RTCVALH or
By writing to the RTCVALH byte, the RTCC Pointer RTCVALL bytes with the RTCPTR<1:0> being
value (the RTCPTR<1:0> bits) decrements by one until decremented.
they reach ‘00’. Once they reach ‘00’, the MINUTES
Note: This only applies to read operations and
and SECONDS value will be accessible through
not write operations.
RTCVALH and RTCVALL until the pointer value is
manually changed.
19.2.2 WRITE LOCK
TABLE 19-1: RTCVAL REGISTER MAPPING To perform a write to any of the RTCC Timer registers,
RTCC Value Register Window the RTCWREN bit (RCFGCAL<13>) must be set (refer
RTCPTR<1:0> to Example 19-1).
RTCVAL<15:8> RTCVAL<7:0>
Note: To avoid accidental writes to the timer, it is
00 MINUTES SECONDS recommended that the RTCWREN bit
01 WEEKDAY HOURS (RCFGCAL<13>) is kept clear at any
other time. For the RTCWREN bit to be
10 MONTH DAY
set, there is only one instruction cycle time
11 — YEAR window allowed between the 55h/AA
The Alarm Value register window (ALRMVALH and sequence and the setting of RTCWREN;
ALRMVALL) uses the ALRMPTR bits therefore, it is recommended that code
(ALCFGRPT<9:8>) to select the desired Alarm register follow the procedure in Example 19-1.
pair (see Table 19-2).
By writing to the ALRMVALH byte, the Alarm Pointer 19.2.3 SELECTING RTCC CLOCK SOURCE
value (ALRMPTR<1:0> bits) decrements by one until The clock source for the RTCC module can be selected
they reach ‘00’. Once they reach ‘00’, the ALRMMIN using the Flash Configuration bit, RTCOSC (CW4<5>).
and ALRMSEC value will be accessible through When the bit is set to ‘1’, the Secondary Oscillator
ALRMVALH and ALRMVALL until the pointer value is (SOSC) is used as the reference clock, and when the
manually changed. bit is ‘0’, LPRC is used as the reference clock.
EXAMPLE 19-1: SETTING THE RTCWREN BIT

asm volatile(“push w7”);
asm volatile(“push w8”);
asm volatile(“disi #5”);
asm volatile(“mov #0x55, w7”);
asm volatile(“mov w7, _NVMKEY”);
asm volatile(“mov #0xAA, w8”);
asm volatile(“mov w8, _NVMKEY”);
asm volatile(“bset _RCFGCAL, #13”); //set the RTCWREN bit
asm volatile(“pop w8”);
asm volatile(“pop w7”);

19.2.4 RTCC CONTROL REGISTERS
REGISTER 19-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1)
R/W-0 U-0 R/W-0 R-0, HSC R-0, HSC R/W-0 R/W-0 R/W-0
(2)
RTCEN — RTCWREN RTCSYNC HALFSEC(3) RTCOE RTCPTR1 RTCPTR0
bit 15 bit 8

CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0
bit 7 bit 0
Legend: HSC = Hardware Settable/Clearable bit

bit 15 RTCEN: RTCC Enable bit(2)

1 = RTCC module is enabled
0 = RTCC module is disabled
bit 13 RTCWREN: RTCC Value Registers Write Enable bit
1 = RTCVALH and RTCVALL registers can be written to by the user
0 = RTCVALH and RTCVALL registers are locked out from being written to by the user
bit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple
resulting in an invalid data read. If the register is read twice and results in the same data, the data
can be assumed to be valid.
0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple
bit 11 HALFSEC: Half Second Status bit(3)
1 = Second half period of a second
0 = First half period of a second
bit 10 RTCOE: RTCC Output Enable bit
1 = RTCC output is enabled
0 = RTCC output is disabled
bit 9-8 RTCPTR<1:0>: RTCC Value Register Window Pointer bits
Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers.
The RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.
RTCVAL<15:8>:
00 = MINUTES
01 = WEEKDAY
10 = MONTH
11 = Reserved
RTCVAL<7:0>:
00 = SECONDS
01 = HOURS
10 = DAY
11 = YEAR
Note 1: The RCFGCAL register is only affected by a POR.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.

REGISTER 19-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED)
bit 7-0 CAL<7:0>: RTC Drift Calibration bits
01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute
.
.
.
01111111 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute
00000000 = No adjustment
11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute
.
.
.
10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute
Note 1: The RCFGCAL register is only affected by a POR.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.
REGISTER 19-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — RTSECSEL1(1) RTSECSEL0(1) PMPTTL
bit 7 bit 0
Legend:

bit 2-1 RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits(1)
10 = RTCC source clock is selected for the RTCC pin (clock can be LPRC or SOSC, depending on the
setting of the RTCOSC bit (CW4<5>))
01 = RTCC seconds clock is selected for the RTCC pin
00 = RTCC alarm pulse is selected for the RTCC pin
bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffers
Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit needs to be set.

REGISTER 19-3: ALCFGRPT: ALARM CONFIGURATION REGISTER
ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0
bit 15 bit 8

ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0
bit 7 bit 0
Legend:
bit 15 ALRMEN: Alarm Enable bit

1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00h and
CHIME = 0)
0 = Alarm is disabled
bit 14 CHIME: Chime Enable bit
1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh
0 = Chime is disabled; ARPT<7:0> bits stop once they reach 00h
bit 13-10 AMASK<3:0>: Alarm Mask Configuration bits
0000 = Every half second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29th, once every 4 years)
101x = Reserved; do not use
11xx = Reserved; do not use
bit 9-8 ALRMPTR<1:0>: Alarm Value Register Window Pointer bits
Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL registers.
The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’.
ALRMVAL<15:8>:
00 = ALRMMIN
01 = ALRMWD
10 = ALRMMNTH
11 = Unimplemented
ALRMVAL<7:0>:
00 = ALRMSEC
01 = ALRMHR
10 = ALRMDAY
11 = Unimplemented
bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits
11111111 = Alarm will repeat 255 more times
.
.
.
00000000 = Alarm will not repeat
The counter decrements on any alarm event; it is prevented from rolling over from 00h to FFh unless
CHIME = 1.

19.2.5 RTCVAL REGISTER MAPPINGS
REGISTER 19-4: YEAR: YEAR VALUE REGISTER(1)

U-0, HSC U-0, HSC U-0, HSC U-0, HSC U-0, HSC U-0, HSC U-0, HSC U-0, HSC
— — — — — — — —
bit 15 bit 8
R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC
YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0
bit 7 bit 0


bit 7-4 YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits
Contains a value from 0 to 9.
bit 3-0 YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits
Note 1: A write to the YEAR register is only allowed when RTCWREN = 1.
REGISTER 19-5: MTHDY: MONTH AND DAY VALUE REGISTER(1)

U-0, HSC U-0, HSC U-0, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC
— — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0
bit 15 bit 8
U-0, HSC U-0, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC
— — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0
bit 7 bit 0


bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of 0 or 1.
bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits
bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits
bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits
Note 1: A write to this register is only allowed when RTCWREN = 1.

REGISTER 19-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1)
U-0, HSC U-0, HSC U-0, HSC U-0, HSC U-0, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC
— — — — — WDAY2 WDAY1 WDAY0
bit 15 bit 8
U-0, HSC U-0, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC
— — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0
bit 7 bit 0


bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits
bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits
bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits
REGISTER 19-7: MINSEC: MINUTES AND SECONDS VALUE REGISTER
U-0, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC
— MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0
bit 15 bit 8
U-0, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC
— SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0
bit 7 bit 0


bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits
bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits
bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits
bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits

19.2.6 ALRMVAL REGISTER MAPPINGS
REGISTER 19-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER(1)

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0
bit 15 bit 8
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0
bit 7 bit 0
Legend:

bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of 0 or 1.
bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits
bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits
bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits
REGISTER 19-9: ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1)

U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x
— — — — — WDAY2 WDAY1 WDAY0
bit 15 bit 8
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0
bit 7 bit 0
Legend:

bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits
bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits
bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits

REGISTER 19-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER
U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0
bit 15 bit 8
U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0
bit 7 bit 0
Legend:

bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits
bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits
bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits
bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits

19.3 Calibration 19.4.1 CONFIGURING THE ALARM
The real-time crystal input can be calibrated using the The alarm feature is enabled using the ALRMEN bit.
periodic auto-adjust feature. When properly calibrated, This bit is cleared when an alarm is issued. Writes to
the RTCC can provide an error of less than 3 seconds ALRMVAL should only take place when ALRMEN = 0.
per month. This is accomplished by finding the number As displayed in Figure 19-2, the interval selection of the
of error clock pulses and storing the value into the alarm is configured through the AMASK bits
lower half of the RCFGCAL register. The 8-bit signed (ALCFGRPT<13:10>). These bits determine which and
value loaded into the lower half of RCFGCAL is how many digits of the alarm must match the clock
multiplied by four and will either be added or subtracted value for the alarm to occur.
from the RTCC timer, once every minute. Refer to the
The alarm can also be configured to repeat based on a
steps below for RTCC calibration:
preconfigured interval. The amount of times this
1. Using another timer resource on the device; the occurs, once the alarm is enabled, is stored in the
user must find the error of the 32.768 kHz crystal. ARPT<7:0> bits (ALCFGRPT<7:0>). When the value
2. Once the error is known, it must be converted to of the ARPT bits equals 00h and the CHIME bit
the number of error clock pulses per minute. (ALCFGRPT<14>) is cleared, the repeat function is
3. a) If the oscillator is faster than ideal (negative disabled and only a single alarm will occur. The alarm
result from step 2), the RCFGCAL register value can be repeated up to 255 times by loading
must be negative. This causes the specified ARPT<7:0> with FFh.
number of clock pulses to be subtracted from After each alarm is issued, the value of the ARPT bits
the timer counter, once every minute. is decremented by one. Once the value has reached
b) If the oscillator is slower than ideal (positive 00h, the alarm will be issued one last time, after which,
result from step 2), the RCFGCAL register value the ALRMEN bit will be cleared automatically and the
must be positive. This causes the specified alarm will turn off.
number of clock pulses to be subtracted from Indefinite repetition of the alarm can occur if the
the timer counter, once every minute. CHIME bit = 1. Instead of the alarm being disabled
Divide the number of error clocks per minute by 4 to get when the value of the ARPT bits reaches 00h, it rolls
the correct calibration value and load the RCFGCAL over to FFh and continues counting indefinitely while
register with the correct value. (Each 1-bit increment in CHIME is set.
the calibration adds or subtracts 4 pulses.)
19.4.2 ALARM INTERRUPT
EQUATION 19-1: At every alarm event, an interrupt is generated. In
(Ideal Frequency† – Measured Frequency) * 60 = addition, an alarm pulse output is provided that
Clocks per Minute operates at half the frequency of the alarm. This output
is completely synchronous to the RTCC clock and can
† Ideal Frequency = 32,768 Hz be used as a trigger clock to other peripherals.
Note: Changing any of the registers, other than
Writes to the lower half of the RCFGCAL register the RCFGCAL and ALCFGRPT registers,
should only occur when the timer is turned off or and the CHIME bit while the alarm is
immediately after the rising edge of the seconds pulse. enabled (ALRMEN = 1), can result in a
false alarm event leading to a false alarm
Note: It is up to the user to include, in the error
interrupt. To avoid a false alarm event, the
value, the initial error of the crystal drift
timer and alarm values should only be
due to temperature and drift due to crystal
changed while the alarm is disabled
aging.
(ALRMEN = 0). It is recommended that the
ALCFGRPT register and CHIME bit be
19.4 Alarm changed when RTCSYNC = 0.
• Configurable from half second to one year
• Enabled using the ALRMEN bit (ALCFGRPT<15>)
• One-time alarm and repeat alarm options are
available

FIGURE 19-2: ALARM MASK SETTINGS
Day of
Alarm Mask Setting the
(AMASK<3:0>) Week Month Day Hours Minutes Seconds
0000 - Every half second
0001 - Every second
0010 - Every 10 seconds s
0011 - Every minute s s
0100 - Every 10 minutes m s s
0101 - Every hour m m s s
0110 - Every day h h m m s s
0111 - Every week d h h m m s s
1000 - Every month d d h h m m s s
1001 - Every year(1) m m d d h h m m s s
Note 1: Annually, except when configured for February 29.

NOTES:

20.0 32-BIT PROGRAMMABLE The programmable CRC generator provides a
hardware-implemented method of quickly generating
CYCLIC REDUNDANCY CHECK
checksums for various networking and security
(CRC) GENERATOR applications. It offers the following features:
Note: This data sheet summarizes the features • User-programmable CRC polynomial equation,
of this group of PIC24F devices. It is not up to 32 bits
intended to be a comprehensive reference • Programmable shift direction (little or big-endian)
source. For more information, refer to the • Independent data and polynomial lengths
“PIC24F Family Reference Manual”, • Configurable interrupt output
Section 41. “32-Bit Programmable
• Data FIFO
Cyclic Redundancy Check (CRC)”
(DS39729). A simplified block diagram of the CRC generator is
shown in Figure 20-1. A simple version of the CRC shift
engine is shown in Figure 20-2.
FIGURE 20-1: CRC BLOCK DIAGRAM
CRCDATH CRCDATL
Variable FIFO FIFO Empty Event

(4x32, 8x16 or 16x8)
CRCISEL
2 * FCY Shift Clock

1
Shift Buffer Set CRCIF
0
0 1 LENDIAN
Shift Complete Event

CRC Shift Engine
CRCWDATH CRCWDATL
FIGURE 20-2: CRC SHIFT ENGINE DETAIL
CRCWDATH CRCWDATL
Read/Write Bus
X(1)(1) X(2)(1) X(n)(1)
Shift Buffer
Data Bit 0 Bit 1 Bit 2 Bit n(2)
Note 1: Each XOR stage of the shift engine is programmable. See text for details.
2: Polynomial length n is determined by ([PLEN<3:0>] + 1)

20.1 User Interface The data for which the CRC is to be calculated must
first be written into the FIFO. Even if the data width is
20.1.1 POLYNOMIAL INTERFACE less than 8, the smallest data element that can be writ-
ten into the FIFO is one byte. For example, if the
The CRC module can be programmed for CRC
DWIDTH value is five, then the size of the data is
polynomials of up to the 32nd order, using up to 32 bits.
DWIDTH + 1, or six. The data is written as a whole byte;
Polynomial length, which reflects the highest exponent
the two unused upper bits are ignored by the module.
in the equation, is selected by the PLEN<4:0> bits
(CRCCON2<4:0>). Once data is written into the MSb of the CRCDAT reg-
isters (that is, MSb as defined by the data width), the
The CRCXORL and CRCXORH registers control which
value of the VWORD<4:0> bits (CRCCON1<12:8>)
exponent terms are included in the equation. Setting a
increments by one. For example, if the DWIDTH value
particular bit includes that exponent term in the
is 24, the VWORD bits will increment when bit 7 of
equation; functionally, this includes an XOR operation
CRCDATH is written. Therefore, CRCDATL must
on the corresponding bit in the CRC engine. Clearing
always be written before CRCDATH.
the bit disables the XOR.
The CRC engine starts shifting data when the CRCGO
For example, consider two CRC polynomials, one a
bit is set and the value of VWORD is greater than zero.
16-bit equation and the other, a 32-bit equation:
Each word is copied out of the FIFO into a buffer
x16 + x12 + x5 + 1 register, which decrements VWORD. The data is then
and shifted out of the buffer. The CRC engine continues
shifting at a rate of two bits per instruction cycle, until
x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 the VWORD value reaches zero. This means that for a
+ x5 + x4 + x2 + x + 1 given data width, it takes half that number of instruc-
To program these polynomials into the CRC generator, tions for each word to complete the calculation. For
set the register bits as shown in Table 20-1. example, it takes 16 cycles to calculate the CRC for a
single word of 32-bit data.
Note that the appropriate positions are set to ‘1’ to indi-
cate that they are used in the equation (for example, X26 When the VWORD value reaches the maximum value
and X23). The 0 bit required by the equation is always for the configured value of DWIDTH (4, 8 or 16), the
XORed; thus, X0 is a don’t care. For a polynomial of CRCFUL bit becomes set. When the VWORD value
length N, it is assumed that the Nth bit will always be reaches zero, the CRCMPT bit becomes set. The FIFO
used, regardless of the bit setting. Therefore, for a poly- is emptied and the VWORD<4:0> bits are set to
nomial length of 32, there is no 32nd bit in the CRCxOR ‘00000’ whenever CRCEN is ‘0’.
register. At least one instruction cycle must pass, after a write to
CRCDAT, before a read of the VWORD bits is done.
20.1.2 DATA INTERFACE
The module incorporates a FIFO that works with a vari-
able data width. Input data width can be configured to
any value between one and 32 bits using the
DWIDTH<4:0> bits (CRCCON2<12:8>). When the
data width is greater than 15, the FIFO is four words
deep. When the DWIDTH value is between 15 and 8,
the FIFO is 8 words deep. When the DWIDTH value is
less than 8, the FIFO is 16 words deep.
TABLE 20-1: CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIAL

CRC Control Bit Values
Bits 16-Bit Polynomial 32-Bit Polynomial
PLEN<4:0> 01111 11111
X<31:16> 0000 0000 0000 000x 0000 0100 1100 0001
X<15:0> 0001 0000 0010 000x 0001 1101 1011 011x

20.1.3 DATA SHIFT DIRECTION 20.2 Registers
The LENDIAN bit (CRCCON1<3>) is used to control There are eight registers associated with the module:
the shift direction. By default, the CRC will shift data
through the engine, MSb first. Setting LENDIAN (= 1) • CRCCON1
causes the CRC to shift data, LSb first. This setting • CRCCON2
allows better integration with various communication • CRCXORL
schemes and removes the overhead of reversing the • CRCXORH
bit order in software. Note that this only changes the • CRCDATL
direction of the data that is shifted into the engine. The
• CRCDATH
result of the CRC calculation will still be a normal CRC
result, not a reverse CRC result. • CRCWDATL
• CRCWDATH
20.1.4 INTERRUPT OPERATION The CRCCON1 and CRCCON2 registers
The module generates an interrupt that is configurable (Register 20-1 and Register 20-2) control the operation
by the user for either of two conditions. of the module, and configure the various settings. The
If CRCISEL is ‘0’, an interrupt is generated when the CRCXOR registers (Register 20-3 and Register 20-4)
VWORD<4:0> bits make a transition from a value of ‘1’ select the polynomial terms to be used in the CRC
to ‘0’. If CRCISEL is ‘1’, an interrupt will be generated equation. The CRCDAT and CRCWDAT registers are
after the CRC operation finishes and the module sets each register pairs that serve as buffers for the
the CRCGO bit to ‘0’. Manually setting CRCGO to ‘0’ double-word, input data and CRC processed output,
will not generate an interrupt. respectively.
20.1.5 TYPICAL OPERATION

To use the module for a typical CRC calculation:
1. Set the CRCEN bit to enable the module.
2. Configure the module for the desired operation:
d) Program the desired polynomial using the
CRCXORL and CRCXORH registers, and
the PLEN<4:0> bits
e) Configure the data width and shift direction
using the DWIDTH and LENDIAN bits
f) Select the desired interrupt mode using the
CRCISEL bit
3. Preload the FIFO by writing to the CRCDATL
and CRCDATH registers until the CRCFUL bit is
set or no data is left
4. Clear old results by writing 00h to CRCWDATL
and CRCWDATH. CRCWDAT can also be left
unchanged to resume a previously halted
calculation.
5. Set the CRCGO bit to start calculation.
6. Write remaining data into the FIFO as space
becomes available.
7. When the calculation completes, CRCGO is
automatically cleared. An interrupt will be
generated if CRCISEL = 1.
8. Read CRCWDATL and CRCWDATH for the
result of the calculation.

REGISTER 20-1: CRCCON1: CRC CONTROL REGISTER 1
R/W-0 U-0 R/W-0 R-0 R-0 R-0 R-0 R-0

CRCEN — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0
bit 15 bit 8
R-0, HCS R-1, HCS R/W-0 R/W-0, HC R/W-0 U-0 U-0 U-0
CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — —
bit 7 bit 0
Legend: HC = Hardware Clearable bit HCS = Hardware Clearable/Settable bit

bit 15 CRCEN: CRC Enable bit

1 = Module is enabled
0 = Module is enabled. All state machines, pointers and CRCWDAT/CRCDAT are reset; other SFRs are
NOT reset.
bit 13 CSIDL: CRC Stop in Idle Mode bit
bit 12-8 VWORD<4:0>: Pointer Value bits
Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN<3:0> > 7, or
16 when PLEN<3:0> 7.
bit 7 CRCFUL: FIFO Full bit
1 = FIFO is full
0 = FIFO is not full
bit 6 CRCMPT: FIFO Empty Bit
1 = FIFO is empty
0 = FIFO is not empty
bit 5 CRCISEL: CRC interrupt Selection bit
1 = Interrupt on FIFO is empty; CRC calculation is not complete
0 = Interrupt on shift is complete and CRCWDAT result is ready
bit 4 CRCGO: Start CRC bit
1 = Start CRC serial shifter
0 = CRC serial shifter is turned off
bit 3 LENDIAN: Data Shift Direction Select bit
1 = Data word is shifted into the CRC starting with the LSb (little endian)
0 = Data word is shifted into the CRC starting with the MSb (big endian)

REGISTER 20-2: CRCCON2: CRC CONTROL REGISTER 2
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0
bit 7 bit 0
Legend:

bit 12-8 DWIDTH<4:0>: Data Width Select bits
Defines the width of the data word (Data Word Width = (DWIDTH<4:0>) + 1).
bit 4-0 PLEN<4:0>: Polynomial Length Select bits
Defines the length of the CRC polynomial (Polynomial Length = (PLEN<4:0>) + 1).
REGISTER 20-3: CRCXORL: CRC XOR POLYNOMIAL REGISTER, LOW BYTE

X15 X14 X13 X12 X11 X10 X9 X8
bit 15 bit 8

X7 X6 X5 X4 X3 X2 X1 —
bit 7 bit 0
Legend:
bit 15-1 X<15:1>: XOR of Polynomial Term Xn Enable bits


REGISTER 20-4: CRCXORH: CRC XOR POLYNOMIAL REGISTER, HIGH BYTE

X31 X30 X29 X28 X27 X26 X25 X24
bit 15 bit 8

X23 X22 X21 X20 X19 X18 X17 X16
bit 7 bit 0
Legend:
bit 15-0 X<31:16>: XOR of Polynomial Term Xn Enable bits

21.0 10-BIT HIGH-SPEED A/D A block diagram of the A/D Converter is shown in
Figure 21-1.
CONVERTER
To perform an A/D conversion:
1. Configure the A/D module:
intended to be a comprehensive reference a) Configure port pins as analog inputs and/or
source. For more information, refer to the select band gap reference inputs
“PIC24F Family Reference Manual”, (AD1PCFGL<15:0> and AD1PCFGH<1:0>).
Section 17. “10-Bit A/D Converter” b) Select voltage reference source to match
(DS39705). expected range on analog inputs
(AD1CON2<15:13>).
The 10-bit A/D Converter has the following key c) Select the analog conversion clock to match
features: the desired data rate with the processor
• Successive Approximation (SAR) conversion clock (AD1CON3<7:0>).
• Conversion speeds of up to 500 ksps d) Select the appropriate sample/conversion
• 13 analog input pins sequence (AD1CON1<7:5> and
• External voltage reference input pins AD1CON3<12:8>).
• Internal band gap reference inputs e) Select how conversion results are
presented in the buffer (AD1CON1<9:8>).
• Automatic Channel Scan mode
f) Select interrupt rate (AD1CON2<5:2>).
• Selectable conversion trigger source
g) Turn on A/D module (AD1CON1<15>).
• 16-word conversion result buffer
2. Configure the A/D interrupt (if required):
• Selectable Buffer Fill modes
a) Clear the AD1IF bit.
• Four result alignment options
b) Select A/D interrupt priority.
• Operation during CPU Sleep and Idle modes
On all PIC24FJ64GA104 family devices, the 10-bit A/D
Converter has 13 analog input pins, designated AN0
through AN12. In addition, there are two analog input
pins for external voltage reference connections (VREF+
and VREF-). These voltage reference inputs may be
shared with other analog input pins.

FIGURE 21-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM
Internal Data Bus

AVDD
VR+
VR Select
AVSS 16
VREF+ VR-
VREF-
Comparator
VINH
VR- VR+
AN0 S/H DAC
VINL
AN1
AN2
10-Bit SAR Conversion Logic
VINH
AN3
AN4
MUX A
Data Formatting
AN5
AN6
VINL ADC1BUF0:
AN7
ADC1BUFF
AN8
AD1CON1
AN9
AD1CON2
AN10 AD1CON3
AD1CHS0
AN11
VINH AD1PCFGL
MUX B
AN12 AD1PCFGH
VDDCORE AD1CSSL
VINL AD1CSSH
VBG/2
VBG
Sample Control
Control Logic
Conversion Control
Input MUX Control
Pin Config Control

REGISTER 21-1: AD1CON1: A/D CONTROL REGISTER 1
R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0

ADON(1) — ADSIDL — — — FORM1 FORM0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0, HCS R/C-0, HCS
SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE
bit 7 bit 0
Legend: C = Clearable bit HCS = Hardware Clearable/Settable bit

bit 15 ADON: A/D Operating Mode bit(1)

1 = A/D Converter module is operating
0 = A/D Converter is off
bit 13 ADSIDL: Stop in Idle Mode bit
bit 9-8 FORM<1:0>: Data Output Format bits
11 = Signed fractional (sddd dddd dd00 0000)
10 = Fractional (dddd dddd dd00 0000)
01 = Signed integer (ssss sssd dddd dddd)
00 = Integer (0000 00dd dddd dddd)
bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = CTMU event ends sampling and starts conversion
101 = Reserved
100 = Timer5 compare ends sampling and starts conversion
011 = Reserved
010 = Timer3 compare ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing the SAMP bit ends sampling and starts conversion
bit 2 ASAM: A/D Sample Auto-Start bit
1 = Sampling begins immediately after the last conversion completes; SAMP bit is auto-set
0 = Sampling begins when the SAMP bit is set
bit 1 SAMP: A/D Sample Enable bit
1 = A/D sample/hold amplifier is sampling input
0 = A/D sample/hold amplifier is holding
bit 0 DONE: A/D Conversion Status bit
1 = A/D conversion is done
0 = A/D conversion is NOT done
Note 1: Values of ADC1BUFx registers will not retain their values once the ADON bit is cleared. Read out the
conversion values from the buffer before disabling the module.

R/W-0 R/W-0 R/W-0 r-0 U-0 R/W-0 U-0 U-0

VCFG2 VCFG1 VCFG0 r — CSCNA — —
bit 15 bit 8
R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS
bit 7 bit 0
Legend: r = Reserved bit

bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits
VCFG<2:0> VR+ VR-

000 AVDD AVSS
001 External VREF+ pin AVSS
010 AVDD External VREF- pin
011 External VREF+ pin External VREF- pin
1xx AVDD AVSS
bit 12 Reserved: Maintain as ‘0’

bit 10 CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit
1 = Scan inputs
0 = Do not scan inputs
bit 7 BUFS: Buffer Fill Status bit (valid only when BUFM = 1)
1 = A/D is currently filling buffer 08-0F; user should access data in 00-07
0 = A/D is currently filling buffer 00-07; user should access data in 08-0F
bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits
1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence
1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence
.....
0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000 = Interrupts at the completion of conversion for each sample/convert sequence
bit 1 BUFM: Buffer Mode Select bit
1 = Buffer is configured as two 8-word buffers (ADC1BUFn<15:8> and ADC1BUFn<7:0>)
0 = Buffer is configured as one 16-word buffer (ADC1BUFn<15:0>)
bit 0 ALTS: Alternate Input Sample Mode Select bit
1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and
MUX A input multiplexer settings for all subsequent samples
0 = Always uses MUX A input multiplexer settings

R/W-0 r-0 r-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADRC r r SAMC4 SAMC3 SAMC2 SAMC1 SAMC0
bit 15 bit 8

ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0
bit 7 bit 0

bit 15 ADRC: A/D Conversion Clock Source bit

1 = A/D internal RC clock
0 = Clock derived from system clock
bit 14-13 Reserved: Maintain as ‘0’
bit 12-8 SAMC<4:0>: Auto-Sample Time bits
11111 = 31 TAD
·····
00001 = 1 TAD
00000 = 0 TAD (not recommended)
bit 7-0 ADCS<7:0>: A/D Conversion Clock Select bits
11111111 to 01000000 = Reserved
······
00111111 = 64 • TCY
······
00000001 = 2 • TCY
00000000 = TCY

REGISTER 21-4: AD1CHS: A/D INPUT SELECT REGISTER
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CH0NB — — CH0SB4(1,2) CH0SB3(1,2) CH0SB2(1,2) CH0SB1(1,2) CH0SB0(1,2)
bit 15 bit 8
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CH0NA — — CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0
bit 7 bit 0
Legend:
bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VR-
bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits(1,2)
11111 = Channel 0 positive input is reserved for CTMU use only(3)
1xxxx = Unimplemented; do not use.
01111 = Channel 0 positive input is internal band gap reference (VBG)
01110 = Channel 0 positive input is VBG/2
01101 = Channel 0 positive input is voltage regulator output (VDDCORE)
01100 = Channel 0 positive input is AN12
bit 7 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VR-
bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits
Implemented combinations are identical to those for CH0SB<4:0> (above).
Note 1: Combinations not shown here are unimplemented; do not use.

2: Analog channels, AN6, AN7, AN8 and AN12, are unavailable on 28-pin devices; do not use.
3: Selecting this internal channel allows the CTMU module to utilize the A/D Converter sample and hold
capacitor (CAD) for the smallest time measurements.

REGISTER 21-5: AD1PCFG: A/D PORT CONFIGURATION REGISTER
R/W-0 R/W-0 R/W-0 R/W-0(1) R/W-0 R/W-0 R/W-0 R/W-0(1)
PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8
bit 15 bit 8
R/W-0(1) R/W-0(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
Legend:
bit 15 PCFG15: A/D Input Band Gap Reference Enable bit

1 = Internal band gap (VBG) reference channel is disabled
0 = Internal band gap reference channel is enabled
bit 14 PCFG14: A/D Input Half Band Gap Reference Enable bit
1 = Internal half band gap (VBG/2) reference channel is disabled
0 = Internal half band gap reference channel is enabled
bit 13 PCFG13: A/D Input Voltage Regulator Output Reference Enable bit
1 = Internal voltage regulator output (VDDCORE) reference channel is disabled
0 = Internal voltage regulator output reference channel is enabled
bit 12-0 PCFG<12:0>: Analog Input Pin Configuration Control bits(1)
1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read is enabled
0 = Pin is configured in Analog mode; I/O port read is disabled, A/D samples pin voltage
Note 1: Analog channels, AN6, AN7, AN8 and AN12, are unavailable on 28-pin devices; leave these corresponding
bits set.

REGISTER 21-6: AD1CSSL: A/D INPUT SCAN SELECT REGISTER
R/W-0 R/W-0 R/W-0 R/W-0(1) R/W-0 R/W-0 R/W-0 R/W-0

CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8(1)
bit 15 bit 8

CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0
bit 7 bit 0
Legend:
bit 15 CSSL15: A/D Input Band Gap Scan Enable bit

1 = Internal band gap (VBG) channel is enabled for input scan
0 = Analog channel is disabled from input scan
bit 14 CSSL14: A/D Input Half Band Gap Scan Enable bit
1 = Internal half band gap (VBG/2) channel is enabled for input scan
bit 13 CSSL13: A/D Input Voltage Regulator Output Scan Enable bit
1 = Internal voltage regulator output (VDDCORE) is enabled for input scan
bit 12-0 CSSL<12:0>: A/D Input Pin Scan Selection bits(1)
1 = Corresponding analog channel is selected for input scan
0 = Analog channel is omitted from input scan
Note 1: Analog channels, AN6, AN7, AN8 and AN12, are unavailable on 28-pin devices; leave these corresponding
bits cleared.

EQUATION 21-1: A/D CONVERSION CLOCK PERIOD(1)
TAD
ADCS = –1
TCY
TAD = TCY • (ADCS + 1)
Note 1: Based on TCY = 2 * TOSC, Doze mode and PLL are disabled.
FIGURE 21-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL
VDD
RIC  250 Sampling RSS  5 k(Typical)
Switch
VT = 0.6V
Rs ANx RSS
CHOLD
VA CPIN ILEAKAGE = ADC capacitance
6-11 pF VT = 0.6V 500 nA = 4.4 pF (Typical)
(Typical)
VSS
Legend: CPIN = Input Capacitance

VT = Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to
various junctions
RIC = Interconnect Resistance
RSS = Sampling Switch Resistance
CHOLD = Sample/Hold Capacitance (from DAC)
Note: CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if Rs  5 k.

FIGURE 21-3: A/D TRANSFER FUNCTION
Output Code
(Binary (Decimal))
11 1111 1111 (1023)

11 1111 1110 (1022)
10 0000 0011 (515)

10 0000 0010 (514)
10 0000 0001 (513)
10 0000 0000 (512)
01 1111 1111 (511)
01 1111 1110 (510)
01 1111 1101 (509)
00 0000 0001 (1)

00 0000 0000 (0)
1023*(VR+ – VR-)
512*(VR+ – VR-)
(VINH – VINL)
VR+ – VR-
VR+
VR-
0
1024
1024
1024
Voltage Level
VR- +
VR- +
VR- +

22.0 TRIPLE COMPARATOR The comparator outputs may be directly connected to
the CxOUT pins. When the respective COE equals ‘1’,
MODULE the I/O pad logic makes the unsynchronized output of
Note: This data sheet summarizes the features the comparator available on the pin.
of this group of PIC24F devices. It is not A simplified block diagram of the module in shown in
intended to be a comprehensive reference Figure 22-1. Diagrams of the possible individual
source. For more information, refer to the comparator configurations are shown in Figure 22-2.
associated “PIC24F Family Reference
Each comparator has its own control register,
Manual”, Section 46. “Scalable
CMxCON (Register 22-1), for enabling and configuring
Comparator Module” (DS39734)
its operation. The output and event status of all three
The triple comparator module provides three dual input comparators are provided in the CMSTAT register
comparators. The inputs to the comparator can be con- (Register 22-2).
figured to use any one of four external analog inputs, as
well as voltage reference inputs from the voltage
reference generator and band gap reference.
FIGURE 22-1: TRIPLE COMPARATOR MODULE BLOCK DIAGRAM
EVPOL<1:0>
CCH<1:0>
CREF
Trigger/Interrupt CEVT
CPOL Logic COE
VIN-
VIN+ C1
CXINB
Input C1OUT
COUT Pin
CXINC Select
Logic
CXIND
EVPOL<1:0>
CVREF-
CPOL Logic COE
VIN-
VIN+ C2
C2OUT
COUT Pin
EVPOL<1:0>
CXINA
CVREF+
CPOL Logic COE
VIN-
VIN+ C3
C3OUT
COUT Pin

FIGURE 22-2: INDIVIDUAL COMPARATOR CONFIGURATIONS
Comparator Off
CEN = 0, CREF = x, CCH<1:0> = xx
COE
VIN-
VIN+ Cx
Off (Read as ‘0’) CxOUT
Pin
Comparator CxINB > CxINA Compare Comparator CxINC > CxINA Compare
CEN = 1, CREF = 0, CCH<1:0> = 00 CEN = 1, CREF = 0, CCH<1:0> = 01
COE COE
VIN- VIN-
CXINB CXINC
VIN+ Cx VIN+ Cx
CXINA CxOUT CXINA CxOUT
Pin Pin
Comparator CxIND > CxINA Compare Comparator CVREF- > CxINA Compare
COE COE
VIN- VIN-
CXIND CVREF-
VIN+ Cx VIN+ Cx
CXINA CxOUT CXINA CxOUT
Pin Pin
Comparator CxINB > CVREF+ Compare Comparator CxINC > CVREF+ Compare
COE COE
VIN- VIN-
CXINB CXINC
VIN+ Cx VIN+ Cx
CVREF+ CxOUT CVREF+ CxOUT
Pin Pin
Comparator CxIND > CVREF+ Compare Comparator CVREF- > CVREF+ Compare
COE COE
VIN- VIN-
CXIND CVREF-
VIN+ Cx VIN+ Cx
CVREF+ CxOUT CVREF+ CxOUT
Pin Pin

REGISTER 22-1: CMxCON: COMPARATOR x CONTROL REGISTERS
(COMPARATORS 1 THROUGH 3)
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R-0
CEN COE CPOL — — — CEVT COUT
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0

EVPOL1 EVPOL0 — CREF — — CCH1 CCH0
bit 7 bit 0
Legend:
bit 15 CEN: Comparator Enable bit

1 = Comparator is enabled
0 = Comparator is disabled
bit 14 COE: Comparator Output Enable bit
1 = Comparator output is present on the CxOUT pin.
0 = Comparator output is internal only
bit 13 CPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 9 CEVT: Comparator Event bit
1 = Comparator event defined by EVPOL<1:0> has occurred; subsequent triggers and interrupts are
disabled until the bit is cleared
0 = Comparator event has not occurred
bit 8 COUT: Comparator Output bit
When CPOL = 0:
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1:
1 = VIN+ < VIN-
0 = VIN+ > VIN-
bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits
11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt generated on transition of the comparator output:
If CPOL = 0 (non-inverted polarity):
High-to-low transition only.
If CPOL = 1 (inverted polarity):
Low-to-high transition only.
01 = Trigger/event/interrupt generated on transition of comparator output:
If CPOL = 0 (non-inverted polarity):
Low-to-high transition only.
If CPOL = 1 (inverted polarity):
High-to-low transition only.
00 = Trigger/event/interrupt generation is disabled

REGISTER 22-1: CMxCON: COMPARATOR x CONTROL REGISTERS
(COMPARATORS 1 THROUGH 3) (CONTINUED)
bit 4 CREF: Comparator Reference Select bits (non-inverting input)
1 = Non-inverting input connects to internal CVREF+ input reference voltage
0 = Non-inverting input connects to CxINA pin
bit 1-0 CCH<1:0>: Comparator Channel Select bits
11 = Inverting input of comparator connects to CVREF- input reference voltage
10 = Inverting input of comparator connects to CxIND pin
01 = Inverting input of comparator connects to CxINC pin
00 = Inverting input of comparator connects to CxINB pin
REGISTER 22-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER

R/W-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
CMIDL — — — — C3EVT C2EVT C1EVT
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0

— — — — — C3OUT C2OUT C1OUT
bit 7 bit 0
Legend:
bit 15 CMIDL: Comparator Stop in Idle Mode bit

1 = Discontinue operation of all comparators when device enters Idle mode
0 = Continue operation of all enabled comparators in Idle mode
bit 10 C3EVT: Comparator 3 Event Status bit (read-only)
Shows the current event status of Comparator 3 (CM3CON<9>).
bit 2 C3OUT: Comparator 3 Output Status bit (read-only)
Shows the current output of Comparator 3 (CM3CON<8>).

23.0 COMPARATOR VOLTAGE voltage, each with 16 distinct levels. The range to be
used is selected by the CVRR bit (CVRCON<5>). The
REFERENCE primary difference between the ranges is the size of the
Note: This data sheet summarizes the features steps selected by the CVREF Selection bits
of this group of PIC24F devices. It is not (CVR<3:0>), with one range offering finer resolution.
intended to be a comprehensive reference The comparator reference supply voltage can come
source. For more information, refer to the from either VDD and VSS, or the external VREF+ and
“PIC24F Family Reference Manual”, VREF-. The voltage source is selected by the CVRSS
Section 20. “Comparator Voltage bit (CVRCON<4>).
Reference Module” (DS39709).
The settling time of the comparator voltage reference
must be considered when changing the CVREF
23.1 Configuring the Comparator output.
Voltage Reference
The voltage reference module is controlled through the
CVRCON register (Register 23-1). The comparator
voltage reference provides two ranges of output
FIGURE 23-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
VREF+
AVDD
CVRSS = 0 8R
CVR<3:0>
CVREFP
CVREN R
R VREF+ 1
R CVREF+
0
R
16-to-1 MUX
16 Steps
CVREF
R
R
CVROE
R
CVREFM<1:0>
CVRR 8R
CVRSS = 1 VREF+ 11
VREF-
VBG/6 10
CVREF-
CVRSS = 0 VBG 01
AVSS VBG/2 00

REGISTER 23-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — CVREFP CVREFM1 CVREFM0
bit 15 bit 8

CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0
bit 7 bit 0
Legend:

bit 10 CVREFP: CVREF+ Reference Output Select bit
1 = Use VREF+ input pin as CVREF+ reference output to comparators
0 = Use comparator voltage reference module’s generated output as CVREF+ reference output to
comparators
bit 9-8 CVREFM<1:0>: CVREF- Reference Output Select bits
11 = Use VREF+ input pin as CVREF- reference output to comparators
10 = Use VBG/6 as CVREF- reference output to comparators
01 = Use VBG as CVREF- reference output to comparators
00 = Use VBG/2 as CVREF- reference output to comparators
bit 7 CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit is powered on
0 = CVREF circuit is powered down
bit 6 CVROE: Comparator VREF Output Enable bit
1 = CVREF voltage level is output on CVREF pin
0 = CVREF voltage level is disconnected from CVREF pin
bit 5 CVRR: Comparator VREF Range Selection bit
1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size
0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size
bit 4 CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source, CVRSRC = VREF+ – VREF-
0 = Comparator reference source, CVRSRC = AVDD – AVSS
bit 3-0 CVR<3:0>: Comparator VREF Value Selection (0  CVR<3:0>  15) bits
When CVRR = 1:
CVREF = (CVR<3:0>/24)  (CVRSRC)
When CVRR = 0:
CVREF = 1/4  (CVRSRC) + (CVR<3:0>/32)  (CVRSRC)

24.0 CHARGE TIME 24.1 Measuring Capacitance
MEASUREMENT UNIT (CTMU) The CTMU module measures capacitance by generat-
ing an output pulse, with a width equal to the time
between edge events, on two separate input channels.
The pulse edge events to both input channels can be
selected from four sources: two internal peripheral
modules (OC1 and Timer1) and two external pins
associated “PIC24F Family Reference
(CTEDG1 and CTEDG2). This pulse is used with the
Manual”, Section 11. “Charge Time
module’s precision current source to calculate
Measurement Unit (CTMU)” (DS39724).
capacitance according to the relationship:
The Charge Time Measurement Unit is a flexible dV
analog module that provides accurate differential time i=C•
dT
measurement between pulse sources, as well as
asynchronous pulse generation. Its key features For capacitance measurements, the A/D Converter
include: samples an external capacitor (CAPP) on one of its
input channels after the CTMU output’s pulse. A Preci-
• Four edge input trigger sources
sion Resistor (RPR) provides current source calibration
• Polarity control for each edge source on a second A/D channel. After the pulse ends, the
• Control of edge sequence converter determines the voltage on the capacitor. The
• Control of response to edges actual calculation of capacitance is performed in
• Time measurement resolution of 1 nanosecond software by the application.
• Accurate current source suitable for capacitive Figure 24-1 shows the external connections used for
measurement capacitance measurements, and how the CTMU and
Together with other on-chip analog modules, the CTMU A/D modules are related in this application. This
can be used to precisely measure time, measure example also shows the edge events coming from
capacitance, measure relative changes in capacitance Timer1, but other configurations using external edge
or generate output pulses that are independent of the sources are possible. A detailed discussion on
system clock. The CTMU module is ideal for interfacing measuring capacitance and time with the CTMU
with capacitive-based sensors. module is provided in the “PIC24F Family Reference
The CTMU is controlled through two registers: Manual”.
CTMUCON and CTMUICON. CTMUCON enables the
module and controls edge source selection, edge
source polarity selection and edge sequencing. The
CTMUICON register controls the selection and trim of
the current source.
FIGURE 24-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR

CAPACITANCE MEASUREMENT
PIC24F Device
Timer1
CTMU
EDG1 Current Source
EDG2
Output Pulse
A/D Converter
ANx
ANY
CAPP RPR

24.2 Measuring Time When the module is configured for pulse generation
delay by setting the TGEN bit (CTMUCON<12>), the
Time measurements on the pulse width can be similarly
internal current source is connected to the B input of
performed using the A/D module’s internal capacitor
Comparator 2. A capacitor (CDELAY) is connected to
(CAD) and a precision resistor for current calibration.
the Comparator 2 pin, C2INB, and the comparator volt-
Figure 24-2 shows the external connections used for
age reference, CVREF, is connected to C2INA. CVREF
time measurements, and how the CTMU and A/D
is then configured for a specific trip point. The module
modules are related in this application. This example
begins to charge CDELAY when an edge event is
also shows both edge events coming from the external
detected. When CDELAY charges above the CVREF trip
CTEDG pins, but other configurations using internal
point, a pulse is output on CTPLS. The length of the
edge sources are possible. For the smallest time
pulse delay is determined by the value of CDELAY and
measurements, select the internal A/D Channel 31,
the CVREF trip point.
CH0Sx <4:0>= 11111. This minimizes any stray capac-
itance that may otherwise be associated with using an Figure 24-3 shows the external connections for pulse
input pin, thus keeping the total capacitance to that of the generation, as well as the relationship of the different
A/D Converter itself (4-5 pF). A detailed discussion on analog modules required. While CTEDG1 is shown as
measuring capacitance and time with the CTMU module the input pulse source, other options are available. A
is provided in the “PIC24F Family Reference Manual”. detailed discussion on pulse generation with the CTMU
module is provided in the “PIC24F Family Reference
24.3 Pulse Generation and Delay Manual”.
The CTMU module can also generate an output pulse
with edges that are not synchronous with the device’s sys-
tem clock. More specifically, it can generate a pulse with
a programmable delay from an edge event input to the
module.
FIGURE 24-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME

MEASUREMENT
PIC24F Device
CTMU
CTEDG1 EDG1
Current Source
CTEDG2 EDG2
Output Pulse
A/D Converter
ANx
CAD
RPR
FIGURE 24-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE

DELAY GENERATION
PIC24F Device
CTMU
CTEDG1 EDG1 CTPLS
Current Source
Comparator
C2INB
C2
CDELAY
CVREF

REGISTER 24-1: CTMUCON: CTMU CONTROL REGISTER
(1)
CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG
bit 15 bit 8

EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT
bit 7 bit 0
Legend:
bit 15 CTMUEN: CTMU Enable bit

1 = Module is enabled
0 = Module is disabled
bit 13 CTMUSIDL: Stop in Idle Mode bit
bit 12 TGEN: Time Generation Enable bit(1)
1 = Enables edge delay generation
0 = Disables edge delay generation
bit 11 EDGEN: Edge Enable bit
1 = Edges are not blocked
0 = Edges are blocked
bit 10 EDGSEQEN: Edge Sequence Enable bit
1 = Edge 1 event must occur before Edge 2 event can occur
0 = No edge sequence is needed
bit 9 IDISSEN: Analog Current Source Control bit
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
bit 8 CTTRIG: Trigger Control bit
1 = Trigger output is enabled
0 = Trigger output is disabled
bit 7 EDG2POL: Edge 2 Polarity Select bit
1 = Edge 2 is programmed for a positive edge response
0 = Edge 2 is programmed for a negative edge response
bit 6-5 EDG2SEL<1:0>: Edge 2 Source Select bits
11 = CTED1 pin
10 = CTED2 pin
01 = OC1 module
00 = Timer1 module
bit 4 EDG1POL: Edge 1 Polarity Select bit
1 = Edge 1 is programmed for a positive edge response
0 = Edge 1 is programmed for a negative edge response
Note 1: If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. For more
information, see Section 10.4 “Peripheral Pin Select (PPS)”.

REGISTER 24-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED)
bit 3-2 EDG1SEL<1:0>: Edge 1 Source Select bits
11 = CTED1 pin
10 = CTED2 pin
01 = OC1 module
00 = Timer1 module
bit 1 EDG2STAT: Edge 2 Status bit
1 = Edge 2 event has occurred
0 = Edge 2 event has not occurred
bit 0 EDG1STAT: Edge 1 Status bit
1 = Edge 1 event has occurred
0 = Edge 1 event has not occurred
Note 1: If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. For more
information, see Section 10.4 “Peripheral Pin Select (PPS)”.
REGISTER 24-2: CTMUICON: CTMU CURRENT CONTROL REGISTER

ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15-10 ITRIM<5:0>: Current Source Trim bits

011111 = Maximum positive change from nominal current
011110
.....
000001 = Minimum positive change from nominal current
000000 = Nominal current output specified by IRNG<1:0>
111111 = Minimum negative change from nominal current
.....
100010
100001 = Maximum negative change from nominal current
bit 9-8 IRNG<1:0>: Current Source Range Select bits
11 = 100  Base Current
10 = 10  Base Current
01 = Base current level (0.55 A nominal)
00 = Current source is disabled

25.0 SPECIAL FEATURES 25.1.1 CONSIDERATIONS FOR
CONFIGURING PIC24FJ64GA104
Note: This data sheet summarizes the features FAMILY DEVICES
intended to be a comprehensive reference In PIC24FJ64GA104 family devices, the configuration
source. For more information, refer to the bytes are implemented as volatile memory. This means
following sections of the “PIC24F Family that configuration data must be programmed each time
Reference Manual”: the device is powered up. Configuration data is stored in
the three words at the top of the on-chip program mem-
• Section 9. “Watchdog Timer (WDT)” ory space, known as the Flash Configuration Words.
(DS39697) Their specific locations are shown in Table 25-1. These
• Section 32. “High-Level Device are packed representations of the actual device Config-
Integration” (DS39719) uration bits, whose actual locations are distributed
• Section 33. “Programming and among several locations in configuration space. The
Diagnostics” (DS39716) configuration data is automatically loaded from the Flash
Configuration Words to the proper Configuration
PIC24FJ64GA104 family devices include several registers during device Resets.
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of Note: Configuration data is reloaded on all types
external components. These are: of device Resets.
• Flexible Configuration When creating applications for these devices, users
• Watchdog Timer (WDT) should always specifically allocate the location of the
• Code Protection Flash Configuration Word for configuration data. This is
• JTAG Boundary Scan Interface to make certain that program code is not stored in this
• In-Circuit Serial Programming address when the code is compiled.
• In-Circuit Emulation The upper byte of all Flash Configuration Words in pro-
gram memory should always be ‘1111 1111’. This
25.1 Configuration Bits makes them appear to be NOP instructions in the
remote event that their locations are ever executed by
The Configuration bits can be programmed (read as ‘0’), accident. Since Configuration bits are not implemented
or left unprogrammed (read as ‘1’), to select various in the corresponding locations, writing ‘1’s to these
device configurations. These bits are mapped starting at locations has no effect on device operation.
program memory location F80000h. A detailed explana-
tion of the various bit functions is provided in Note: Performing a page erase operation on the
Register 25-1 through Register 25-6. last page of program memory clears the
Flash Configuration Words, enabling code
Note that address F80000h is beyond the user program protection as a result. Therefore, users
memory space. In fact, it belongs to the configuration should avoid performing page erase
memory space (800000h-FFFFFFh) which can only be operations on the last page of program
accessed using table reads and table writes. memory.
TABLE 25-1: FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJ64GA104 FAMILY

DEVICES
Configuration Word Addresses
Device
1 2 3 4
PIC24FJ32GA10x 57FEh 57FCh 57FAh 57F8h
PIC24FJ64GA10x ABFEh ABFCh ABFAh ABF8h

REGISTER 25-1: CW1: FLASH CONFIGURATION WORD 1
U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1
— — — — — — — —
bit 23 bit 16
r-x R/PO-1 R/PO-1 R/PO-1 R/PO-1 U-1 R/PO-1 R/PO-1

r JTAGEN(1) GCP GWRP DEBUG — ICS1 ICS0
bit 15 bit 8
R/PO-1 R/PO-1 U-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1

FWDTEN WINDIS — FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0
bit 7 bit 0

R = Readable bit PO = Program Once bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 15 Reserved: The value is unknown; program as ‘0’
bit 14 JTAGEN: JTAG Port Enable bit(1)
1 = JTAG port is enabled
0 = JTAG port is disabled
bit 13 GCP: General Segment Program Memory Code Protection bit
1 = Code protection is disabled
0 = Code protection is enabled for the entire program memory space
bit 12 GWRP: General Segment Code Flash Write Protection bit
1 = Writes to program memory are allowed
0 = Writes to program memory are disabled
bit 11 DEBUG: Background Debugger Enable bit
1 = Device resets into Operational mode
0 = Device resets into Debug mode
bit 9-8 ICS<1:0>: Emulator Pin Placement Select bits
11 = Emulator functions are shared with PGEC1/PGED1
bit 7 FWDTEN: Watchdog Timer Enable bit
1 = Watchdog Timer is enabled
0 = Watchdog Timer is disabled
bit 6 WINDIS: Windowed Watchdog Timer Disable bit
1 = Standard Watchdog Timer is enabled
0 = Windowed Watchdog Timer is enabled; FWDTEN must be ‘1’
bit 4 FWPSA: WDT Prescaler Ratio Select bit
1 = Prescaler ratio of 1:128
0 = Prescaler ratio of 1:32
Note 1: The JTAGEN bit can only be modified using In-Circuit Serial Programming™ (ICSP™). It cannot be
modified while connected through the JTAG interface.

REGISTER 25-1: CW1: FLASH CONFIGURATION WORD 1 (CONTINUED)
bit 3-0 WDTPS<3:0>: Watchdog Timer Postscaler Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
Note 1: The JTAGEN bit can only be modified using In-Circuit Serial Programming™ (ICSP™). It cannot be
modified while connected through the JTAG interface.

U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1
— — — — — — — —
bit 23 bit 16
R/PO-1 U-1 U-1 U-1 U-1 R/PO-1 R/PO-1 R/PO-1

IESO — — — — FNOSC2 FNOSC1 FNOSC0
bit 15 bit 8
R/PO-1 R/PO-1 R/PO-1 R/PO-1 U-1 R/PO-1 R/PO-1 R/PO-1

FCKSM1 FCKSM0 OSCIOFCN IOL1WAY — I2C1SEL POSCMD1 POSCMD0
bit 7 bit 0
Legend:

bit 15 IESO: Internal External Switchover bit
1 = IESO mode (Two-Speed Start-up) is enabled
0 = IESO mode (Two-Speed Start-up) is disabled
bit 10-8 FNOSC<2:0>: Initial Oscillator Select bits
110 = Reserved
bit 7-6 FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Configuration bits
1x = Clock switching and Fail-Safe Clock Monitor are disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 5 OSCIOFCN: OSCO Pin Configuration bit
If POSCMD<1:0> = 11 or 00:
1 = OSCO/CLKO/RA3 functions as CLKO (FOSC/2)
0 = OSCO/CLKO/RA3 functions as port I/O (RC15)
If POSCMD<1:0> = 10 or 01:
OSCIOFCN has no effect on OSCO/CLKO/RA3.
bit 4 IOL1WAY: IOLOCK One-Way Set Enable bit
1 = The IOLOCK bit (OSCCON<6>) can be set once, provided the unlock sequence has been
completed. Once set, the Peripheral Pin Select registers cannot be written to a second time.
0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been
completed
bit 2 I2C1SEL: I2C1 Pin Select bit
1 = Use default SCL1/SDA1 pins
0 = Use alternate SCL1/SDA1 pins
bit 1-0 POSCMD<1:0>: Primary Oscillator Configuration bits
11 = Primary Oscillator is disabled
10 = HS Oscillator mode is selected
01 = XT Oscillator mode is selected
00 = EC Oscillator mode is selected

U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1
— — — — — — — —
bit 23 bit 16
R/PO-1 R/PO-1 R/PO-1 U-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1

WPEND WPCFG WPDIS — WUTSEL1 WUTSEL0 SOSCSEL1(1) SOSCSEL0(1)
bit 15 bit 8
U-1 U-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1

— — WPFP5 WPFP4 WPFP3 WPFP2 WPFP1 WPFP0
bit 7 bit 0
Legend:

bit 15 WPEND: Segment Write Protection End Page Select bit
1 = Protected code segment lower boundary is at the bottom of program memory (000000h); upper
boundary is the code page specified by WPFP<8:0>
0 = Protected code segment upper boundary is at the last page of program memory; lower boundary
is the code page specified by WPFP<8:0>
bit 14 WPCFG: Configuration Word Code Page Protection Select bit
1 = Last page (at the top of program memory) and Flash Configuration Words are not protected
0 = Last page and Flash Configuration Words are code-protected
bit 13 WPDIS: Segment Write Protection Disable bit
1 = Segmented code protection is disabled
0 = Segmented code protection is enabled; protected segment defined by WPEND, WPCFG and
WPFPx Configuration bits
bit 11-10 WUTSEL<1:0>: Voltage Regulator Standby Mode Wake-up Time Select bits
11 = Default regulator start-up time used
01 = Fast regulator start-up time used
x0 = Reserved; do not use
bit 9-8 SOSCSEL<1:0>: Secondary Oscillator Power Mode Select bits(1)
11 = SOSC pins are in default (high drive strength) oscillator mode
01 = SOSC pins are in Low-Power (low drive strength) Oscillator mode
00 = SOSC pins have digital I/O functions (RA4, RB4); SCLKI can be used
10 = Reserved
bit 5-0 WPFP5:WPFP0: Protected Code Segment Boundary Page bits
Designates the 512 instruction page that is the boundary of the protected code segment, starting with
Page 9 at the bottom of program memory.
If WPEND = 1:
Last address of designated code page is the upper boundary of the segment.
If WPEND = 0:
First address of designated code page is the lower boundary of the segment.
Note 1: Digital functions on the SOSCI and SOSCO pins are only available when configured in Digital I/O mode
(‘00’).

U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1
— — — — — — — —
bit 23 bit 16
U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1

— — — — — — — —
bit 15 bit 8
R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1

DSWDTEN DSBOREN RTCOSC DSWDTOSC DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0
bit 7 bit 0
Legend:

bit 7 DSWDTEN: Deep Sleep Watchdog Timer Enable bit
1 = DSWDT is enabled
0 = DSWDT is disabled
bit 6 DSBOREN: Deep Sleep BOR Enable bit
1 = BOR is enabled in Deep Sleep
0 = BOR is disabled in Deep Sleep (does not affect Sleep mode)
bit 5 RTCOSC: RTCC Reference Clock Select bit
1 = RTCC uses SOSC as reference clock
0 = RTCC uses LPRC as reference clock
bit 4 DSWDTOSC: DSWDT Reference Clock Select bit
1 = DSWDT uses LPRC as reference clock
0 = DSWDT uses SOSC as reference clock
bit 3-0 DSWDTPS<3:0>: DSWDT Postscale select bits
The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms.
1111 = 1:2,147,483,648 (25.7 days)
1110 = 1:536,870,912 (6.4 days)
1101 = 1:134,217,728 (38.5 hours)
1100 = 1:33,554,432 (9.6 hours)
1011 = 1:8,388,608 (2.4 hours)
1010 = 1:2,097,152 (36 minutes)
1001 = 1:524,288 (9 minutes)
1000 = 1:131,072 (135 seconds)
0111 = 1:32,768 (34 seconds)
0110 = 1:8,192 (8.5 seconds)
0101 = 1:2,048 (2.1 seconds)
0100 = 1:512 (528 ms)
0011 = 1:128 (132 ms)
0010 = 1:32 (33 ms)
0001 = 1:8 (8.3 ms)
0000 = 1:2 (2.1 ms)

REGISTER 25-5: DEVID: DEVICE ID REGISTER
U U U U U U U U
— — — — — — — —
bit 23 bit 16
R R R R R R R R
FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2 FAMID1 FAMID0
bit 15 bit 8
R R R R R R R R
DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0
bit 7 bit 0
Legend: R = Read-Only bit U = Unimplemented bit

bit 15-8 FAMID<7:0>: Device Family Identifier bits
01000010 = PIC24FJ64GA104 family
bit 7-0 DEV<7:0>: Individual Device Identifier bits
00000010 = PIC24FJ32GA102
00000110 = PIC24FJ64GA102
00001010 = PIC24FJ32GA104
00001110 = PIC24FJ64GA104
REGISTER 25-6: DEVREV: DEVICE REVISION REGISTER

U U U U U U U U
— — — — — — — —
bit 23 bit 16
U U U U U U U U
— — — — — — — —
bit 15 bit 8
U U U U R R R R
— — — — REV3 REV2 REV1 REV0
bit 7 bit 0
Legend: R = Read-only bit U = Unimplemented bit

bit 3-0 REV<3:0>: Minor Revision Identifier bits
Encodes revision number of the device (sequential number only; no major/minor fields).

25.2 On-Chip Voltage Regulator FIGURE 25-1: CONNECTIONS FOR THE
ON-CHIP REGULATOR
All PIC24FJ64GA104 family devices power their core
digital logic at a nominal 2.5V. This may create an issue Regulator Enabled (DISVREG tied to VSS):
for designs that are required to operate at a higher 3.3V
typical voltage, such as 3.3V. To simplify system PIC24FJ64GA104
design, all devices in the PIC24FJ64GA104 family
VDD
incorporate an on-chip regulator that allows the device
DISVREG
to run its core logic from VDD.
The regulator is controlled by the DISVREG pin. Tying VSS VDDCORE/VCAP
to the pin enables the regulator, which in turn, provides CEFC
(10 F typ) VSS
power to the core from the other VDD pins. When the reg-
ulator is enabled, a low-ESR capacitor (such as ceramic)
must be connected to the VDDCORE/VCAP pin
(Figure 25-1). This helps to maintain the stability of the Regulator Disabled (DISVREG tied to VDD):
regulator. The recommended value for the Filter Capacitor 2.5V(1) 3.3V(1)
(CEFC) is provided in Section 28.1 “DC Characteristics”.
PIC24FJ64GA104
If DISVREG is tied to VDD, the regulator is disabled. In VDD
this case, separate power for the core logic, at a nomi-
DISVREG
nal 2.5V, must be supplied to the device on the
VDDCORE/VCAP pin to run the I/O pins at higher voltage VDDCORE/VCAP
levels, typically 3.3V. Alternatively, the VDDCORE/VCAP
and VDD pins can be tied together to operate at a lower VSS
nominal voltage. Refer to Figure 25-1 for possible
configurations.
Regulator Disabled (VDD tied to VDDCORE):
25.2.1 VOLTAGE REGULATOR TRACKING
2.5V(1)
MODE AND LOW-VOLTAGE
DETECTION PIC24FJ64GA104
VDD
When it is enabled, the on-chip regulator provides a
DISVREG
constant voltage of 2.5V nominal to the digital core
logic. VDDCORE/VCAP
The regulator can provide this level from a VDD of about
VSS
2.5V, all the way up to the device’s VDDMAX. It does not
have the capability to boost VDD levels below 2.5V. In
order to prevent “brown-out” conditions when the volt-
age drops too low for the regulator, the regulator enters Note 1: These are typical operating voltages. Refer
Tracking mode. In Tracking mode, the regulator output to Section 28.1 “DC Characteristics” for
follows VDD with a typical voltage drop of 100 mV. the full operating ranges of VDD and
VDDCORE.
When the device enters Tracking mode, it is no longer
possible to operate at full speed. To provide information
about when the device enters Tracking mode, the 25.2.2 ON-CHIP REGULATOR AND POR
on-chip regulator includes a simple, Low-Voltage When the voltage regulator is enabled, it takes approxi-
Detect circuit. When VDD drops below full-speed oper- mately 10 s for it to generate output. During this time,
ating voltage, the circuit sets the Low-Voltage Detect designated as TPM, code execution is disabled. TPM is
Interrupt Flag, LVDIF (IFS4<8>). This can be used to applied every time the device resumes operation after
generate an interrupt and put the application into a any power-down, including Sleep mode. TPM is
Low-Power Operational mode or trigger an orderly determined by the setting of the PMSLP bit (RCON<8>)
shutdown. and the WUTSEL Configuration bits (CW3<11:10>).
Low-Voltage Detection is only available when the
Note: For more information on TPM, see
regulator is enabled.
Section 28.0 “Electrical Characteristics”.
If the regulator is disabled, a separate Power-up Timer
(PWRT) is automatically enabled. The PWRT adds a
fixed delay of 64 ms nominal delay at device start-up
(POR or BOR only).

When waking up from Sleep with the regulator 25.3 Watchdog Timer (WDT)
disabled, TPM is used to determine the wake-up time.
To decrease the device wake-up time when operating For PIC24FJ64GA104 family devices, the WDT is
with the regulator disabled, the PMSLP bit can be set. driven by the LPRC Oscillator. When the WDT is
enabled, the clock source is also enabled.
25.2.3 ON-CHIP REGULATOR AND BOR The nominal WDT clock source from LPRC is 31 kHz.
When the on-chip regulator is enabled, This feeds a prescaler that can be configured for either
PIC24FJ64GA104 family devices also have a simple 5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
brown-out capability. If the voltage supplied to the The prescaler is set by the FWPSA Configuration bit.
regulator is inadequate to maintain the tracking level, the With a 31 kHz input, the prescaler yields a nominal
regulator Reset circuitry will generate a Brown-out WDT time-out period (TWDT) of 1 ms in 5-bit mode, or
Reset. This event is captured by the BOR flag bit 4 ms in 7-bit mode.
(RCON<1>). The brown-out voltage specifications are A variable postscaler divides down the WDT prescaler
provided in Section 28.0 “Electrical Characteristics”. output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPS<3:0>
25.2.4 POWER-UP REQUIREMENTS Configuration bits (CW1<3:0>), which allow the selec-
The on-chip regulator is designed to meet the power-up tion of a total of 16 settings, from 1:1 to 1:32,768. Using
requirements for the device. If the application does not the prescaler and postscaler time-out periods, ranges
use the regulator, then strict power-up conditions must from 1 ms to 131 seconds can be achieved.
be adhered to. While powering up, VDDCORE must The WDT, prescaler and postscaler are reset:
never exceed VDD by 0.3 volts.
• On any device Reset
Note: For more information, see Section 28.0 • On the completion of a clock switch, whether
“Electrical Characteristics”. invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
25.2.5 VOLTAGE REGULATOR STANDBY (i.e., Fail-Safe Clock Monitor)
MODE • When a PWRSAV instruction is executed
When enabled, the on-chip regulator always consumes (i.e., Sleep or Idle mode is entered)
a small incremental amount of current over IDD/IPD, • When the device exits Sleep or Idle mode to
including when the device is in Sleep mode, even resume normal operation
though the core digital logic does not require power. To • By a CLRWDT instruction during normal execution
provide additional savings in applications where power
resources are critical, the regulator automatically If the WDT is enabled, it will continue to run during
places itself into Standby mode whenever the device Sleep or Idle modes. When the WDT time-out occurs,
goes into Sleep mode by removing power from the the device will wake the device and code execution will
Flash program memory. This feature is controlled by continue from where the PWRSAV instruction was
the PMSLP bit (RCON<8>). By default, this bit is executed. The corresponding SLEEP or IDLE bits
cleared, which enables Standby mode. (RCON<3:2>) will need to be cleared in software after
the device wakes up.
For PIC24FJ64GA104 family devices, the time
required for regulator wake-up from Standby mode is The WDT Flag bit, WDTO (RCON<4>), is not auto-
controlled by the WUTSEL<1:0> Configuration bits matically cleared following a WDT time-out. To detect
(CW3<11:10>). The default wake-up time for all subsequent WDT events, the flag must be cleared in
devices is 190 s, which is a Legacy mode provided to software.
match older PIC24F device wake-up times. Note: The CLRWDT and PWRSAV instructions
Implementing the WUTSEL Configuration bits provides clear the prescaler and postscaler counts
a fast wake-up option. When WUTSEL<1:0> = 01, the when executed.
regulator wake-up time is TPM, 10 s.
When the regulator’s Standby mode is turned off
(PMSLP = 1), Flash program memory stays powered in
Sleep mode. That enables device wake-up without wait-
ing for TPM. With PMSLP set, however, the power
consumption, while in Sleep mode, will be approximately
40 A higher than what it would be if the regulator was
allowed to enter Standby mode.

25.3.1 WINDOWED OPERATION 25.3.2 CONTROL REGISTER
The Watchdog Timer has an optional Fixed Window The WDT is enabled or disabled by the FWDTEN
mode of operation. In this Windowed mode, CLRWDT Configuration bit. When the FWDTEN Configuration bit
instructions can only reset the WDT during the last 1/4 is set, the WDT is always enabled.
of the programmed WDT period. A CLRWDT instruction
The WDT can be optionally controlled in software when
is executed before that window causes a WDT Reset;
the FWDTEN Configuration bit has been programmed
this is similar to a WDT time-out.
to ‘0’. The WDT is enabled in software by setting the
Windowed WDT mode is enabled by programming the SWDTEN control bit (RCON<5>). The SWDTEN
WINDIS Configuration bit (CW1<6>) to ‘0’. control bit is cleared on any device Reset. The WDT
software option allows the user to enable the WDT for
critical code segments, and disable the WDT during
non-critical segments, for maximum power savings.
FIGURE 25-2: WDT BLOCK DIAGRAM

SWDTEN
FWDTEN LPRC Control
Wake From Sleep
FWPSA WDTPS<3:0>
Prescaler WDT Postscaler

LPRC Input (5-bit/7-bit) Counter 1:1 to 1:32.768 WDT Overflow
Reset
31 kHz 1 ms/4 ms
All Device Resets
Transition to
New Clock Source
Exit Sleep or
Idle Mode
CLRWDT Instr.
PWRSAV Instr.
Sleep or Idle Mode
25.4 Deep Sleep Watchdog Timer 25.5 Program Verification and

(DSWDT) Code Protection
PIC24FJ64GA104 family devices have both a WDT PIC24FJ64GA104 family devices provide two compli-
module and a DSWDT module. The latter runs, if mentary methods to protect application code from
enabled, when a device is in Deep Sleep and is driven overwrites and erasures. These also help to protect the
by either the SOSC or LPRC Oscillator. The clock device from inadvertent configuration changes during
source is selected by the DSWDTOSC (CW4<4>) run time.
Configuration bit.
25.5.1 GENERAL SEGMENT PROTECTION
The DSWDT can be configured to generate a time-out
at 2.1 ms to 25.7 days by selecting the respective For all devices in the PIC24FJ64GA104 family, the
postscaler.The postscaler can be selected by the on-chip program memory space is treated as a single
Configuration bits, DSWDTPS<3:0> (CW4<3:0>). block, known as the General Segment (GS). Code pro-
When the DSWDT is enabled, the clock source is also tection for this block is controlled by one Configuration
enabled. DSWDT is one of the sources that can wake bit, GCP. This bit inhibits external reads and writes to
the device from Deep Sleep mode. the program memory space. It has no direct effect in
normal execution mode.
Write protection is controlled by the GWRP bit in the
Configuration Word. When GWRP is programmed to
‘0’, internal write and erase operations to program
memory are blocked.

25.5.2 CODE SEGMENT PROTECTION A separate bit, WPCFG, is used to independently protect
the last page of program space, including the Flash Con-
In addition to global General Segment protection, a
figuration Words. Programming WPCFG (= 0) protects
separate subrange of the program memory space can
the last page, regardless of the other bit settings. This
be individually protected against writes and erases.
may be useful in circumstances where write protection is
This area can be used for many purposes where a
needed for both a code segment in the bottom of
separate block of erase and write-protected code is
memory, as well as the Flash Configuration Words.
needed, such as bootloader applications. Unlike
common boot block implementations, the specially The various options for segment code protection are
protected segment in the PIC24FJ64GA104 family shown in Table 25-2.
devices can be located by the user anywhere in the
program space and configured in a wide range of sizes. 25.5.3 CONFIGURATION REGISTER
PROTECTION
Code segment protection provides an added level of
protection to a designated area of program memory, by The Configuration registers are protected against
disabling the NVM safety interlock, whenever a write or inadvertent or unwanted changes, or reads in two
erase address falls within a specified range. It does not ways. The primary protection method is the same as
override General Segment protection controlled by the that of the RP registers – shadow registers contain a
GCP or GWRP bits. For example, if GCP and GWRP complimentary value which is constantly compared
are enabled, enabling segmented code protection for with the actual value.
the bottom half of program memory does not undo To safeguard against unpredictable events, Configura-
General Segment protection for the top half. tion bit changes resulting from individual cell level
The size and type of protection for the segmented code disruptions (such as ESD events) will cause a parity
range are configured by the WPFPx, WPEND, WPCFG error and trigger a device Reset.
and WPDIS bits in Configuration Word 3. Code seg- The data for the Configuration registers is derived from
ment protection is enabled by programming the WPDIS the Flash Configuration Words in program memory.
bit (= 0). The WPFP bits specify the size of the segment When the GCP bit is set, the source data for device
to be protected by specifying the 512-word code page configuration is also protected as a consequence. Even
that is the start or end of the protected segment. The if General Segment protection is not enabled, the
specified region is inclusive, therefore, this page will device configuration can be protected by using the
also be protected. appropriate code cement protection setting.
The WPEND bit determines if the protected segment
uses the top or bottom of the program space as a
boundary. Programming WPEND (= 0) sets the bottom
of program memory (000000h) as the lower boundary
of the protected segment. Leaving WPEND unpro-
grammed (= 1) protects the specified page through the
last page of implemented program memory, including
the Configuration Word locations.
TABLE 25-2: SEGMENT CODE PROTECTION CONFIGURATION OPTIONS

Segment Configuration Bits
Write/Erase Protection of Code Segment
WPDIS WPEND WPCFG
1 x 1 No additional protection enabled; all program memory protection is configured
by GCP and GWRP
1 x 0 Last code page protected, including Flash Configuration Words
0 1 0 Addresses from the first address of code page are defined by WPFP<5:0>
through the end of implemented program memory (inclusive) are protected,
including Flash Configuration Words
0 0 0 Address, 000000h, through the last address of code page, defined by
WPFP<5:0> (inclusive) is protected
0 1 1 Addresses from first address of code page, defined by WPFP<5:0> through the
end of implemented program memory (inclusive), are protected, including Flash
Configuration Words
0 0 1 Addresses from first address of code page, defined by WPFP<5:0> through the
end of implemented program memory (inclusive), are protected

25.6 JTAG Interface 25.8 In-Circuit Debugger
PIC24FJ64GA104 family devices implement a JTAG When MPLAB® ICD 2 is selected as a debugger, the
interface, which supports boundary scan device in-circuit debugging functionality is enabled. This func-
testing. tion allows simple debugging functions when used with
MPLAB IDE. Debugging functionality is controlled
25.7 In-Circuit Serial Programming through the PGECx (Emulation/Debug Clock) and
PGEDx (Emulation/Debug Data) pins.
PIC24FJ64GA104 family microcontrollers can be seri-
To use the in-circuit debugger function of the device,
ally programmed while in the end application circuit.
the design must implement ICSP connections to
This is simply done with two lines for clock (PGECx)
MCLR, VDD, VSS and the PGECx/PGEDx pin pair des-
and data (PGEDx), and three other lines for power,
ignated by the ICS Configuration bits. In addition, when
ground and the programming voltage. This allows
the feature is enabled, some of the resources are not
customers to manufacture boards with unprogrammed
available for general use. These resources include the
devices and then program the microcontroller just
first 80 bytes of data RAM and two I/O pins.
before shipping the product. This also allows the most
recent firmware or a custom firmware to be
programmed.

26.0 DEVELOPMENT SUPPORT 26.1 MPLAB Integrated Development
Environment Software
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software The MPLAB IDE software brings an ease of software
and hardware development tools: development previously unseen in the 8/16/32-bit
• Integrated Development Environment microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools
- MPLAB C Compiler for Various Device - Simulator
Families - Programmer (sold separately)
- HI-TECH C for Various Device Families - In-Circuit Emulator (sold separately)
- MPASMTM Assembler - In-Circuit Debugger (sold separately)
- MPLINKTM Object Linker/ • A full-featured editor with color-coded context
MPLIBTM Object Librarian • A multiple project manager
- MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of
Various Device Families contents
• Simulators • High-level source code debugging
- MPLAB SIM Software Simulator • Mouse over variable inspection
• Emulators • Drag and drop variables from source to watch
- MPLAB REAL ICE™ In-Circuit Emulator windows
• In-Circuit Debuggers • Extensive on-line help
- MPLAB ICD 3 • Integration of select third party tools, such as
- PICkit™ 3 Debug Express IAR C Compilers
• Device Programmers The MPLAB IDE allows you to:
- PICkit™ 2 Programmer • Edit your source files (either C or assembly)
- MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to
• Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically
Evaluation Kits, and Starter Kits updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.

26.2 MPLAB C Compilers for Various 26.5 MPLINK Object Linker/
Device Families MPLIB Object Librarian
The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable
are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the
PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects
dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a
lers. These compilers provide powerful integration linker script.
capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and
use. modification of library files of precompiled code. When
For easy source level debugging, the compilers provide a routine from a library is called from a source file, only
symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in
debugger. with the application. This allows large libraries to be
used efficiently in many different applications.
26.3 HI-TECH C for Various Device The object linker/library features include:
Families • Efficient linking of single libraries instead of many
The HI-TECH C Compiler code development systems smaller files
are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping
family of microcontrollers and the dsPIC family of digital related modules together
signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module
integration capabilities, omniscient code generation listing, replacement, deletion and extraction
and ease of use.
For easy source level debugging, the compilers provide 26.6 MPLAB Assembler, Linker and
symbol information that is optimized to the MPLAB IDE Librarian for Various Device
debugger. Families
The compilers include a macro assembler, linker, pre-
MPLAB Assembler produces relocatable machine
processor, and one-step driver, and can run on multiple
code from symbolic assembly language for PIC24,
platforms.
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
26.4 MPASM Assembler generates relocatable object files that can then be
The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and
macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set
files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data
reference, absolute LST files that contain source lines • Command line interface
and generated machine code and COFF files for • Rich directive set
debugging.
• Flexible macro language
The MPASM Assembler features include: • MPLAB IDE compatibility
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process

26.7 MPLAB SIM Software Simulator 26.9 MPLAB ICD 3 In-Circuit Debugger
The MPLAB SIM Software Simulator allows code
System
development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro-
ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware
level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig-
examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU)
a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon-
logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy-
buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated
the simulator to record and track program execution, Development Environment (IDE).
actions on I/O, most peripherals and internal registers.
The MPLAB ICD 3 In-Circuit Debugger probe is con-
The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed
symbolic debugging using the MPLAB C Compilers, USB 2.0 interface and is connected to the target with a
and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB
ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers.
ronment, making it an excellent, economical software
development tool. 26.10 PICkit 3 In-Circuit Debugger/
Programmer and
26.8 MPLAB REAL ICE In-Circuit
PICkit 3 Debug Express
Emulator System
The MPLAB PICkit 3 allows debugging and program-
MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a
Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical
Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development
programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected
with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB
the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an
included with each kit. Microchip debug (RJ-11) connector (compatible with
The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector
using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple-
to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro-
circuit debugger systems (RJ11) or with the new high- gramming™.
speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo
(LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM
The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and
downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software.
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers signifi-
cant advantages over competitive emulators including
low-cost, full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, a rugge-
dized probe interface and long (up to three meters) inter-
connection cables.

26.11 PICkit 2 Development 26.13 Demonstration/Development
Programmer/Debugger and Boards, Evaluation Kits, and
PICkit 2 Debug Express Starter Kits
The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and
a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC
face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func-
families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for
Windows® programming interface supports baseline adding custom circuitry and provide application firmware
(PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification.
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232
microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional
products. With Microchip’s powerful MPLAB Integrated EEPROM memory.
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be
trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom
steps the program while the PIC microcontroller is circuits and for learning about various microcontroller
embedded in the application. When halted at a break- applications.
point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon-
The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip
board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software
with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN,
MPLAB IDE software. IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
26.12 MPLAB PM3 Device Programmer
Also available are starter kits that contain everything
The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually
CE compliant device programmer with programmable includes a single application and debug capability, all
voltage verification at VDDMIN and VDDMAX for on one board.
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu- Check the Microchip web page (www.microchip.com)
lar, detachable socket assembly to support various for the complete list of demonstration, development
package types. The ICSP™ cable assembly is included and evaluation kits.
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.

27.0 INSTRUCTION SET SUMMARY The literal instructions that involve data movement may
use some of the following operands:
Note: This chapter is a brief summary of the • A literal value to be loaded into a W register or file
PIC24F instruction set architecture, and is register (specified by the value of ‘k’)
not intended to be a comprehensive
• The W register or file register where the literal
reference source.
value is to be loaded (specified by ‘Wb’ or ‘f’)
The PIC24F instruction set adds many enhancements However, literal instructions that involve arithmetic or
to the previous PIC® MCU instruction sets, while main- logical operations use some of the following operands:
taining an easy migration from previous PIC MCU
instruction sets. Most instructions are a single program • The first source operand, which is a register ‘Wb’
memory word. Only three instructions require two without any address modifier
program memory locations. • The second source operand, which is a literal
value
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode, which specifies the instruction • The destination of the result (only if not the same
type and one or more operands, which further specify as the first source operand), which is typically a
the operation of the instruction. The instruction set is register ‘Wd’ with or without an address modifier
highly orthogonal and is grouped into four basic The control instructions may use some of the following
categories: operands:
• Word or byte-oriented operations • A program memory address
• Bit-oriented operations • The mode of the table read and table write
• Literal operations instructions
• Control operations All instructions are a single word, except for certain
Table 27-1 shows the general symbols used in double-word instructions, which were made
describing the instructions. The PIC24F instruction set double-word instructions so that all the required infor-
summary in Table 27-2 lists all of the instructions, along mation is available in these 48 bits. In the second word,
with the status flags affected by each instruction. the 8 MSbs are ‘0’s. If this second word is executed as
an instruction (by itself), it will execute as a NOP.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three Most single-word instructions are executed in a single
operands: instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
• The first source operand, which is typically a tion. In these cases, the execution takes two instruction
register ‘Wb’ without any address modifier cycles, with the additional instruction cycle(s) executed
• The second source operand, which is typically a as a NOP. Notable exceptions are the BRA (uncondi-
register ‘Ws’ with or without an address modifier tional/computed branch), indirect CALL/GOTO, all table
• The destination of the result, which is typically a reads and writes, and RETURN/RETFIE instructions,
register ‘Wd’ with or without an address modifier which are single-word instructions but take two or three
However, word or byte-oriented file register instructions cycles.
have two operands: Certain instructions that involve skipping over the sub-
• The file register specified by the value, ‘f’ sequent instruction require either two or three cycles if
the skip is performed, depending on whether the
• The destination, which could either be the file
instruction being skipped is a single-word or two-word
register, ‘f’, or the W0 register, which is denoted
instruction. Moreover, double-word moves require two
as ‘WREG’
cycles. The double-word instructions execute in two
Most bit-oriented instructions (including simple instruction cycles.
rotate/shift instructions) have two operands:
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register (specified
by a literal value or indirectly by the contents of
register, ‘Wb’)

TABLE 27-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field Description
#text Means literal defined by “text”

(text) Means “content of text”
[text] Means “the location addressed by text”
{ } Optional field or operation
<n:m> Register bit field
.b Byte mode selection
.d Double-Word mode selection
.S Shadow register select
.w Word mode selection (default)
bit4 4-bit bit selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr Absolute address, label or expression (resolved by the linker)
f File register address {0000h...1FFFh}
lit1 1-bit unsigned literal {0,1}
lit4 4-bit unsigned literal {0...15}
lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit23 23-bit unsigned literal {0...8388607}; LSB must be ‘0’
None Field does not require an entry, may be blank
PC Program Counter
Slit10 10-bit signed literal {-512...511}
Wb Base W register {W0..W15}
Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo Destination W register 
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn Dividend, Divisor working register pair (direct addressing)
Wn One of 16 working registers {W0..W15}
Wnd One of 16 destination working registers {W0..W15}
Wns One of 16 source working registers {W0..W15}
WREG W0 (working register used in file register instructions)
Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }

TABLE 27-2: INSTRUCTION SET OVERVIEW
Assembly # of # of Status Flags
Assembly Syntax Description
Mnemonic Words Cycles Affected
ADD ADD f f = f + WREG 1 1 C, DC, N, OV, Z

ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z
ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z
ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z
ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z
ADDC ADDC f f = f + WREG + (C) 1 1 C, DC, N, OV, Z
ADDC f,WREG WREG = f + WREG + (C) 1 1 C, DC, N, OV, Z
ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C, DC, N, OV, Z
ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C, DC, N, OV, Z
ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C, DC, N, OV, Z
AND AND f f = f .AND. WREG 1 1 N, Z
AND f,WREG WREG = f .AND. WREG 1 1 N, Z
AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N, Z
AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N, Z
AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N, Z
ASR ASR f f = Arithmetic Right Shift f 1 1 C, N, OV, Z
ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C, N, OV, Z
ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C, N, OV, Z
ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N, Z
ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N, Z
BCLR BCLR f,#bit4 Bit Clear f 1 1 None
BCLR Ws,#bit4 Bit Clear Ws 1 1 None
BRA BRA C,Expr Branch if Carry 1 1 (2) None
BRA GE,Expr Branch if Greater than or Equal 1 1 (2) None
BRA GEU,Expr Branch if Unsigned Greater than or Equal 1 1 (2) None
BRA GT,Expr Branch if Greater than 1 1 (2) None
BRA GTU,Expr Branch if Unsigned Greater than 1 1 (2) None
BRA LE,Expr Branch if Less than or Equal 1 1 (2) None
BRA LEU,Expr Branch if Unsigned Less than or Equal 1 1 (2) None
BRA LT,Expr Branch if Less than 1 1 (2) None
BRA LTU,Expr Branch if Unsigned Less than 1 1 (2) None
BRA N,Expr Branch if Negative 1 1 (2) None
BRA NC,Expr Branch if Not Carry 1 1 (2) None
BRA NN,Expr Branch if Not Negative 1 1 (2) None
BRA NOV,Expr Branch if Not Overflow 1 1 (2) None
BRA NZ,Expr Branch if Not Zero 1 1 (2) None
BRA OV,Expr Branch if Overflow 1 1 (2) None
BRA Expr Branch Unconditionally 1 2 None
BRA Z,Expr Branch if Zero 1 1 (2) None
BRA Wn Computed Branch 1 2 None
BSET BSET f,#bit4 Bit Set f 1 1 None
BSET Ws,#bit4 Bit Set Ws 1 1 None
BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None
BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None
BTG BTG f,#bit4 Bit Toggle f 1 1 None
BTG Ws,#bit4 Bit Toggle Ws 1 1 None
BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None
(2 or 3)
BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None
(2 or 3)

TABLE 27-2: INSTRUCTION SET OVERVIEW (CONTINUED)
BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None

(2 or 3)
BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None
(2 or 3)
BTST BTST f,#bit4 Bit Test f 1 1 Z
BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C
BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z
BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C
BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z
BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z
BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C
BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z
CALL CALL lit23 Call Subroutine 2 2 None
CALL Wn Call Indirect Subroutine 1 2 None
CLR CLR f f = 0x0000 1 1 None
CLR WREG WREG = 0x0000 1 1 None
CLR Ws Ws = 0x0000 1 1 None
CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO, Sleep
COM COM f f=f 1 1 N, Z
COM f,WREG WREG = f 1 1 N, Z
COM Ws,Wd Wd = Ws 1 1 N, Z
CP CP f Compare f with WREG 1 1 C, DC, N, OV, Z
CP Wb,#lit5 Compare Wb with lit5 1 1 C, DC, N, OV, Z
CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C, DC, N, OV, Z
CP0 CP0 f Compare f with 0x0000 1 1 C, DC, N, OV, Z
CP0 Ws Compare Ws with 0x0000 1 1 C, DC, N, OV, Z
CPB CPB f Compare f with WREG, with Borrow 1 1 C, DC, N, OV, Z
CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C, DC, N, OV, Z
CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C, DC, N, OV, Z
(Wb – Ws – C)
CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, Skip if = 1 1 None
(2 or 3)
CPSGT CPSGT Wb,Wn Compare Wb with Wn, Skip if > 1 1 None
(2 or 3)
CPSLT CPSLT Wb,Wn Compare Wb with Wn, Skip if < 1 1 None
(2 or 3)
CPSNE CPSNE Wb,Wn Compare Wb with Wn, Skip if  1 1 None
(2 or 3)
DAW DAW.B Wn Wn = Decimal Adjust Wn 1 1 C
DEC DEC f f=f–1 1 1 C, DC, N, OV, Z
DEC f,WREG WREG = f – 1 1 1 C, DC, N, OV, Z
DEC Ws,Wd Wd = Ws – 1 1 1 C, DC, N, OV, Z
DEC2 DEC2 f f=f–2 1 1 C, DC, N, OV, Z
DEC2 f,WREG WREG = f – 2 1 1 C, DC, N, OV, Z
DEC2 Ws,Wd Wd = Ws – 2 1 1 C, DC, N, OV, Z
DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None
DIV DIV.SW Wm,Wn Signed 16/16-bit Integer Divide 1 18 N, Z, C, OV
DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N, Z, C, OV
DIV.UW Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N, Z, C, OV
DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N, Z, C, OV
EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None
FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C
FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C

GOTO GOTO Expr Go to Address 2 2 None

GOTO Wn Go to Indirect 1 2 None
INC INC f f=f+1 1 1 C, DC, N, OV, Z
INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z
INC Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z
INC2 INC2 f f=f+2 1 1 C, DC, N, OV, Z
INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z
INC2 Ws,Wd Wd = Ws + 2 1 1 C, DC, N, OV, Z
IOR IOR f f = f .IOR. WREG 1 1 N, Z
IOR f,WREG WREG = f .IOR. WREG 1 1 N, Z
IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N, Z
IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N, Z
IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N, Z
LNK LNK #lit14 Link Frame Pointer 1 1 None
LSR LSR f f = Logical Right Shift f 1 1 C, N, OV, Z
LSR f,WREG WREG = Logical Right Shift f 1 1 C, N, OV, Z
LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C, N, OV, Z
LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N, Z
LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N, Z
MOV MOV f,Wn Move f to Wn 1 1 None
MOV [Wns+Slit10],Wnd Move [Wns + Slit10] to Wnd 1 1 None
MOV f Move f to f 1 1 N, Z
MOV f,WREG Move f to WREG 1 1 N, Z
MOV #lit16,Wn Move 16-bit Literal to Wn 1 1 None
MOV.b #lit8,Wn Move 8-bit Literal to Wn 1 1 None
MOV Wn,f Move Wn to f 1 1 None
MOV Wns,[Wns+Slit10] Move Wns to [Wns + Slit10] 1 1
MOV Wso,Wdo Move Ws to Wd 1 1 None
MOV WREG,f Move WREG to f 1 1 N, Z
MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None
MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None
MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = Signed(Wb) * Signed(Ws) 1 1 None
MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = Signed(Wb) * Unsigned(Ws) 1 1 None
MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = Unsigned(Wb) * Signed(Ws) 1 1 None
MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = Unsigned(Wb) * Unsigned(Ws) 1 1 None
MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = Signed(Wb) * Unsigned(lit5) 1 1 None
MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = Unsigned(Wb) * Unsigned(lit5) 1 1 None
MUL f W3:W2 = f * WREG 1 1 None
NEG NEG f f=f+1 1 1 C, DC, N, OV, Z
NEG f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z
NEG Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z
NOP NOP No Operation 1 1 None
NOPR No Operation 1 1 None
POP POP f Pop f from Top-of-Stack (TOS) 1 1 None
POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None
POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd + 1) 1 2 None
POP.S Pop Shadow Registers 1 1 All
PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None
PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None
PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack (TOS) 1 2 None
PUSH.S Push Shadow Registers 1 1 None

PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep

RCALL RCALL Expr Relative Call 1 2 None
RCALL Wn Computed Call 1 2 None
REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None
REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None
RESET RESET Software Device Reset 1 1 None
RETFIE RETFIE Return from Interrupt 1 3 (2) None
RETLW RETLW #lit10,Wn Return with Literal in Wn 1 3 (2) None
RETURN RETURN Return from Subroutine 1 3 (2) None
RLC RLC f f = Rotate Left through Carry f 1 1 C, N, Z
RLC f,WREG WREG = Rotate Left through Carry f 1 1 C, N, Z
RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C, N, Z
RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N, Z
RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N, Z
RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N, Z
RRC RRC f f = Rotate Right through Carry f 1 1 C, N, Z
RRC f,WREG WREG = Rotate Right through Carry f 1 1 C, N, Z
RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C, N, Z
RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N, Z
RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N, Z
RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N, Z
SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C, N, Z
SETM SETM f f = FFFFh 1 1 None
SETM WREG WREG = FFFFh 1 1 None
SETM Ws Ws = FFFFh 1 1 None
SL SL f f = Left Shift f 1 1 C, N, OV, Z
SL f,WREG WREG = Left Shift f 1 1 C, N, OV, Z
SL Ws,Wd Wd = Left Shift Ws 1 1 C, N, OV, Z
SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N, Z
SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N, Z
SUB SUB f f = f – WREG 1 1 C, DC, N, OV, Z
SUB f,WREG WREG = f – WREG 1 1 C, DC, N, OV, Z
SUB #lit10,Wn Wn = Wn – lit10 1 1 C, DC, N, OV, Z
SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C, DC, N, OV, Z
SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C, DC, N, OV, Z
SUBB SUBB f f = f – WREG – (C) 1 1 C, DC, N, OV, Z
SUBB f,WREG WREG = f – WREG – (C) 1 1 C, DC, N, OV, Z
SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C, DC, N, OV, Z
SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C, DC, N, OV, Z
SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C, DC, N, OV, Z
SUBR SUBR f f = WREG – f 1 1 C, DC, N, OV, Z
SUBR f,WREG WREG = WREG – f 1 1 C, DC, N, OV, Z
SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C, DC, N, OV, Z
SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C, DC, N, OV, Z
SUBBR SUBBR f f = WREG – f – (C) 1 1 C, DC, N, OV, Z
SUBBR f,WREG WREG = WREG – f – (C) 1 1 C, DC, N, OV, Z
SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C, DC, N, OV, Z
SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C, DC, N, OV, Z
SWAP SWAP.b Wn Wn = Nibble Swap Wn 1 1 None
SWAP Wn Wn = Byte Swap Wn 1 1 None

TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None

TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None
TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None
TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None
ULNK ULNK Unlink Frame Pointer 1 1 None
XOR XOR f f = f .XOR. WREG 1 1 N, Z
XOR f,WREG WREG = f .XOR. WREG 1 1 N, Z
XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N, Z
XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N, Z
XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N, Z
ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C, Z, N

NOTES:

28.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC24FJ64GA104 family electrical characteristics. Additional information will
be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC24FJ64GA104 family are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other
conditions above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings(†)

Ambient temperature under bias.............................................................................................................-40°C to +135°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any combined analog and digital pin, and MCLR, with respect to VSS ........................ -0.3V to (VDD + 0.3V)
Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +6.0V
Voltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +3.0V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin (Note 1)................................................................................................................250 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 1)....................................................................................................200 mA
Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 28-1).
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

28.1 DC Characteristics
FIGURE 28-1: PIC24FJ64GA104 FAMILY VOLTAGE/FREQUENCY GRAPH (INDUSTRIAL)
3.00V
2.75V 2.75V
Voltage (VDDCORE)(1)
2.50V PIC24FJ64GA104 Family
2.35V 2.35V
2.00V
16 MHz 32 MHz
Frequency
For frequencies between 16 MHz and 32 MHz, FMAX = (45.7 MHz/V) * (VDDCORE – 2V) + 16 MHz.
Note 1: When the voltage regulator is disabled, VDD and VDDCORE must be maintained so that
VDDCOREVDD3.6V.
FIGURE 28-2: PIC24FJ64GA104 FAMILY VOLTAGE/FREQUENCY GRAPH

(EXTENDED TEMPERATURE)
3.00V
2.75V 2.75V
(VDDCORE)(1)
2.50V PIC24FJ64GA104 Family

2.35V
2.25V
2.00V
Voltage
16 MHz 24 MHz
Frequency
For frequencies between 16 MHz and 24 MHz, FMAX = (22.9 MHz/V) * (VDDCORE – 2V) + 16 MHz.
Note 1: When the voltage regulator is disabled, VDD and VDDCORE must be maintained so that
VDDCOREVDD3.6V.

TABLE 28-1: THERMAL OPERATING CONDITIONS
Rating Symbol Min Typ Max Unit
PIC24FJ64GA104 Family:
Operating Junction Temperature Range TJ -40 — +140 °C
Operating Ambient Temperature Range TA -40 — +125 °C
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD –  IOH) PD PINT + PI/O W
I/O Pin Power Dissipation:
PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL)
Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W
TABLE 28-2: THERMAL PACKAGING CHARACTERISTICS

Characteristic Symbol Typ Max Unit Notes
Package Thermal Resistance, 300 mil SOIC JA 49 — °C/W (Note 1)
Package Thermal Resistance, 6x6x0.9 mm QFN JA 33.7 — °C/W (Note 1)
Package Thermal Resistance, 8x8x1 mm QFN JA 28 — °C/W (Note 1)
Package Thermal Resistance, 10x10x1 mm TQFP JA 39.3 — °C/W (Note 1)
Note 1: Junction to ambient thermal resistance; Theta-JA (JA) numbers are achieved by package simulations.

TABLE 28-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Param
Symbol Characteristic Min Typ(1) Max Units Conditions
No.
Operating Voltage
DC10 Supply Voltage
VDD 2.2 — 3.6 V Regulator enabled
VDD VDDCORE — 3.6 V Regulator disabled
VDDCORE 2.0 — 2.75 V Regulator disabled
DC12 VDR RAM Data Retention 1.5 — — V
Voltage(2)
DC16 VPOR VDD Start Voltage VSS — — V
to Ensure Internal
Power-on Reset Signal
DC17 SVDD VDD Rise Rate 0.05 — — V/ms 0-3.3V in 0.1s
to Ensure Internal 0-2.5V in 60 ms
Power-on Reset Signal
DC18 VBOR Brown-out Reset — 2.05 — V
Voltage
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: This is the limit to which VDD can be lowered without losing RAM data.

TABLE 28-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Parameter
Typical(1) Max Units Conditions
No.
Operating Current (IDD)(2)
DC21 0.24 0.395 mA -40°C
DC21a 0.25 0.395 mA +25°C
2.0V(3)
DC21b 0.25 0.395 mA +85°C
DC21f 0.3 0.395 mA +125°C
0.5 MIPS
DC21c 0.44 0.78 mA -40°C
DC21d 0.41 0.78 mA +25°C
3.3V(4)
DC21e 0.41 0.78 mA +85°C
DC21g 0.6 0.78 mA +125°C
DC20 0.5 0.75 mA -40°C
DC20a 0.5 0.75 mA +25°C
2.0V(3)
DC20b 0.5 0.75 mA +85°C
DC20c 0.6 0.75 mA +125°C
1 MIPS
DC20d 0.75 1.4 mA -40°C
DC20e 0.75 1.4 mA +25°C
3.3V(4)
DC20f 0.75 1.4 mA +85°C
DC20g 1.0 1.4 mA +125°C
DC23 2.0 3.0 mA -40°C
DC23a 2.0 3.0 mA +25°C
2.0V(3)
DC23b 2.0 3.0 mA +85°C
DC23c 2.4 3.0 mA +125°C
4 MIPS
DC23d 2.9 4.2 mA -40°C
DC23e 2.9 4.2 mA +25°C
3.3V(4)
DC23f 2.9 4.2 mA +85°C
DC23g 3.5 4.2 mA +125°C
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption. The test conditions for all IDD measurements are as follows: OSCI driven
with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD.
MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are
operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set.
3: On-chip voltage regulator is disabled (DISVREG is tied to VDD).
4: On-chip voltage regulator is enabled (DISVREG is tied to VSS). Low-Voltage Detect (LVD) and Brown-out
Detect (BOD) are enabled.

TABLE 28-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED)
Parameter
No.
Operating Current (IDD)(2)
DC24 10.5 15.5 mA -40°C
DC24a 10.5 15.5 mA +25°C
2.5V(3)
DC24b 10.5 15.5 mA +85°C
DC24c 11.3 15.5 mA +125°C
16 MIPS
DC24d 11.3 15.5 mA -40°C
DC24e 11.3 15.5 mA +25°C
3.3V(4)
DC24f 11.3 15.5 mA +85°C
DC24g 11.3 15.5 mA +125°C
DC31 15.0 18.0 A -40°C
DC31a 15.0 19.0 A +25°C
2.0V(3)
DC31b 20.0 36.0 A +85°C
DC31c 42.0 55.0 A +125°C
LPRC (31 kHz)
DC31d 57.0 120.0 A -40°C
DC31e 57.0 125.0 A +25°C
3.3V(4)
DC31f 95.0 160.0 A +85°C
DC31g 114.0 180.0 A +125°C
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption. The test conditions for all IDD measurements are as follows: OSCI driven
with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD.
MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are
operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set.

TABLE 28-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Parameter
No.
Idle Current (IIDLE)(2)
DC41 67 100 A -40°C
DC41a 68 100 A +25°C
2.0V(3)
DC41b 74 100 A +85°C
DC41f 102 120 A +125°C
0.5 MIPS
DC41c 166 265 A -40°C
DC41d 167 265 A +25°C
3.3V(4)
DC41e 177 265 A +85°C
DC41g 225 285 A +125°C
DC40 125 180 A -40°C
DC40a 125 180 A +25°C
2.0V(3)
DC40b 125 180 A +85°C
DC40c 167 200 A +125°C
1 MIPS
DC40d 210 350 A -40°C
DC40e 210 350 A +25°C
3.3V(4)
DC40f 210 350 A +85°C
DC40g 305 370 A +125°C
DC43 0.5 0.6 mA -40°C
DC43a 0.5 0.6 mA +25°C
2.0V(3)
DC43b 0.5 0.6 mA +85°C
DC43c 0.54 0.62 mA +125°C
4 MIPS
DC43d 0.75 0.95 mA -40°C
DC43e 0.75 0.95 mA +25°C
3.3V(4)
DC43f 0.75 0.95 mA +85°C
DC43g 0.8 0.97 mA +125°C
DC47 2.6 3.3 mA -40°C
DC47a 2.6 3.3 mA +25°C
2.5V(3)
DC47b 2.6 3.3 mA +85°C
DC47f 2.7 3.4 mA +125°C
16 MIPS
DC47c 2.9 3.5 mA -40°C
DC47d 2.9 3.5 mA +25°C
3.3V(4)
DC47e 2.9 3.5 mA +85°C
DC47g 3.0 3.6 mA +125°C
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: Base IIDLE current is measured with the core off, OSCI driven with external square wave from rail to rail. All I/O
pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. No peripheral
modules are operating and all of the Peripheral Module Disable (PMD) bits are set.
4: On-chip voltage regulator is enabled (DISVREG is tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect
(BOD) are enabled.

TABLE 28-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)
Parameter
No.
Idle Current (IIDLE)(2)
DC50 0.8 1.0 mA -40°C
DC50a 0.8 1.0 mA +25°C
2.0V(3)
DC50b 0.8 1.0 mA +85°C
DC50c 0.9 1.1 mA +125°C
FRC (4 MIPS)
DC50d 1.1 1.3 mA -40°C
DC50e 1.1 1.3 mA +25°C
3.3V(4)
DC50f 1.1 1.3 mA +85°C
DC50g 1.2 1.4 mA +125°C
DC51 2.4 8.0 A -40°C
DC51a 2.2 8.0 A +25°C
2.0V(3)
DC51b 7.2 21 A +85°C
DC51c 35 50 A +125°C
LPRC (31 kHz)
DC51d 38 55 A -40°C
DC51e 44 60 A +25°C
3.3V(4)
DC51f 70 100 A +85°C
DC51g 96 150 A +125°C
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: Base IIDLE current is measured with the core off, OSCI driven with external square wave from rail to rail. All I/O
pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. No peripheral
modules are operating and all of the Peripheral Module Disable (PMD) bits are set.
4: On-chip voltage regulator is enabled (DISVREG is tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect
(BOD) are enabled.

TABLE 28-6: DC CHARACTERISTICS: POWER-DOWN BASE CURRENT (IPD)
Parameter
No.
Power-Down Current (IPD)(2)
DC60 0.05 1.0 A -40°C
DC60a 0.2 1.0 A +25°C
DC60i 2.0 6.5 A +60°C 2.0V(3)
DC60b 3.5 12 A +85°C
DC60m 29.9 50 A +125°C
DC60c 0.1 1.0 A -40°C
DC60d 0.4 1.0 A +25°C
DC60j 2.5 15 A +60°C 2.5V(3) Base Power-Down Current(5)
DC60e 4.2 25 A +85°C
DC60n 36.2 75 A +125°C
DC60f 3.3 9.0 A -40°C
DC60g 3.3 10 A +25°C
DC60k 5.0 20 A +60°C 3.3V(4)
DC60h 7.0 30 A +85°C
DC60p 39.2 80 A +125°C
DC70c 0.003 0.2 A -40°C
DC70d 0.02 0.2 A +25°C
DC70j 0.2 0.35 A +60°C 2.5V(4)
DC70e 0.51 1.5 A +85°C
DC70a 6.1 12 A +125°C
Base Deep Sleep Current
DC70f 0.01 0.3 A -40°C
DC70g 0.04 0.3 A +25°C
DC70k 0.2 0.5 A +60°C 3.3V(4)
DC70h 0.71 2.0 A +85°C
DC70b 7.2 16 A +125°C
Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
2: Base IPD is measured with the device in Sleep mode (all peripherals and clocks shut down). All I/Os are
configured as inputs and pulled high. WDT, etc., are all switched off, PMSLP bit is clear and the Peripheral
Module Disable (PMD) bits for all unused peripherals are set.
5: The  current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.

TABLE 28-7: DC CHARACTERISTICS: POWER-DOWN PERIPHERAL
MODULE CURRENT (IPD)
Parameter
No.
 Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2)
DC61 0.2 0.7 A -40°C
DC61a 0.2 0.7 A +25°C
DC61i 0.2 0.7 A +60°C 2.0V(3)
DC61b 0.23 0.7 A +85°C
DC61m 0.3 1.0 A +125°C
DC61c 0.25 0.9 A -40°C
DC61d 0.25 0.9 A +25°C 31 kHz LPRC Oscillator with
DC61j 0.25 0.9 A +60°C 2.5V(3) RTCC, WDT, DSWDT or
DC61e 0.28 0.9 A +85°C Timer 1: ILPRC(5)
DC61p 0.5 1.2 A +125°C
DC61f 0.6 1.5 A -40°C
DC61g 0.6 1.5 A +25°C
DC61k 0.6 1.5 A +60°C 3.3V(4)
DC61h 0.8 1.5 A +85°C
DC61n 1.0 1.7 A +125°C
DC62 0.5 1.0 A -40°C
DC62a 0.5 1.0 A +25°C
DC62i 0.5 1.0 A +60°C 2.0V(3)
DC62b 0.5 1.3 A +85°C
DC62m 0.6 1.6 A +125°C
DC62c 0.7 1.5 A -40°C
DC62d 0.7 1.5 A +25°C Low drive strength, 32 kHz Crystal
with RTCC, DSWDT or
DC62j 0.7 1.5 A +60°C 2.5V(3)
Timer1: ISOSC;
DC62e 0.7 1.8 A +85°C SOSCSEL = 01
DC62n 0.8 2.1 A +125°C
DC62f 1.5 2.0 A -40°C
DC62g 1.5 2.0 A +25°C
DC62k 1.5 2.0 A +60°C 3.3V(4)
DC62h 1.5 2.5 A +85°C
DC62p 1.9 3.0 A +125°C
2: Peripheral IPD deltas are measured with the device in Sleep mode (all peripherals and clocks shut down).
All I/Os are configured as inputs and pulled high. Only the peripheral or clock being measured is enabled.
PMSLP bit is clear and the Peripheral Module Disable bits (PMD) for all unused peripherals are set.

TABLE 28-7: DC CHARACTERISTICS: POWER-DOWN PERIPHERAL
MODULE CURRENT (IPD) (CONTINUED)
Parameter
No.
 Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2)
DC63 1.8 2.3 A -40°C
DC63a 1.8 2.7 A +25°C
DC63i 1.8 3.0 A +60°C 2.0V(3)
DC63b 1.8 3.0 A +85°C
DC63m 2.2 3.3 A +125°C
DC63c 2 2.7 A -40°C
DC63d 2 2.9 A +25°C 32 kHz Crystal with RTCC,
DC63j 2 3.2 A +60°C 2.5V(3) DSWDT or Timer1: ISOSC;
DC63e 2 3.5 A +85°C SOSCSEL = 11(5)
DC63n 2.5 3.8 A +125°C
DC63f 2.25 3.0 A -40°C
DC63g 2.25 3.0 A +25°C
DC63k 2.25 3.3 A +60°C 3.3V(4)
DC63h 2.25 3.5 A +85°C
DC63p 2.8 4.0 A +125°C
DC71c 0.001 0.25 A -40°C
DC71d 0.03 0.25 A +25°C
DC71j 0.05 0.60 A +60°C 2.5V(4)
DC71e 0.08 2.0 A +85°C
DC71a 3.9 10 A +125°C
Deep Sleep BOR: IDSBOR
DC71f 0.001 0.50 A -40°C
DC71g 0.03 0.50 A +25°C
DC71k 0.05 0.75 A +60°C 3.3V(4)
DC71h 0.08 2.5 A +85°C
DC71b 3.9 12.5 A +125°C
2: Peripheral IPD deltas are measured with the device in Sleep mode (all peripherals and clocks shut down).
All I/Os are configured as inputs and pulled high. Only the peripheral or clock being measured is enabled.
PMSLP bit is clear and the Peripheral Module Disable bits (PMD) for all unused peripherals are set.

TABLE 28-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise
stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
Param
Sym Characteristic Min Typ(1) Max Units Conditions
No.
VIL Input Low Voltage(4)
DI10 I/O Pins with ST Buffer VSS — 0.2 VDD V
DI11 I/O Pins with TTL Buffer VSS — 0.15 VDD V
DI15 MCLR VSS — 0.2 VDD V
DI16 OSC1 (XT mode) VSS — 0.2 VDD V
DI17 OSC1 (HS mode) VSS — 0.2 VDD V
2
DI18 I/O Pins with I C™ Buffer: VSS — 0.3 VDD V
DI19 I/O Pins with SMBus Buffer: VSS — 0.8 V SMBus enabled
VIH Input High Voltage(4)
DI20 I/O Pins with ST Buffer:
with Analog Functions, 0.8 VDD — VDD V
Digital Only 0.8 VDD — 5.5 V
DI21 I/O Pins with TTL Buffer:
with Analog Functions, 0.25 VDD + 0.8 — VDD V
Digital Only 0.25 VDD + 0.8 — 5.5 V
DI25 MCLR 0.8 VDD — VDD V
DI26 OSC1 (XT mode) 0.7 VDD — VDD V
DI27 OSC1 (HS mode) 0.7 VDD — VDD V
DI28 I/O Pins with I2C
Buffer:
with Analog Functions, 0.7 VDD — VDD V
Digital Only 0.7 VDD — 5.5 V
DI29 I/O Pins with SMBus Buffer: 2.5V  VPIN  VDD
with Analog Functions, 2.1 VDD V
Digital Only 2.1 5.5 V
DI30 ICNPU CNx Pull-up Current 50 250 400 A VDD = 3.3V, VPIN = VSS
IIL Input Leakage Current(2,3)
DI50 I/O Ports — — +50 nA VSS  VPIN  VDD,
Pin at high-impedance
DI51 Analog Input Pins — — +50 nA VSS  VPIN  VDD,
Pin at high-impedance
DI55 MCLR — — +50 nA VSS VPIN VDD
DI56 OSC1 — — +50 nA VSS VPIN VDD,
XT and HS modes
and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Refer to Table 1-2 for I/O pins buffer types.

TABLE 28-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Param
No.
VOL Output Low Voltage
DO10 I/O Ports — — 0.4 V IOL = 8.5 mA, VDD = 3.6V
— — 0.4 V IOL = 5.0 mA, VDD = 2.0V
DO16 I/O Ports — — 0.4 V IOL = 8.0 mA, VDD = 3.6V, 125°C
— — 0.4 V IOL = 4.5 mA, VDD = 2.0V, 125°C
VOH Output High Voltage
DO20 I/O Ports 3.0 — — V IOH = -3.0 mA, VDD = 3.6V
2.4 — — V IOH = -6.0 mA, VDD = 3.6V
1.65 — — V IOH = -1.0 mA, VDD = 2.0V
1.4 — — V IOH = -3.0 mA, VDD = 2.0V
DO26 I/O Ports 3.0 — — V IOH = -2.5 mA, VDD = 3.6V, 125°C
1.65 — — V IOH = -0.5 mA, VDD = 2.0V, 125°C
and are not tested.
TABLE 28-10: DC CHARACTERISTICS: PROGRAM MEMORY

Standard Operating Conditions: 2.0V to 3.6V (unless
otherwise stated)
DC CHARACTERISTICS
Param
No.
D130 EP Cell Endurance 10,000 — — E/W -40C to +85C
D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum
operating voltage
VPEW Supply Voltage for Self-Timed Writes
D132A VDDCORE 2.25 — 3.6 V
D132B VDD 2.35 — 3.6 V
D133A TIW Self-Timed Write Cycle Time — 3 — ms
D133B TIE Self-Timed Page Erase Time 40 — — ms
D134 TRETD Characteristic Retention 20 — — Year Provided no other
specifications are violated
D135 IDDP Supply Current during Programming — 7 — mA
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

TABLE 28-11: COMPARATOR SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
Symbol Characteristic Min Typ Max Units Comments
No.
D300 VIOFF Input Offset Voltage* — 20 40 mV
D301 VICM Input Common Mode Voltage* 0 — VDD V
D302 CMRR Common Mode Rejection 55 — — dB
Ratio*
300 TRESP Response Time*(1) — 150 400 ns
301 TMC2OV Comparator Mode Change to — — 10 s
Output Valid*
* Parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from
VSS to VDD.
TABLE 28-12: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS

Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
Symbol Characteristic Min Typ Max Units Comments
No.
VRD310 CVRES Resolution VDD/24 — VDD/32 LSb
VRD311 CVRAA Absolute Accuracy — — AVDD – 1.5 LSb
VRD312 CVRUR Unit Resistor Value (R) — 2k — 
VR310 TSET Settling Time(1) — — 10 s
Note 1: Settling time measured while CVRR = 1 and CVR<3:0> bits transition from ‘0000’ to ‘1111’.
TABLE 28-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)
Param
Symbol Characteristics Min Typ Max Units Comments
No.
VBG Band Gap Reference Voltage 1.14 1.2 1.26 V
TBG Band Gap Reference Start-up — 1 — ms
Time
VRGOUT Regulator Output Voltage 2.35 2.5 2.75 V
CEFC External Filter Capacitor Value 4.7 10 — F Series resistance < 3 Ohm
recommended;
< 5 Ohm required.

28.2 AC Characteristics and Timing Parameters
The information contained in this section defines the PIC24FJ64GA104 family AC characteristics and timing parameters.
TABLE 28-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

Operating temperature -40°C  TA  +85°C for Industrial and
AC CHARACTERISTICS
Operating voltage VDD range as described in Section 28.1 “DC Characteristics”.
FIGURE 28-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSCO Load Condition 2 – for OSCO
VDD/2
RL Pin CL
VSS
CL
Pin RL = 464
CL = 50 pF for all pins except OSCO
VSS
15 pF for OSCO output
TABLE 28-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

Param
Symbol Characteristic Min Typ(1) Max Units Conditions
No.
DO50 COSC2 OSCO/CLKO Pin — — 15 pF In XT and HS modes when
external clock is used to drive
OSCI.
DO56 CIO All I/O Pins and OSCO — — 50 pF EC mode.
DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode.
and are not tested.

FIGURE 28-4: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
OSCI
OS20
OS30 OS30 OS31 OS31
OS25
CLKO
OS40 OS41
TABLE 28-16: EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.50 to 3.6V (unless otherwise stated)
AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial
Param
No.
OS10 FOSC External CLKI Frequency DC — 32 MHz EC, -40°C  TA  +85°C
(External clocks allowed 4 — 8 MHz ECPLL, -40°C  TA  +85°C
only in EC mode) DC — 24 MHz EC, -40°C  TA  +125°C
4 — 6 MHz ECPLL, -40°C  TA  +125°C
Oscillator Frequency 3 — 10 MHz XT
3 — 8 MHz XTPLL, -40°C  TA  +85°C
10 — 32 MHz HS, -40°C  TA  +85°C
31 — 33 kHz SOSC
3 — 6 MHz XTPLL, -40°C  TA  +125°C
10 — 24 MHz HS, -40°C  TA  +125°C
OS20 TOSC TOSC = 1/FOSC — — — — See parameter OS10
for FOSC value
OS25 TCY Instruction Cycle Time(2) 62.5 — DC ns
OS30 TosL, External Clock in (OSCI) 0.45 x TOSC — — ns EC
TosH High or Low Time
OS31 TosR, External Clock in (OSCI) — — 20 ns EC
TosF Rise or Fall Time
OS40 TckR CLKO Rise Time(3) — 6 10 ns
OS41 TckF CLKO Fall Time(3) — 6 10 ns
and are not tested.
2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “Min.”
values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the
“Max.” cycle time limit is “DC” (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for
the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).

TABLE 28-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V)
Param
Sym Characteristic(1) Min Typ(2) Max Units Conditions
No.
OS50 FPLLI PLL Input Frequency 3 — 8 MHz ECPLL, HSPLL, XTPLL
Range modes, -40°C  TA  +85°C
3 — 6 MHz ECPLL, HSPLL, XTPLL
modes, -40°C  TA  +125°C
OS51 FSYS PLL Output Frequency 8 — 32 MHz -40°C  TA  +85°C
Range 8 — 24 MHz -40°C  TA  +125°C
OS52 TLOCK PLL Start-up Time — — 2 ms
(Lock Time)
OS53 DCLK CLKO Stability (Jitter) -2 1 2 % Measured over 100 ms period
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 28-18: INTERNAL RC OSCILLATOR SPECIFICATIONS

Param
Sym Characteristic(1) Min Typ Max Units Conditions
No.
TFRC FRC Start-up Time — 15 — s
TLPRC LPRC Start-up Time — 500 — s
TABLE 28-19: INTERNAL RC OSCILLATOR ACCURACY

AC CHARACTERISTICS Operating temperature -40°C  TA +85°C for Industrial
Param
Characteristic Min Typ Max Units Conditions
No.
F20 FRC Accuracy @ 8 MHz(1,3) -1.25 +0.25 1.0 % -40°C  TA +85°C, 3.0V  VDD 3.6V
F21 LPRC Accuracy @ 31 kHz(2) -15 — 15 % -40°C  TA +85°C, 3.0V  VDD 3.6V
Note 1: Frequency calibrated at 25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift.
2: Change of LPRC frequency as VDD changes.
3: To achieve this accuracy, physical stress applied to the microcontroller package (ex: by flexing the PCB)
must be kept to a minimum.

FIGURE 28-5: CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin Old Value New Value

(Output)
DO31
DO32
Note: Refer to Figure 28-3 for load conditions.
TABLE 28-20: CLKO AND I/O TIMING REQUIREMENTS

Param
No.
DO31 TIOR Port Output Rise Time — 10 25 ns
DO32 TIOF Port Output Fall Time — 10 25 ns
DI35 TINP INTx pin High or Low 20 — — ns
Time (output)
DI40 TRBP CNx High or Low Time 2 — — TCY
(input)
TABLE 28-21: RESET, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Param
Symbol Characteristic Min. Typ(1) Max. Units Conditions
No.
SY10 TmcL MCLR Pulse Width (low) 2 — — s
SY11 TPWRT Power-up Timer Period — 64 — ms
SY12 TPOR Power-on Reset Delay — 2 — s
SY13 TIOZ I/O High-Impedance from MCLR — — 100 ns
Low or Watchdog Timer Reset
SY25 TBOR Brown-out Reset Pulse Width 1 — — s VDD VBOR
TRST Internal State Reset Time — 50 — s
TDSWU Wake-up from Deep Sleep Time — 200 — s Based on full discharge of
10 F capacitor on VCAP.
Includes TPOR and TRST.
TPM — 10 — s Sleep wake-up with PMSLP = 0
— 190 — s and WUTSEL<1:0> = 11

TABLE 28-22: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param
Symbol Characteristic Min. Typ Max. Units Conditions
No.
Device Supply
AD01 AVDD Module VDD Supply Greater of — Lesser of V
VDD – 0.3 VDD + 0.3
or 2.0 or 3.6
AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V
Reference Inputs
AD05 VREFH Reference Voltage High AVSS + 1.7 — AVDD V
AD06 VREFL Reference Voltage Low AVSS — AVDD – 1.7 V
AD07 VREF Absolute Reference AVSS – 0.3 — AVDD + 0.3 V
Voltage
AD08 IVREF Reference Voltage Input — — 1.25 mA (Note 3)
Current
AD09 ZVREF Reference Input — 10K —  (Note 4)
Impedance
Analog Input
AD10 VINH-VINL Full-Scale Input Span VREFL — VREFH V (Note 2)
AD11 VIN Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V
AD12 VINL Absolute VINL Input AVSS – 0.3 — AVDD/2 V
Voltage
AD13 — Leakage Current — ±0.001 ±0.610 A VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V,
Source Impedance = 2.5 k
AD17 RIN Recommended Impedance — — 2.5K  10-bit
of Analog Voltage Source
ADC Accuracy
AD20b NR Resolution — 10 — bits
AD21b INL Integral Nonlinearity — ±1 <±2 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD22b DNL Differential Nonlinearity — ±0.5 <±1.25 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD23b GERR Gain Error — ±1 ±3 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD24b EOFF Offset Error — ±1 ±2 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD25b — Monotonicity(1) — — — — Guaranteed
Note 1: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes.
2: Measurements taken with external VREF+ and VREF- are used as the ADC voltage reference.
3: External reference voltage is applied to the VREF+/- pins. IVREF is current during conversion at 3.3V, 25°C.
Parameter is for design guidance only and is not tested.
4: Impedance during sampling at 3.3V, 25°C. Parameter is for design guidance only and is not tested.

TABLE 28-23: ADC CONVERSION TIMING REQUIREMENTS(1)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C
Param
Symbol Characteristic Min. Typ Max. Units Conditions
No.
Clock Parameters
AD50 TAD ADC Clock Period 75 — — ns TCY = 75 ns, AD1CON3
in default state
AD51 tRC ADC Internal RC Oscillator — 250 — ns
Period
Conversion Rate
AD55 tCONV Conversion Time — 12 — TAD
AD56 FCNV Throughput Rate — — 500 ksps AVDD > 2.7V
AD57 tSAMP Sample Time — 1 — TAD
Clock Parameters
AD61 tPSS Sample Start Delay from setting 2 — 3 TAD
Sample bit (SAMP)
Note 1: Because the sample capacitors will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.

29.0 PACKAGING INFORMATION
29.1 Package Marking Information
Example
28-Lead QFN
24FJ32GA
XXXXXXXX
102/ML e3
XXXXXXXX
1010017
YYWWNNN
Example
28-Lead SOIC (.300”)
PIC24FJ32GA102/SO e3
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX 1010017
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
Example
28-Lead SPDIP
PIC24FJ32GA102
XXXXXXXXXXXXXXXXX -I/SP e3
XXXXXXXXXXXXXXXXX 1010017
YYWWNNN
28-Lead SSOP Example
XXXXXXXXXXXX PIC24FJ32GA
XXXXXXXXXXXX 102-I/SS e3
YYWWNNN 1010017
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

44-Lead QFN Example
XXXXXXXXXX 24FJ32GA
XXXXXXXXXX 104-I/ML e3
XXXXXXXXXX 1010017
YYWWNNN
44-Lead TQFP Example
XXXXXXXXXX 24FJ32GA
XXXXXXXXXX 104-I/PT e3
XXXXXXXXXX 1010017
YYWWNNN

29.2 Package Details
The following sections give the technical details of the packages.

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NOTES:

APPENDIX A: REVISION HISTORY
Revision A (August 2009)

Original data sheet for the PIC24FJ64GA104 family of
devices.
Revision B (October 2009)

Corrected Section 10.3 “Input Change Notification”
regarding the number of ICN inputs and the availability
of pull-downs.
Updated Section 10.4.2 “Available Peripherals” by
removing the Timer 1 clock input from Table 10-2.
Updated Section 28.1 “DC Characteristics” as
follows:
• Added new specifications to Tables 29-4 and 29-5
for IDD and IIDLE at 0.5 MIPS operation.
• Updated Table 29-4 with revised maximum IDD
specifications for 1 MIP and 4 MIPS.
• Renumbered the parameters for the delta IPD
current (32 kHz, SOSCEL = 11) from DC62n to
DC63n.
Revision C (August 2010)

This revision includes the following updates:
Pin Diagrams
• Updated Pin 7 and Pin 14 in 28-Pin SPDIP, SOIC.
• Updated the device name, Pin13 and Pin 23, in
28-Pin QFN.
Removed IEC5, IFS5 and IPC21 rows from Table 4-5.
Updated CLKDIV bit details in Table 4-23.
Removed JTAG from Flash programming list in
Section 5.0 “Flash Program Memory”.
Updated Section 10.4.5 “Considerations for
Peripheral Pin Selection” as follows:
• Replaced the code in Example 10-2.
• Added the new code as Example 10-3.
Updated shaded note in Section 20.0 “32-Bit Pro-
grammable Cyclic Redundancy Check (CRC)
Generator” and Section 22.0 “Triple Comparator
Module”.
Updated Section 28.1 “DC Characteristics” as
follows:
• Updated the device name in Table 28-1.
• Added the “125°C data” in
Table 28-4,Table 28-5,Table 28-6 and Table 28-7.
• Updated Min and Typ columns of DC16 in
Table 28-3.
• Added rows, AD08 and AD09, in Table 28-22.
• Added Figure 28-2.
Added the 28-pin SSOP package to Section 29.0
“Packaging Information”.

NOTES:

INDEX
A Partially Multiplexed Addressing Application
Example ........................................................... 199
A/D Converter
PIC24F CPU Core ...................................................... 26
Analog Input Model ................................................... 227
PIC24FJ64GA104 Family (General)........................... 12
Transfer Function...................................................... 228
PMP Module Overview ............................................. 191
AC Characteristics
PSV Operation............................................................ 50
ADC Specifications ................................................... 281
Reset System ............................................................. 59
Capacitive Loading Requirements on
RTCC........................................................................ 201
Output Pins ....................................................... 277
Shared I/O Port Structure ......................................... 121
CLKO and I/O Timing................................................ 280
SPI Master, Frame Master Connection .................... 173
Conversion Requirements ........................................ 282
SPI Master, Frame Slave Connection ...................... 173
External Clock Requirements ................................... 278
SPI Master/Slave Connection
Internal RC Oscillator Accuracy ................................ 279
(Enhanced Buffer Modes)................................. 172
Internal RC Oscillator Specifications......................... 279
SPI Master/Slave Connection (Standard Mode)....... 172
Load Conditions and Requirements for
SPI Slave, Frame Master Connection ...................... 173
Timing Specifications ....................................... 277
SPI Slave, Frame Slave Connection ........................ 173
PLL Clock Timing Specifications............................... 279
SPIx Module (Enhanced Mode)................................ 167
Reset, Power-up Timer and Brown-out
SPIx Module (Standard Mode) ................................. 166
Reset Timing..................................................... 280
System Clock............................................................ 101
Temperature and Voltage Specifications .................. 277
Triple Comparator Module........................................ 229
Alternate Interrupt Vector Table (AIVT) .............................. 65
UART (Simplified)..................................................... 183
Assembler
Watchdog Timer (WDT)............................................ 248
MPASM Assembler................................................... 252
B C
Block Diagrams C Compilers
10-Bit High-Speed A/D Converter............................. 220 MPLAB C18.............................................................. 252
Charge Time Measurement Unit. See CTMU.
16-Bit Asynchronous Timer3 and Timer5 ................. 147
16-Bit Synchronous Timer2 and Timer4 ................... 147 Code Examples
16-Bit Timer1 Module................................................ 143 Basic Sequence for Clock Switching ........................ 107
Configuring UART1 Input and Output
32-Bit Timer2/3 and Timer4/5 ................................... 146
8-Bit Multiplexed Address and Data Functions (PPS), ‘C’ ......................................... 128
Application Example ......................................... 200 Configuring UART1 Input and Output
Functions (PPS), Assembly.............................. 128
Accessing Program Memory Using
Table Instructions .............................................. 49 Erasing a Program Memory Block, ‘C’........................ 55
Addressable PSP Example....................................... 198 Erasing a Program Memory Block, Assembly ............ 54
I/O Port Write/Read .................................................. 122
Addressing for Table Registers................................... 51
CALL Stack Frame...................................................... 47 Initiating a Programming Sequence, ‘C’ ..................... 56
Initiating a Programming Sequence, Assembly.......... 56
Comparator Voltage Reference ................................ 233
Loading the Write Buffers, ‘C’..................................... 56
CPU Programmer’s Model .......................................... 27
CRC Module ............................................................. 213 Loading the Write Buffers, Assembly ......................... 55
CRC Shift Engine...................................................... 213 PWRSAV Instruction Syntax .................................... 111
Setting the RTCWREN Bit ........................................ 202
CTMU Connections and Internal Configuration
for Capacitance Measurement.......................... 235 Single-Word Flash Programming, ‘C’ ......................... 57
CTMU Typical Connections and Internal Single-Word Flash Programming, Assembly.............. 57
Code Protection ................................................................ 248
Configuration for Pulse Delay Generation ........ 236
Code Segment.......................................................... 249
CTMU Typical Connections and Internal
Code Segment Protection
Configuration for Time Measurement ............... 236
Configuration Options....................................... 249
Data Access From Program Space Address
Configuration Register.............................................. 249
Generation .......................................................... 48
General Segment ..................................................... 248
I2C Module ................................................................ 176
Comparator Voltage Reference ........................................ 233
Individual Comparator Configurations....................... 230
Input Capture ............................................................ 151 Configuring ............................................................... 233
Configuration Bits ............................................................. 239
LCD Control Example, Byte Mode ............................ 200
Legacy PSP Example ............................................... 198 Core Features....................................................................... 9
Master Mode, Demultiplexed Addressing ................. 198 CPU
Arithmetic Logic Unit (ALU) ........................................ 29
Master Mode, Fully Multiplexed Addressing ............. 199
Master Mode, Partially Multiplexed Addressing ........ 199 Control Registers........................................................ 28
Multiplexed Addressing Application Example ........... 199 Core Registers............................................................ 27
Programmer’s Model .................................................. 25
On-Chip Regulator Connections ............................... 246
Output Compare (16-Bit Mode)................................. 156
Parallel EEPROM Example, 16-Bit Data .................. 200
Parallel EEPROM Example, 8-Bit Data .................... 200

CRC F
Registers ................................................................... 215
Flash Configuration Words ................................. 32, 239–244
Typical Operation ...................................................... 215
Flash Program Memory ...................................................... 51
User Interface ........................................................... 214
and Table Instructions ................................................ 51
Data .................................................................. 214
Enhanced ICSP Operation ......................................... 52
Polynomial ........................................................ 214
JTAG Operation.......................................................... 52
CTMU
Programming Algorithm .............................................. 54
Measuring Capacitance ............................................ 235
RTSP Operation ......................................................... 52
Measuring Time ........................................................ 236
Single-Word Programming ......................................... 57
Pulse Generation and Delay ..................................... 236
Customer Change Notification Service ............................. 303 I
Customer Notification Service........................................... 303 I/O Ports
Customer Support ............................................................. 303 Analog Input Voltage Considerations ....................... 122
D Analog Port Pins Configuration................................. 122
Input Change Notification ......................................... 123
Data Memory
Open-Drain Configuration......................................... 122
Address Space............................................................ 33
Parallel (PIO) ............................................................ 121
Memory Map ............................................................... 33
Peripheral Pin Select ................................................ 123
Near Data Space ........................................................ 34
Pull-ups and Pull-Downs........................................... 123
SFR Space.................................................................. 34
I2C
Software Stack ............................................................ 47
Clock Rates .............................................................. 177
Space Organization and Alignment ............................ 34
Communicating as Master in a Single
DC Characteristics
Master Environment ......................................... 175
Comparator Specifications ........................................ 276
Reserved Addresses ................................................ 177
Comparator Voltage Reference Specifications ......... 276
Setting Baud Rate When Operating as
I/O Pin Input Specifications ....................................... 274
Bus Master ....................................................... 177
I/O Pin Output Specifications .................................... 275
Slave Address Masking ............................................ 177
Idle Current ............................................................... 269
Input Capture
Internal Voltage Regulator Specifications ................. 276
32-Bit Mode .............................................................. 152
Operating Current ..................................................... 267
Operations ................................................................ 152
Power-Down Base Current ....................................... 271
Synchronous and Trigger Modes.............................. 151
Power-Down Peripheral Module Current (IPD) .......... 272
Input Capture with Dedicated Timers ............................... 151
Program Memory ...................................................... 275
Instruction Based Power-Saving Modes........................... 111
Temperature and Voltage Specifications .................. 266
Deep Sleep ....................................................... 112, 119
Deep Sleep Watchdog Timer (DSWDT) ........................... 248
Idle ............................................................................ 112
Development Support ....................................................... 251
Sleep ........................................................................ 111
DISVREG Pin.................................................................... 246
Instruction Set
E Overview................................................................... 257
Summary .................................................................. 255
Electrical Characteristics
Symbols Used in Opcode Descriptions .................... 256
Absolute Maximum Ratings ...................................... 263
Inter-Integrated Circuit. See I2C. ...................................... 175
Thermal Operating Conditions .................................. 265
Internet Address ............................................................... 303
Thermal Packaging ................................................... 265
Interrupt Vector Table (IVT) ................................................ 65
V/F Graph (Extended Temperature) ......................... 264
Interrupts
V/F Graph (Industrial) ............................................... 264
Control and Status Registers...................................... 68
Equations
Implemented Vectors.................................................. 67
A/D Conversion Clock Period ................................... 227
Reset Sequence ......................................................... 65
Baud Rate Reload Calculation .................................. 177
Setup and Service Procedures ................................... 99
Calculating the PWM Period ..................................... 159
Trap Vectors ............................................................... 66
Calculation for Maximum PWM Resolution............... 159
Vector Table ............................................................... 66
Relationship Between Device and SPI
Clock Speed...................................................... 174 J
UART Baud Rate with BRGH = 0 ............................. 184 JTAG Interface.................................................................. 250
UART Baud Rate with BRGH = 1 ............................. 184
Errata .................................................................................... 8 M
Examples Microchip Internet Web Site.............................................. 303
Baud Rate Error Calculation (BRGH = 0) ................. 184 MPLAB ASM30 Assembler, Linker, Librarian ................... 252
MPLAB Integrated Development
Environment Software .............................................. 251
MPLAB PM3 Device Programmer .................................... 254
MPLAB REAL ICE In-Circuit Emulator System ................ 253
MPLINK Object Linker/MPLIB Object Librarian ................ 252

N NVM............................................................................ 46
Output Compare ......................................................... 40
Near Data Space ................................................................ 34
Pad Configuration....................................................... 43
O Parallel Master/Slave Port .......................................... 44
Oscillator Configuration Peripheral Pin Select .................................................. 45
Bit Values for Clock Selection................................... 102 PMD............................................................................ 46
Clock Switching......................................................... 106 PORTA ....................................................................... 42
Sequence.......................................................... 107 PORTB ....................................................................... 42
Control Registers ...................................................... 103 PORTC ....................................................................... 42
CPU Clocking Scheme ............................................. 102 RTCC.......................................................................... 44
Initial Configuration on POR ..................................... 102 SPI.............................................................................. 42
Reference Clock Output............................................ 108 System........................................................................ 46
Secondary Oscillator (SOSC) ................................... 108 Timers......................................................................... 38
Output Compare UART.......................................................................... 41
32-Bit Mode............................................................... 155 Registers
Operations ................................................................ 157 AD1CHS (A/D Input Select)...................................... 224
Subcycle Resolution ................................................. 160 AD1CON1 (A/D Control 1)........................................ 221
Synchronous and Trigger Modes.............................. 155 AD1CON2 (A/D Control 2)........................................ 222
Output Compare with Dedicated Timers ........................... 155 AD1CON3 (A/D Control 3)........................................ 223
AD1CSSL (A/D Input Scan Select)........................... 226
P AD1PCFG (A/D Port Configuration) ......................... 225
Packaging ......................................................................... 283 ALCFGRPT (Alarm Configuration) ........................... 205
Details ....................................................................... 285 ALMINSEC (Alarm Minutes and
Marking ..................................................................... 283 Seconds Value) ................................................ 209
Parallel Master Port. See PMP. ........................................ 191 ALMTHDY (Alarm Month and Day Value) ................ 208
Peripheral Module Disable Bits ......................................... 119 ALWDHR (Alarm Weekday and Hours Value) ......... 208
Peripheral Pin Select (PPS) .............................................. 123 CLKDIV (Clock Divider) ............................................ 105
Available Peripherals and Pins ................................. 123 CMSTAT (Comparator Module Status) .................... 232
Configuration Control Changes................................. 126 CMxCON (Comparator x Control) ............................ 231
Considerations for Use ............................................. 127 CORCON (CPU Control) ............................................ 29
Function Priority ........................................................ 123 CORCON (CPU Core Control) ................................... 69
Input Mapping ........................................................... 124 CRCCON1 (CRC Control 1) ..................................... 216
Output Mapping ........................................................ 125 CRCCON2 (CRC Control 2) ..................................... 217
Pinout Descriptions ............................................................. 13 CRCXORH (CRC XOR Polynomial, High Byte) ....... 218
Power-Saving Features .................................................... 111 CRCXORL (CRC XOR Polynomial, Low Byte)......... 217
Clock Frequency and Clock Switching...................... 111 CTMUCON (CTMU Control)..................................... 237
Product Identification System ........................................... 305 CTMUICON (CTMU Current Control) ....................... 238
Program Memory CVRCON (Comparator Voltage
Access Using Table Instructions................................. 49 Reference Control) ........................................... 234
Address Space............................................................ 31 CW1 (Flash Configuration Word 1) .......................... 240
Addressing Space....................................................... 47 CW2 (Flash Configuration Word 2) .......................... 242
Flash Configuration Words ......................................... 32 CW3 (Flash Configuration Word 3) .......................... 243
Memory Maps ............................................................. 31 DEVID (Device ID).................................................... 245
Organization................................................................ 32 DEVREV (Device Revision)...................................... 245
Program Space Visibility ............................................. 50 DSCON (Deep Sleep Control).................................. 117
Program Space Visibility (PSV) .......................................... 50 DSWAKE (Deep Sleep Wake-up Source) ................ 118
Program Verification ......................................................... 248 I2CxCON (I2Cx Control)........................................... 178
Pulse-Width Modulation (PWM) Mode .............................. 158 I2CxMSK (I2Cx Slave Mode Address Mask)............ 182
Pulse-Width Modulation. See PWM. I2CxSTAT (I2Cx Status) ........................................... 180
PWM ICxCON1 (Input Capture x Control 1)....................... 153
Duty Cycle and Period .............................................. 159 ICxCON2 (Input Capture x Control 2)....................... 154
IEC0 (Interrupt Enable Control 0) ............................... 77
R IEC1 (Interrupt Enable Control 1) ............................... 78
Reader Response ............................................................. 304 IEC2 (Interrupt Enable Control 2) ............................... 79
Register Maps IEC3 (Interrupt Enable Control 3) ............................... 80
A/D Converter ............................................................. 43 IEC4 (Interrupt Enable Control 4) ............................... 81
Comparators ............................................................... 45 IFS0 (Interrupt Flag Status 0) ..................................... 72
CPU Core.................................................................... 35 IFS1 (Interrupt Flag Status 1) ..................................... 73
CRC ............................................................................ 44 IFS2 (Interrupt Flag Status 2) ..................................... 74
CTMU.......................................................................... 43 IFS3 (Interrupt Flag Status 3) ..................................... 75
Deep Sleep ................................................................. 46 IFS4 (Interrupt Flag Status 4) ..................................... 76
I2C............................................................................... 41 INTCON1 (Interrupt Control 1) ................................... 70
ICN.............................................................................. 36 INTCON2 (Interrupt Control 2) ................................... 71
Input Capture .............................................................. 39 INTTREG (Interrupt Control and Status) .................... 98
Interrupt Controller ...................................................... 37 IPC0 (Interrupt Priority Control 0) ............................... 82

IPC1 (Interrupt Priority Control 1) ............................... 83 TxCON (Timer2 and Timer4 Control) ....................... 148
IPC10 (Interrupt Priority Control 10) ........................... 92 TyCON (Timer3 and Timer5 Control) ....................... 149
IPC11 (Interrupt Priority Control 11) ........................... 93 UxMODE (UARTx Mode).......................................... 186
IPC12 (Interrupt Priority Control 12) ........................... 94 UxSTA (UARTx Status and Control)......................... 188
IPC15 (Interrupt Priority Control 15) ........................... 95 WKDYHR (RTCC Weekday and Hours Value)......... 207
IPC16 (Interrupt Priority Control 16) ........................... 96 YEAR (RTCC Year Value)........................................ 206
IPC18 (Interrupt Priority Control 18) ........................... 97 Resets
IPC19 (Interrupt Priority Control 19) ........................... 97 BOR (Brown-out Reset).............................................. 59
IPC2 (Interrupt Priority Control 2) ............................... 84 Clock Source Selection............................................... 61
IPC3 (Interrupt Priority Control 3) ............................... 85 CM (Configuration Mismatch Reset)........................... 59
IPC4 (Interrupt Priority Control 4) ............................... 86 Deep Sleep BOR (DSBOR) ........................................ 63
IPC5 (Interrupt Priority Control 5) ............................... 87 Delay Times................................................................ 62
IPC6 (Interrupt Priority Control 6) ............................... 88 Device Times .............................................................. 61
IPC7 (Interrupt Priority Control 7) ............................... 89 IOPUWR (Illegal Opcode Reset) ................................ 59
IPC8 (Interrupt Priority Control 8) ............................... 90 MCLR (Pin Reset)....................................................... 59
IPC9 (Interrupt Priority Control 9) ............................... 91 POR (Power-on Reset)............................................... 59
MINSEC (RTCC Minutes and Seconds Value) ......... 207 RCON Flags Operation............................................... 61
MTHDY (RTCC Month and Day Value) .................... 206 SFR States ................................................................. 63
NVMCON (Flash Memory Control) ............................. 53 SWR (RESET Instruction) .......................................... 59
OCxCON1 (Output Compare x Control 1) ................ 161 TRAPR (Trap Conflict Reset) ..................................... 59
OCxCON2 (Output Compare x Control 2) ................ 163 UWR (Uninitialized W Register Reset) ....................... 59
OSCCON (Oscillator Control) ................................... 103 WDT (Watchdog Timer Reset) ................................... 59
OSCTUN (FRC Oscillator Tune) ............................... 106 Revision History................................................................ 297
PADCFG1 (Pad Configuration Control) ............ 197, 204 RTCC
PMADDR (Parallel Port Address) ............................. 195 Alarm Configuration .................................................. 210
PMAEN (Parallel Port Enable) .................................. 195 Alarm Mask Settings (figure) .................................... 211
PMCON (Parallel Port Control) ................................. 192 Calibration ................................................................ 210
PMMODE (Parallel Port Mode) ................................. 194 Clock Source Selection............................................. 202
PMSTAT (Parallel Port Status) ................................. 196 Register Mapping...................................................... 202
RCFGCAL (RTCC Calibration and Source Clock ............................................................ 201
Configuration) ................................................... 203 Write Lock................................................................. 202
RCON (Reset Control) ................................................ 60
REFOCON (Reference Oscillator Control)................ 109 S
RPINR0 (Peripheral Pin Select Input 0) .................... 129 Selective Peripheral Control ............................................. 119
RPINR1 (Peripheral Pin Select Input 1) .................... 129 Serial Peripheral Interface. See SPI.
RPINR11 (Peripheral Pin Select Input 11) ................ 132 SFR Space ......................................................................... 34
RPINR18 (Peripheral Pin Select Input 18) ................ 133 Software Simulator (MPLAB SIM) .................................... 253
RPINR19 (Peripheral Pin Select Input 19) ................ 133 Software Stack.................................................................... 47
RPINR20 (Peripheral Pin Select Input 20) ................ 134 Special Features................................................................. 10
RPINR21 (Peripheral Pin Select Input 21) ................ 134 SPI
RPINR22 (Peripheral Pin Select Input 22) ................ 135
RPINR23 (Peripheral Pin Select Input 23) ................ 135
T
RPINR3 (Peripheral Pin Select Input 3) .................... 130 Timer1............................................................................... 143
RPINR4 (Peripheral Pin Select Input 4) .................... 130 Timer2/3 and Timer4/5 ..................................................... 145
RPINR7 (Peripheral Pin Select Input 7) .................... 131 Timing Diagrams
RPINR8 (Peripheral Pin Select Input 8) .................... 131 CLKO and I/O Characteristics .................................. 280
RPINR9 (Peripheral Pin Select Input 9) .................... 132 External Clock........................................................... 278
RPOR0 (Peripheral Pin Select Output 0) .................. 136 Triple Comparator............................................................. 229
RPOR1 (Peripheral Pin Select Output 1) .................. 136
U
RPOR10 (Peripheral Pin Select Output 10) .............. 141
RPOR11 (Peripheral Pin Select Output 11) .............. 141 UART ................................................................................ 183
RPOR12 (Peripheral Pin Select Output 12) .............. 142 Baud Rate Generator (BRG) .................................... 184
RPOR2 (Peripheral Pin Select Output 2) .................. 137 IrDA Support ............................................................. 185
RPOR3 (Peripheral Pin Select Output 3) .................. 137 Operation of UxCTS and UxRTS Pins...................... 185
RPOR4 (Peripheral Pin Select Output 4) .................. 138 Receiving
RPOR5 (Peripheral Pin Select Output 5) .................. 138 8-Bit or 9-Bit Data Mode ................................... 185
RPOR6 (Peripheral Pin Select Output 6) .................. 139 Transmitting
RPOR7 (Peripheral Pin Select Output 7) .................. 139 8-Bit Data Mode................................................ 185
RPOR8 (Peripheral Pin Select Output 8) .................. 140 9-Bit Data Mode................................................ 185
RPOR9 (Peripheral Pin Select Output 9) .................. 140 Break and Sync Sequence ............................... 185
SPIxCON1 (SPIx Control 1) ...................................... 170 Universal Asynchronous Receiver Transmitter. See UART.
SPIxCON2 (SPIx Control 2) ...................................... 171
SPIxSTAT (SPIx Status and Control) ....................... 168
SR (ALU STATUS) ............................................... 28, 69
T1CON (Timer1 Control)........................................... 144

V W
VDDCORE/VCAP Pin............................................................ 246 Watchdog Timer (WDT).................................................... 247
Voltage Regulator (On-Chip) ............................................ 246 Control Register........................................................ 248
and BOR ................................................................... 247 Windowed Operation ................................................ 248
and POR ................................................................... 246 WWW Address ................................................................. 303
Power-up Requirements ........................................... 247 WWW, On-Line Support ....................................................... 8
Standby Mode........................................................... 247
Tracking Mode .......................................................... 246

NOTES:

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It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
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Device: PIC24FJ64GA104 Family Literature Number: DS39951C
Questions:
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PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PIC 24 FJ 64 GA1 04 T - I / PT - XXX Examples:

a) PIC24FJ64GA104-I/PT:
Microchip Trademark PIC24F device with, 64-Kbyte program
memory, 44-pin, Industrial temp.,
Architecture TQFP package.
Flash Memory Family b) PIC24FJ32GA102-I/ML:
PIC24F device with32-Kbyte program memory,
Program Memory Size (KB) 28-pin, Industrial temp.,QFN package.
Product Group
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Architecture 24 = 16-bit modified Harvard without DSP
Flash Memory Family FJ = Flash program memory
Product Group GA1 = General purpose microcontrollers
Pin Count 02 = 28-pin

04 = 44-pin
Temperature Range I = -40C to +85C (Industrial)

E = -40C to +125C (Extended)
Package ML = 28-lead (6x6 mm) or 44-lead (8x8 mm) QFN

(Quad Flat)
PT = 44-lead (10x10x1 mm) TQFP (Thin Quad Flatpack)
SO = 28-lead (7.50 mm wide) SOIC (Small Outline)
SP = 28-lead (300 mil) SPDIP (Skinny Plastic Dual In-Line)
SS = 28-lead (530 mm) SSOP (Plastic Shrink Small)
Pattern Three-digit QTP, SQTP, Code or Special Requirements

(blank otherwise)
ES = Engineering Sample

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07/15/10

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PIC24FJ64GA104 Family

 2010 Microchip Technology Inc. DS39951C

Information contained in this publication regarding device Trademarks

DS39951C-page 2  2010 Microchip Technology Inc.

Special Microcontroller Features:

 2010 Microchip Technology Inc. DS39951C-page 3

28-Pin SPDIP, SOIC, SSOP(1)

Legend: RPn represents remappable peripheral pins.

DS39951C-page 4  2010 Microchip Technology Inc.

Legend: RPn represents remappable peripheral pins.

 2010 Microchip Technology Inc. DS39951C-page 5

Legend: RPn represents remappable peripheral pins.

DS39951C-page 6  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. DS39951C-page 7

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

DS39951C-page 8  2010 Microchip Technology Inc.

1.1 Core Features 1.1.3 OSCILLATOR OPTIONS AND

 2010 Microchip Technology Inc. DS39951C-page 9

DS39951C-page 10  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. DS39951C-page 11

Interrupt Data Bus

PSV & Table Data Latch

Address Latch Read AGU

VDDCORE/VCAP VDD, VSS MCLR

IC PWM/OC SPI I2C UART

DS39951C-page 12  2010 Microchip Technology Inc.

28-Pin 44-Pin Input

AN0 2 27 19 I ANA A/D Analog Inputs.

 2010 Microchip Technology Inc. DS39951C-page 13

28-Pin 44-Pin Input

CN0 12 9 34 I ST Interrupt-on-Change Inputs.

DS39951C-page 14  2010 Microchip Technology Inc.

28-Pin 44-Pin Input

INT0 16 13 43 I ST External Interrupt Input.

 2010 Microchip Technology Inc. DS39951C-page 15

28-Pin 44-Pin Input

RA0 2 27 19 I/O ST PORTA Digital I/O.

DS39951C-page 16  2010 Microchip Technology Inc.

28-Pin 44-Pin Input

RP0 4 1 21 I/O ST Remappable Peripheral (input or output).

 2010 Microchip Technology Inc. DS39951C-page 17

28-Pin 44-Pin Input

VCAP 20 17 7 P — External Filter Capacitor Connection (regulator enabled).

DS39951C-page 18  2010 Microchip Technology Inc.

Getting started with the PIC24FJ64GA104 family of

 2010 Microchip Technology Inc. DS39951C-page 19

DS39951C-page 20  2010 Microchip Technology Inc.

supply voltage or to ground. The particular connection

 2010 Microchip Technology Inc. DS39951C-page 21

DS39951C-page 22  2010 Microchip Technology Inc.

2.8 Unused I/Os

 2010 Microchip Technology Inc. DS39951C-page 23

DS39951C-page 24  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. DS39951C-page 25

PSV & Table

Address Bus EA MUX

Data Latch ROM Latch