Pic18f45k80 PDF
Pic18f45k80 PDF
Pic18f45k80 PDF
Data Sheet
28/40/44/64-Pin, Enhanced Flash
Microcontrollers, with ECAN
and nanoWatt XLP Technology
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
ISBN: 978-1-60932-851-1
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Companys quality system processes and procedures
are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchips quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
BORMV/LVD
8-Bit/16-Bit
12-Bit A/D
Channels
EUSART
ECAN
Timers
Data
CTMU
MSSP
ECCP
CCP/
DSM
Program Data EE
Device Memory Pins I/O
Memory (Bytes)
(Bytes)
28-Pin QFN(1)
RB4/AN9/C2INA/ECCP1/P1A/CTPLS/KBI0
RB5/T0CKI/T3CKI/CCP5/KBI1
RB7/PGD/T3G/RX2/DT2/KBI3
RA0/CVREF/AN0/ULPWU
RB6/PGC/TX2/CK2/KBI2
MCLR/RE3
RA1/AN1
28
27
25
22
26
24
23
RA2/VREF-/AN2 1 21 RB3/CANRX/C2OUT/P1D/CTED2/INT3
RA3/VREF+/AN3 2 20 RB2/CANTX/C1OUT/P1C/CTED1/INT2
VDDCORE/VCAP 3 PIC18F2XK80 19 RB1/AN8/C1INB/P1B/CTDIN/INT1
RA5/AN4/C2INB/HLVDIN/T1CKI/SS/CTMUI 4 18 RB0/AN10/C1INA/FLT0/INT0
PIC18LF2XK80
VSS 5 17 VDD
OSC1/CLKIN/RA7 6 16 VSS
OSC2/CLKOUT/RA6 7 15 RC7/CANRX/RX1/DT1/CCP4
14
10
11
12
13
8
9
RC4/SDA/SDI
RC5/SDO
RC0/SOSCO/SCLKI
RC6/CANTX/TX1/CK1/CCP3
RC1/SOSCI
RC3/REFO/SCL/SCK
RC2/T1G/CCP2
Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS.
28-Pin SSOP/SPDIP/SOIC
MCLR/RE3 1 28 RB7/PGD/T3G/RX2/DT2/KBI3
RA0/CVREF/AN0/ULPWU 2 27 RB6/PGC/TX2/CK2/KBI2
RA1/AN1 3 26 RB5/T0CKI/T3CKI/CCP5/KBI1
RA2/VREF-/AN2 4 25 RB4/AN9/C2INA/ECCP1/P1A/CTPLS/KBI0
RA3/VREF+/AN3 5 24 RB3/CANRX/C2OUT/P1D/CTED2/INT3
VDDCORE/VCAP 6 23 RB2/CANTX/C1OUT/P1C/CTED1/INT2
RA5/AN4/C2INB/HLVDIN/T1CKI/SS/CTMUI 7
PIC18F2XK80 22 RB1/AN8/C1INB/P1B/CTDIN/INT1
VSS 8 PIC18LF2XK80 21 RB0/AN10/C1INA/FLT0/INT0
OSC1/CLKIN/RA7 9 20 VDD
OSC2/CLKOUT/RA6 10 19 VSS
RC0/SOSCO/SCLKI 11 18 RC7/CANRX/RX1/DT1/CCP4
RC1/ISOSCI 12 17 RC6/CANTX/TX1/CK1/CCP3
RC2/T1G/CCP2 13 16 RC5/SDO
RC3/REFO/SCL/SCK 14 15 RC4/SDA/SDI
40-Pin PDIP
MCLR/RE3 1 40 RB7/PGD/T3G/KBI3
RA0/CVREF/AN0/ULPWU 2 39 RB6/PGC/KBI2
RA1/AN1/C1INC 3 38 RB5/T0CKI/T3CKI/CCP5/KBI1
RA2/VREF-/AN2/C2INC 4 37 RB4/AN9/CTPLS/KBI0
RA3/VREF+/AN3 5 36 RB3/CANRX/CTED2/INT3
VDDCORE/VCAP 6 35 RB2/CANTX/CTED1/INT2
RA5/AN4/HLVDIN/T1CKI/SS 7 34 RB1/AN8/CTDIN/INT1
RE0/AN5/RD 8 33 RB0/AN10/FLT0/INT0
RE1/AN6/C1OUT/WR 9 32 VDD
RE2/AN7/C2OUT/CS 10 PIC18F4XK80 31 VSS
VDD 11 PIC18LF4XK80 30 RD7/RX2/DT2/P1D/PSP7
VSS 12 29 RD6/TX2/CK2/P1C/PSP6
OSC1/CLKIN/RA7 13 28 RD5/P1B/PSP5
OSC2/CLKOUT/RA6 14 27 RD4/ECCP1/P1A/PSP4
RC0/SOSCO/SCLKI 15 26 RC7/CANRX/RX1/DT1/CCP4
RC1/SOSCI 16 25 RC6/CANTX/TX1/CK1/CCP3
RC2/T1G/CCP2 17 24 RC5/SDO
RC3/REFO/SCL/SCK 18 23 RC4/SDA/SDI
RD0/C1INA/PSP0 19 22 RD3/C2INB/CTMUI/PSP3
RD1/C1INB/PSP1 20 21 RD2/C2INA/PSP2
44-Pin TQFP
RC6/CANTX/TX1/CK1/CCP3
RD3/C2INB/CTMUI/PSP3
RC3/REFO/SCL/SCK
RD2/C2INA/PSP2
RD1/C1INB/PSP1
RD0/C1INA/PSP0
RC2/T1G/CCP2
RC4/SDA/SDI
RC1/SOSCI
RC5/SDO
N/C
38
44
43
42
41
36
35
34
37
39
40
RC7/CANRX/RX1/DT1/CCP4 1 33 N/C
RD4/ECCP1/P1A/PSP4 2 32 RC0/SOSCO/SCLKI
RD5/P1B/PSP5 3 31 OSC2/CLKOUT/RA6
RD6/TX2/CK2/P1C/PSP6 4 30 OSC1/CLKIN/RA7
RD7/RX2/DT2/P1D/PSP7 5 PIC18F4XK80 VSS
29
VSS 6 PIC18LF4XK80 28 VDD
VDD 7 27 RE2/AN7/C2OUT/CS
RB0/AN10/FLT0/INT0 8 26 RE1/AN6/C1OUT/WR
RB1/AN8/CTDIN/INT1 9 25 RE0/AN5/RD
RB2/CANTX/CTED1/INT2 10 24 RA5/AN4/HLVDIN/T1CKI/SS
RB3/CANRX/CTED2/INT3 11 23 VDDCORE/VCAP
18
12
13
14
15
20
21
22
19
17
16
RA3/VREF+/AN3
N/C
N/C
RA0/CVREF/AN0/ULPWU
RA1/AN1/C1INC
RA2/VREF-/AN2/C2INC
RB5/T0CKI/T3CKI/CCP5/KBI1
RB4/AN9/CTPLS/KBI0
MCLR/RE3
RB6/PGC/KBI2
RB7/PGD/T3G/KBI3
44-Pin QFN(1)
RC6/CANTX/TX1/CK1/CCP3
RD3/C2INB/CTMUI/PSP3
RC3/REFO/SCL/SCK
RD2/C2INA/PSP2
RD1/C1INB/PSP1
RD0/C1INA/PSP0
RC2/T1G/CCP2
RC4/SDA/SDI
RC1/SOSCI
RC5/SDO
N/C
38
44
43
42
41
36
35
34
37
39
RC7/CANRX/RX1/DT1/CCP4 1 40 33 N/C
RD4/ECCP1/P1A/PSP4 2 32 RC0/SOSCO/SCLKI
RD5/P1B/PSP5 3 31 OSC2/CLKOUT/RA6
RD6/TX2/CK2/P1C/PSP6 4 30 OSC1/CLKIN/RA7
RD7/RX2/DT2/P1D/PSP7 5 PIC18F4XK80 VSS
29
VSS 6 PIC18LF4XK80 28 VDD
VDD 7 27 RE2/AN7/C2OUT/CS
RB0/AN10/FLT0/INT0 8 26 RE1/AN6/C1OUT/WR
RB1/AN8/CTDIN/INT1 9 25 RE0/AN5/RD
RB2/CANTX/CTED1/INT2 10 24 RA5/AN4/HLVDIN/T1CKI/SS
RB3/CANRX/CTED2/INT3 11 23 VDDCORE/VCAP
18
12
13
14
15
20
21
22
19
17
16
RA3/VREF+/AN3
N/C
N/C
RA0/CVREF/AN0/ULPWU
RA1/AN1/C1INC
RA2/VREF-/AN2/C2INC
RB5/T0CKI/T3CKI/CCP5/KBI1
RB4/AN9/CTPLS/KBI0
MCLR/RE3
RB6/PGC/KBI2
RB7/PGD/T3G/KBI3
Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS.
64-Pin QFN(1)/TQFP
RD3/C2INB/CTMUI/PSP3
RC3/REFO/SCL/SCK
RD2/C2INA/PSP2
RD1/C1INB/PSP1
RD0/C1INA/PSP0
RC2/T1G/CCP2
RE6/RX2/DT2
RE7/TX2/CK2
RC4/SDA/SDI
RF6/MDOUT
RC1/SOSCI
RC6/CCP3
RC5/SDO
RF7
VDD
VSS
58
53
64
63
62
61
56
55
54
51
50
49
59
57
52
60
48 RC0/SOSCO/SCLKI
RC7/CCP4 1 47 OSC2/CLKOUT/RA6
RD4/ECCP1/P1A/PSP4 2
46 OSC1/CLKIN/RA7
RD5/P1B/PSP5 3
45 RF5
RD6/P1C/PSP6 4
44 RF4/MDCIN2
RD7/P1D/PSP7 5
43 VSS
RG0/RX1/DT1 6
42 AVSS
RG1/CANTX2 7
PIC18F6XK80 41 VDD
VSS 8
40 AVDD
AVDD 9 PIC18LF6XK80
39 RE2/AN7/C2OUT/CS
VDD 10
38 RE1/AN6/C1OUT/WR
RG2/T3CKI 11
37 RE0/AN5/RD
RG3/TX1/CK1 12
RB0/AN10/FLT0/INT0 13 36 RF3
RB1/AN8/CTDIN/INT1 14 35 RF2/MDCIN1
RB2/CANTX/CTED1/INT2 15 34 RA5/AN4/HLVDIN/T1CKI/SS
RB3/CANRX/CTED2/INT3 16 33 VDDCORE/VCAP
17
19
20
21
23
25
26
27
28
30
31
32
18
22
24
29
RG4/T0CKI
RF0/MDMIN
RA1/AN1/C1INC
RA2/VREF-/AN2/C2INC
VSS
RF1
VDD
RA3/VREF+/AN3
RB5/T0CKI/T3CKI/CCP5/KBI1
RE4/CANRX
RB4/AN9/CTPLS/KBI0
MCLR/RE3
RA0/CVREF/AN0/ULPWU
RB7/PGD/T3G/KBI3
RB6/PGC/KBI2
RE5/CANTX
Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
20 Address Latch
PCU PCH PCL
Program Counter 12 PORTB
Data Address<12>
RB0:RB7(1)
31-Level Stack
Address Latch 4 12 4
BSR FSR0 Access
Program Memory STKPTR Bank
FSR1
FSR2 12
Data Latch PORTC
inc/dec RC0:RC7(1)
8 logic
Table Latch
8
Instruction State Machine
Decode and Control Signals
Control
PRODH PRODL
8 x 8 Multiply
Timing 3
Power-up 8
OSC2/CLKO Generation
OSC1/CLKI Timer
BITOP W
INTOSC Oscillator 8
8 8
Oscillator Start-up Timer
16 MHz
Oscillator Power-on 8 8
Reset
Precision ALU<8>
Band Gap Watchdog
Reference Timer
8
BOR and
Voltage LVD
Regulator
20 Address Latch
PCU PCH PCL
Program Counter 12 PORTB
Data Address<12>
RB0:RB7(1)
31-Level Stack
Address Latch 4 12 4
BSR FSR0 Access
Program Memory STKPTR Bank
FSR1
FSR2 12
Data Latch PORTC
inc/dec RC0:RC7(1)
8 logic
Table Latch
8
Instruction State Machine
Decode and Control Signals
Control
PRODH PRODL PORTE
RE0:RE3(1,3)
8 x 8 Multiply
Timing 3
Power-up 8
OSC2/CLKO Generation
OSC1/CLKI Timer
BITOP W
INTOSC Oscillator 8
8 8
Oscillator Start-up Timer
16 MHz
Oscillator Power-on 8 8
Reset
Precision ALU<8>
Band Gap Watchdog
Reference Timer
8
BOR and
Voltage LVD
Regulator
CCP
2/3/4/5 ECCP1 EUSART1 EUSART2 MSSP ECAN PSP
Data Bus<8>
Table Pointer<21>
PORTA
Data Latch
inc/dec logic 8 8 RA0:RA3
Data Memory RA5:RA7(1,2)
(2/4 Kbytes)
21 PCLATU PCLATH
20 Address Latch
PCU PCH PCL
Program Counter 12 PORTB
Data Address<12>
RB0:RB7(1)
31-Level Stack
Address Latch 4 12 4
BSR FSR0 Access
Program Memory STKPTR Bank
FSR1
FSR2 12
Data Latch PORTC
inc/dec RC0:RC7(1)
8 logic
Table Latch
8
Instruction State Machine
Decode and Control Signals
Control
PRODH PRODL PORTE
RE0:RE7(1,3)
8 x 8 Multiply
Timing 3
Power-up 8
OSC2/CLKO Generation
OSC1/CLKI Timer
BITOP W
INTOSC Oscillator 8 8
Oscillator 8
Start-up Timer
16 MHz PORTF
Oscillator Power-on 8 8
Reset RF0:RF7(1)
Precision ALU<8>
Band Gap Watchdog
Reference Timer
8
BOR and
Voltage LVD
Regulator
PORTG
RG0:RG4(1)
VDDCORE/VCAP VDD, VSS MCLR
MCLR/RE3 1 18
MCLR I ST Master Clear (input) or programming voltage (input).This
pin is an active-low Reset to the device.
RE3 I ST General purpose, input only pin.
OSC1/CLKIN/RA7 13 30
OSC1 I ST Oscillator crystal input.
CLKIN I CMOS External clock source input. Always associated with pin
function, OSC1. (See related OSC1/CLKI, OSC2/CLKO
pins.
RA7 I/O ST/ General purpose I/O pin.
CMOS
OSC2/CLKOUT/RA6 14 31
OSC2 O Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode.
CLKOUT O In certain oscillator modes, OSC2 pin outputs CLKO, which
has 1/4 the frequency of OSC1 and denotes the instruction
cycle rate.
RA6 I/O ST/ General purpose I/O pin.
CMOS
Legend: I2C = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power
MCLR/RE3 28
MCLR I ST Master Clear (input) or programming voltage (input).This pin is an
active-low Reset to the device.
RE3 I ST General purpose, input only pin.
OSC1/CLKIN/RA7 46
OSC1 I ST Oscillator crystal input.
CLKIN I CMOS External clock source input. Always associated with pin function,
OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.)
RA7 I/O ST/ General purpose I/O pin.
CMOS
OSC2/CLKOUT/RA6 47
OSC2 O Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode.
CLKOUT O In certain oscillator modes, OSC2 pin outputs CLKO, which has 1/4
the frequency of OSC1 and denotes the instruction cycle rate.
RA6 I/O ST/ General purpose I/O pin.
CMOS
Legend: I2C = I2C/SMBus input buffer CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power
VDD
VSS
R1
8-bit microcontrollers requires attention to a minimal R2
set of device pin connections before proceeding with MCLR
development. VCAP/VDDCORE
C1
The following pins must always be connected: C7(1)
PIC18FXXKXX
All VDD and VSS pins
VDD
(see Section 2.2 Power Supply Pins) VSS
C6(1) C3(1)
All AVDD and AVSS pins, regardless of whether or VSS
VDD
not the analog device features are used
AVDD
AVSS
VDD
VSS
(see Section 2.2 Power Supply Pins)
MCLR pin
(see Section 2.3 Master Clear (MCLR) Pin)
C5(1) C4(1)
These pins must also be connected if they are being
used in the end application:
PGC/PGD pins used for In-Circuit Serial Key (all values are recommendations):
Programming (ICSP) and debugging purposes C1 through C6: 0.1 F, 20V ceramic
(see Section 2.5 ICSP Pins) R1: 10 k
OSCI and OSCO pins when an external oscillator R2: 100 to 470
source is used
Note 1: The example shown is for a PIC18F device
(see Section 2.6 External Oscillator Pins) with five VDD/VSS and AVDD/AVSS pairs.
Additionally, the following pins may be required: Other devices may have more or less pairs;
adjust the number of decoupling capacitors
VREF+/VREF- pins are used when external voltage appropriately.
reference for analog modules is implemented
Note: The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
The minimum mandatory connections are shown in
Figure 2-1.
ESR ()
tantalum. Suitable examples of capacitors are shown in 0.1
When the regulator is disabled, a 0.1F capacitor Note: Typical data measurement at 25C, 0V DC bias.
should be connected from the VCAP/VDDCORE pin to
ground. This capacitors characteristics must be similar
to those of the decoupling capacitors explained in 2.5 ICSP Pins
Section 2.2.1. For details on the VDD requirement,
when the regulator is disabled, see Parameter D001 in The PGC and PGD pins are used for In-Circuit Serial
Section 31.0 Electrical Characteristics. Programming (ICSP) and debugging purposes. It
Some PIC18FXXKXX families or some devices within is recommended to keep the trace length between the
a family do not provide the option of enabling or ICSP connector and the ICSP pins on the device as
disabling the on-chip voltage regulator: short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recom-
The PIC18LFXXKXX devices permanently mended, with the value in the range of a few tens of
disable the voltage regulator. ohms, not to exceed 100.
These devices require a 0.1F capacitor on the Pull-up resistors, series diodes, and capacitors on the
VCAP/VDDCORE pin. The VDD level of these PGC and PGD pins are not recommended as they will
devices must comply with the voltage regulator interfere with the programmer/debugger communica-
disabled specification for Parameter D001, in tions to the device. If such discrete components are an
Section 31.0 Electrical Characteristics. application requirement, they should be removed from
PIC18FXXKXX devices permanently enable the the circuit during programming and debugging. Alter-
voltage regulator. natively, refer to the AC/DC characteristics and timing
requirements information in the respective device
These devices require a 10 F capacitor on the
Flash programming specification for information on
VCAP/VDDCORE pin.
capacitive loading limits, and pin input voltage high
For details on all members of the PIC18F66K80 family, (VIH) and input low (VIL) requirements.
see Section 28.3 On-Chip Voltage Regulator.
For device emulation, ensure that the Communication
Channel Select (i.e., PGCx/PGDx pins) programmed
into the device matches the physical connections for
the ICSP to the Microchip debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 30.0 Development Support.
2.6 External Oscillator Pins MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
Many microcontrollers have options for at least two board, avoid any traces on the other side of the board
oscillators: a high-frequency primary oscillator and a where the crystal is placed.
low-frequency secondary oscillator (refer to
Section 3.0 Oscillator Configurations for details). Layout suggestions are shown in Figure 2-4. In-line
packages may be handled with a single-sided layout
The oscillator circuit should be placed on the same that completely encompasses the oscillator pins. With
side of the board as the device. Place the oscillator fine-pitch packages, it is not always possible to com-
circuit close to the respective oscillator pins with no pletely surround the pins and components. A suitable
more than 0.5 inch (12 mm) between the circuit solution is to tie the broken guard sections to a mirrored
components and the pins. The load capacitors should ground layer. In all cases, the guard trace(s) must be
be placed next to the oscillator itself, on the same side returned to ground.
of the board.
Use a grounded copper pour around the oscillator cir-
cuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
For additional information and design guidance on Copper Pour Primary Oscillator
oscillator circuits, please refer to these Microchip (tied to ground) Crystal
T1OSO
2.7 Unused I/Os
T1OS I
Timer1 Oscillator
Unused I/O pins should be configured as outputs and Crystal
driven to a logic low state. Alternatively, connect a 1 k `
to 10 k resistor to VSS on unused pins and drive the
output to logic low.
T1 Oscillator: C1 T1 Oscillator: C2
Bottom Layer
Copper Pour
(tied to ground)
OSCO
C2
Oscillator
GND Crystal
C1
OSCI
DEVICE PINS
SOSCO
SOSCI
4x PLL Peripherals
MUX
MUX
OSC2
MUX
CPU
OSC1 PLLEN
FOSC<3:0> and PLLCFG
IDLEN
101
HF-INTOSC 2 MHz 2 MHz
MUX
100 FOSC<3:0>
16 MHz to 1 MHz 1 MHz
011
31 kHz 500 kHz 500 kHz
010
250 kHz 250 kHz
001
31 kHz 31 kHz
000
MUX
500 kHz
Postscaler
IRCF<2:0>
MF-INTOSC 250 kHz
MUX
500 kHz to
31 kHz
31 kHz
INTSRC
MFIOSEL
LF-INTOSC 31 kHz
31 kHz
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: Reset state depends on the state of the IESO Configuration bit (CONFIG1H<7>).
2: Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing
the device clocks.
3: Source selected by the INTSRC bit (OSCTUNE<7>).
4: Modifying these bits will cause an immediate clock source switch.
5: INTSRC = OSCTUNE<7> and MFIOSEL = OSCCON2<0>.
6: Lowest power option for an internal source.
Note 1: Reset state depends on the state of the IESO Configuration bit (CONFIG1H<7>).
2: Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing
the device clocks.
3: Source selected by the INTSRC bit (OSCTUNE<7>).
4: Modifying these bits will cause an immediate clock source switch.
5: INTSRC = OSCTUNE<7> and MFIOSEL = OSCCON2<0>.
6: Lowest power option for an internal source.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
OSC2 Sleep
Note 1: See Table 3-2 and Table 3-3 for initial values of
C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the oscillator mode chosen.
MUX
CONFIGURATION)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: For ROSEL (REFOCON<4>), the primary oscillator is available only when configured as the default via the
FOSC settings. This is regardless of whether the device is in Sleep mode.
These categories define which portions of the device 4.1.2 ENTERING POWER-MANAGED
are clocked, and sometimes, at what speed. The Run MODES
and Idle modes may use any of the three available
clock sources (primary, secondary or internal oscillator Switching from one power-managed mode to another
block). The Sleep mode does not use a clock source. begins by loading the OSCCON register. The
SCS<1:0> bits select the clock source and determine
The ULPWU mode, on the RA0 pin, enables a slow fall- which Run or Idle mode is used. Changing these bits
ing voltage to generate a wake-up, even from Sleep, causes an immediate switch to the new clock source,
without excess current consumption. (See Section 4.7 assuming that it is running. The switch may also be
Ultra Low-Power Wake-up.) subject to clock transition delays. These considerations
The power-managed modes include several power- are discussed in Section 4.1.3 Clock Transitions
saving features offered on previous PIC devices. One and Status Indicators and subsequent sections.
is the clock switching feature, offered in other PIC18 Entering the power-managed Idle or Sleep modes is
devices. This feature allows the controller to use the triggered by the execution of a SLEEP instruction. The
SOSC oscillator instead of the primary one. Another actual mode that results depends on the status of the
power-saving feature is Sleep mode, offered by all PIC IDLEN bit.
devices, where all device clocks are stopped.
Depending on the current and impending mode, a
change to a power-managed mode does not always
4.1 Selecting Power-Managed Modes
require setting all of the previously discussed bits. Many
Selecting a power-managed mode requires two transitions can be done by changing the oscillator select
decisions: bits, or changing the IDLEN bit, prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured as
Will the CPU be clocked or not
desired, it may only be necessary to perform a SLEEP
What will be the clock source instruction to switch to the desired mode.
SOSCI 1 2 3 n-1 n
CPU
Clock
Peripheral
Clock
Program
Counter PC PC + 2 PC + 4
FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
SOSC
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock
Transition(2)
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4
Counter
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
4.2.3 RC_RUN MODE This mode is entered by setting the SCS1 bit to 1. To
maintain software compatibility with future devices, it is
In RC_RUN mode, the CPU and peripherals are
recommended that the SCS0 bit also be cleared, even
clocked from the internal oscillator block using the
though the bit is ignored. When the clock source is
INTOSC multiplexer. In this mode, the primary clock is
switched to the INTOSC multiplexer (see Figure 4-3),
shut down. When using the LF-INTOSC source, this
the primary oscillator is shut down and the OSTS bit is
mode provides the best power conservation of all the
cleared. The IRCF bits may be modified at any time to
Run modes, while still executing code. It works well for
immediately change the clock speed.
user applications which are not highly timing-sensitive
or do not require high-speed clocks at all times. Note: Caution should be used when modifying a
If the primary clock source is the internal oscillator single IRCF bit. At a lower VDD, it is
block either LF-INTOSC or INTOSC (MF-INTOSC or possible to select a higher clock speed
HF-INTOSC) there are no distinguishable differences than is supportable by that VDD. Improper
between the PRI_RUN and RC_RUN modes during device operation may result if the VDD/
execution. Entering or exiting RC_RUN mode, how- FOSC specifications are violated.
ever, causes a clock switch delay. Therefore, if the
primary clock source is the internal oscillator block,
using RC_RUN mode is not recommended.
Clocks to the device continue while the INTOSC source On transitions from RC_RUN mode to PRI_RUN mode,
stabilizes after an interval of TIOBST (Parameter 39, the device continues to be clocked from the INTOSC
Table 31-11). multiplexer while the primary clock is started. When the
If the IRCF bits were previously at a non-zero value, or primary clock becomes ready, a clock switch to the
if INTSRC was set before setting SCS1 and the primary clock occurs (see Figure 4-4). When the clock
INTOSC source was already stable, the HFIOFS or switch is complete, the HFIOFS or MFIOFS bit is
MFIOFS bit will remain set. cleared, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The LF-INTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor (FSCM) is enabled.
LF-INTOSC 1 2 3 n-1 n
CPU
Clock
Peripheral
Clock
Program
Counter PC PC + 2 PC + 4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
INTOSC
Multiplexer
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock
Transition(2)
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4
Counter
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter PC PC + 2
OSC1
TOST(1) TPLL(1)
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4 PC + 6
Counter
Wake Event OSTS Bit Set
Note1:TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Q1 Q2 Q3 Q4 Q1
OSC1
CPU Clock
Peripheral
Clock
Program PC PC + 2
Counter
FIGURE 4-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1 Q2 Q3 Q4
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program PC
Counter
Wake Event
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
External Reset
MCLRE
MCLR
( )_IDLE
Sleep
WDT
Time-out
OST/PWRT
OST 1024 Cycles
Chip_Reset
10-Bit Ripple Counter R Q
OSC1
32 s PWRT 65.5 ms
INTOSC(1) 11-Bit Ripple Counter
Enable PWRT
Enable OST(2)
Note 1: This is the INTOSC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
2: See Table 5-2 for time-out situations.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent
Power-on Resets may be detected.
2: Brown-out Reset is said to have occurred when BOR is 0 and POR is 1 (assuming that POR was set to
1 by software immediately after a Power-on Reset).
HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2)
HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC
EC, ECIO 66 ms(1)
RC, RCIO 66 ms(1)
INTIO1, INTIO2 66 ms(1)
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.
FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
5V
VDD 0V 1V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
TPWRT
PLL TIME-OUT
INTERNAL RESET
TABLE 5-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
PIC18FX5K80 PIC18FX6K80
000000h
On-Chip On-Chip
Memory Memory
007FFFh
00FFFFh
Unimplemented Unimplemented
Read as 0 Read as 0
1FFFFFh
Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.
00011
Top-of-Stack 001A34h 00010
000D58h 00001
00000
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
Phase
Q3 Clock
Q4
PC PC PC + 2 PC + 4
OSC2/CLKO
(RC mode)
Execute INST (PC 2)
Fetch INST (PC) Execute INST (PC)
Fetch INST (PC + 2) Execute INST (PC + 2)
Fetch INST (PC + 4)
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is flushed from the pipeline while the new instruction is being fetched and then executed.
6.2.4 TWO-WORD INSTRUCTIONS used by the instruction sequence. If the first word is
skipped for some reason and the second word is
The standard PIC18 instruction set has four, two-word
executed by itself, a NOP is executed instead. This is
instructions: CALL, MOVFF, GOTO and LSFR. In all cases,
necessary for cases when the two-word instruction is
the second word of the instructions always has 1111 as
preceded by a conditional instruction that changes the
its four Most Significant bits (MSbs). The other 12 bits
PC. Example 6-4 shows how this works.
are literal data, usually a data memory address.
The use of 1111 in the 4 MSbs of an instruction Note: For information on two-word instructions
specifies a special form of NOP. If the instruction is in the extended instruction set, see
executed in proper sequence, immediately after the Section 6.5 Program Memory and the
first word, the data in the second word is accessed and Extended Instruction Set.
Note 1: Addresses, E41h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
Users must always use the complete address, or load the proper BSR value, to access these
registers.
Bank 3
through
Bank 13
FFh
E00h
00h
Bank 14
F00h FFh
00h
Bank 15
FFFh FFh
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>)
to the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
6.3.2 ACCESS BANK however, the instruction is forced to use the Access
Bank address map. In that case, the current value of
While the use of the BSR, with an embedded 8-bit
the BSR is ignored entirely.
address, allows users to address the entire range of data
memory, it also means that the user must ensure that the Using this forced addressing allows the instruction to
correct bank is selected. If not, data may be read from, operate on a data address in a single cycle without
or written to, the wrong location. This can be disastrous updating the BSR first. For 8-bit addresses of 60h and
if a GPR is the intended target of an operation, but an above, this means that users can evaluate and operate
SFR is written to instead. Verifying and/or changing the on SFRs more efficiently. The Access RAM below 60h
BSR for each read or write to data memory can become is a good place for data values that the user might need
very inefficient. to access rapidly, such as immediate computational
results or common program variables.
To streamline access for the most commonly used data
memory locations, the data memory is configured with Access RAM also allows for faster and more code
an Access Bank, which allows users to access a efficient context saving and switching of variables.
mapped block of memory without specifying a BSR. The mapping of the Access Bank is slightly different
The Access Bank consists of the first 96 bytes of when the extended instruction set is enabled (XINST
memory (00h-5Fh) in Bank 0 and the last 160 bytes of Configuration bit = 1). This is discussed in more detail
memory (60h-FFh) in Bank 15. The lower half is known in Section 6.6.3 Mapping the Access Bank in
as the Access RAM and is composed of GPRs. The Indexed Literal Offset Mode.
upper half is where the devices SFRs are mapped.
These two areas are mapped contiguously in the 6.3.3 GENERAL PURPOSE
Access Bank and can be addressed in a linear fashion REGISTER FILE
by an eight-bit address (Figure 6-6).
PIC18 devices may have banked memory in the GPR
The Access Bank is used by core PIC18 instructions area. This is data RAM which is available for use by all
that include the Access RAM bit (the a parameter in instructions. GPRs start at the bottom of Bank 0
the instruction). When a is equal to 1, the instruction (address 000h) and grow upwards towards the bottom of
uses the BSR and the 8-bit address included in the the SFR area. GPRs are not initialized by a Power-on
opcode for the data memory address. When a is 0, Reset and are unchanged on all other Resets.
F9Fh IPR1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP 92
F9Eh PIR1 PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF 92
F9Dh PIE1 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE 92
F9Ch PSTR1CON CMPL1 CMPL0 STRSYNC STRD STRC STRB STRA 92
F9Bh OSCTUNE INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 93
F9Ah REFOCON ROON ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 93
F99h CCPTMRS C5TSEL C4TSEL C3TSEL C2TSEL C1TSEL 93
F98h TRISG TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 93
F97h TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 93
F96h TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE2 TRISE1 TRISE0 93
F95h TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 93
F94h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 93
F93h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 93
F92h TRISA TRISA7 TRISA6 TRISA5 TRISA3 TRISA2 TRISA1 TRISA0 93
F91h ODCON SSPOD CCP5OD CCP4OD CCP3OD CCP2OD CCP1OD U2OD U1OD 93
F90h SLRCON SLRG SLRF SLRE SLRD SLRC SLRB SLRA 93
F8Fh LATG LATG4 LATG3 LATG2 LATG1 LATG0 93
F8Eh LATF LATF7 LATF6 LATF5 LATF4 LATF2 LATF1 LATF0 93
F8Dh LATE LATE7 LATE6 LATE5 LATE4 LATE2 LATE1 LATE0 93
F8Ch LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 93
F8Bh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 93
F8Ah LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 93
F89h LATA LATA7 LATA6 LATA5 LATA3 LATA2 LATA1 LATA0 93
F88h T4CON T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 93
F87h TMR4 Timer4 Register 93
F86h PORTG RG4 RG3 RG2 RG1 RG0 93
F85h PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 93
F84h PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 93
F83h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 93
F82h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 93
F81h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 93
F80h PORTA RA7 RA6 RA5 RA3 RA2 RA1 RA0 93
F7Fh EECON1 EEPGD CFGS FREE WRERR WREN WR RD 93
F7Eh EECON2 Flash Self-Program Control Register (not a physical register) 93
F7Dh SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 93
F7Ch SPBRGH2 EUSART2 Baud Rate Generator Register High Byte 93
F7Bh SPBRG2 EUSART2 Baud Rate Generator Register Low Byte 93
F7Ah RCREG2 EUSART2 Receive Register 93
F79h TXREG2 EUSART2 Transmit Register 94
F78h IPR5 IRXIP WAKIP ERRIP TX2BIP TXB1IP TXB0IP RXB1IP RXB0IP 94
F77h PIR5 IRXIF WAKIF ERRIF TXB2IF TXB1IF TXB0IF RXB1IF RXB0IF 94
F76H PIE5 IRXIE WAKIE ERRIE TX2BIE TXB1IE TXB0IE RXB1IE RXB0IE 94
F75h EEADRH Data EE Address Register High Byte 94
F74h EEADR Data EE Address Register Low Byte 94
F73h EEDATA Data EE Data Register 94
F72h ECANCON MDSEL1 MDSEL0 FIFOWM EWIN4 EWIN3 EWIN2 EWIN1 EWIN0 94
F71h COMSTAT RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN 94
F70h CIOCON TX2SRC TX2EN ENDRHI CANCAP CLKSEL 94
F6Fh CANCON REQOP2 REQOP1 REQOP0 ABAT WIN2/FP3 WIN1/FP2 WIN0/FP1 FP0 94
F6Eh CANSTAT OPMODE2 OPMODE1 OPMODE0 / ICODE2/ ICODE1/ ICODE0/ / 94
EICOD4 EICODE3 EICODE2 EICODE1 EICODE0
F6Dh RXB0D7 RXB0D77 RXB0D76 RXB0D75 RXB0D74 RXB0D73 RXB0D72 RXB0D71 RXB0D70 94
F6Ch RXB0D6 RXB0D67 RXB0D66 RXB0D65 RXB0D64 RXB0D63 RXB0D62 RXB0D61 RXB0D60 94
F6Bh RXB0D5 RXB0D57 RXB0D56 RXB0D55 RXB0D54 RXB0D53 RXB0D52 RXB0D51 RXB0D50 94
F6Ah RXB0D4 RXB0D47 RXB0D46 RXB0D45 RXB0D44 RXB0D43 RXB0D42 RXB0D41 RXB0D40 94
F69h RXB0D3 RXB0D37 RXB0D36 RXB0D35 RXB0D34 RXB0D33 RXB0D32 RXB0D31 RXB0D30 94
F68h RXB0D2 RXB0D27 RXB0D26 RXB0D25 RXB0D24 RXB0D23 RXB0D22 RXB0D21 RXB0D20 94
F67h RXB0D1 RXB0D17 RXB0D16 RXB0D15 RXB0D14 RXB0D13 RXB0D12 RXB0D11 RXB0D10 94
F66h RXB0D0 RXB0D07 RXB0D06 RXB0D05 RXB0D04 RXB0D03 RXB0D02 RXB0D01 RXB0D00 94
F65h RXB0DLC RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 94
F64h RXB0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 94
F63h RXB0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 94
F62h RXB0SIDL SID2 SID1 SID0 SRR EXID EID17 EID16 94
F61h RXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 94
F60h RXB0CON RXFUL RXM1 RXM0 RXRTRRO RXB0DBEN JTOFF FILHIT0 94
F60h RXB0CON RXFUL RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 94
F5Fh CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 94
F5Eh CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 94
F5Dh ANCON0 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 94
F5Ch ANCON1 ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8 94
F5Bh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 94
F5Ah IOCB IOCB7 IOCB6 IOCB5 IOCB4 94
F59h PMD0 CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD 94
F58h PMD1 PSPMD CTMUMD ADCMD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD 95
F57h PMD2 MODMD ECANMD CMP2MD CMP1MD 95
F56h PADCFG1 RDPU REPU RFPU RGPU CTMUDS 95
F55h CTMUCONH CTMUEN CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 95
F54h CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 95
F53h CTMUICON ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 95
F52h CCPR2H Capture/Compare/PWM Register 2 High Byte 95
F51h CCPR2L Capture/Compare/PWM Register 2 Low Byte 95
F50h CCP2CON DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 95
F4Fh CCPR3H Capture/Compare/PWM Register 3 High Byte 95
F4Eh CCPR3L Capture/Compare/PWM Register 3 Low Byte 95
F4Dh CCP3CON DC3B1 D32B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 95
F4Ch CCPR4H Capture/Compare/PWM Register 4 High Byte 95
F4Bh CCPR4L Capture/Compare/PWM Register 4 Low Byte 95
F4Ah CCP4CON DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 95
F49H CCPR5H Capture/Compare/PWM Register 5 High Byte 95
F48h CCPR5L Capture/Compare/PWM Register 5 Low Byte 95
F47h CCP5CON DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 95
F46h PSPCON IBF OBF IBOV PSPMODE 95
F45h MDCON MDEN MDOE MDSLR MDOPOL MDO MDBIT 95
F44h MDSRC MDSODIS MDSRC3 MDSRC2 MDSRC1 MDSRC0 95
F43h MDCARH MDCHODIS MDCHPOL MDCHSYNC MDCH3 MDCH2 MDCH1 MDCH0 95
F42h MDCARL MDCLODIS MDCLPOL MDCLSYNC MDCL3 MDCL2 MDCL1 MDCL0 95
F41h Unimplemented
F40h Unimplemented
F3Fh CANCON_RO0 CANCON_RO0 95
F3Eh CANSTAT_RO0 CANSTAT_RO0 95
F3Dh RXB1D7 RXB1D77 RXB1D76 RXB1D75 RXB1D74 RXB1D73 RXB1D72 RXB1D71 RXB1D70 95
F3Ch RXB1D6 RXB1D67 RXB1D66 RXB1D65 RXB1D64 RXB1D63 RXB1D62 RXB1D61 RXB1D60 95
F3Bh RXB1D5 RXB1D57 RXB1D56 RXB1D55 RXB1D54 RXB1D53 RXB1D52 RXB1D51 RXB1D50 95
F3Ah RXB1D4 RXB1D47 RXB1D46 RXB1D45 RXB1D44 RXB1D43 RXB1D42 RXB1D41 RXB1D40 95
F39h RXB1D3 RXB1D37 RXB1D36 RXB1D35 RXB1D34 RXB1D33 RXB1D32 RXB1D31 RXB1D30 95
F38h RXB1D2 RXB1D27 RXB1D26 RXB1D25 RXB1D24 RXB1D23 RXB1D22 RXB1D21 RXB1D20 95
F37h RXB1D1 RXB1D17 RXB1D16 RXB1D15 RXB1D14 RXB1D13 RXB1D12 RXB1D11 RXB1D10 95
F36h RXB1D0 RXB1D07 RXB1D06 RXB1D05 RXB1D04 RXB1D03 RXB1D02 RXB1D01 RXB1D00 95
F35h RXB1DLC RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 95
F34h RXB1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 96
F33h RXB1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 96
F32h RXB1SIDL SID2 SID1 SID0 SRR EXID EID17 EID16 96
F31h RXB1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 96
F30h RXB1CON RXFUL RXM1 RXM0 RXRTRRO RXBODBEN JTOFF FILHIT0 96
F30h RXB1CON RXFUL RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 96
F2Fh CANCON_RO1 CANCON_RO1 96
F2Eh CANSTAT_RO1 CANSTAT_RO1 96
F2Dh TXB0D7 TXB0D77 TXB0D76 TXB0D75 TXB0D74 TXB0D73 TXB0D72 TXB0D71 TXB0D70 96
F2Ch TXB0D6 TXB0D67 TXB0D66 TXB0D65 TXB0D64 TXB0D63 TXB0D62 TXB0D61 TXB0D60 96
F2Bh TXB0D5 TXB0D57 TXB0D56 TXB0D55 TXB0D54 TXB0D53 TXB0D52 TXB0D51 TXB0D50 96
F2Ah TXB0D4 TXB0D47 TXB0D46 TXB0D45 TXB0D44 TXB0D43 TXB0D42 TXB0D41 TXB0D40 96
F29h TXB0D3 TXB0D37 TXB0D36 TXB0D35 TXB0D34 TXB0D33 TXB0D32 TXB0D31 TXB0D30 96
F28h TXB0D2 TXB0D27 TXB0D26 TXB0D25 TXB0D24 TXB0D23 TXB0D22 TXB0D21 TXB0D20 96
F27h TXB0D1 TXB0D17 TXB0D16 TXB0D15 TXB0D14 TXB0D13 TXB0D12 TXB0D11 TXB0D10 96
F26h TXB0D0 TXB0D07 TXB0D06 TXB0D05 TXB0D04 TXB0D03 TXB0D02 TXB0D01 TXB0D00 96
F25h TXB0DLC TXRTR DLC3 DLC2 DLC1 DLC0 96
F24h TXB0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 96
F23h TXB0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 96
F22h TXB0SIDL SID2 SID1 SID0 SRR EXID EID17 EID16 96
F21h TXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 96
F20h TXB0CON TXBIF TXABT TXLARB TXERR TXREQ TXPRI1 TXPRI0 96
F1Fh CANCON_RO2 CANCON_RO2 96
F1Eh CANSTAT_RO2 CANSTAT_RO2 96
F1Dh TXB1D7 TXB1D77 TXB1D76 TXB1D75 TXB1D74 TXB1D73 TXB1D72 TXB1D71 TXB1D70 96
F1Ch TXB1D6 TXB1D67 TXB1D66 TXB1D65 TXB1D64 TXB1D63 TXB1D62 TXB1D61 TXB1D60 96
F1Bh TXB1D5 TXB1D57 TXB1D56 TXB1D55 TXB1D54 TXB1D53 TXB1D52 TXB1D51 TXB1D50 96
F1Ah TXB1D4 TXB1D47 TXB1D46 TXB1D45 TXB1D44 TXB1D43 TXB1D42 TXB1D41 TXB1D40 96
F19h TXB1D3 TXB1D37 TXB1D36 TXB1D35 TXB1D34 TXB1D33 TXB1D32 TXB1D31 TXB1D30 96
F18h TXB1D2 TXB1D27 TXB1D26 TXB1D25 TXB1D24 TXB1D23 TXB1D22 TXB1D21 TXB1D20 96
F17h TXB1D1 TXB1D17 TXB1D16 TXB1D15 TXB1D14 TXB1D13 TXB1D12 TXB1D11 TXB1D10 96
F16h TXB1D0 TXB1D07 TXB1D06 TXB1D05 TXB1D04 TXB1D03 TXB1D02 TXB1D01 TXB1D00 96
F15h TXB1DLC TXRTR DLC3 DLC2 DLC1 DLC0 96
F14h TXB1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 96
F13h TXB1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 96
F12h TXB1SIDL SID2 SID1 SID0 SRR EXID EID17 EID16 96
F11h TXB1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 96
F10h TXB1CON TXBIF TXABT TXLARB TXERR TXREQ TXPRI1 TXPRI0 96
F0Fh CANCON_RO3 CANCON_RO3 96
F0Eh CANSTAT_RO3 CANSTAT_RO3 96
F0Dh TXB2D7 TXB2D77 TXB2D76 TXB2D75 TXB2D74 TXB2D73 TXB2D72 TXB2D71 TXB2D70 96
F0Ch TXB2D6 TXB2D67 TXB2D66 TXB2D65 TXB2D64 TXB2D63 TXB2D62 TXB2D61 TXB2D60 97
F0Bh TXB2D5 TXB2D57 TXB2D56 TXB2D55 TXB2D54 TXB2D53 TXB2D52 TXB2D51 TXB2D50 97
F0Ah TXB2D4 TXB2D47 TXB2D46 TXB2D45 TXB2D44 TXB2D43 TXB2D42 TXB2D41 TXB2D40
F09h TXB2D3 TXB2D37 TXB2D36 TXB2D35 TXB2D34 TXB2D33 TXB2D32 TXB2D31 TXB2D30 97
F08h TXB2D2 TXB2D27 TXB2D26 TXB2D25 TXB2D24 TXB2D23 TXB2D22 TXB2D21 TXB2D20 97
F07h TXB2D1 TXB2D17 TXB2D16 TXB2D15 TXB2D14 TXB2D13 TXB2D12 TXB2D11 TXB2D10 97
F06h TXB2D0 TXB2D07 TXB2D06 TXB2D05 TXB2D04 TXB2D03 TXB2D02 TXB2D01 TXB2D00 97
F05h TXB2DLC TXRTR DLC3 DLC2 DLC1 DLC0 97
F04h TXB2EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 97
F03h TXB2EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 97
F02h TXB2SIDL SID2 SID1 SID0 SRR EXID EID17 EID16 97
F01h TXB2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 97
F00h TXB2CON TXBIF TXABT TXLARB TXERR TXREQ TXPRI1 TXPRI0 97
EFFh RXM1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 97
EFEh RXM1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 97
EFDh RXM1SIDL SID2 SID1 SID0 EXIDEN EID17 EID16 97
EFCh RXM1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 97
EFBh RXM0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 97
EFAh RXM0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 97
EF9h RXM0SIDL SID2 SID1 SID0 EXIDEN EID17 EID16 97
EF8h RXM0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 97
EF7h RXF5EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 97
EF6h RXF5EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 97
EF5h RXF5SIDL SID2 SID1 SID0 EXIDEN EID17 EID16 97
EF4h RXF5SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 97
EF3h RXF4EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 97
EF2h RXF4EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 97
EF1h RXF4SIDL SID2 SID1 SID0 EXIDEN EID17 EID16 97
EF0h RXF4SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 98
EEFh RXF3EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 98
EEEh RXF3EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 98
EEDh RXF3SIDL SID2 SID1 SID0 EXIDEN EID17 EID16 98
EECh RXF3SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 98
EEBh RXF2EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 98
EEAh RXF2EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 98
EE9h RXF2SIDL SID2 SID1 SID0 EXIDEN EID17 EID16 98
EE8h RXF2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 98
EE7h RXF1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 98
EE6h RXF1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 98
EE5h RXF1SIDL SID2 SID1 SID0 EXIDEN EID17 EID16 98
EE4h RXF1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 98
EE3h RXF0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 98
EE2h RXF0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 98
EE1h RXF0SIDL SID2 SID1 SID0 EXIDEN EID17 EID16 98
EE0h RXF0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 98
EDFh CANCON_RO4 CANCON_RO4 98
EDEh CANSTAT_RO4 CANSTAT_RO4 98
EDDh B5D7 B5D77 B5D76 B5D75 B5D74 B5D73 B5D72 B5D71 B5D70 98
EDCh B5D6 B5D67 B5D66 B5D65 B5D64 B5D63 B5D62 B5D61 B5D60 98
EDBh B5D5 B5D57 B5D56 B5D55 B5D54 B5D53 B5D52 B5D51 B5D50 98
EDAh B5D4 B5D47 B5D46 B5D45 B5D44 B5D43 B5D42 B5D41 B5D40 98
ED9h B5D3 B5D37 B5D36 B5D35 B5D34 B5D33 B5D32 B5D31 B5D30 98
ED8h B5D2 B5D27 B5D26 B5D25 B5D24 B5D23 B5D22 B5D21 B5D20 98
ED7h B5D1 B5D17 B5D16 B5D15 B5D14 B5D13 B5D12 B5D11 B5D10 98
ED6h B5D0 B5D07 B5D06 B5D05 B5D04 B5D03 B5D02 B5D01 B5D00 98
ED5h B5DLC TXRTR DLC3 DLC2 DLC1 DLC0 98
ED4h B5EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 98
ED3h B5EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 98
ED2h B5SIDL SID2 SID1 SID0 SRR EXID EID17 EID16 98
ED1h B5SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 98
ED0h B5CON TXBIF TXABT TXLARB TXERR TXREQ TXPRI1 TXPRI0 98
ECFh CANCON_RO5 CANCON_RO5 98
ECEh CANSTAT_RO5 CANSTAT_RO5 99
ECDh B4D7 B4D77 B4D76 B4D75 B4D74 B4D73 B4D72 B4D71 B4D70 99
ECCh B4D6 B4D67 B4D66 B4D65 B4D64 B4D63 B4D62 B4D61 B4D60 99
ECBh B4D5 B4D57 B4D56 B4D55 B4D54 B4D53 B4D52 B4D51 B4D50 99
ECAh B4D4 B4D47 B4D46 B4D45 B4D44 B4D43 B4D42 B4D41 B4D40 99
EC9h B4D3 B4D37 B4D36 B4D35 B4D34 B4D33 B4D32 B4D31 B4D30 99
EC8h B4D2 B4D27 B4D26 B4D25 B4D24 B4D23 B4D22 B4D21 B4D20 99
EC7h B4D1 B4D17 B4D16 B4D15 B4D14 B4D13 B4D12 B4D11 B4D10 99
EC6h B4D0 B4D07 B4D06 B4D05 B4D04 B4D03 B4D02 B4D01 B4D00 99
EC5h B4DLC TXRTR DLC3 DLC2 DLC1 DLC0 99
EC4h B4EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 99
EC3h B4EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 99
EC2h B4SIDL SID2 SID1 SID0 SRR EXID EID17 EID16 99
EC1h B4SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 99
EC0h B4CON TXBIF TXABT TXLARB TXERR TXREQ TXPRI1 TXPRI0 99
EBFh CANCON_RO6 CANCON_RO6 99
EBEh CANSTAT_RO6 CANSTAT_RO6 99
EBDh B3D7 B3D77 B3D76 B3D75 B3D73 B3D73 B3D72 B3D71 B3D70 99
EBCh B3D6 B3D67 B3D66 B3D65 B3D63 B3D63 B3D62 B3D61 B3D60 99
EBBh B3D5 B3D57 B3D56 B3D55 B3D53 B3D53 B3D52 B3D51 B3D50 99
EBAh B3D4 B3D47 B3D46 B3D45 B3D43 B3D43 B3D42 B3D41 B3D40 99
EB9h B3D3 B3D37 B3D36 B3D35 B3D33 B3D33 B3D32 B3D31 B3D30 99
EB8h B3D2 B3D27 B3D26 B3D25 B3D23 B3D23 B3D22 B3D21 B3D20 99
EB7h B3D1 B3D17 B3D16 B3D15 B3D13 B3D13 B3D12 B3D11 B3D10 99
EB6h B3D0 B3D07 B3D06 B3D05 B3D03 B3D03 B3D02 B3D01 B3D00 99
EB5h B3DLC TXRTR DLC3 DLC2 DLC1 DLC0 99
EB4h B3EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 99
EB3h B3EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 99
EB2h B3SIDL SID2 SID1 SID0 SRR EXID EID17 EID16 99
EB1h B3SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 99
EB0h B3CON TXBIF TXABT TXLARB TXERR TXREQ TXPRI1 TXPRI0 99
EAFh CANCON_RO7 CANCON_RO7 99
EAEh CANSTAT_RO7 CANSTAT_RO7 99
EADh B2D7 B2D77 B2D76 B2D75 B2D72 B2D73 B2D72 B2D71 B2D70 99
EACh B2D6 B2D67 B2D66 B2D65 B2D62 B2D63 B2D62 B2D61 B2D60 99
EABh B2D5 B2D57 B2D56 B2D55 B2D52 B2D53 B2D52 B2D51 B2D50 100
EAAh B2D4 B2D47 B2D46 B2D45 B2D42 B2D43 B2D42 B2D41 B2D40 100
EA9h B2D3 B2D37 B2D36 B2D35 B2D32 B2D33 B2D32 B2D31 B2D30 100
EA8h B2D2 B2D27 B2D26 B2D25 B2D22 B2D23 B2D22 B2D21 B2D20 100
EA7h B2D1 B2D17 B2D16 B2D15 B2D12 B2D13 B2D12 B2D11 B2D10 100
EA6h B2D0 B2D07 B2D06 B2D05 B2D02 B2D03 B2D02 B2D01 B2D00 100
EA5h B2DLC TXRTR DLC3 DLC2 DLC1 DLC0 100
EA4h B2EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 100
EA3h B2EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 100
EA2h B2SIDL SID2 SID1 SID0 SRR EXID EID17 EID16
EA1h B2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 100
EA0h B2CON TXBIF TXABT TXLARB TXERR TXREQ TXPRI1 TXPRI0 100
E9Fh CANCON_RO8 CANCON_RO8 100
E9Eh CANSTAT_RO8 CANSTAT_RO8 100
E9Dh B1D7 B1D77 B1D76 B1D75 B1D71 B1D73 B1D72 B1D71 B1D70 100
E9Ch B1D6 B1D67 B1D66 B1D65 B1D61 B1D63 B1D62 B1D61 B1D60 100
E9Bh B1D5 B1D57 B1D56 B1D55 B1D51 B1D53 B1D52 B1D51 B1D50 100
E9Ah B1D4 B1D47 B1D46 B1D45 B1D41 B1D43 B1D42 B1D41 B1D40 100
E99h B1D3 B1D37 B1D36 B1D35 B1D31 B1D33 B1D32 B1D31 B1D30 100
E98h B1D2 B1D27 B1D26 B1D25 B1D21 B1D23 B1D22 B1D21 B1D20 100
E97h B1D1 B1D17 B1D16 B1D15 B1D11 B1D13 B1D12 B1D11 B1D10 100
E96h B1D0 B1D07 B1D06 B1D05 B1D01 B1D03 B1D02 B1D01 B1D00 100
E95h B1DLC TXRTR DLC3 DLC2 DLC1 DLC0 100
E94h B1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 100
E93h B1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 100
E92h B1SIDL SID2 SID1 SID0 SRR EXID EID17 EID16 100
E91h B1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 100
E90h B1CON TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 100
E90h B1CON RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 100
E8Fh CANCON_RO9 CANCON_RO9 100
E8Eh CANSTAT_RO9 CANSTAT_RO9 100
E8Dh B0D7 B0D77 B0D76 B0D75 B0D70 B0D73 B0D72 B0D71 B0D70 100
E8Ch B0D6 B0D67 B0D66 B0D65 B0D60 B0D63 B0D62 B0D61 B0D60 100
E8Bh B0D5 B0D57 B0D56 B0D55 B0D50 B0D53 B0D52 B0D51 B0D50 100
E8Ah B0D4 B0D47 B0D46 B0D45 B0D40 B0D43 B0D42 B0D41 B0D40 100
E89h B0D3 B0D37 B0D36 B0D35 B0D30 B0D33 B0D32 B0D31 B0D30 100
E88h B0D2 B0D27 B0D26 B0D25 B0D20 B0D23 B0D22 B0D21 B0D20 101
E87h B0D1 B0D17 B0D16 B0D15 B0D10 B0D13 B0D12 B0D11 B0D10 101
E86h B0D0 B0D07 B0D06 B0D05 B0D00 B0D03 B0D02 B0D01 B0D00 101
E85h B0DLC RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 101
E84h B0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 101
E83h B0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 101
E82h B0SIDL SID2 SID1 SID0 SRR EXID EID17 EID16 101
E81h B0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 101
E80h B0CON TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 101
E80h B0CON RTXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 101
E7Fh TXBIE CAN TX Buffer Interrupt Enable 101
E7Eh BIE0 CAN Buffer Interrupt Enable 101
E7Dh BSEL0 Mode Select Register 0 101
E7Ch MSEL3 CAN Mask Select Register 3 101
E7Bh MSEL2 CAN Mask Select Register 2 101
E7Ah MSEL1 CAN Mask Select Register 1 101
E79h MSEL0 CAN Mask Select Register 0 101
E78h RXFBCON7 CAN Buffer 15/14 Pointer Register 101
E77h RXFBCON6 CAN Buffer 13/12 Pointer Register 101
E76h RXFBCON5 CAN Buffer 11/10 Pointer Register 101
E75h RXFBCON4 CAN Buffer 9/8 Pointer Register 101
E74h RXFBCON3 CAN Buffer 7/6 Pointer Register 101
E73h RXFBCON2 CAN Buffer 5/4 Pointer Register 101
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the 2s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.
2: For borrow, the polarity is reversed. A subtraction is executed by adding the 2s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the
source register.
000h
When a = 0 and f 60h:
The instruction executes in 060h
Direct Forced mode. f is Bank 0
interpreted as a location in the 100h
Access RAM between 060h 00h
and FFFh. This is the same as Bank 1 60h
locations, F60h to FFFh, through
Bank 14 Valid range
(Bank 15) of data memory. for f
Locations below 060h are not FFh
F00h
available in this addressing Access RAM
Bank 15
mode.
F40h
SFRs
FFFh
Data Memory
BSR
When a = 1 (all values of f): 000h 00000000
Bank 0
The instruction executes in
060h
Direct mode (also known as
Direct Long mode). f is 100h
interpreted as a location in
one of the 16 banks of the data Bank 1 001001da ffffffff
memory space. The bank is through
Bank 14
designated by the Bank Select
Register (BSR). The address
can be in any implemented F00h
bank in the data memory Bank 15
space. F40h
SFRs
FFFh
Data Memory
Example Situation:
ADDWF f, d, a 000h
Not Accessible
FSR2H:FSR2L = 120h 05Fh
Instruction: TBLRD*
Program Memory
Table Pointer(1)
Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Instruction: TBLWT*
Program Memory
Holding Registers
Table Pointer(1) Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR)
Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Section 7.5 Writing to Flash Program Memory.
7.2 Control Registers The FREE bit, when set, allows a program memory
erase operation. When FREE is set, the erase
Several control registers are used in conjunction with operation is initiated on the next WR command. When
the TBLRD and TBLWT instructions. These include the: FREE is clear, only writes are enabled.
EECON1 register The WREN bit, when set, allows a write operation. On
EECON2 register power-up, the WREN bit is clear. The WRERR bit is set
TABLAT register in hardware when the WR bit is set and cleared when
TBLPTR registers the internal programming timer expires and the write
operation is complete.
7.2.1 EECON1 AND EECON2 REGISTERS Note: During normal operation, the WRERR is
The EECON1 register (Register 7-1) is the control read as 1. This can indicate that a write
register for memory accesses. The EECON2 register, operation was prematurely terminated by
not a physical register, is used exclusively in the a Reset, or a write operation was
memory write and erase sequences. Reading attempted improperly.
EECON2 will read all 0s.
The WR control bit initiates write operations. The bit
The EEPGD control bit determines if the access is a
cannot be cleared, only set, in software. It is cleared in
program or data EEPROM memory access. When
hardware at the completion of the write operation.
clear, any subsequent operations operate on the data
EEPROM memory. When set, any subsequent Note: The EEIF interrupt flag bit (PIR4<6>) is
operations operate on the program memory. set when the write is complete. It must be
The CFGS control bit determines if the access is to the cleared in software.
Configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
operate on Configuration registers regardless of
EEPGD (see Section 28.0 Special Features of the
CPU). When clear, memory selection access is
determined by EEPGD.
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
TABLE 7-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example Operation on Table Pointer
TBLRD*
TBLPTR is not modified
TBLWT*
TBLRD*+
TBLPTR is incremented after the read/write
TBLWT*+
TBLRD*-
TBLPTR is decremented after the read/write
TBLWT*-
TBLRD+*
TBLPTR is incremented before the read/write
TBLWT+*
Program Memory
8 8 8 8
Program Memory
The EEADRH:EEADR register pair is used to address Note: The EEIF interrupt flag bit (PIR4<6>) is
the data EEPROM for read and write operations. set when the write is complete. It must be
EEADRH holds the two MSbs of the address; the upper cleared in software.
6 bits are ignored. The 10-bit range of the pair can Control bits, RD and WR, start read and erase/write
address a memory range of 1024 bytes (00h to 3FFh). operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 7.1 Table Reads
and Table Writes regarding table reads.
The EECON2 register is not a physical register. It is
used exclusively in the memory write and erase
sequences. Reading EECON2 will read all 0s.
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
PIR1<7:0>
PIE1<7:0> TMR0IF Wake-up if in
IPR1<7:0> TMR0IE Idle or Sleep modes
TMR0IP
RBIF
PIR2<7,5:0> RBIE
PIE2<7,5:0> RBIP
IPR2<7,5:0> INT0IF
INT0IE
PIR3<7,5> INT1IF
PIE3<7,5> INT1IE Interrupt to CPU
IPR3<7,5> INT1IP Vector to Location
INT2IF
INT2IE 0008h
PIR4<7:0>
PIE4<7:0> INT2IP
IPR4<7:0> INT3IF
INT3IE
INT3IP
GIE/GIEH
PIR5<7:0>
PIE5<7:0>
IPR5<7:0> IPEN
IPEN
PEIE/GIEL
IPEN
PIR1<7:0>
PIE1<7:0>
IPR1<7:0>
PIR2<7, 5:0>
PIE2<7, 5:0>
IPR2<7, 5:0> Interrupt to CPU
TMR0IF Vector to Location
TMR0IE IPEN
PIR3<7, 5:0> 0018h
PIE3<7, 5:0> TMR0IP
IPR3<7, 5:0>
RBIF
PIR4<7:0> RBIE
PIE4<7:0> RBIP GIE/GIEH
IPR4<7:0> PEIE/GIEL
INT1IF
INT1IE
PIR5<7:0> INT1IP
PIE5<7:0> INT2IF
IPR5<7:0> INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: A mismatch condition will continue to set this bit. To end the mismatch condition and allow the bit to be
cleared, read PORTB and wait one additional instruction cycle.
2: Each pin on PORTB for interrupt-on-change is individually enabled and disabled in the IOCB register. By
default, all pins are enabled.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: Interrupt-on-change also requires that the RBIE bit of the INTCON register be set.
RD TRIS
Q D
ENEN
RD PORT
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
MDBIT 0000
MDMIN 0001
SSP (SDO) 0010 0
EUSART1 (TX) 0011
EUSART2 (TX) 0100 MDCHSYNC
ECCP1 0101
CCP2 0110 MOD
CCP3 0111
CCP4 1000 MDOUT
CCP5 1001
MDOE
1010 MDOPOL
Reserved
No Channel *
*
Selected 1111
D
MDCL<3:0> SYNC
Q 1
VSS 0000
MDCIN1 0001
MDCIN2 0010
REFO Clock 0011 0
ECCP1 0100
CCP2 0101 CARL MDCLSYNC
CCP3 0110
CCP4 0111
CCP5 1000
1001 MDCLPOL
Reserved
No Channel Selected **
1111
Modulator (MOD)
MDCHSYNC = 1
MDCLSYNC = 0
MDCHSYNC = 1
MDCLSYNC = 1
MDCHSYNC = 0
MDCLSYNC = 0
MDCHSYNC = 0
MDCLSYNC = 1
Modulator (MOD)
MDCHSYNC = 0
MDCLSYNC = 0
Modulator (MOD)
MDCHSYNC = 1
MDCLSYNC = 0
Modulator (MOD)
MDCHSYNC = 0
MDCLSYNC = 1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: The MDBIT must be selected as the modulation source in the MDSRC register for this operation.
2: The modulated output frequency can be greater and asynchronous from the clock that updates this
register bit. The bit value may not be valid for higher speed modulator or carrier signals.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MDCARH MDCHODIS MDCHPOL MDCHSYNC MDCH3 MDCH2 MDCH1 MDCH0
MDCARL MDCLODIS MDCLPOL MDCLSYNC MDCL3 MDCL2 MDCL1 MDCL0
MDCON MDEN MDOE MDSLR MDOPOL MDO MDBIT
MDSRC MDSODIS MDSRC3 MDSRC2 MDSRC1 MDSRC0
PMD2 MODMD ECANMD CMP2MD CMP1MD
Legend: = unimplemented, read as 0. Shaded cells are not used in the Data Signal Modulator mode.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
FOSC/4 0
1
Sync with Set
1 Internal TMR0L TMR0IF
T0CKI Pin Programmable 0 Clocks on Overflow
Prescaler
T0SE (2 TCY Delay)
T0CS 8
3
T0PS<2:0>
8
PSA Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FOSC/4 0
1
Sync with Set
Internal TMR0
1 TMR0L High Byte TMR0IF
T0CKI Pin Programmable 0 Clocks on Overflow
Prescaler 8
T0SE (2 TCY Delay)
T0CS 3 Read TMR0L
T0PS<2:0>
Write TMR0L
PSA
8
8
TMR0H
8
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare
features.
Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare
features.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
T1GSS<1:0>
T1G 00 T1GSPM
TMR1CS<1:0> T1SYNC
SOSCO/SCLKI OUT(4)
Note: The Special Event Trigger from the ECCP TABLE 14-3: TIMER1 GATE ENABLE
module will only clear the TMR1 registers SELECTIONS
content, but not set the TMR1IF interrupt T1GPOL Timer1
flag bit (PIR1<0>). T1CLK() T1G Pin
(T1GCON<6>) Operation
0 0 Counts
0 1 Holds Count
1 0 Holds Count
1 1 Counts
The clock on which TMR1 is running. For more
information, see Figure 14-1.
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
TMR1GE
T1GPOL
T1GSPM
Cleared by Hardware on
T1GGO/ Set by Software Falling Edge of T1GVAL
T1DONE
Counting Enabled on
Rising Edge of T1G
T1G_IN
T1CKI
T1GVAL
TMR1GE
T1GPOL
T1GSPM
T1GTM
Cleared by Hardware on
T1GGO/ Set by Software Falling Edge of T1GVAL
T1DONE Counting Enabled on
Rising Edge of T1G
T1G_IN
T1CKI
T1GVAL
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
4 1:1 to 1:16
T2OUTPS<3:0> Set TMR2IF
Postscaler
2
T2CKPS<1:0> TMR2 Output
(to PWM or MSSP)
TMR2/PR2
Reset Match
1:1, 1:4, 1:16
FOSC/4 TMR2 Comparator PR2
Prescaler
8 8
8
Internal Data Bus
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: When SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no
effect.
T3GSS<1:0>
T3G 00 T3GSPM
From TMR4 0
01 T3G_IN Data Bus
Match PR4 0 T3GVAL
D Q
From Comparator 1 Single Pulse RD
Output 10 1
Q1 EN T3GCON
Acq. Control
D Q 1
From Comparator 2
11 Interrupt
Output T3GGO/T3DONE Set
CK Q
TMR3ON det TMR3GIF
R
T3GPOL T3GTM
TMR3GE
Set Flag bit, TMR3ON
TMR3IF, on
Overflow TMR3(2)
EN Synchronized
0 Clock Input
TMR3H TMR3L T3CLK
Q D
1
TMR3CS<1:0> T3SYNC
SOSCO/SCLKI OUT(4)
TMR3GE
T3GPOL
T3G_IN
T3CKI
T3GVAL
16.5.2.1 T3G Pin Gate Operation 16.5.3 TIMER3 GATE TOGGLE MODE
The T3G pin is one source for Timer3 gate control. It can When Timer3 Gate Toggle mode is enabled, it is
be used to supply an external source to the Timerx gate possible to measure the full cycle length of a Timer3
circuitry. gate signal, as opposed to the duration of a single level
pulse.
16.5.2.2 Timer4 Match Gate Operation
The Timer3 gate source is routed through a flip-flop that
The TMR4 register will increment until it matches the changes state on every incrementing edge of the
value in the PR4 register. On the very next increment signal. (For timing details, see Figure 16-3.)
cycle, TMR4 will be reset to 00h. When this Reset
The T3GVAL bit will indicate when the Toggled mode is
occurs, a low-to-high pulse will automatically be gener-
active and the timer is counting.
ated and internally supplied to the Timerx gate circuitry.
The pulse will remain high for one instruction cycle and Timer3 Gate Toggle mode is enabled by setting the
will return back to a low state until the next match. T3GTM bit (T3GCON<5>). When the T3GTM bit is
cleared, the flip-flop is cleared and held clear. This is
Depending on T3GPOL, Timerx increments differently
necessary in order to control which edge is measured.
when TMR4 matches PR4. When T3GPOL = 1, Timer3
increments for a single instruction cycle following a
TMR3GE
T3GPOL
T3GTM
T3G_IN
T3CKI
T3GVAL
TMR3GE
T3GPOL
T3GSPM
Cleared by Hardware on
T3GGO/ Set by Software Falling Edge of T3GVAL
T3DONE
Counting Enabled on
Rising Edge of T3G
T3G_IN
T3CKI
T3GVAL
Cleared by
TMR3GIF Cleared by Software Set by Hardware on Software
Falling Edge of T3GVAL
TMR3GE
T3GPOL
T3GSPM
T3GTM
Cleared by Hardware on
T3GGO/ Set by Software Falling Edge of T3GVAL
T3DONE
Counting Enabled on
Rising Edge of T3G
T3G_IN
T3CKI
T3GVAL
16.5.5 TIMER3 GATE VALUE STATUS 16.5.6 TIMER3 GATE EVENT INTERRUPT
When Timer3 gate value status is utilized, it is possible When the Timer3 gate event interrupt is enabled, it is
to read the most current level of the gate control value. possible to generate an interrupt upon the completion
The value is stored in the T3GVAL bit (T3GCON<2>). of a gate event. When the falling edge of T3GVAL
The T3GVAL bit is valid even when the Timer3 gate is occurs, the TMR3GIF flag bit in the PIR2 register will be
not enabled (TMR3GE bit is cleared). set. If the TMR3GIE bit in the PIE2 register is set, then
an interrupt will be recognized.
The TMR3GIF flag bit operates even when the Timer3
gate is not enabled (TMR3GE bit is cleared).
The Timer4 modules have a control register shown in A write to the TMR4 register
Register 17-1. Timer4 can be shut off by clearing A write to the T4CON register
control bit, TMR4ON (T4CON<2>), to minimize power Any device Reset Power-on Reset (POR),
consumption. The prescaler and postscaler selection of MCLR Reset, Watchdog Timer Reset (WDTR) or
Timer4 also are controlled by this register. Figure 17-1 Brown-out Reset (BOR)
is a simplified block diagram of the Timer4 modules. A TMR4 is not cleared when a T4CON is written.
17.1 Timer4 Operation Note: The CCP and ECCP modules use Timers,
1 through 4, for some modes. The assign-
Timer4 can be used as the PWM time base for the ment of a particular timer to a CCP/ECCP
PWM mode of the ECCP modules. The TMR4 registers module is determined by the Timer to CCP
are readable and writable, and are cleared on any enable bits in the CCPTMRS register. For
device Reset. The input clock (FOSC/4) has a prescale more details, see Register 20-2 and
option of 1:1, 1:4 or 1:16, selected by control bits, Register 19-2.
T4CKPS<1:0> (T4CON<1:0>). The match output of
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
4 1:1 to 1:16
T4OUTPS<3:0> Set TMR4IF
Postscaler
2
T4CKPS<1:0> TMR4 Output
(to PWM)
TMRx/PRx
Reset Match
1:1, 1:4, 1:16
FOSC/4 TMR4 Comparator PR4
Prescaler
8 8
8
Internal Data Bus
CTMUCONH:CTMUCONL
EDGEN CTMUICON
EDGSEQEN
ITRIM<5:0> TGEN
EDG1SEL<1:0>
EDG1POL IRNG<1:0> IDISSEN
EDG2SEL<1:0> EDG1STAT CTTRIG
EDG2POL EDG2STAT Current Source
CTED1 Edge
CTMU
Control Control A/D Trigger
CTED2 Logic Current Logic
Control
CCP2
Pulse CTPLS
ECCP1 Generator
A/D Converter Comparator 2
Input
Comparator 2 Output
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
6. Select the operating mode (Measurement or The current source needs calibration to set it to a
Time Delay) with the TGEN bit precise current.
(CTMUCONH<4>). The circuit being measured needs calibration to
measure or nullify any capacitance other than that
The default mode is Time/Capacitance
to be measured.
Measurement.
7. Configure the module to automatically trigger 18.4.1 CURRENT SOURCE CALIBRATION
an A/D conversion when the second edge The current source on board the CTMU module has a
event has occurred using the CTTRIG bit range of 62% nominal for each of three current
(CTMUCONH<0>). ranges. For precise measurements, it is possible to
The conversion trigger is disabled by default. measure and adjust this current source by placing a
8. Discharge the connected circuit by setting the high-precision resistor, RCAL, onto an unused analog
IDISSEN bit (CTMUCONH<1>). channel. An example circuit is shown in Figure 18-2.
9. After waiting a sufficient time for the circuit to To measure the current source:
discharge, clear the IDISSEN bit. 1. Initialize the A/D Converter.
10. Disable the module by clearing the CTMUEN bit 2. Initialize the CTMU.
(CTMUCONH<7>). 3. Enable the current source by setting EDG1STAT
11. Clear the Edge Status bits, EDG2STAT and (CTMUCONL<0>).
EDG1STAT (CTMUCONL<1:0>). 4. Issue time delay for voltage across RCAL to
Both bits should be cleared simultaneously, if stabilize and ADC sample/hold capacitor to
possible, to avoid re-enabling the CTMU current charge.
source. 5. Perform the A/D conversion.
12. Enable both edge inputs by setting the EDGEN 6. Calculate the current source current using
bit (CTMUCONH<3>). I = V / RCAL, where RCAL is a high-precision
13. Enable the module by setting the CTMUEN bit. resistance and V is measured by performing an
A/D conversion.
A/D
Trigger
A/D Converter
ANx
A/D
RCAL MUX
/**************************************************************************/
//Setup AD converter;
/**************************************************************************/
// ADCON1
ADCON2bits.ADFM=1; // Result format 1= Right justified
ADCON2bits.ACQT=1; // Acquisition time 7 = 20TAD 2 = 4TAD 1=2TAD
ADCON2bits.ADCS=2; // Clock conversion bits 6= FOSC/64 2=FOSC/32
// ADCON1
ADCON1bits.VCFG0 =0; // Vref+ = AVdd
ADCON1bits.VCFG1 =0; // Vref+ = AVdd
ADCON1bits.VNCFG = 0; // Vref- = AVss
ADCON1bits.CHS=2; // Select ADC channel
int main(void)
{
int i;
int j = 0; //index for loop
unsigned int Vread = 0;
double VTot = 0;
float Vavg=0, Vcal=0, CTMUISrc = 0; //float values stored for calcs
Where:
I is known from the current source measurement
step
t is a fixed delay
V is measured by performing an A/D conversion
int main(void)
{
int i;
int j = 0; //index for loop
unsigned int Vread = 0;
float CTMUISrc, CTMUCap, Vavg, VTot, Vcal;
int main(void)
{
unsigned int Vread; //storage for reading
unsigned int switchState;
int i;
PIC18F66K80
CTMU
CTED1 EDG1
Current Source
CTED2 EDG2
A/D Voltage
A/D Converter
ANX
CAD
CEXT
kT I CTMU
VF =
q
(
1n 1 F
IS ) Current Source
18.7.2 IMPLEMENTATION
IF ADC
To implement this theory, all that is needed is to con-
nect a regular junction diode to one of the microcon-
VF
trollers A/D pins (Figure 18-2). The A/D channel
multiplexer is shared by the CTMU and the ADC.
// Initialize ADC
ADCON0 = 0xE5; // Enable ADC and connect to Internal diode
ADCON1 = 0x00;
ADCON2 = 0xBE; //Right Justified
Note: The temperature diode is not calibrated or standardized; the user must calibrate the diode to their application.
FIGURE 18-5: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY
GENERATION
PIC18F66K80
CTMU
CTED1 EDG1 CTPLS
Current Source
Comparator CTMUDS
CTMUI CTDIN
C2
CDELAY
CVREF
C1
External Reference
External Comparator
// Initialize CTMU
CTMUICON = 0x03;
CTMUCONHbits.CTMUEN = 1;
CTMUCONLbits.EDG1STAT = 1;
// Initialize ADC
ADCON0 = 0xE5; // Enable ADC and connect to Internal diode
ADCON1 = 0x00;
ADCON2 = 0xBE; //Right Justified
Note: The temperature diode is not calibrated or standardized; the user must calibrate the diode to their application.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: CCPxM<3:0> = 1011 will only reset the timer and not start an A/D conversion on CCPx match.
2: Available only on CCP2. Selected by the CANCAP (CIOCON<4>) bit. Overrides the CCP2 input pin
source.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
19.1.1 CCP MODULES AND TIMER The assignment of a particular timer to a module is
RESOURCES determined by the Timer to CCP enable bits in the
CCPTMRS register (see Register 19-2). All of the
The CCP modules utilize Timers, 1 through 4, varying modules may be active at once and may share the
with the selected mode. Various timers are available to same timer resource if they are configured to operate
the CCP modules in Capture, Compare or PWM in the same mode (Capture/Compare or PWM) at the
modes, as shown in Table 19-1. same time.
The CCPTMRS register selects the timers for CCP
modules, 2, 3, 4 and 5. The possible configurations are
shown in Table 19-2.
19.1.2 OPEN-DRAIN OUTPUT OPTION The open-drain output option is controlled by the
CCPxOD bits (ODCON<6:2>). Setting the appropriate
When operating in Output mode (the Compare or PWM
bit configures the pin for the corresponding module for
modes), the drivers for the CCPx pins can be optionally
open-drain operation.
configured as open-drain outputs. This feature allows
the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor and allows the
output to communicate with external circuits without the
need for additional level shifters.
4 TMR1H TMR1L
CCP3CON<3:0> Set CCP4IF
4
Q1:Q4
4
CCP4CON<3:0>
TMR3H TMR3L
C4TSEL
TMR3
Enable
CCP4 Pin
Prescaler and CCPR4H CCPR4L
1, 4, 16 Edge Detect
TMR1
Enable
Note: This block diagram uses CCP3 and CCP4, and their appropriate timers as an example. For details on all of
the CCP modules and their timer assignments, see Table 19-2.
Compare Output S Q
Comparator
Match Logic
R
TRIS
4 Output Enable
CCP5CON<3:0>
TMR1H TMR1L 0
TMR3H TMR3L 1
C5TSEL
0 TMR1H TMR1L
1 TMR3H TMR3L
Special Event Trigger
(Timer1/Timer3 Reset)
C4TSEL
Compare Output S Q
Comparator
Match Logic
R
TRIS
4 Output Enable
CCPR4H CCPR4L
CCP4CON<3:0>
Note: This block diagram uses CCP4 and CCP5, and their appropriate timers as an example. For details on all of
the CCP modules and their timer assignments, see Table 19-2.
19.4.3 SETUP FOR PWM OPERATION 3. Make the CCP4 pin an output by clearing the
appropriate TRIS bit.
To configure the CCP module for PWM operation,
using CCP4 as an example: 4. Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
1. Set the PWM period by writing to the PR2
5. Configure the CCP4 module for PWM operation.
register.
2. Set the PWM duty cycle by writing to the
CCPR4L register and CCP4CON<5:4> bits.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
TMR3H TMR3L
Set CCP1IF
C1TSEL0
C1TSEL1 TMR3
ECCP1 Pin C1TSEL2 Enable
Prescaler and CCPR1H CCPR1L
1, 4, 16 Edge Detect
C1TSEL0 TMR1
C1TSEL1 Enable
C1TSEL2
4 TMR1H TMR1L
CCP1CON<3:0>
4
Q1:Q4
0 TMR1H TMR1L
1 TMR3H TMR3L
Compare Output S Q
Comparator
Match Logic
R
TRIS
4 Output Enable
CCPR1H CCPR1L
CCP1CON<3:0>
FIGURE 20-3: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
DC1B<1:0> P1M<1:0> CCP1M<3:0>
Duty Cycle Registers
2 4
CCPR1L
ECCP1/P1A ECCP1/Output Pin
TRIS
CCPR1H (Slave)
P1B Output Pin
Output TRIS
Comparator R Q
Controller
P1C Output Pin
TMR2 (1)
S TRIS
Note 1: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create
the 10-bit time base.
Note 1: The TRIS register value for each PWM output must be configured appropriately.
2: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.
Period
P1A Active
P1D Modulated
P1A Inactive
P1D Inactive
Relationships:
Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
Delay = 4 * TOSC * (ECCP1DEL<6:0>)
Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 20.4.6 Programmable Dead-Band
Delay Mode).
Pulse PR2 + 1
P1M<1:0> Signal 0
Width
Period
P1A Modulated
Delay(1) Delay(1)
10 (Half-Bridge) P1B Modulated
P1A Active
P1D Modulated
P1A Inactive
P1D Inactive
Relationships:
Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
Delay = 4 * TOSC * (ECCP1DEL<6:0>)
Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 20.4.6 Programmable Dead-Band
Delay Mode).
FET
Driver +
P1A
-
Load
FET
Driver
+
P1B
-
V+
FET FET
Driver Driver
P1A
Load
FET FET
Driver Driver
P1B
FET QA QC FET
Driver Driver
P1A
Load
P1B
FET FET
Driver Driver
P1C
QB QD
V-
P1D
P1B(2)
P1C(2)
P1D(2)
(1) (1)
Reverse Mode
Period
Pulse Width
P1A(2)
P1B(2)
P1C(2)
P1D(2)
(1) (1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: The output signal is shown as active-high.
P1A (Active-High)
P1B (Active-High)
Pulse Width
P1C (Active-High)
(2)
P1D (Active-High)
Pulse Width
Note 1: The direction bit, P1M1 of the CCP1CON register, is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The
modulated P1B and P1D signals are inactive at this time. The length of this time is:
(1/FOSC) TMR2 Prescale Value.
P1A
P1B
PW
P1C
P1D PW
TON
External Switch C
TOFF
External Switch D
20.4.3 START-UP CONSIDERATIONS damage to the application circuit. The Enhanced PWM
modes must be enabled in the proper Output mode and
When any PWM mode is used, the application
complete a full PWM cycle before enabling the PWM
hardware must use the proper external pull-up and/or
pin output drivers. The completion of a full PWM cycle
pull-down resistors on the PWM output pins.
is indicated by the TMR2IF or TMR4IF bit of the PIR1
Note: When the microcontroller is released from or PIR4 register being set as the second PWM period
Reset, all of the I/O pins are in the begins.
high-impedance state. The external
circuits must keep the power switch 20.4.4 ENHANCED PWM
devices in the OFF state until the micro- AUTO-SHUTDOWN MODE
controller drives the I/O pins with the The PWM mode supports an Auto-Shutdown mode that
proper signal levels or activates the PWM will disable the PWM outputs when an external
output(s). shutdown event occurs. Auto-Shutdown mode places
The CCP1M<1:0> bits of the CCP1CON register allow the PWM output pins into a predetermined state. This
the user to choose whether the PWM output signals are mode is used to help prevent the PWM from damaging
active-high or active-low for each pair of PWM output the application.
pins (P1A/P1C and P1B/P1D). The PWM output The auto-shutdown sources are selected using the
polarities must be selected before the PWM pin output ECCP1AS<2:0> bits (ECCP1AS<6:4>). A shutdown
drivers are enabled. Changing the polarity configura- event may be generated by:
tion while the PWM pin output drivers are enabled is
A logic 0 on the pin that is assigned the FLT0
not recommended since it may result in damage to the
input function
application circuits.
Comparator C1
The P1A, P1B, P1C and P1D output latches may not be
Comparator C2
in the proper states when the PWM module is
initialized. Enabling the PWM pin output drivers at the Setting the ECCP1ASE bit in firmware
same time as the Enhanced PWM modes may cause
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is
present, the auto-shutdown will persist.
2: Writing to the ECCP1ASE bit is disabled while an auto-shutdown condition persists.
3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or
auto-restart), the PWM signal will always restart at the beginning of the next PWM period.
PWM Period
Shutdown Event
ECCP1ASE bit
PWM Activity
Normal PWM
ECCP1ASE
Cleared by
Start of Shutdown Shutdown Firmware PWM
PWM Period Event Occurs Event Clears Resumes
20.4.5 AUTO-RESTART MODE The module will wait until the next PWM period begins,
however, before re-enabling the output pin. This behav-
The Enhanced PWM can be configured to automatically
ior allows the auto-shutdown with auto-restart features
restart the PWM signal once the auto-shutdown condi-
to be used in applications based on current mode of
tion has been removed. Auto-restart is enabled by
PWM control.
setting the P1RSEN bit (ECCP1DEL<7>).
If auto-restart is enabled, the ECCP1ASE bit will
remain set as long as the auto-shutdown condition is
active. When the auto-shutdown condition is removed,
the ECCP1ASE bit will be cleared via hardware and
normal operation will resume.
PWM Period
Shutdown Event
ECCP1ASE bit
PWM Activity
Normal PWM
FET
Driver +
P1A V
-
Load
FET
Driver
+
P1B V
-
V-
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
20.4.7 PULSE STEERING MODE While the PWM Steering mode is active, the
CCP1M<1:0> bits (CCP1CON<1:0>) select the PWM
In Single Output mode, pulse steering allows any of the
output polarity for the P1<D:A> pins.
PWM pins to be the modulated signal. Additionally, the
same PWM signal can simultaneously be available on The PWM auto-shutdown operation also applies to the
multiple pins. PWM Steering mode, as described in Section 20.4.4
Enhanced PWM Auto-shutdown mode. An
Once the Single Output mode is selected
auto-shutdown event will only affect pins that have
(CCP1M<3:2> = 11 and P1M<1:0> = 00 of the
PWM outputs enabled.
CCP1CON register), the user firmware can bring out
the same PWM signal to one, two, three or four output
pins by setting the appropriate STR<D:A> bits
(PSTR1CON<3:0>), as provided in Table 20-2.
Note: The associated TRIS bits must be set to
output (0) to enable the pin output driver
in order to see the PWM signal on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 7-6 CMPL<1:0>: Complementary Mode Output Assignment Steering Sync bits
00 = See STR<D:A>.
01 = PA and PB are selected as the complementary output pair
10 = PA and PC are selected as the complementary output pair
11 = PA and PD are selected as the complementary output pair
bit 5 Unimplemented: Read as 0
bit 4 STRSYNC: Steering Sync bit
1 = Output steering update occurs on the next PWM period
0 = Output steering update occurs at the beginning of the instruction cycle boundary
bit 3 STRD: Steering Enable bit D
1 = P1D pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1D pin is assigned to port pin
bit 2 STRC: Steering Enable bit C
1 = P1C pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1C pin is assigned to port pin
bit 1 STRB: Steering Enable bit B
1 = P1B pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1B pin is assigned to port pin
bit 0 STRA: Steering Enable bit A
1 = P1A pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1A pin is assigned to port pin
Note 1: The PWM Steering mode is available only when the CCP1CON register bits, CCP1M<3:2> = 11 and
P1M<1:0> = 00.
Port Data 0
TRIS
Note 1: Port outputs are configured as displayed when
the CCP1CON register bits, P1M<1:0> = 00
and CCP1M<3:2> = 11.
2: Single PWM output requires setting at least
one of the STR<D:A> bits.
PWM
STR<D:A>
P1n = PWM
PWM
STR<D:A>
P1n = PWM
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
2: When enabled, these pins must be properly configured as inputs or outputs.
3: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only.
SDO SDI
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Four Clock
SCK Modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Input
Sample
(SMP = 1)
SSPIF
Next Q4 Cycle
SSPSR to after Q2
SSPBUF
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI bit 0
(SMP = 0) bit 7 bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
SSPSR to after Q2
SSPBUF
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
SSPSR to after Q2
SSPBUF
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDI
(SMP = 0) bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2
SSPSR to
SSPBUF
SSPBUF reg
SSPADD contains the slave device address when the
SCL MSSP is configured in I2C Slave mode. When the
MSSP is configured in Master mode, the lower seven
Shift
Clock bits of SSPADD act as the Baud Rate Generator reload
value.
SSPSR reg
SDA MSb LSb SSPMSK holds the slave address mask value when
the module is configured for 7-Bit Address Masking
mode. While it is a separate register, it shares the same
Match Detect Addr Match
SFR address as SSPADD; it is only accessible when
Address Mask the SSPM<3:0> bits are specifically set to permit
access. Additional details are provided in
Section 21.4.3.4 7-Bit Address Masking Mode.
SSPADD reg
In receive operations, SSPSR and SSPBUF together,
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
Start and Set, Reset and the SSPIF interrupt is set.
Stop bit Detect S, P bits
(SSPSTAT reg) During transmission, the SSPBUF is not
double-buffered. A write to SSPBUF will write to both
Note: Only port I/O names are used in this diagram for SSPBUF and SSPSR.
the sake of brevity. Refer to the text for a full list of
multiplexed functions.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: When enabled, the SDA and SCL pins must be configured as inputs.
2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
3: When SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address actually access the
SSPMSK register.
4: This mode is only available when 7-Bit Address Masking mode is selected (MSSPMSK Configuration bit
is 1).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
2: If the I2C module is active, these bits may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: If the I2C module is active, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
REGISTER 21-7: SSPMSK: I2C SLAVE ADDRESS MASK REGISTER (7-BIT MASKING MODE)(1)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: This register shares the same SFR address as SSPADD and is only addressable in select MSSP
operating modes. See Section 21.4.3.4 7-Bit Address Masking Mode for more details.
2: MSK0 is not used as a mask bit in 7-bit addressing.
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
BF (SSPSTAT<0>)
Preliminary
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
CKP (SSPCON<4>)
(CKP does not reset to 0 when SEN = 0)
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
PIC18F66K80 FAMILY
DS39977C-page 311
FIGURE 21-9:
DS39977C-page 312
Receiving Address R/W = 0 Receiving Data ACK Receiving Data ACK
SDA A7 A6 A5 X A3 X X ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
terminates
transfer
BF (SSPSTAT<0>)
Preliminary
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
CKP (SSPCON<4>)
2: In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt.
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
Data in SCL held low P
sampled while CPU
responds to SSPIF
BF (SSPSTAT<0>)
Cleared in software Cleared in software
Preliminary
From SSPIF ISR From SSPIF ISR
SSPBUF is written in software SSPBUF is written in software
Clear by reading
CKP (SSPCON<4>)
I2C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
DS39977C-page 313
FIGURE 21-11:
DS39977C-page 314
Clock is held low until Clock is held low until
update of SSPADD has update of SSPADD has
taken place taken place
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte
R/W = 0 ACK
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Bus master
terminates
SSPIF (PIR1<3> or PIR3<7>) transfer
BF (SSPSTAT<0>)
PIC18F66K80 FAMILY
SSPOV is set
Preliminary
because SSPBUF is
still full. ACK is not sent.
UA (SSPSTAT<1>)
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte
R/W = 0 ACK
Bus master
terminates
SSPIF (PIR1<3> or PIR3<7>) transfer
BF (SSPSTAT<0>)
SSPOV is set
Preliminary
because SSPBUF is
still full. ACK is not sent.
UA (SSPSTAT<1>)
DS39977C-page 315
FIGURE 21-13:
DS39977C-page 316
Bus master
terminates
Clock is held low until Clock is held low until transfer
update of SSPADD has update of SSPADD has Clock is held low until
taken place taken place CKP is set to 1
R/W = 0
Receive First Byte of Address Receive Second Byte of Address Receive First Byte of Address R/W = 1 Transmitting Data Byte ACK
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S Sr P
BF (SSPSTAT<0>)
Preliminary
Dummy read of SSPBUF Write of SSPBUF Completion of
contents of SSPSR to clear BF flag BF flag is clear
to clear BF flag initiates transmit data transmission
at the end of the
UA (SSPSTAT<1>) third address sequence clears BF flag
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA DX DX 1
SCL
Master device
CKP asserts clock
Master device
deasserts clock
WR
SSPCON1
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
BF (SSPSTAT<0>)
Preliminary
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
CKP (SSPCON<4>)
CKP
If BF is cleared written
prior to the falling to 1 in
edge of the 9th clock, software
CKP will not be reset BF is set after falling
to 0 and no clock edge of the 9th clock,
stretching will occur CKP is reset to 0 and
clock stretching occurs
I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
PIC18F66K80 FAMILY
DS39977C-page 319
FIGURE 21-16:
DS39977C-page 320
Clock is held low until
update of SSPADD has update of SSPADD has Clock is not held low
Clock is held low until
taken place taken place because ACK = 1
CKP is set to 1
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte
R/W = 0 ACK
ACK ACK
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
BF (SSPSTAT<0>)
PIC18F66K80 FAMILY
SSPOV is set
Preliminary
because SSPBUF is
still full. ACK is not sent.
UA (SSPSTAT<1>)
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>) 0
GCEN (SSPCON2<7>)
1
Internal SSPM<3:0>
Data Bus SSPADD<6:0>
Read Write
SSPBUF Baud
Rate
Generator
SDA Shift
Clock Arbitrate/WCOL Detect
SDA In Clock
SSPSR
(hold off clock source)
MSb LSb
Receive Enable
Acknowledge
Generate
SCL
SSPM<3:0> SSPADD<6:0>
SDA DX DX 1
BRG decrements on
Q2 and Q4 cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
SCL
TBRG
S
Sr = Repeated Start
Preliminary
BF (SSPSTAT<0>)
PEN
R/W
I 2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
PIC18F66K80 FAMILY
DS39977C-page 329
FIGURE 21-24:
DS39977C-page 330
Write to SSPCON2<4>
to start Acknowledge sequence,
SDA = ACKDT (SSPCON2<5>) = 0
Write to SSPCON2<0> (SEN = 1),
begin Start condition ACK from master, Set ACKEN, start Acknowledge sequence,
Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
SEN = 0 by programming SSPCON2<3> (RCEN = 1)
PEN bit = 1
Write to SSPBUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
start XMIT automatically
Transmit Address to Slave R/W = 1 Receiving Data from Slave Receiving Data from Slave
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Bus master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSPIF at end
of receive Set SSPIF interrupt
at end of Acknowledge
PIC18F66K80 FAMILY
Set P bit
Cleared in software Cleared in software Cleared in software Cleared in software (SSPSTAT<4>)
Cleared in
SDA = 0, SCL = 1,
Preliminary
software and SSPIF
while CPU
responds to SSPIF
BF
(SSPSTAT<0>) Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
SSPOV
ACKEN
I 2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
SCL 8 9
SSPIF
Cleared in
SSPIF set at software
the end of receive Cleared in
software SSPIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
TBRG
SCL
SDA ACK
P
TBRG TBRG TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to set up Stop condition
SDA
BCLIF
SDA
SCL
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL = 1 MSSP module reset into Idle state.
SEN
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
BCLIF SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software
SSPIF
TBRG TBRG
SDA
SSPIF 0 0
FIGURE 21-30: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSPIF
Less than TBRG
TBRG
SCL S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
BCLIF 0
SSPIF
SDA = 0, SCL = 1, Interrupts cleared
set SSPIF in software
SDA
SCL
RSEN
BCLIF
Cleared in software
S 0
SSPIF 0
TBRG TBRG
SDA
SCL
S 0
SSPIF
PEN
BCLIF
P 0
SSPIF 0
SDA
SCL goes low before SDA goes high,
Assert SDA
set BCLIF
SCL
PEN
BCLIF
P 0
SSPIF 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
0.3
1.2 1.221 1.73 255 1.202 0.16 129
2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64
9.6 9.615 0.16 103 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15
19.2 19.231 0.16 51 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7
57.6 58.824 2.13 16 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2
115.2 111.111 -3.55 8 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1
0.3
1.2
2.4 2.441 1.73 255
9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64
19.2 19.417 1.13 207 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31
57.6 59.701 3.65 68 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10
115.2 121.212 5.22 34 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4
0.3 0.300 0.00 13332 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082
1.2 1.200 0.00 3332 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520
2.4 2.400 0.00 1666 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259
9.6 9.592 -0.08 416 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64
19.2 19.417 1.13 207 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31
57.6 59.701 3.65 68 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10
115.2 121.212 5.22 34 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4
0.3 0.300 -0.04 1665 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207
1.2 1.201 -0.16 415 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51
2.4 2.403 -0.16 207 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25
9.6 9.615 -0.16 51 9.615 0.16 25 9.615 -0.16 12
19.2 19.230 -0.16 25 19.231 0.16 12
57.6 55.555 3.55 8 62.500 8.51 3
115.2 125.000 8.51 1
0.3 0.300 0.00 53332 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332
1.2 1.200 0.00 13332 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082
2.4 2.400 0.00 6666 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040
9.6 9.598 -0.02 1666 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259
19.2 19.208 0.04 832 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129
57.6 57.348 -0.44 278 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42
115.2 115.108 -0.08 138 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21
0.3 0.300 -0.01 6665 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832
1.2 1.200 -0.04 1665 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207
2.4 2.400 -0.04 832 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103
9.6 9.615 -0.16 207 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25
19.2 19.230 -0.16 103 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12
57.6 57.142 0.79 34 58.824 2.12 16 55.555 3.55 8
115.2 117.647 -2.12 16 111.111 -3.55 8
BRG Clock
RCxIF bit
(Interrupt)
Read
RCREGx
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
BRG Clock
ABDEN bit
ABDOVF bit
FFFFh
BRG Value XXXXh 0000h 0000h
TRMT SPEN
BRG16 SPBRGHx SPBRGx
TX9
Baud Rate Generator TX9D
Write to TXREGx
Word 1
BRG Output
(Shift Clock)
TXx (pin)
Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXxIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
Word 1
TRMT bit
Transmit Shift Reg
(Transmit Shift
Reg. Empty Flag)
Write to TXREGx
Word 1 Word 2
BRG Output
(Shift Clock)
TXx (pin)
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
RX9
SPEN
8
RCxIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user Auto-Cleared
WUE bit(1)
RXx/DTx Line
RCxIF
Cleared due to user read of RCREGx
Note 1: The EUSART remains in Idle while the WUE bit is set.
RXx/DTx Line
Note 1
RCxIF
Cleared due to user read of RCREGx
SLEEP Command Executed Sleep Ends
Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This
sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Write to TXREGx
Dummy Write
BRG Output
(Shift Clock)
Break
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB sampled here Auto-Cleared
SENDB bit
(Transmit Shift
Reg. Empty Flag)
RC7/CANRX/RX1/
DT1/CCP4Pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
RC6/CANTX/TX1/CK1/
CCP3/Pin (TXCKP = 0)
RC6/CANTX/TX1/CK1/
CCP3/Pin (TXCKP = 1)
Write to
TxREG1 Reg
Write Word 1 Write Word 2
Tx1IF bit
(Interrupt Flag)
TRMT bit
TxEN bit 1 1
Note: Sync Master mode, SPBRGx = 0; continuous transmission of two 8-bit words. This example is equally applicable to EUSART2
(RB6/PGC/TX2/CK2/KBI2 and RB7/PGD/T3G/RX2/DT2/KBI3).
RC6/CANTX/TX1/CK1/
CCP3 Pin
Write to
TXREG1 reg
TX1IF bit
TRMT bit
TXEN bit
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/CANRX/
RX1/DT1/CCP4 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
RC6/CANTX/TX1/
CK1/CCP3 (TXCKP = 0)
RC6/CANTX/TX1/
CK1/CCP3 (TXCKP = 0)
Write to
bit, SREN
SREN bit
CREN bit 0 0
RC1IF bit
(Interrupt)
Read
RCREG1
Note: Timing diagram demonstrates Sync Master mode with bit, SREN = 1, and bit, BRGH = 0. This example is equally applicable to EUSART2
(RB6/PGC/TX2/CK2/KBI2 and RB7/PGD/T3G/RX2/DT2/KBI3).
AVSS
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
12-Bit Result
Left Justified Right Justified
ADFM = 0 ADFM = 1
REGISTER 23-4: ADRESH: A/D RESULT HIGH BYTE REGISTER, LEFT JUSTIFIED (ADFM = 0)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES11 ADRES10 ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4
bit 7
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
REGISTER 23-6: ADRESH: A/D RESULT HIGH BYTE REGISTER, RIGHT JUSTIFIED (ADFM = 1)
U-x U-x U-x U-x R/W-x R/W-x R/W-x R/W-x
ADSGN ADSGN ADSGN ADSGN ADRES11 ADRES10 ADRES9 ADRES8
bit 7
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
REGISTER 23-7: ADRESL: A/D RESULT LOW BYTE REGISTER, RIGHT JUSTIFIED (ADFM = 1)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0
bit 7
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 7-0 ANSEL<7:0>: Analog Port Configuration bits (AN7 and AN0)(1)
1 = Pin configured as an analog channel: digital input disabled and any inputs read as 0
0 = Pin configured as a digital port
Note 1: AN14 through AN11 and AN7 to AN5 are implemented only on 40/44-pin and 64-pin devices. For 28-pin
devices, the corresponding ANSELx bits are still implemented for these channels, but have no effect.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: AN14 through AN11 and AN7 to AN5 are implemented only on 40/44-pin and 64-pin devices. For 28-pin
devices, the corresponding ANSELx bits are still implemented for these channels, but have no effect.
The analog reference voltage is software selectable to Each port pin associated with the A/D Converter can be
either the devices positive and negative supply voltage configured as an analog input or a digital I/O. The
(AVDD and AVSS) or the voltage level on the ADRESH and ADRESL registers contain the result of
RA3/VREF+/AN3 and RA2/VREF-/AN2 pins. VREF+ has the A/D conversion. When the A/D conversion is com-
two additional internal voltage reference selections: plete, the result is loaded into the ADRESH:ADRESL
2.048V and 4.096V. register pair, the GO/DONE bit (ADCON0<1>) is cleared
and the A/D Interrupt Flag bit, ADIF (PIR1<6>), is set.
The A/D Converter can uniquely operate while the
device is in Sleep mode. To operate in Sleep, the A/D A device Reset forces all registers to their Reset state.
conversion clock must be derived from the A/Ds This forces the A/D module to be turned off and any
internal RC oscillator. conversion in progress is aborted. The value in the
ADRESH:ADRESL register pair is not modified for a
The output of the sample and hold is the input into the Power-on Reset. These registers will contain unknown
converter, which generates the result via successive data after a Power-on Reset.
approximation.
The block diagram of the A/D module is shown in
Figure 23-4.
11111
1.024V Band Gap
11110
VDDCORE
11101 Reserved
Temperature Diode
11100
(MUX Disconnected)(3)
11011
(Unimplemented)
11010
(Unimplemented)
11001
(Unimplemented)
11000
(Unimplemented)
01110
AN14(1)
12-Bit 01101
A/D AN13(1)
Converter
00100
AN4
00011
AN3
00010
AN2
00001
AN1
00000
AN0
Positive Input Voltage
CHSN<2:0>
111
Negative Input Voltage AN6
110
AN5
Reference VCFG<1:0>
Voltage
Internal VREF+
11 (4.096V) 001
10 Internal VREF+ AN0
VREF+ (2.048V) 000
AVSS(4)
01
VREF- AN3
00 VDD(4)
VNCFG
AN2
VSS(2,4)
Note 1: Channels, AN14 through AN11, and AN7 through AN5, are implemented only on 40/44-pin and 64-pin devices.
For 28-pin devices, the corresponding ANSELx bits are still implemented for those channels, but have no effect.
2: I/O pins have diode protection to VDD and VSS.
3: Channel 28 turns off analog MUX switches to allow for minimum capacitive loading of ADC inputs for finer
resolution CTMU time measurements.
4: I/O pins have diode protection to VDD and VSS.
VSS
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
FIGURE 23-7: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Automatic
Acquisition Conversion starts
Time (Holding capacitor is disconnected)
CCH<1:0> CMPxOUT
(CMSTAT<7:6>)
CxINB 0
CxINC 1
Interrupt
2 CMPxIF
C2INB/C2IND(1) Logic
VBG 3
EVPOL<1:0>
CREF COE
VIN- CxOUT
Polarity
CxINA 0
VIN+ Cx Logic
CVREF 1
CON CPOL
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: The CMPxIF is automatically set any time this mode is selected and must be cleared by the application
after the initial configuration.
2: Comparator 1 uses C2INB as an input to the inverting terminal. Comparator 2 uses C1INB as an input to
the inverted terminal.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
VDD
VT = 0.6V RIC
RS
Comparator
<10 k AIN Input
CPIN ILEAKAGE
VA VT = 0.6V 100 nA
5 pF
VSS
VIN+ Cx
Off (Read as 0) CxOUT
Pin
Comparator CxINB > CxINA Compare Comparator CxINC > CxINA Compare
CON = 1, CREF = 0, CCH<1:0> = 00 CON = 1, CREF = 0, CCH<1:0> = 01
COE COE
VIN- VIN-
CxINB CxINC
VIN+ Cx VIN+ Cx
CxINA CxOUT CxINA CxOUT
Pin Pin
Comparator C2INB/C1INB > CxINA Compare Comparator VBG > CxINA Compare
CON = 1, CREF = 0, CCH<1:0> = 10 CON = 1, CREF = 0, CCH<1:0> = 11
COE COE
C2INB/ VIN- VIN-
C1INB VBG
VIN+
Cx VIN+ Cx
CxINA CxOUT CxINA CxOUT
Pin Pin
Comparator CxINB > CVREF Compare Comparator CxINC > CVREF Compare
CON = 1, CREF = 1, CCH<1:0> = 00 CON = 1, CREF = 1, CCH<1:0> = 01
COE COE
VIN- VIN-
CxINB CxINC
VIN+ Cx VIN+ Cx
CVREF CxOUT CVREF CxOUT
Pin Pin
Comparator C2INB/C1INB > CVREF Compare Comparator VBG > CVREF Compare
CON = 1, CREF = 1, CCH<1:0> = 10 CON = 1, CREF = 1, CCH<1:0> = 11
COE COE
C2INB/ VIN- VIN-
C1INB VBG
VIN+ Cx VIN+ Cx
CVREF CxOUT CVREF
CxOUT
Pin Pin
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
CVRSS = 1
VREF+
AVDD
CVRSS = 0 8R
CVR<4:0>
CVREN R
32-to-1 MUX
32 Steps
CVREF
R
R
R
CVRSS = 1
VREF-
CVRSS = 0
PIC18F66K80
CVREF
Module R(1)
+
Voltage RA0 CVREF Output
Reference
Output
Impedance
Note 1: R is dependent upon the Voltage Reference Configuration bits, CVRCON<3:0> and CVRCON<5>.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: For the electrical specifications, see Parameter D042 in Section 31.0 Electrical Characteristics.
HLVDEN VDIRMAG
HLVDIN
Set
16-to-1 MUX
HLVDIF
HLVDEN
Internal Voltage
BOREN Reference
1.024V Typical
VDD
VHLVD
HLVDIF
Enable HLVD
TIRVST
IRVST
HLVDIF cleared in software
Internal reference is stable
CASE 2:
VDD
VHLVD
HLVDIF
Enable HLVD
TIRVST
IRVST
Internal reference is stable
HLVDIF cleared in software
VHLVD
VDD
HLVDIF
Enable HLVD
IRVST TIRVST
CASE 2:
VHLVD
VDD
HLVDIF
Enable HLVD
IRVST TIRVST
Acceptance Mask
BUFFERS 16 - 4 to 1 MUXs
RXM0
Acceptance Filters
TXB0 TXB1 TXB2 (RXF0-RXF05)
VCC
A MODE 0
c
MESSAGE
MESSAGE
MESSAGE
MTXBUFF
MTXBUFF
MTXBUFF
MSGREQ
MSGREQ
MSGREQ
c
TXERR
TXERR
TXERR
Acceptance Mask
MLOA
MLOA
MLOA
ABTF
ABTF
ABTF
e
p Acceptance Filters RXF15
RXM1
t (RXF06-RXF15)
MODE 1, 2
Message MODE 0
2 RX Identifier
Queue
Control
Buffers M
A
Transmit Byte Sequencer Data Field B
Transmit Option
MESSAGE
BUFFERS
Transmit Err-Pas
Error Bus-Off
Counter
Transmit<7:0> Receive<8:0>
Shift<14:0>
{Transmit<5:0>, Receive<8:0>}
Comparator
Protocol
Finite
State
CRC<14:0> Machine
Bit
Transmit Clock
Timing
Logic Logic Generator
Configuration
TX RX Registers
Note 1: This bit will clear when all transmissions are aborted.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: To achieve maximum power saving and/or able to wake-up on CAN bus activity, switch the CAN module in
Disable/Sleep mode before putting the device to Sleep.
2: If the buffer is configured as a receiver, the EICODE bits will contain 10000 upon interrupt.
EXAMPLE 27-2: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS
TX/RX BUFFERS
; Save application required context.
; Poll interrupt flags and determine source of interrupt
; This was found to be CAN interrupt
; TempCANCON and TempCANSTAT are variables defined in Access Bank low
MOVFF CANCON, TempCANCON ; Save CANCON.WIN bits
; This is required to prevent CANCON
; from corrupting CAN buffer access
; in-progress while this interrupt
; occurred
MOVFF CANSTAT, TempCANSTAT ; Save CANSTAT register
; This is required to make sure that
; we use same CANSTAT value rather
; than one changed by another CAN
; interrupt.
MOVF TempCANSTAT, W ; Retrieve ICODE bits
ANDLW B00001110
ADDWF PCL, F ; Perform computed GOTO
; to corresponding interrupt cause
BRA NoInterrupt ; 000 = No interrupt
BRA ErrorInterrupt ; 001 = Error interrupt
BRA TXB2Interrupt ; 010 = TXB2 interrupt
BRA TXB1Interrupt ; 011 = TXB1 interrupt
BRA TXB0Interrupt ; 100 = TXB0 interrupt
BRA RXB1Interrupt ; 101 = RXB1 interrupt
BRA RXB0Interrupt ; 110 = RXB0 interrupt
; 111 = Wake-up on interrupt
WakeupInterrupt
BCF PIR3, WAKIF ; Clear the interrupt flag
;
; User code to handle wake-up procedure
;
;
; Continue checking for other interrupt source or return from here
NoInterrupt
; PC should never vector here. User may
; place a trap such as infinite loop or pin/port
; indication to catch this error.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: These bits can only be changed in Configuration mode. See Register 27-1 to change to Configuration mode.
2: This bit is used in Mode 2 only.
3: If FIFO is configured to contain four or less buffers, then the FIFO interrupt will trigger.
bit 7 Mode 0:
RXB0OVFL: Receive Buffer 0 Overflow bit
1 = Receive Buffer 0 has overflowed
0 = Receive Buffer 0 has not overflowed
Mode 1:
Unimplemented: Read as 0
Mode 2:
FIFOEMPTY: FIFO Not Empty bit
1 = Receive FIFO is not empty
0 = Receive FIFO is empty
bit 6 Mode 0:
RXB1OVFL: Receive Buffer 1 Overflow bit
1 = Receive Buffer 1 has overflowed
0 = Receive Buffer 1 has not overflowed
Mode 1, 2:
RXBnOVFL: Receive Buffer n Overflow bit
1 = Receive Buffer n has overflowed
0 = Receive Buffer n has not overflowed
bit 5 TXBO: Transmitter Bus-Off bit
1 = Transmit error counter > 255
0 = Transmit error counter 255
bit 4 TXBP: Transmitter Bus Passive bit
1 = Transmit error counter > 127
0 = Transmit error counter 127
bit 3 RXBP: Receiver Bus Passive bit
1 = Receive error counter > 127
0 = Receive error counter 127
bit 2 TXWARN: Transmitter Warning bit
1 = Transmit error counter > 95
0 = Transmit error counter 95
bit 1 RXWARN: Receiver Warning bit
1 = 127 Receive error counter > 95
0 = Receive error counter 95
bit 0 EWARN: Error Warning bit
This bit is a flag of the RXWARN and TXWARN bits.
1 = The RXWARN or the TXWARN bits are set
0 = Neither the RXWARN or the TXWARN bits are set
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 7-0 EID<15:8>: Extended Identifier bits (not used when transmitting standard identifier message)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 7-0 EID<7:0>: Extended Identifier bits (not used when transmitting standard identifier message)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 7-0 TXBnDm<7:0>: Transmit Buffer n Data Field Byte m bits (where 0 n < 3 and 0 m < 8)
Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0
to TXB0D7.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
; Now that all data bytes are loaded, mark it for transmission.
MOVLW B00001000 ; Normal priority; Request transmission
MOVWF TXB0CON
; Message is transmitted.
; Now that all data bytes are loaded, mark it for transmission.
MOVLW B00001000 ; Normal priority; Request transmission
MOVWF RXB0CON
; Message is transmitted.
; If required, reset the WIN bits to default state.
Note 1: This bit is set by the CAN module upon receiving a message and must be cleared by software after the
buffer is read. As long as RXFUL is set, no new message will be loaded and the buffer will be considered
full. After clearing the RXFUL flag, the PIR5 bit, RXB0IF, can be cleared. If RXB0IF is cleared, but RXFUL
is not cleared, then RXB0IF is set again.
2: This bit allows the same filter jump table for both RXB0CON and RXB1CON.
Note 1: This bit is set by the CAN module upon receiving a message and must be cleared by software after the
buffer is read. As long as RXFUL is set, no new message will be loaded and the buffer will be considered
full. After clearing the RXFUL flag, the PIR5 bit, RXB0IF, can be cleared. If RXB0IF is cleared, but RXFUL
is not cleared, then RXB0IF is set again.
2: This bit allows the same filter jump table for both RXB0CON and RXB1CON.
Note 1: This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer
is read. As long as RXFUL is set, no new message will be loaded and the buffer will be considered full.
Note 1: This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer
is read. As long as RXFUL is set, no new message will be loaded and the buffer will be considered full.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 7-0 RXBnDm<7:0>: Receive Buffer n Data Field Byte m bits (where 0 n < 1 and 0 < m < 7)
Each receive buffer has an array of registers. For example, Receive Buffer 0 has 8 registers: RXB0D0
to RXB0D7.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
REGISTER 27-32: BnDm: TX/RX BUFFER n DATA FIELD BYTE m REGISTERS IN RECEIVE MODE
[0 n 5, 0 m 7, TXnEN (BSEL<n>) = 0](1)
R-x R-x R-x R-x R-x R-x R-x R-x
BnDm7 BnDm6 BnDm5 BnDm4 BnDm3 BnDm2 BnDm1 BnDm0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 7-0 BnDm<7:0>: Receive Buffer n Data Field Byte m bits (where 0 n < 3 and 0 < m < 8)
Each receive buffer has an array of registers. For example, Receive Buffer 0 has 7 registers: B0D0 to
B0D7.
REGISTER 27-33: BnDm: TX/RX BUFFER n DATA FIELD BYTE m REGISTERS IN TRANSMIT MODE
[0 n 5, 0 m 7, TXnEN (BSEL<n>) = 1](1)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
BnDm7 BnDm6 BnDm5 BnDm4 BnDm3 BnDm2 BnDm1 BnDm0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 7-0 BnDm<7:0>: Transmit Buffer n Data Field Byte m bits (where 0 n < 3 and 0 < m < 8)
Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0
to TXB0D7.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 7-0 SID<10:3>: Standard Identifier Mask bits or Extended Identifier Mask bits (EID<28:21>)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 7-5 SID<2:0>: Standard Identifier Mask bits or Extended Identifier Mask bits (EID<20:18>)
bit 4 Unimplemented: Read as 0
bit 3 Mode 0:
Unimplemented: Read as 0
Mode 1, 2:
EXIDEN: Extended Identifier Filter Enable Mask bit(1)
1 = Messages selected by the EXIDEN bit in RXFnSIDL will be accepted
0 = Both standard and extended identifier messages will be accepted
bit 2 Unimplemented: Read as 0
bit 1-0 EID<17:16>: Extended Identifier Mask bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note: Register 27-46 through Register 27-51 are writable in Configuration mode only.
REGISTER 27-46: SDFLC: STANDARD DATA BYTES FILTER LENGTH COUNT REGISTER(1)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLC4 FLC3 FLC2 FLC1 FLC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: Always set this bit when using a differential bus to avoid signal crosstalk in CANTX from other nearby pins.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 7 IRXIF: CAN Bus Error Message Received Interrupt Flag bit
1 = An invalid message has occurred on the CAN bus
0 = No invalid message on the CAN bus
bit 6 WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit
1 = Activity on the CAN bus has occurred
0 = No activity on the CAN bus
bit 5 ERRIF: CAN Module Error Interrupt Flag bit
1 = An error has occurred in the CAN module (multiple sources; refer to Section 27.15.6 Error Interrupt)
0 = No CAN module errors
bit 4 When CAN is in Mode 0:
TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit
1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 2 has not completed transmission of a message
When CAN is in Mode 1 or 2:
TXBnIF: Any Transmit Buffer Interrupt Flag bit
1 = One or more transmit buffers have completed transmission of a message and may be reloaded
0 = No transmit buffer is ready for reload
bit 3 TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit(1)
1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 1 has not completed transmission of a message
bit 2 TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit(1)
1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 0 has not completed transmission of a message
bit 1 When CAN is in Mode 0:
RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit
1 = Receive Buffer 1 has received a new message
0 = Receive Buffer 1 has not received a new message
When CAN is in Mode 1 or 2:
RXBnIF: Any Receive Buffer Interrupt Flag bit
1 = One or more receive buffers has received a new message
0 = No receive buffer has received a new message
bit 0 When CAN is in Mode 0:
RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit
1 = Receive Buffer 0 has received a new message
0 = Receive Buffer 0 has not received a new message
When CAN is in Mode 1:
Unimplemented: Read as 0
When CAN is in Mode 2:
FIFOWMIF: FIFO Watermark Interrupt Flag bit
1 = FIFO high watermark is reached
0 = FIFO high watermark is not reached
Note 1: In CAN Mode 1 and 2, these bits are forced to 0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 7 IRXIE: CAN Bus Error Message Received Interrupt Enable bit
1 = Enable invalid message received interrupt
0 = Disable invalid message received interrupt
bit 6 WAKIE: CAN bus Activity Wake-up Interrupt Enable bit
1 = Enable bus activity wake-up interrupt
0 = Disable bus activity wake-up interrupt
bit 5 ERRIE: CAN bus Error Interrupt Enable bit
1 = Enable CAN module error interrupt
0 = Disable CAN module error interrupt
bit 4 When CAN is in Mode 0:
TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit
1 = Enable Transmit Buffer 2 interrupt
0 = Disable Transmit Buffer 2 interrupt
When CAN is in Mode 1 or 2:
TXBnIE: CAN Transmit Buffer Interrupts Enable bit
1 = Enable transmit buffer interrupt; individual interrupt is enabled by TXBIE and BIE0
0 = Disable all transmit buffer interrupts
bit 3 TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit(1)
1 = Enable Transmit Buffer 1 interrupt
0 = Disable Transmit Buffer 1 interrupt
bit 2 TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit(1)
1 = Enable Transmit Buffer 0 interrupt
0 = Disable Transmit Buffer 0 interrupt
bit 1 When CAN is in Mode 0:
RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit
1 = Enable Receive Buffer 1 interrupt
0 = Disable Receive Buffer 1 interrupt
When CAN is in Mode 1 or 2:
RXBnIE: CAN Receive Buffer Interrupts Enable bit
1 = Enable receive buffer interrupt; individual interrupt is enabled by BIE0
0 = Disable all receive buffer interrupts
bit 0 When CAN is in Mode 0:
RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit
1 = Enable Receive Buffer 0 interrupt
0 = Disable Receive Buffer 0 interrupt
When CAN is in Mode 1:
Unimplemented: Read as 0
When CAN is in Mode 2:
FIFOWMIE: FIFO Watermark Interrupt Enable bit
1 = Enable FIFO watermark interrupt
0 = Disable FIFO watermark interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 7 IRXIP: CAN Bus Error Message Received Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6 WAKIP: CAN Bus Activity Wake-up Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 ERRIP: CAN Module Error Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 When CAN is in Mode 0:
TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 1 or 2:
TXBnIP: CAN Transmit Buffer Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit(1)
1 = High priority
0 = Low priority
bit 2 TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit(1)
1 = High priority
0 = Low priority
bit 1 When CAN is in Mode 0:
RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 1 or 2:
RXBnIP: CAN Receive Buffer Interrupts Priority bit
1 = High priority
0 = Low priority
bit 0 When CAN is in Mode 0:
RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 1:
Unimplemented: Read as 0
When CAN is in Mode 2:
FIFOWMIP: FIFO Watermark Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 7-2 B<5:0>IE: Programmable Transmit/Receive Buffer 5-0 Interrupt Enable bits(2)
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 1-0 RXB<1:0>IE: Dedicated Receive Buffer 1-0 Interrupt Enable bits(2)
1 = Interrupt is enabled
0 = Interrupt is disabled
MESSAGE
MESSAGE
MESSAGE
TXLARB
TXLARB
TXLARB
TXLARB
TXREQ
TXREQ
TXREQ
TXREQ
TXERR
TXERR
TXERR
TXERR
TXB0IF
TXB1IF
TXB2IF
TXB2IF
TXABT
TXABT
TXABT
TXABT
Message
Queue
Control
Transmit Byte Sequencer
RXFn0 RXMn0
RXFnn RXMnn
Input
Signal
TQ
Sample Point
Nominal Bit Time
Nominal Clock
Once these considerations are taken into account, it is For example, assume a CAN bit rate of 125 Kb/s, which
possible to show that the relation between the jitter and gives an NBT of 8 s. For a 16 MHz clock generated
the total frequency error can be defined as: from a 4x PLL, the jitter at this clock frequency is:
T jitter 2 P jitter 1 0.02
f = ------------------------ = ----------------------- 2% ------------------- = ----------------- = 1.25ns
- 16 MHz 6
10 NBT 10 NBT 16 10
TABLE 27-2: FREQUENCY ERROR FROM JITTER AT VARIOUS PLL GENERATED CLOCK SPEEDS
Frequency Error at Various Nominal Bit Times (Bit Rates)
PLL
Pjitter Tjitter 8 s 4 s 2 s 1 s
Output
(125 Kb/s) (250 Kb/s) (500 Kb/s) (1 Mb/s)
40 MHz 0.5 ns 1 ns 0.00125% 0.00250% 0.005% 0.01%
24 MHz 0.83 ns 1.67 ns 0.00209% 0.00418% 0.008% 0.017%
16 MHz 1.25 ns 2.5 ns 0.00313% 0.00625% 0.013% 0.025%
TABLE 27-3: TOTAL FREQUENCY ERROR AT VARIOUS PLL GENERATED CLOCK SPEEDS
(100 PPM OSCILLATOR DRIFT, INCLUDING ERROR FROM JITTER)
Frequency Error at Various Nominal Bit Times (Bit Rates)
Nominal PLL Output 8 s 4 s 2 s 1 s
(125 Kb/s) (250 Kb/s) (500 Kb/s) (1 Mb/s)
40 MHz 0.01125% 0.01250% 0.015% 0.02%
24 MHz 0.01209% 0.01418% 0.018% 0.027%
16 MHz 0.01313% 0.01625% 0.023% 0.035%
Input
Signal
TQ
Sample Point
Nominal Bit Length
TQ Sample Point
Actual Bit Length
Nominal Bit Length
27.11 Programming Time Segments By the rules above, the Sync Jump Width could be the
maximum of 4 TQ. However, normally a large SJW is
Some requirements for programming of the time only necessary when the clock generation of the
segments: different nodes is inaccurate or unstable, such as using
Prop_Seg + Phase_Seg 1 Phase_Seg 2 ceramic resonators. Typically, an SJW of 1 is enough.
Phase_Seg 2 Sync Jump Width.
For example, assume that a 125 kHz CAN baud rate is
27.12 Oscillator Tolerance
desired, using 20 MHz for FOSC. With a TOSC of 50 ns, As a rule of thumb, the bit timing requirements allow
a baud rate prescaler value of 04h gives a TQ of 500 ns. ceramic resonators to be used in applications with
To obtain a Nominal Bit Rate of 125 kHz, the Nominal transmission rates of up to 125 Kbit/sec. For the full bus
Bit Time must be 8 s or 16 TQ. speed range of the CAN protocol, a quartz oscillator is
Using 1 TQ for the Sync_Seg, 2 TQ for the Prop_Seg required. Refer to ISO11898-1 for oscillator tolerance
and 7 TQ for Phase Segment 1 would place the sample requirements.
point at 10 TQ after the transition. This leaves 6 TQ for
Phase Segment 2.
The PRSEG bits set the length of the propagation seg- 27.14.4 BIT ERROR
ment in terms of TQ. The SEG1PH bits set the length of
A bit error occurs if a transmitter sends a dominant bit
Phase Segment 1 in TQ. The SAM bit controls how
and detects a recessive bit, or if it sends a recessive bit
many times the RXCAN pin is sampled. Setting this bit
and detects a dominant bit, when monitoring the actual
to a 1 causes the bus to be sampled three times: twice
bus level and comparing it to the just transmitted bit. In
at TQ/2 before the sample point and once at the normal
the case where the transmitter sends a recessive bit
sample point (which is at the end of Phase Segment 1).
and a dominant bit is detected during the arbitration
The value of the bus is determined to be the value read
field and the Acknowledge slot, no bit error is
during at least two of the samples. If the SAM bit is set
generated because normal arbitration is occurring.
to a 0, then the RXCAN pin is sampled only once at
the sample point. The SEG2PHTS bit controls how the
27.14.5 STUFF BIT ERROR
length of Phase Segment 2 is determined. If this bit is
set to a 1, then the length of Phase Segment 2 is lf, between the Start-of-Frame (SOF) and the CRC
determined by the SEG2PH bits of BRGCON3. If the delimiter, six consecutive bits with the same polarity are
SEG2PHTS bit is set to a 0, then the length of Phase detected, the bit stuffing rule has been violated. A stuff
Segment 2 is the greater of Phase Segment 1 and the bit error occurs and an error frame is generated. The
information processing time (which is fixed at 2 TQ for message is repeated.
the PIC18F66K80 family).
27.14.6 ERROR STATES
27.13.3 BRGCON3 Detected errors are made public to all other nodes via
The PHSEG2<2:0> bits set the length (in TQ) of Phase error frames. The transmission of the erroneous mes-
Segment 2 if the SEG2PHTS bit is set to a 1. If the sage is aborted and the frame is repeated as soon as
SEG2PHTS bit is set to a 0, then the PHSEG2<2:0> possible. Furthermore, each CAN node is in one of the
bits have no effect. three error states; error-active, error-passive or
bus-off, according to the value of the internal error
27.14 Error Detection counters. The error-active state is the usual state
where the bus node can transmit messages and acti-
The CAN protocol provides sophisticated error vate error frames (made of dominant bits) without any
detection mechanisms. The following errors can be restrictions. In the error-passive state, messages and
detected. passive error frames (made of recessive bits) may be
transmitted. The bus-off state makes it temporarily
27.14.1 CRC ERROR impossible for the node to participate in the bus
With the Cyclic Redundancy Check (CRC), the trans- communication. During this state, messages can neither
mitter calculates special check bits for the bit be received nor transmitted.
sequence, from the start of a frame until the end of the
data field. This CRC sequence is transmitted in the 27.14.7 ERROR MODES AND ERROR
CRC field. The receiving node also calculates the CRC COUNTERS
sequence using the same formula and performs a The PIC18F66K80 family devices contain two error
comparison to the received sequence. If a mismatch is counters: the Receive Error Counter (RXERRCNT) and
detected, a CRC error has occurred and an error frame the Transmit Error Counter (TXERRCNT). The values of
is generated. The message is repeated. both counters can be read by the MCU. These counters
are incremented or decremented in accordance with the
CAN bus specification.
Reset
Error-
Passive
TXERRCNT > 255
Bus-
Off
27.15 CAN Interrupts The interrupts can be broken up into two categories:
receive and transmit interrupts.
The module has several sources of interrupts. Each of
these interrupts can be individually enabled or dis- The receive related interrupts are:
abled. The PIR5 register contains interrupt flags. The Receive Interrupts
PIE5 register contains the enables for the 8 main inter- Wake-up Interrupt
rupts. A special set of read-only bits in the CANSTAT Receiver Overrun Interrupt
register, the ICODE bits, can be used in combination
Receiver Warning Interrupt
with a jump table for efficient handling of interrupts.
Receiver Error-Passive Interrupt
All interrupts have one source, with the exception of the
error interrupt and buffer interrupts in Mode 1 and 2. Any The transmit related interrupts are:
of the error interrupt sources can set the error interrupt Transmit Interrupts
flag. The source of the error interrupt can be determined Transmitter Warning Interrupt
by reading the Communication Status register,
Transmitter Error-Passive Interrupt
COMSTAT. In Mode 1 and 2, there are two interrupt
enable/disable and flag bits one for all transmit buffers Bus-Off Interrupt
and the other for all receive buffers.
27.15.6.6 Bus-Off
The transmit error counter has exceeded 255 and the
device has gone to bus-off state.
Note 1: For the specifications, see Section 31.1 DC Characteristics: Supply Voltage PIC18F66K80 Family
(Industrial/Extended).
2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently
controlled.
Note 1: Implemented only on the 64-pin devices (PIC18F6XK80). Maintain as 0 on 28-pin, 40-pin and 44-pin
devices.
Note 1: For the memory size of the blocks, see Figure 28-6.
Note 1: For the memory size of the blocks, see Figure 28-6. The boot block size changes with BBSIZ0.
Note 1: For the memory size of the blocks, see Figure 28-6.
Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode.
2: For the memory size of the blocks, see Figure 28-6.
Note 1: For the memory size of the blocks, see Figure 28-6.
Note 1: For the memory size of the blocks, see Figure 28-6.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: These values for DEV<10:3> may be shared with other devices. The specific device is always identified by
using the entire DEV<10:0> bit sequence.
WDT Enabled,
SWDTEN Disabled
WDT Controlled with
SWDTEN bit Setting
WDT Enabled only while
Device Active, Disabled
WDT Disabled in Hardware,
SWDTEN Disabled
WDTPS<3:0> 4
Sleep
INTOSC Source
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: This bit has no effect if the Configuration bits, WDTEN<1:0>, are enabled.
2: This bit is available only when RETEN = 0.
3: This bit is disabled on PIC18LF devices.
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock
Transition(2)
CPU Clock
Peripheral
Clock
Program
Counter PC PC + 2 PC + 4 PC + 6
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
Sample Clock
Device Oscillator
Clock Failure
Output
CM Output
(Q)
Failure
Detected
OSCFIF
000000h
Code Memory
01FFFFh Device/Memory Size(1)
PIC18FX6K80 PIC18FX5K80
3FFFFFh
28.6.1 PROGRAM MEMORY location outside of that block is not allowed to read and
CODE PROTECTION will result in reading 0s. Figures 28-7 through 28-9
illustrate table write and table read protection.
The program memory may be read to, or written from,
any location using the table read and table write Note: Code protection bits may only be written
instructions. The Device ID may be read with table to a 0 from a 1 state. It is not possible to
reads. The Configuration registers may be read and write a 1 to a bit in the 0 state. Code
written with the table read and table write instructions. protection bits are only set to 1 by a full
In normal execution mode, the CPx bits have no direct chip erase or block erase function. The full
effect. CPx bits inhibit external reads and writes. A block chip erase and block erase functions can
of user memory may be protected from table writes if the only be initiated via ICSP or an external
WRTx Configuration bit is 0. programmer. Refer to the device
programming specification for more
The EBTRx bits control table reads. For a block of user information.
memory with the EBTRx bit set to 0, a table read
instruction that executes from within that block is allowed
to read. A table read instruction that executes from a
TBLPTR = 0008FFh
WRT0, EBTR0 = 01
00FFFFh
000000h
WRTB, EBTRB = 11
0007FFh
000800h
TBLPTR = 0008FFh
WRT0, EBTR0 = 10
003FFFh
004000h
PC = 007FFEh TBLRD* WRT1, EBTR1 = 11
007FFFh
008000h
WRT2, EBTR2 = 11
00BFFFh
00C000h
WRT3, EBTR3 = 11
00FFFFh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRx = 0.
The TABLAT register returns a value of 0.
00FFFFh
Field Description
a RAM access bit:
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb Bit address within an 8-bit file register (0 to 7).
BSR Bank Select Register. Used to select the current RAM bank.
C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
d Destination select bit:
d = 0: store result in WREG
d = 1: store result in file register f
dest Destination: either the WREG register or the specified register file location.
f 8-bit register file address (00h to FFh), or 2-bit FSR designator (0h to 3h).
fs 12-bit register file address (000h to FFFh). This is the source address.
fd 12-bit register file address (000h to FFFh). This is the destination address.
GIE Global Interrupt Enable bit.
k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
label Label name.
mm The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
* No Change to register (such as TBLPTR with table reads and writes)
*+ Post-Increment register (such as TBLPTR with table reads and writes)
*- Post-Decrement register (such as TBLPTR with table reads and writes)
+* Pre-Increment register (such as TBLPTR with table reads and writes)
n The relative address (2s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions.
PC Program Counter.
PCL Program Counter Low Byte.
PCH Program Counter High Byte.
PCLATH Program Counter High Byte Latch.
PCLATU Program Counter Upper Byte Latch.
PD Power-Down bit.
PRODH Product of Multiply High Byte.
PRODL Product of Multiply Low Byte.
s Fast Call/Return mode select bit:
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
TBLPTR 21-bit Table Pointer (points to a Program Memory location).
TABLAT 8-bit Table Latch.
TO Time-out bit.
TOS Top-of-Stack.
u Unused or Unchanged.
WDT Watchdog Timer.
WREG Working register (accumulator).
x Dont care (0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
zs 7-bit offset value for Indirect Addressing of register files (source).
zd 7-bit offset value for Indirect Addressing of register files (destination).
{ } Optional argument.
[text] Indicates an Indexed Address.
(text) The contents of text.
[expr]<n> Specifies bit n of the register indicated by the pointer expr.
Assigned to.
< > Register bit field.
In the set of.
italics User-defined term (font is Courier New).
Literal operations
15 8 7 0
OPCODE k (literal) MOVLW 7Fh
Control operations
CALL, GOTO and Branch operations
15 8 7 0
OPCODE n<7:0> (literal) GOTO Label
15 12 11 0
1111 n<19:8> (literal)
15 8 7 0
OPCODE S n<7:0> (literal) CALL MYFUNC
15 12 11 0
1111 n<19:8> (literal)
S = Fast bit
15 11 10 0
OPCODE n<10:0> (literal) BRA MYFUNC
15 8 7 0
OPCODE n<7:0> (literal) BC MYFUNC
BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2
ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2
ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2
CLRF f, a Clear f 1 0110 101a ffff ffff Z 2
COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2
CPFSEQ f, a Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None 4
CPFSGT f, a Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None 4
CPFSLT f, a Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2
DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4
DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2
INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4
INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2
IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2
MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1
MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None
fd (destination) 2nd word 1111 ffff ffff ffff
MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None
MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2
NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N
RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2
RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N
RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N
RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N
SETF f, a Set f 1 0110 100a ffff ffff None 1, 2
SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N
Borrow
SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2
SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N
Borrow
SWAPF f, d, a Swap Nibbles in f 1 0011 10da ffff ffff None 4
TSTFSZ f, a Test f, Skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2
XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is 1 for a pin configured as an input
and is driven low by an external device, the data will be written back with a 0.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared if assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that
all program memory locations have a valid instruction.
BIT-ORIENTED OPERATIONS
BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2
BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2
BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4
BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4
BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2
CONTROL OPERATIONS
BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None
BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None
BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None
BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None
BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None
BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None
BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None
BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None
BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None
CALL n, s Call Subroutine 1st word 2 1110 110s kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
CLRWDT Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD
DAW Decimal Adjust WREG 1 0000 0000 0000 0111 C
GOTO n Go to Address 1st word 2 1110 1111 kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
NOP No Operation 1 0000 0000 0000 0000 None
NOP No Operation 1 1111 xxxx xxxx xxxx None 4
POP Pop Top of Return Stack (TOS) 1 0000 0000 0000 0110 None
PUSH Push Top of Return Stack (TOS) 1 0000 0000 0000 0101 None
RCALL n Relative Call 2 1101 1nnn nnnn nnnn None
RESET Software Device Reset 1 0000 0000 1111 1111 All
RETFIE s Return from Interrupt Enable 2 0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None
RETURN s Return from Subroutine 2 0000 0000 0001 001s None
SLEEP Go into Standby mode 1 0000 0000 0000 0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is 1 for a pin configured as an input
and is driven low by an external device, the data will be written back with a 0.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared if assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that
all program memory locations have a valid instruction.
LITERAL OPERATIONS
ADDLW k Add Literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N
ANDLW k AND Literal with WREG 1 0000 1011 kkkk kkkk Z, N
IORLW k Inclusive OR Literal with WREG 1 0000 1001 kkkk kkkk Z, N
LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None
to FSR(f) 1st word 1111 0000 kkkk kkkk
MOVLB k Move Literal to BSR<3:0> 1 0000 0001 0000 kkkk None
MOVLW k Move Literal to WREG 1 0000 1110 kkkk kkkk None
MULLW k Multiply Literal with WREG 1 0000 1101 kkkk kkkk None
RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None
SUBLW k Subtract WREG from Literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N
XORLW k Exclusive OR Literal with WREG 1 0000 1010 kkkk kkkk Z, N
DATA MEMORY PROGRAM MEMORY OPERATIONS
TBLRD* Table Read 2 0000 0000 0000 1000 None
TBLRD*+ Table Read with Post-Increment 0000 0000 0000 1001 None
TBLRD*- Table Read with Post-Decrement 0000 0000 0000 1010 None
TBLRD+* Table Read with Pre-Increment 0000 0000 0000 1011 None
TBLWT* Table Write 2 0000 0000 0000 1100 None
TBLWT*+ Table Write with Post-Increment 0000 0000 0000 1101 None
TBLWT*- Table Write with Post-Decrement 0000 0000 0000 1110 None
TBLWT+* Table Write with Pre-Increment 0000 0000 0000 1111 None
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is 1 for a pin configured as an input
and is driven low by an external device, the data will be written back with a 0.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared if assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that
all program memory locations have a valid instruction.
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write to
register f Data destination
BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set
Description: Clears the contents of the specified Encoding: 0000 0000 0000 0100
register. Description: CLRWDT instruction resets the
If a is 0, the Access Bank is selected. Watchdog Timer. It also resets the
If a is 1, the BSR is used to select the postscaler of the WDT. Status bits, TO
and PD, are set.
GPR bank.
If a is 0 and the extended instruction Words: 1
set is enabled, this instruction operates Cycles: 1
in Indexed Literal Offset Addressing Q Cycle Activity:
mode whenever f 95 (5Fh). See
Q1 Q2 Q3 Q4
Section 29.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed Decode No Process No
Literal Offset Mode for details. operation Data operation
Words: 1
Example: CLRWDT
Cycles: 1
Before Instruction
Q Cycle Activity:
WDT Counter = ?
Q1 Q2 Q3 Q4 After Instruction
Decode Read Process Write WDT Counter = 00h
register f Data register f WDT Postscaler = 0
TO = 1
Example: CLRF FLAG_REG,1 PD = 1
Before Instruction
FLAG_REG = 5Ah
After Instruction
FLAG_REG = 00h
CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W
Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a}
Operands: 0 f 255 Operands: 0 f 255
a [0,1] a [0,1]
Operation: (f) W),
Operation: (f) W),
skip if (f) > (W) skip if (f) < (W)
(unsigned comparison) (unsigned comparison)
Status Affected: None
Status Affected: None
Encoding: 0110 010a ffff ffff
Encoding: 0110 000a ffff ffff
Description: Compares the contents of data memory
location f to the contents of the W by Description: Compares the contents of data memory
performing an unsigned subtraction. location f to the contents of W by
performing an unsigned subtraction.
If the contents of f are greater than the
contents of WREG, then the fetched If the contents of f are less than the
instruction is discarded and a NOP is contents of W, then the fetched
executed instead, making this a instruction is discarded and a NOP is
two-cycle instruction. executed instead, making this a
two-cycle instruction.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the If a is 0, the Access Bank is selected.
GPR bank. If a is 1, the BSR is used to select the
GPR bank.
If a is 0 and the extended instruction
set is enabled, this instruction operates Words: 1
in Indexed Literal Offset Addressing Cycles: 1(2)
mode whenever f 95 (5Fh). See Note: 3 cycles if skip and followed
Section 29.2.3 Byte-Oriented and by a 2-word instruction.
Bit-Oriented Instructions in Indexed
Q Cycle Activity:
Literal Offset Mode for details.
Q1 Q2 Q3 Q4
Words: 1
Decode Read Process No
Cycles: 1(2) register f Data operation
Note: 3 cycles if skip and followed
If skip:
by a 2-word instruction.
Q1 Q2 Q3 Q4
Q Cycle Activity:
No No No No
Q1 Q2 Q3 Q4
operation operation operation operation
Decode Read Process No
register f Data operation If skip and followed by 2-word instruction:
If skip: Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 No No No No
No No No No operation operation operation operation
operation operation operation operation No No No No
If skip and followed by 2-word instruction: operation operation operation operation
Q1 Q2 Q3 Q4
No No No No Example: HERE CPFSLT REG, 1
operation operation operation operation NLESS :
No No No No LESS :
operation operation operation operation Before Instruction
PC = Address (HERE)
Example: HERE CPFSGT REG, 0 W = ?
NGREATER : After Instruction
GREATER : If REG < W;
Before Instruction PC = Address (LESS)
If REG W;
PC = Address (HERE) PC = Address (NLESS)
W = ?
After Instruction
If REG W;
PC = Address (GREATER)
If REG W;
PC = Address (NGREATER)
POP Pop Top of Return Stack PUSH Push Top of Return Stack
RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry
Words: 1 C register f
Cycles: 1
Words: 1
Q Cycle Activity:
Cycles: 1
Q1 Q2 Q3 Q4
Decode Read Process Write to Q Cycle Activity:
register f Data destination Q1 Q2 Q3 Q4
Decode Read Process Write to
Example: RLNCF REG, 1, 0 register f Data destination
Before Instruction
REG = 1010 1011 Example: RRCF REG, 0, 0
After Instruction Before Instruction
REG = 0101 0111 REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 0111 0011
C = 0
ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return
Syntax: ADDFSR f, k Syntax: ADDULNK k
Operands: 0 k 63 Operands: 0 k 63
f [ 0, 1, 2 ] Operation: FSR2 + k FSR2,
Operation: FSR(f) + k FSR(f) (TOS) PC
Status Affected: None Status Affected: None
Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk
Description: The 6-bit literal k is added to the Description: The 6-bit literal k is added to the
contents of the FSR specified by f. contents of FSR2. A RETURN is then
Words: 1 executed by loading the PC with the
TOS.
Cycles: 1
Q Cycle Activity: The instruction takes two cycles to
execute; a NOP is performed during
Q1 Q2 Q3 Q4
the second cycle.
Decode Read Process Write to
literal k Data FSR This may be thought of as a special
case of the ADDFSR instruction,
where f = 3 (binary 11); it operates
Example: ADDFSR 2, 23h only on FSR2.
Words: 1
Before Instruction
FSR2 = 03FFh Cycles: 2
After Instruction Q Cycle Activity:
FSR2 = 0422h Q1 Q2 Q3 Q4
Decode Read Process Write to
literal k Data FSR
No No No No
Operation Operation Operation Operation
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2
Syntax: MOVSS [zs], [zd] Syntax: PUSHL k
Operands: 0 zs 127 Operands: 0k 255
0 zd 127
Operation: k (FSR2),
Operation: ((FSR2) + zs) ((FSR2) + zd) FSR2 1 FSR2
Status Affected: None Status Affected: None
Encoding:
Encoding: 1111 1010 kkkk kkkk
1st word (source) 1110 1011 1zzz zzzzs
2nd word (dest.) 1111 xxxx xzzz zzzzd Description: The 8-bit literal k is written to the data
Description The contents of the source register are memory address specified by FSR2.
FSR2 is decremented by 1 after the
moved to the destination register. The
addresses of the source and destination operation.
registers are determined by adding the This instruction allows users to push
7-bit literal offsets, zs or zd, values onto a software stack.
respectively, to the value of FSR2. Both Words: 1
registers can be located anywhere in
the 4096-byte data memory space Cycles: 1
(000h to FFFh). Q Cycle Activity:
The MOVSS instruction cannot use the Q1 Q2 Q3 Q4
PCL, TOSU, TOSH or TOSL as the Decode Read k Process Write to
destination register. data destination
If the resultant source address points to
an Indirect Addressing register, the
value returned will be 00h. If the Example: PUSHL 08h
resultant destination address points to Before Instruction
an Indirect Addressing register, the FSR2H:FSR2L = 01ECh
instruction will execute as a NOP. Memory (01ECh) = 00h
Words: 2
After Instruction
Cycles: 2 FSR2H:FSR2L = 01EBh
Q Cycle Activity: Memory (01ECh) = 08h
Q1 Q2 Q3 Q4
Decode Determine Determine Read
source addr source addr source reg
Decode Determine Determine Write
dest addr dest addr to dest reg
SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return
Syntax: SUBFSR f, k Syntax: SUBULNK k
Operands: 0 k 63 Operands: 0 k 63
f [ 0, 1, 2 ] Operation: FSR2 k FSR2,
Operation: FSRf k FSRf (TOS) PC
Status Affected: None Status Affected: None
Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk
Description: The 6-bit literal k is subtracted from Description: The 6-bit literal k is subtracted from the
the contents of the FSR specified contents of the FSR2. A RETURN is then
by f. executed by loading the PC with the
Words: 1 TOS.
Cycles: 1 The instruction takes two cycles to
Q Cycle Activity: execute; a NOP is performed during the
second cycle.
Q1 Q2 Q3 Q4
Decode Read Process Write to This may be thought of as a special case
of the SUBFSR instruction, where f = 3
register f Data destination
(binary 11); it operates only on FSR2.
Words: 1
Example: SUBFSR 2, 23h Cycles: 2
Before Instruction Q Cycle Activity:
FSR2 = 03FFh Q1 Q2 Q3 Q4
After Instruction Decode Read Process Write to
FSR2 = 03DCh register f Data destination
No No No No
Operation Operation Operation Operation
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
6V
5.5V
5V
4V PIC18F66K80 Family
Voltage (VDD)
3V
3V
1.8V
Note 1: For VDD values 1.8V to 3V, FMAX = (VDD 1.72)/0.02 MHz.
4V
3.75V
3.6V
2.5V
1.8V
4 MHz 64 MHz
Frequency
Note 1: When the on-chip voltage regulator is disabled, VDD must be maintained so that VDD 3.6V.
2: For VDD values 1.8V to 3V, FMAX = (VDD 1.72)/0.02 MHz.
Param
Device Typ Max Units Conditions
No.
3 6 A +125C
PIC18LFXXK80 14 500 nA -40C
34 600 nA +25C VDD = 3.3V
92 850 nA +60C (Sleep mode)
312 1250 nA +85C Regulator Disabled
4 8 A +125C
PIC18FXXK80 200 700 nA -40C
230 800 nA +25C VDD = 3.3V
320 1050 nA +60C (Sleep mode)
510 1500 nA +85C Regulator Enabled
5 9 A +125C
PIC18FXXK80 220 1000 nA -40C
240 1000 nA +25C VDD = 5V
340 1100 nA +60C (Sleep mode)
540 1580 nA +85C Regulator Enabled
5 10 A +125C
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the
part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, SOSC oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature
crystals are available at a much higher cost.
4: For LF devices, RETEN (CONFIG1L<0>) = 1.
5: For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
7 11 mA +125C
PIC18FXXK80 8 12 mA -40C
8 12 mA +60C
VDD = 5V(5)
8 12 mA +25C
Regulator Enabled
8 12 mA +85C
8 12 mA +125C
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the
part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, SOSC oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature
crystals are available at a much higher cost.
4: For LF devices, RETEN (CONFIG1L<0>) = 1.
5: For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0.
Param
Device Typ Max Units Conditions
No.
7 11 mA +125C
PIC18FXXK80 8 12 mA -40C
8 12 mA +25C
VDD = 5V(5)
8 12 mA +60C
Regulator Enabled
8 12 mA +85C
8 12 mA +125C
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the
part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, SOSC oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature
crystals are available at a much higher cost.
4: For LF devices, RETEN (CONFIG1L<0>) = 1.
5: For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Sym Characteristics Min Typ Max Units Comments
No.
D300 VIOFF Input Offset Voltage 5.0 40 mV
D301 VICM Input Common Mode Voltage AVDD 1.5 V
D302 CMRR Common Mode Rejection Ratio 55 dB
D303 TRESP Response Time(1) 150 400 ns
D304 TMC2OV Comparator Mode Change to 10 s
Output Valid*
Note 1: Response time measured with one comparator input at (AVDD 1.5)/2, while the other input transitions
from VSS to VDD.
Param
Sym Characteristics Min Typ Max Units Comments
No.
D310 VRES Resolution VDD/24 VDD/32 LSb
D311 VRAA Absolute Accuracy 1/2 LSb
D312 VRUR Unit Resistor Value (R) 2k
D313 TSET Settling Time(1) 10 s
Note 1: Settling time measured while CVRR = 1 and CVR<3:0> transitions from 0000 to 1111.
Param
Sym Characteristics Min Typ Max Units Comments
No.
VRGOUT Regulator Output Voltage 3.3 V
CEFC External Filter Capacitor Value 4.7 10 F Capacitor must be
low-ESR, a low series
resistance (< 5)
VDD/2
RL
CL Pin CL
Pin
VSS VSS
RL = 464
CL = 50 pF for all pins except OSC2/CLKO/RA6
and including D and E outputs as ports
CL = 15 pF for OSC2/CLKO/RA6
OSC1
1 3 3 4 4
2
CLKO
OSC1
10 11
CLKO
13 12
14 19 18
16
I/O pin
(Input)
17 15
20, 21
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34 34
I/O pins
VDD BVDD
35
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable 36
TABLE 31-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
Symbol Characteristic Min Typ Max Units Conditions
No.
30 TmcL MCLR Pulse Width (low) 2 s
31 TWDT Watchdog Timer Time-out Period 4.00 ms
(no postscaler)
32 TOST Oscillation Start-up Timer Period 1024 TOSC 1024 TOSC TOSC = OSC1 period
33 TPWRT Power-up Timer Period 65.5 ms
34 TIOZ I/O High-Impedance from MCLR 2 s
Low or Watchdog Timer Reset
35 TBOR Brown-out Reset Pulse Width 200 s VDD BVDD (see D005)
36 TIVRST Time for Internal Reference 25 s
Voltage to become Stable
37 THLVD High/Low-Voltage Detect Pulse Width 200 s VDD VHLVD
38 TCSD CPU Start-up Time 5 10 s
39 TIOBST Time for INTOSC to Stabilize 1 s
VHLVD
VHLVD
HLVDIF
TxCKI
40 41
42
SOSCO/SCLKI
45 46
47 48
TMR0 or
TMR1
CCPx
(Capture Mode)
50 51
52
CCPx
(Compare or PWM Mode)
53 54
SCKx
(CKPx = 0)
78 79
SCKx
(CKPx = 1)
79 78
80
75, 76
81
SCKx
(CKPx = 0)
79
73
SCKx
(CKPx = 1)
80
78
75, 76
74
SSx
70
SCKx
(CKPx = 0) 83
71 72
78 79
SCKx
(CKP = 1)
79 78
80
75, 76 77
TABLE 31-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
Symbol Characteristic Min Max Units Conditions
No.
70 TSSL2SCH, SSx to SCKx or SCKx Input 3 TCY ns
TSSL2SCL
70A TSSL2WB SSx to write to SSPBUF 3 TCY ns
71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 ns
71A (Slave mode) Single Byte 40 ns (Note 1)
72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 ns
72A (Slave mode) Single Byte 40 ns (Note 1)
73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 20 ns
TDIV2SCL
73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 ns (Note 2)
74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 ns
TSCL2DIL
75 TDOR SDOx Data Output Rise Time 25 ns
76 TDOF SDOx Data Output Fall Time 25 ns
77 TSSH2DOZ SSx to SDOx Output High-impedance 10 50 ns
78 TSCR SCKx Output Rise Time (Master mode) 25 ns
79 TSCF SCKx Output Fall Time (Master mode) 25 ns
80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge 50 ns
TSCL2DOV
83 TSCH2SSH, SSx after SCKx Edge 1.5 TCY + 40 ns
TSCL2SSH
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
70
SCKx 83
(CKPx = 0)
71 72
SCKx
(CKPx = 1)
80
75, 76 77
SDIx
MSb In bit 6 - - - - 1 LSb In
74
Note: Refer to Figure 31-3 for load conditions.
SCLx
91 93
90 92
SDAx
Start Stop
Condition Condition
91 92
SDAx
In
110
109 109
SDAx
Out
SCLx
91 93
90 92
SDAx
Start Stop
Condition Condition
SDAx
Out
TXx/CKx
pin
121 121
RXx/DTx
pin
120
122
Note: Refer to Figure 31-3 for load conditions.
TXx/CKx
pin 125
RXx/DTx
pin
126
BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK 132
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to
be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
XXXXXXXX 18F25K80
XXXXXXXX /MM e3
YYWWNNN 1010017
XXXXXXXXXXXXXXXXXXXX PIC18F26K80/SO e3
XXXXXXXXXXXXXXXXXXXX 1010017
XXXXXXXXXXXXXXXXXXXX
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XXXXXXXXXXXXXXXXX PIC18F26K80-I/SP e3
XXXXXXXXXXXXXXXXX 1010017
YYWWNNN
XXXXXXXXXXXX PIC18F26K80
XXXXXXXXXXXX -I/SS e3
YYWWNNN 1010017
Note: In the event the full Microchip part number cannot be marked on one line, it will
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characters for customer-specific information.
XXXXXXXXXXXXXXXXXX PIC18F45K80-I/P e3
XXXXXXXXXXXXXXXXXX 1010017
XXXXXXXXXXXXXXXXXX
YYWWNNN
XXXXXXXXXX 18F45K80
XXXXXXXXXX -I/ML e3
XXXXXXXXXX 1010017
YYWWNNN
XXXXXXXXXX 18F45K80
XXXXXXXXXX -I/PT e3Example
XXXXXXXXXX 1010017
YYWWNNN
64-Lead QFN
XXXXXXXXXX 18F65K80
XXXXXXXXXX -I/MR e3
XXXXXXXXXX 1010017
YYWWNNN
XXXXXXXXXX 18F65K80
XXXXXXXXXX -I/PT e3
XXXXXXXXXX 1010017
YYWWNNN
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TABLE B-1: NOTABLE DIFFERENCES BETWEEN 28, 40 AND 44-PIN DEVICES PIC18F66K80,
PIC18F4580 AND PIC18F4680 FAMILIES
Characteristic PIC18F66K80 Family PIC18F4680 Family PIC18F4580 Family
Max Operating Frequency 64 MHz 40 MHz 40 MHz
Max Program Memory 64 Kbytes 64 Kbytes 32 Kbytes
Data Memory (bytes) 3,648 3,328 1,536
CTMU Yes No No
SOSC Oscillator Options Low-power oscillator option for SOSC No options No options
T1CKI Clock T1CKI can be used as a clock without No No
enabling the SOSC oscillator
INTOSC Up to 16 MHz Up to 8 MHz Up to 8 MHz
Timers Two 8-bit, three 16-bit One 8-bit, three 16-bit One 8-bit, three 16-bit
ECCP One for all devices 40 and 44-pin devices One 40 and 44-pin devices One
28-pin devices None 28-pin devices None
CCP Four One One
Data EEPROM (bytes) 1,024 1,024 256
WDT Prescale Options 22 16 16
5V Operation 18FXXK80 parts 5V operation Yes Yes
18LFXXK80 parts 3.3V operation
nanoWatt XLP Yes No No
Regulator 18FXXK80 parts Yes No No
18LFXXK80 parts No
Low-Power BOR Yes No No
A/D Converter 12-bit signed differential 10-bit 10-bit
A/D Channels 28-pin devices Eight Channels 8 Channels for 28-pin devices/ 8 Channels for 28-pin devices/
40 and 44-pin devices 15 Channels 11 Channels for 40 and 44-pin 11 Channels for 40 and 44-pin
devices devices
Internal Temp Sensor Yes No No
EUSART Two One One
Comparators Two 28-pin devices None 28-pin devices None
40 and 44-pin devices Two 40 and 44-pin devices Two
Oscillator Options 14 Nine Nine
Ultra Low-Power Wake-up Yes No No
(ULPW)
Adjustable Slew Rate Yes No No
for I/O
PLL Available for all oscillator options Available only for high-speed Available only for high-speed
crystal and internal oscillator crystal and internal oscillator
TXM Modulator No No No
Questions:
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
08/04/10